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1206 commits

Author SHA1 Message Date
igneum-labs
0ccf0f5f27 Merge canary-203-fleet 70ac965c into master (gate: green on 3e3e0c60, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:40:04 +00:00
igneum-labs
70ac965cd0 Merge master f6b6a804b into canary-203-fleet under the master-landing lock 2026-10-09 12:40:01 +00:00
igneum-labs
f6b6a804b4 Merge proving-live 5c4a4f56 into master (gate: green on 069aa1f5, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:39:01 +00:00
igneum-labs
5c4a4f5614 Merge master ba0c920c8 into proving-live under the master-landing lock 2026-10-09 12:38:59 +00:00
igneum-labs
ba0c920c87 Merge canary-shard-unavailable 02c4e234 into master (gate: green on da1ae05c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:37:58 +00:00
igneum-labs
02c4e2344b Merge master b7f3e57a0 into canary-shard-unavailable under the master-landing lock 2026-10-09 12:37:56 +00:00
igneum-labs
b7f3e57a03 Merge lab-search-docs 516ab8c6 into master (gate: green on 8a50c4a6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 12:36:53 +00:00
igneum-labs
516ab8c6fc Merge master baec97d00 into lab-search-docs under the master-landing lock 2026-10-09 12:36:50 +00:00
igneum-labs
baec97d007 Merge canary-203-fleet 3446366c into master (gate: green on 3e3e0c60, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:34:21 +00:00
igneum-labs
3446366cb2 Merge master 06d06ae3c into canary-203-fleet under the master-landing lock 2026-10-09 12:34:18 +00:00
igneum-labs
06d06ae3cd Merge lab-20261009 baaf2e34 into master (gate: green on 3700ed30, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 12:33:09 +00:00
igneum-labs
baaf2e3497 Merge master 773b05c4d into lab-20261009 under the master-landing lock 2026-10-09 12:33:05 +00:00
igneum-labs
da1ae05c65 canary-check: the shard.unavailable form for a prover whose mechanics ran but found no segment inside the margin while the fleet's provers hold the worklist (main's ruling, 9 October 2026 13:0x UK, the 2.0.3 hive canary): a fact read back with the mechanics proved and the proving lane's allocation sentence, never a replacement for a shard refused through the entry's own fault; self-test both ways 2026-10-09 12:30:31 +00:00
igneum-labs
069aa1f574 Canary segment: every 32nd segment held 300 DAA for a CANARY=1 prover (box-prover.py canary_rule, self-test 6 cases, no chain change); the design with today's record 2026-10-09 12:30:22 +00:00
igneum-labs
773b05c4d3 Merge site-claims-1p5x ece33c2a into master (gate: green on f0e99a7c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:29:30 +00:00
igneum-labs
ece33c2ac9 Merge master 3f07cf74 into site-claims-1p5x under the master-landing lock 2026-10-09 12:29:26 +00:00
igneum-labs
8a50c4a6b5 lab search: the lane's record (the system, the twenty candidates and the three handed, the rankings on sets v0, v2 and v3, the ILP and headroom rows, the X10 fault and x10b, the alu-520k rejection, every artefact by path and sha) 2026-10-09 12:29:21 +00:00
igneum-labs
3e3e0c60af 27f54124 record: the datadir path named without a box-local path (the identity grep refused /root/fleet) 2026-10-09 12:26:40 +00:00
igneum-labs
3700ed3057 1.5x lab: the 520k cell closed by measurement (2.7x v6 per unit, P03 failed), the headroom row closed, a lockable rented host for knee rows, the search's top three as SCREEN behind the ledger
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:26:22 +00:00
igneum-labs
3f07cf74a6 Merge lab-20261009 9c174e90 into master (gate: green on 25e56c1b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 12:23:49 +00:00
igneum-labs
9c174e9054 Merge master 355ce5a94 into lab-20261009 under the master-landing lock 2026-10-09 12:23:46 +00:00
igneum-labs
355ce5a943 Merge canary-db9f8db9-mac e778db90 into master (gate: green on d479b4a1, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:22:28 +00:00
igneum-labs
e778db9003 Merge master 2216068a2 into canary-db9f8db9-mac under the master-landing lock 2026-10-09 12:22:25 +00:00
igneum-labs
f0e99a7c1a Site: the rendered pages after the merge of master 2216068a (built on the box)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:20:45 +00:00
igneum-labs
f0f66f71d8 Merge master 2216068a into site-claims-1p5x (the ledger lane's /gpu-ledger beside /resistance and /public-test in the nav, the footer, the nav contract and the sitemap; the rebuilt pages taken from master and rebuilt on the box; the claims page links the comparative review and the GPU network ledger) 2026-10-09 12:19:47 +00:00
igneum-labs
3ff1b02114 The comparative review of what other GPU chains publish on chip resistance (the 8c.9 row), linked from the claims page
Ravencoin, ProgPoW, Iron Fish, Ethereum Classic, Ergo and Firo: each statement verbatim under 15 words with its URL and date read, each chain's convention, and whether a priced or measured attacker row exists in its record (none found on the pages read, with where we looked). It licenses no ranking sentence.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:18:48 +00:00
igneum-labs
2216068a26 Merge gpu-ledger 23e419cd into master (gate: green on daca8918, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:17:38 +00:00
igneum-labs
23e419cdba Merge master 37bcb15f into gpu-ledger under the master-landing lock 2026-10-09 12:17:35 +00:00
igneum-labs
992ff44f3f rule 33: the 27f54124 node canary record, the lp-4090-11 fleet block as it reads (sync to within ten, mining, quit, version PASS; the shard line none: the fleet's provers hold every whole segment in the 900 s window; verdict FAIL by the rule, main's 13:1x ruling rolls the hubs on the node lines), lines under build-1:/srv/canary/27f54124/lp-4090-11/ 2026-10-09 12:17:31 +00:00
igneum-labs
25e56c1b95 1.5x lab: the 4090 decider closed, Autolykos2 on set v3, the no-emergency-intervention row (8g) with the finality rule v3 pause as measured behaviour, the lab on watch until the ledger page
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:17:04 +00:00
igneum-labs
37bcb15f7a Merge proving-live e75867da into master (gate: green on e9da127d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 12:16:28 +00:00
igneum-labs
e75867daf0 Merge master b824ad68c into proving-live under the master-landing lock 2026-10-09 12:16:25 +00:00
igneum-labs
d479b4a180 Rule 33 canary record db9f8db9: the mac block (the release lane, 9 October 2026; eight lines read back under build-1:/srv/canary/) 2026-10-09 12:15:39 +00:00
igneum-labs
b824ad68cc Merge lab-20261009 27c25eeb into master (gate: green on 27c25eeb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 12:15:20 +00:00
igneum-labs
e9da127ddb Proving live on Devnet 4: the claim-order design (duplicates measured at 43 percent of carried records) and the proving-live record skeleton for the epoch of evidence 2026-10-09 12:09:13 +00:00
igneum-labs
daca8918e1 GPU network ledger: the rendered site pages (gpu-ledger.html and every page with the new Learn entry), built on the box
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:08:42 +00:00
igneum-labs
27c25eeb9b 1.5x lab table: the controls' done line (Etchash, Autolykos2, OpenCL coop-arx), the cross-chain phase A and B with the E9 Pro calibration, the phase B tier rows on the on-chain read, the stale box claims cleared
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:08:38 +00:00
igneum-labs
936883fe05 GPU network ledger: Ergo Autolykos2 moves from NOT RUN to a chain row (CONTROLS' in-house control at the live 7.27 GB table), its public line by source
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:07:56 +00:00
igneum-labs
c63cdb2981 GPU network ledger: phase A and B for Ravencoin, Iron Fish and Ethereum Classic at their 100/0 splits in their own units (ADVERSARY d7db3e596), the public revenue lines by source
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:06:02 +00:00
igneum-labs
c88a378b6a Merge lab-20261009 758d32e9 into master (gate: green on 1ac15116, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 12:04:23 +00:00
igneum-labs
906dcf3301 GPU network ledger: the proving clause labelled LIVE ON DEVNET from the PROVING LIVE lane's on-chain evidence (663 paid v1 segment records, file bd3f53c1 on build-1)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:04:20 +00:00
igneum-labs
758d32e9f6 Merge master a273e6aa1 into lab-20261009 under the master-landing lock 2026-10-09 12:04:20 +00:00
igneum-labs
d8cefefa84 Site: the rendered pages for /resistance and /public-test and the nav with the two new routes (built on the box)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:03:19 +00:00
igneum-labs
3bdbc6f711 Claims page: the phase B row names what runs on chain today (the fleet's prover stack, paid on the devnet) and keeps NOT LIVE until a shipped package proves
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:01:57 +00:00
igneum-labs
1e4d6ba6da The GPU network ledger: the record (docs/analysis/class-v6/1p5x/ledger), the page source (docs/ledger/gpu-ledger.md) and the renderer that fills both from ledger.json; the site registration for /gpu-ledger (build.mjs row, nav panel and sheet, nav check, footer, sitemap)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 12:01:48 +00:00
igneum-labs
a273e6aa12 Merge lab-install-20 fa6549d0 into master (gate: green on 780ea6c2, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:59:42 +00:00
igneum-labs
fa6549d034 Merge master 4d6675fb5 into lab-install-20 under the master-landing lock 2026-10-09 11:59:37 +00:00
igneum-labs
5295e96146 Site: the chip claim in the approved wording (/resistance), the public-test page (/public-test), the 2.0.3 download note and the staged announcement
The claims page serves the laboratory's approved wording verbatim (lab/README.md 8c.9) and nothing stronger: the measured 4 GiB card rows on rented pods, the same-node DRAM board at the 5090 knee and at the worst cohort cell, both conventions with the ProgPoW 0.9.4 and FishHash controls pending, the coexistence table with the cost ratio at all three tested tariffs and the meeting tariff, the new-buyer and used-card columns, phase A and phase B with phase B NOT LIVE, the SRAM die as the residual with its break-even fleet; every figure linked to its row. The litepaper, the miner page and evidence row 6 carry the same wording in place of the 8 October 1.5x bracket. The public-test page: Devnet 4, 2.0.3, not value-bearing, the 30-day independent-operator clock, join per platform, what to report and where, the five gates with their state. The download page: the 2.0.3 note with the five-target dial list and the Windows under-32 GB refusal. docs/public-test/announcement.md staged for the founder's go, not posted. The deploy script carries the served-identity guard in its export (a site-only export built unguarded) and checks the explorer by its title.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:59:09 +00:00
igneum-labs
1ac151166c 1.5x lab: the decider closed on both cards (the 4 GiB object 2 to 3 percent, the 2.4x withdrawn), the read-headroom row answered, the uncapped 5090 cell, the shipping facts with the Devnet 4 correction, the 4 GiB cap defined, the ledger order (8f)
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:57:11 +00:00
igneum-labs
780ea6c252 lab-install: the engine's machine id is the first 8 hex of api/state.machine_id (LabInstall-IdOf; the VM read api/state.machine empty); 11 of 11 agent-side cases on the VM 2026-10-09 11:52:20 +00:00
igneum-labs
4a587eb729 1.5x lab table: the read-headroom row answered (both cards at their activation limit; the ILP lever under 1 percent), the 2.4x reading withdrawn as a contention fault, the shipping row's facts by file and line, the 4 GiB correction on the interface
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:48:24 +00:00
igneum-labs
4d6675fb57 Merge lab-20261009 0f90b549 into master (gate: green on 0f90b549, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 11:45:28 +00:00
igneum-labs
0f90b5491c 1.5x lab: ctl-v6's first full NVIDIA cohort score (the 4090 at stock 5.67x on the board), the 4 GiB correction, the shipping row (a HiveOS prover a 2.0.3.1 item), the sixth review's rulings, the twenty search candidates on set v3
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:38:38 +00:00
igneum-labs
52f65ddd2c Merge site-mac-16gb-note fbef81a2 into master (gate: green on 6847983f, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:37:31 +00:00
igneum-labs
fbef81a230 Merge master 30f2c3390 into site-mac-16gb-note under the master-landing lock 2026-10-09 11:37:28 +00:00
igneum-labs
30f2c33907 Merge lab-20261009 205195b1 into master (gate: green on 205195b1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 11:35:46 +00:00
igneum-labs
6847983f34 Download and miner pages (9 October 2026, main's ruling 12:4x UK): the fresh-sync memory note says plainly that a 16 GB Mac completes the sync in about an hour on swap (macOS pages the node's memory rather than ending it), until 2.0.3.1 snapshot sync 2026-10-09 11:30:39 +00:00
igneum-labs
205195b11b 1.5x lab: the first cohort cells and the X10 measured cell on the table, sets v2 and v3, the X10 facts of record (8a.1), the scoreboard rulings of the fourth to sixth reviews (8c), the bundle (8d), the 4 GiB rule (8e)
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:29:00 +00:00
igneum-labs
4324bec738 Merge lab-install-20 b3a8cb2e into master (gate: green on 311eabdb, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:27:06 +00:00
igneum-labs
b3a8cb2e72 Merge master bb56bdc2a into lab-install-20 under the master-landing lock 2026-10-09 11:27:03 +00:00
igneum-labs
311eabdb31 relay: the lab-install kind (main's ruling 9 Oct 2026): node tools/relay.mjs lab-install <PC> <lab Setup> <sha256> <machine id> queues the one task an agent accepts beside a public engine: a run whose comment-only body pins the lab Setup's name and sha256 and the engine machine id of one of the two house rigs, signed by the lab OTA key (flags.lab_sig) beside the run key and the machine tag; relay/lib/guard.mjs checkLabInstall is the publisher's and the relay's check, relay/clients/lab-install.ps1 the agent's (plus the engine's own id beside it). Tests: relay/test/lab-install.test.mjs (5), relay/clients/lab-install.test.ps1 (9 of 9 on the Windows canary VM). Every other machine refuses as F14 says; the public OTA channel is untouched 2026-10-09 11:20:02 +00:00
igneum-labs
bb56bdc2ab Merge lab-20261009 a7dc07e7 into master (gate: green on a7dc07e7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 11:18:34 +00:00
igneum-labs
a7dc07e7a7 1.5x lab table: set v2 (the v6 board 2.60x WITNESS, its energy split), the ctl-v6 coexistence table as the headline, X10 as SCREEN with the card modelled, the ctl-v6 pins
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:11:39 +00:00
igneum-labs
b9a1b63716 Merge lab-20261009 bc360df4 into master (gate: green on db2eb5d1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 11:09:07 +00:00
igneum-labs
bc360df44f Merge master 0ffae7018 into lab-20261009 under the master-landing lock 2026-10-09 11:09:03 +00:00
igneum-labs
0ffae70187 Merge workers-page-cards 9159a107 into master (gate: green on 410ba706, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:06:29 +00:00
igneum-labs
9159a10769 Merge master 75812c8f into workers-page-cards under the master-landing lock 2026-10-09 11:06:26 +00:00
igneum-labs
75812c8fb2 Merge rule38-packed-update-guard 446abf18 into master (gate: green on 9d88bb09, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:05:16 +00:00
igneum-labs
446abf189c Merge master 9bcdcdf57 into rule38-packed-update-guard under the master-landing lock 2026-10-09 11:05:13 +00:00
igneum-labs
db2eb5d147 1.5x lab: the coexistence table as the scoreboard's headline (section 8b), adversarial set v1 on the table (the frozen v6 board 2.57x, the fused tail CLAIMED), SEARCH's first screen
Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 11:02:10 +00:00
igneum-labs
9bcdcdf576 Merge watch-memory-guard 2236437fe into master (gate: green on 2236437fe, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 11:01:49 +00:00
igneum-labs
cebdc64fac Merge lab-20261009 93c50a14 into master (gate: green on 93c50a14, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:58:29 +00:00
igneum-labs
9d88bb094b Rule 38 (9 October 2026): no entry publishes whose app cannot find its update manifest. tools/ci/packed-update-check.sh opens the DMG, the Windows payload zip (or the zip beside a Setup exe) or the HiveOS tarball as the installer would and refuses a packaged config with no update_manifest, one off the token-folder pattern, a token none of the publisher's known tokens, or the packager's 'update check is disabled' line (the first 2.0.3 DMG built on a Mac without the download token, 11:46 UK, would have shipped an app that never updates); wired into publish-manifest.sh (--mac, --win) and publish-public.sh --hive, self-tested in the gate; tokens never printed 2026-10-09 10:58:14 +00:00
igneum-labs
410ba70626 served-identity-guard self-test: the two no-list cases point the box hashed list at missing paths too (red on every box carrying /srv/builds/_identity since the 10:37 install)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:57:09 +00:00
igneum-labs
2236437fe2 Merge master 53e3cedcb into watch-memory-guard 2026-10-09 10:54:30 +00:00
igneum-labs
b1a6490bed memory guard: the feed's age before any height compare (a feed older than three minutes is a FEED FAULT, never a sync count), two consecutive passes before a unit counts, a datadir older than 30 minutes is a resume and is never stopped (11:32 UK, 9 Oct: the frozen feed read three synced nodes as three fresh syncs and the seed and hand were stopped by their units); the box's backward-read and unit-age checks carried onto master; the fault line in docs/ops.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:51:45 +00:00
igneum-labs
93c50a141a 1.5x lab: X10 (the full-sector fold candidate, the scoped same-node board claim) in the interface and the table; the AMD and Intel tiers NOT RUN with the reason; the lab batch note amended
Section 8a of the interface: the working scope (the same-node board as the energy claim; the die and node-ahead chips as coexistence rows), the object as reviewed, the per-lane assignments with clocks, the verdict line owed to main, the twin ruling. Documents only; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:51:27 +00:00
igneum-labs
53e3cedcbe Merge lab-20261009 72a1139d into master (gate: green on 72a1139d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:48:54 +00:00
igneum-labs
b4c9fbd9f9 Workers page: cards open their detail in place, no compact rows, the Fleet tab links the fleet page; fleet page.py tolerates thin registry rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:47:14 +00:00
igneum-labs
72a1139d6d 1.5x lab: the one evaluation (recipe, adversary interface, worst-cohort score, filters, regression set), the candidate table, the R15 cell lab:candidate (every row NOT RUN)
The laboratory's interface document and candidate table under docs/analysis/class-v6/1p5x/lab/ (the measurement recipe with the read-only twin, the adversary interface with WITNESS and BOUND rows per design, the score as the worst comparison over the cohort same node and one node ahead, the rejection filters F1 to F6, the regression set REG-01 to REG-08 from the 8 and 9 October failures), and the registry batch lab-20261009-01 recording the new map cell lab:candidate on R15-01, R15-08 and R15-09, every row NOT RUN in progress. Documents only; no served figure moves; nothing on the devnet touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:41:30 +00:00
igneum-labs
266caaa9ec Merge snapshot-sync-design-2 133fcb17 into master (gate: green on 4289f056, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:30:06 +00:00
igneum-labs
133fcb17aa Merge master fecee3697 into snapshot-sync-design-2 under the master-landing lock 2026-10-09 10:30:03 +00:00
igneum-labs
fecee36974 Merge mhpow-b4 661ce930 into master (gate: green on 05a20317, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:28:00 +00:00
igneum-labs
661ce9307f Merge master 6e50e87d2 into mhpow-b4 under the master-landing lock 2026-10-09 10:27:57 +00:00
igneum-labs
6e50e87d2d Merge edge-light-host 614f46ef into master (gate: green on 68e7fae3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:26:42 +00:00
igneum-labs
614f46ef8e Merge master b124a9432 into edge-light-host under the master-landing lock 2026-10-09 10:26:39 +00:00
igneum-labs
b124a9432f Merge proving-market-plan c752418f into master (gate: green on 1c88168c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:24:39 +00:00
igneum-labs
c752418f4a Merge master 49422b9fb into proving-market-plan under the master-landing lock 2026-10-09 10:24:35 +00:00
igneum-labs
49422b9fb8 Merge ci-x4-batch 17fa0f12 into master (gate: green on 26ac1d58, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 10:23:23 +00:00
igneum-labs
17fa0f121b Merge master 6f3637e55 into ci-x4-batch under the master-landing lock 2026-10-09 10:23:19 +00:00
igneum-labs
4289f056f2 Snapshot sync: the morning's mechanism as it ran (the shipper's record: mini-snapshot.sh, the app's own quit, the whole devnet-4 tree tarred, 5.06 GB, sha256 5790ee71, 89 s to tar and 639 s to push, the node at lp-04's epoch-13 cut, the 2.0.2 root at 284fb765) and the served form it becomes (the exec state alone, 56 MB, as the first file; the consensus store optional; the certificate-anchored root the thing verified, the sha the transport check; one file per lock per seed)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:22:56 +00:00
igneum-labs
6f3637e552 Merge guard-miner-bench 8afdfba3 into master (gate: green on 40548420, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 10:22:09 +00:00
igneum-labs
8afdfba3a3 Merge master 602f98b64 into guard-miner-bench under the master-landing lock 2026-10-09 10:22:05 +00:00
igneum-labs
602f98b641 Merge 1p5x-int8-docs 41d38666 into master (gate: green on 02b6a53e, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:20:51 +00:00
igneum-labs
41d38666c9 Merge master 4a0e7c45d into 1p5x-int8-docs under the master-landing lock 2026-10-09 10:20:47 +00:00
igneum-labs
05a2031787 registry: R15-07 moves with B4's evidence (batch mhpow-b4-20261009-02, NOT RUN; the tensor page, B2's correction, params section 9)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 10:20:03 +00:00
igneum-labs
4a0e7c45df Merge snapshot-sync-design c04b55e7 into master (gate: green on b95fea6a, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:19:18 +00:00
igneum-labs
c04b55e766 Merge master d506767bf into snapshot-sync-design under the master-landing lock 2026-10-09 10:19:15 +00:00
igneum-labs
ffe57ad755 Merge master d506767bf into mhpow-b4 under the master-landing lock 2026-10-09 10:19:10 +00:00
igneum-labs
d506767bf2 Merge 925e17cdff 79436594 into master (gate: green on 925e17cd, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:17:56 +00:00
igneum-labs
794365942b Merge master 6206427b5 into 925e17cdff under the master-landing lock 2026-10-09 10:17:52 +00:00
igneum-labs
6206427b5b Merge agent-watchdog fa73c348 into master (gate: green on ee98e453, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 10:16:42 +00:00
igneum-labs
fa73c3484a Merge master 8dbdf28bb into agent-watchdog under the master-landing lock 2026-10-09 10:16:38 +00:00
igneum-labs
8dbdf28bbc Merge mhpow-b3 5fbac7a4 into master (gate: green on 8d5d392f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:15:09 +00:00
igneum-labs
26ac1d586a X4's batch recorded on R15-04: the three byte-identical reg64c forms (CPU differential EQUIVALENT, GPU self-test and fingerprint, 4090 pairs g 0.959 to 0.969, chip rows modelled), NOT RUN in progress, the cell rows:1p5x-x4 carried in the batch; recorded from the X4 lane's file under its README
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:14:41 +00:00
igneum-labs
5fbac7a481 Merge master 0653f8d60 into mhpow-b3 under the master-landing lock 2026-10-09 10:12:03 +00:00
igneum-labs
0653f8d60d Merge ci-r15-track-b e16301c8 into master (gate: green on c0343953, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 10:10:43 +00:00
igneum-labs
e16301c8e3 Merge master 4bf9442cf into ci-r15-track-b under the master-landing lock 2026-10-09 10:10:38 +00:00
igneum-labs
d6afb6558c mhpow B4: requirements for a tensor-dominated class (one page), B2's fake-winner correction in README 5b, params section 9
requirements-tensor.md: the one sentence (no tensor-dominated mix can be proved at or below 1.5x on today's rows: the additive
bridge is a weighted harmonic mean, r >= min(s) = 2.35x at the ARX term, 3.1x to 14.8x over 50 to 90 percent tensor), and T1 to
T5 (dataset reads at a floor, the small-SRAM refusal as recompute cost, the systolic array at the class's exact tile, the
fresh-state lottery rule, the certificate's losses). README 5b: the spot checks do not price a fake winner at R1's bound (B2 O-17).
requirements.md marked superseded. NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 10:09:31 +00:00
igneum-labs
4bf9442cf3 Merge ca3-coord-record 98206212 into master (gate: green on 9e745ab7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:09:11 +00:00
igneum-labs
982062124d Merge master 87e6ba139 into ca3-coord-record under the master-landing lock 2026-10-09 10:09:08 +00:00
igneum-labs
b95fea6abe Snapshot sync (node 2.0.3.1), the design page (main's ruling 9 October 2026, 11:1x UK: the fresh-sync memory is a public blocker — a fresh 2.0.2 node reads 29 GB at DAA 43,816 and a 2.0.3 node 34 GB at the tip on a quiet box, ten reset boxes OOM-killed at 16 to 38 GB): the executor's existing exec snapshot (56 MB at the tip) cut at a locked block and served with a manifest signed by the seed's vote key; the joiner's verification (the key in the finality table, the sha, the chain id and digest, the tip under its own verified lock on its selected chain, the state root by the rebuilt accounts, the record's root and the first attesting segment record); the executor's start from it with the body sync from the snapshot's tip; persist-and-drop of the records below the proving window (FULL_RECORDS as a window, the record store answering below it) so the in-memory set is bounded by the window (about 4.7 GB) and a 16 GB fresh install fits; the P2P and HTTPS serving paths; the known-failed tests first; the 16 GB canary by 15:00
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:08:59 +00:00
igneum-labs
87e6ba139e Merge mhpow-b4 4aaa2ad4 into master (gate: green on a9e933a9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:07:56 +00:00
igneum-labs
4aaa2ad4c1 Merge master 4fe7e5fac into mhpow-b4 under the master-landing lock 2026-10-09 10:07:52 +00:00
igneum-labs
1c88168c42 The proving market: one page (main's item 2, 9 October 2026, 12:00 UK): the payment rule as shipped by line on 5d53a591 and 27f54124, what a 16 GB card earns per day at launch demand in native units from the measured inputs, the three steps to a live internal proving market on devnet-4 with their lanes and clocks; nothing here is a registry PASS (NOT RUN)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:07:35 +00:00
igneum-labs
4fe7e5fac5 Merge ci-r15-b1 4d2f4925 into master (gate: green on af7124c9, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 10:06:28 +00:00
igneum-labs
4d2f49256b Merge master b04e9681f into ci-r15-b1 under the master-landing lock 2026-10-09 10:06:23 +00:00
igneum-labs
925e17cdff /download and /miner: the fresh-sync memory blocker stated as the real minimum (64 GB today, 48 GB the floor at this hour, growing with the chain until the snapshot path 2.0.3.1 ships; the measured growth and the 16 GB and 32 GB outcomes in plain words); the class v4 pairing lines that go whatever the X0 amendment says (the 5 October recompute-chip line on the litepaper and /claims, the latency-shadow clauses, the ledger's 3.0x to 3.2x figure); the devnet runs class v5 from its first block per the manifest
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:06:11 +00:00
igneum-labs
68e7fae3f7 memory guard: a node whose RPC does not answer is unknown, never syncing; only a height more than 100 behind the feed counts (a timed-out read of the synced seed stopped the light-reader at 11:04 UK).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:05:58 +00:00
igneum-labs
02b6a53e91 1.5x: the int8-dominated and ARX-only classes as a closed research record (0592e48e8 on 1p5x-int8, five packs on the signing pair, every run row NOT RUN); the test-map cell and the NOT RUN batch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:05:16 +00:00
igneum-labs
b04e9681f4 Merge mhpow-b2 e6132ca1 into master (gate: green on 840ef385, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:05:06 +00:00
igneum-labs
e6132ca197 Merge master 3bc321ab0 into mhpow-b2 under the master-landing lock 2026-10-09 10:05:03 +00:00
igneum-labs
2f43c81931 edge check: /light is read on the devnet RPC host where its Caddy block lives (build.igneum.network answers 404 for it by its own matcher); a read is ok at 200 or a redirect with a body.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 10:04:51 +00:00
igneum-labs
3bc321ab01 Merge 1p5x-x4 2a527417 into master (gate: green on 390fbd8d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 10:03:52 +00:00
igneum-labs
8d5d392ffe mhpow B3: close X-5 against B1's landed fixtures; candidate 2 record (research, withdrawn)
B3 control: B1 landed byte-identical to the working copy the oracle used,
so every row stands. Candidate 2 (fresh-state class v6 labels under the
MTP commitment): the Rust reference over the frozen igneum-pow db36d8060
(fingerprint 5f4d6dc6 read back), KATs at 4 MiB and 1 GiB in both dataset
modes, the known-failed cases refused, the honest rows, the 4090 GPU pair
(chi pack = day pack within 0.04 percent). Finding: H1 recomputation (the
closed-form 1 GiB costs the prover 65 MB; the memory-hard mode's verifier
holds 256 MiB at 0.94 s per proof) and H2 the label chain is a path.
NOT RUN; nothing activates.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 10:01:48 +00:00
igneum-labs
2f83828b27 Merge build/master into mhpow-b3 (export-exclude: both lanes' lines kept, rule 26)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 10:00:50 +00:00
igneum-labs
9e745ab72e Counter ASIC 3.0 status: X7's f and the memory-route verdict (no read-dominated design reaches 1.5x), main's redirect to the int8 class and the founder's first priority, X8's chip side, X5's placement bracket closed, X1, X2 and X3 landed, the 2.0.3 cut, the mini's worker watchdog class, the fresh-sync memory read, Track B's landings, the hash-rate facts and the miners started, the canary's harness fault, the pods
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:58:47 +00:00
igneum-labs
af7124c99d R15 rows opened on main's orders: B1's reference batch recorded as the lane wrote it and the steward's R15-05 row carrying F-3 (BOUND) and F-4; the int8-dominated class's cell (class:int8 on R15-03 and R15-04, three weights and the ARX-only points, nothing measured yet); X7's memory-route verdict as a BOUND-side negative control under R15-02 (f 0.854 on the 4090, s 13 to 39), X8 to follow at its landing; every row NOT RUN; cells carried in the batches
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:58:12 +00:00
igneum-labs
2a527417f5 Merge master c08b06312 into 1p5x-x4 under the master-landing lock 2026-10-09 09:56:58 +00:00
igneum-labs
c08b063124 Merge ca3-coord-record a93595ac into master (gate: green on 2ca9029f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:55:34 +00:00
igneum-labs
a93595ac7a Merge master 4158a2b8c into ca3-coord-record under the master-landing lock 2026-10-09 09:55:31 +00:00
igneum-labs
840ef38549 mhpow B2: O-17, B4's lottery rule adopted with its fake-winner budget; B4's answers to B-T1 to B-T8
B4 (requirements.md on mhpow-b4 a9e933a9a, README 5b on master b67b89cf8) answered B-T3 in shape: trial id
in chi, W = H('W', chi || tau), winners verified in full, spot checks as the pre-filter. B2 adopts it as
O-17 and states the budget B4 asked for (B4-OB-LOT-1): the pre-filter does not price a fake winner, which
keeps one labelling and re-rolls the red sink, (log2 N + 1)/p calls against 2N/p for a real winner, so an
attacker with 1e-6 of the network makes 1.34 fakes per real block at N = 2^24, each costing every
validator it reaches a full labelling (figures section 6). B4 5b's sentence that R1's bound prices the
fake is corrected here. New row B-N4 to the node lane with B6. B-T4, B-T6, B-T7, B-T8 answered; B-T1,
B-T2, B-T5 stay BLOCKED.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:55:03 +00:00
igneum-labs
4158a2b8cb Merge tv-d02 ed578475 into master (gate: green on 45e09729, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:54:18 +00:00
igneum-labs
ed578475b9 Merge master 45eb2acc4 into tv-d02 under the master-landing lock 2026-10-09 09:54:14 +00:00
igneum-labs
4054842093 The public bench table under the served-file guard: site/miner-bench.json (served as /miner-bench.json) joins the site build's guard call and the daily edge check's list; it carried the same UK clock readings the release manifest did
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:54:08 +00:00
igneum-labs
45eb2acc45 Merge mhpow-b1-land 3e6a5282 into master (gate: green on f0e43729, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:53:00 +00:00
igneum-labs
3e6a528217 Merge master 28012e97f into mhpow-b1-land under the master-landing lock 2026-10-09 09:52:57 +00:00
igneum-labs
a9e933a9a0 mhpow B4: the one-page requirements for a Track B construction (Q1 to Q5) and B2's B-T1 to B-T8 answered or BLOCKED
docs/analysis/mhpow/b4/requirements.md: Q1 a lottery draw costs a fresh labelling (B4 Lemma C; B1's fixture A6 as witness);
Q2 the honest path bandwidth-bound at row-sized access, GPU wall pJ per byte moved <= 99 / 57 / 33 against X7's GDDR7 board /
HBM3 / near-memory rows; Q3 the instance above the declared SRAM ceiling for the graph's low-space schedule (log2 N x M_SRAM / C
for DRSample); Q4 composed losses under 2x with the lemma to change per loss; Q5 B2's template cap. Rows R-Q2 (the kill test),
R-Q3 (the panel's M_SRAM), R-Q4 (B4). NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:52:08 +00:00
igneum-labs
28012e97f8 Merge ci-tv02-batch 017c1b5e into master (gate: green on b70b27b8, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:51:36 +00:00
igneum-labs
017c1b5e84 Merge master 6c063f629 into ci-tv02-batch under the master-landing lock 2026-10-09 09:51:32 +00:00
igneum-labs
6c063f6296 Merge mhpow-b2 757c7296 into master (gate: green on 8dd7f281, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:49:46 +00:00
igneum-labs
757c729661 Merge master b67b89cf8 into mhpow-b2 under the master-landing lock 2026-10-09 09:49:43 +00:00
igneum-labs
ee98e45302 relay clients: the task's account domain is the machine name on a workgroup box
Over ssh on a workgroup box USERDOMAIN reads WORKGROUP and schtasks refuses the task's UserId with "No mapping between
account names and security IDs" (the Windows canary VM, 9 October 2026). The machine name is used there, and whenever
the domain\user pair does not translate to a SID.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:49:11 +00:00
igneum-labs
b67b89cf8c Merge mhpow-b4 3f8982ed into master (gate: green on 51ab950a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:48:34 +00:00
igneum-labs
3f8982ed3d Merge master 02d2ce5f8 into mhpow-b4 under the master-landing lock 2026-10-09 09:48:30 +00:00
igneum-labs
390fbd8de9 Merge build/master into 1p5x-x4 (X4 landing, second) 2026-10-09 09:47:35 +00:00
igneum-labs
02d2ce5f8c Merge guard-band 86eb0a8d into master (gate: green on 55e9e70d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 09:47:16 +00:00
igneum-labs
86eb0a8d6c Merge master e601547ae into guard-band under the master-landing lock 2026-10-09 09:47:13 +00:00
igneum-labs
c03439533c Track B recorded as BOUND and NOT RUN rows: B2's binding batch (model:mhpow-b2-binding on POW-05 and POW-06) and B4's composed-theorem batch (theory:mhpow-b4 on R15-07) recorded as the lanes wrote them, plus the steward's R15-07 row (theory:r15-07-track-b) carrying B4's bound (no 1.5x certificate from the published constants) and B2's O-07 finding, no pass or fail claimed; the three cells carried in the batches (map_cell_requested); the harness map page regenerated
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:46:46 +00:00
igneum-labs
f0e4372988 Merge box/master 0b8b8d094 into mhpow-b1-land (the export list both ways under rule 26)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:45:34 +00:00
igneum-labs
e601547aec Merge x2-1p5x-landing b458f3d2 into master (gate: green on 468918c9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:45:32 +00:00
igneum-labs
45e09729ae D02: fee dependence in TV-04's frame, TV-04 emission reconciled (52 rows exact); rows move with the README (batch -03 supersedes -02)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:45:31 +00:00
igneum-labs
b458f3d2a0 Merge master 0b8b8d094 into x2-1p5x-landing under the master-landing lock 2026-10-09 09:45:28 +00:00
igneum-labs
382d5a375a mhpow B3 (R15-06): GPU adaptation of the MTP/DRSample MHPoW, control rows
CUDA labelling, Merkle commitment and proof creation for B1's reference
encoding (BLAKE2b-256, tags L/M/C/G) and the lane's SHA-256 control
reading, batched at 32/128/512 MiB per instance on a rented RTX 5090 and
RTX 4090 (stock clocks, board power at 1 Hz, idle not subtracted). The
C port reproduces B1's five known-answer fixtures byte for byte; the GPU
matches on every checked instance; every GPU proof is accepted; the
known-failed test (DRSample long edges deleted) fires. Finding: the
card is caught in the per-instance chain trap (52 to 87 one-thread CPU
instances at 32 MiB, 3.5 to 5.8 at 512 MiB). Registry batch NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:45:22 +00:00
igneum-labs
2ca9029f92 Counter ASIC 3.0 status: TV-04's second cut and D02's second version, the build-1 guards, the founder's blocks on the explorer, the 10:35 per-box line, X7's chip side (s) and kit, X5's first row, the reset's fault and the re-roll of 30 boxes, the PCs mining, the mini's protoc, main's Track B pivot and the founder's clocks, B1's attack fixtures, B3's oracle on B1, B2's obligations landed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:44:41 +00:00
igneum-labs
0b8b8d0944 Merge class-v6-adversary-docs-7 f8077063 into master (gate: green on 42c21869, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:44:18 +00:00
igneum-labs
b70b27b8f4 TV-02 recorded: the two independent supply replays (A on the node issuance code, B from the rules in words) EQUAL to the integer on devnet-4, mainnet and the TV-01 spec, NOT RUN in progress until the independent panel reads it; the cell native:tv-02 carried in the batch (map_cell_requested), the lane's proposed batch recorded as tools/ci/batches/tv-02-20261009-01.json
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:44:15 +00:00
igneum-labs
f8077063ab Merge master 4a80303a2 into class-v6-adversary-docs-7 under the master-landing lock 2026-10-09 09:44:15 +00:00
igneum-labs
0f79872e0d D02: the stretch sweep reads 4x and 10x; B's 1x edge stated
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:44:08 +00:00
igneum-labs
4a80303a22 Merge 1p5x-x1-docs f5e278bd into master (gate: green on 8078c023, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:43:08 +00:00
igneum-labs
f5e278bd4d Merge master 10f91159c into 1p5x-x1-docs under the master-landing lock 2026-10-09 09:43:04 +00:00
igneum-labs
efa188419c D02: a quote in the fee-series line
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:42:45 +00:00
igneum-labs
10f91159c8 Merge b6-verification-budget-2 425eb91a into master (gate: green on 4182e2be, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 09:42:08 +00:00
igneum-labs
425eb91aa4 Merge master 858a2b395 into b6-verification-budget-2 under the master-landing lock 2026-10-09 09:42:05 +00:00
igneum-labs
b13a804368 D02: fee dependence in TV-04's frame (one BU, the 0.1x to 10x multiples); TV-04's emission reconciled
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:41:48 +00:00
igneum-labs
8dd7f281c6 mhpow B2: O-07 cites B1's executed re-roll fixture A6
B1's fixture A6 (attacks-n10-k16.json 805035eb, mhpow-b1 29d7bfebd) runs the O-07 counter-example: one
labelling, a red sink, 26 calls a try, 193 to 200 of 200 tries accepted by the full verifier, matching
(1 - 2^-10)^16. The row now says the paper's bound holds once per trace, not once per certificate.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:40:07 +00:00
igneum-labs
858a2b395c Merge ca3-coord-record bb0ffacd into master (gate: green on d74bf816, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:39:55 +00:00
igneum-labs
bb0ffacddd Merge master 490ef1fb8 into ca3-coord-record under the master-landing lock 2026-10-09 09:39:52 +00:00
igneum-labs
51ab950a38 mhpow B4: the lottery draw as the composed statement's first obligation (B4-OB-LOT), the control in the head as BOUND (L)
Section 5b: why the naive root lottery fails in the composed statement's terms (B4 Lemma C, the sink re-roll: one trace, one cmc
bound, log2 N + 1 queries per draw, accepted with probability (1 - 1/N)^k, 0.9946 at log2 N = 22), what a draw must cost (a fresh
labelling, phi = 1), the construction change (trial id in chi, v = H(tag_lot, chi, tau), full verification of winners, spot checks
as the pre-filter) and its effect on the losses (L2 and L10 removed for winners, L11 open for terms 2 and 3, the generic route
0.151 -> 0.213, the red-blue route unchanged). Rows B4-OB-LOT and -1 to -4 taken by name (B2, B1, B4, B6). params.py section 8.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:39:03 +00:00
igneum-labs
490ef1fb89 Merge tv-d02 b74e04f6 into master (gate: green on 9ffffc40, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:38:38 +00:00
igneum-labs
b74e04f6f5 Merge master c0b97150f into tv-d02 under the master-landing lock 2026-10-09 09:38:35 +00:00
igneum-labs
29d7bfebd1 B1 (R15-05): the published MTP/DRSample primitive reproduced, with its complete verifier and fixtures
Blocki and Smearsoll (eprint 2025/1456 as archived, sha256 13c3646e...) Sec 2.2, 3.2 and App. C over
DRSample (ABH17 Alg. 1, eprint 2017/443 as archived): CPython reference in tools/mhpow/b1 (params, drsample,
mtp, attacks), the verifier's named checks in the paper's order with a known-failed test each (17 of 17 OK
on build-6), five deterministic known-answer fixtures (n 4 to 20), honest rows n 12 to 24, the malicious
provers A1 to A6 (Dinur-Nadler eprint 2017/497 Sec 4.1, 4.3/5, 8; the paper's Attack 1; the LuckyQuery
regrind) and the k table. Encoding pinned with B2 (BLAKE2b-256, tags L/M/C/G, u64 LE, raw leaves,
LSB-at-root, public graph seed). Findings: proven k with ABH17's constant exceeds N to about n 25 (F-3);
one labelling yields many accepted roots (F-4); lambda 256 meets Lemma 3 only for q <= 2^31.5 (F-5).
Research paths added to tools/ci/export-exclude.txt beside B2's. Registry batch NOT RUN for the steward.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:38:00 +00:00
igneum-labs
c0b97150f5 Merge mhpow-b4 ebf95e9d into master (gate: green on 7eaaa9f2, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:37:14 +00:00
igneum-labs
42c2186987 1.5x X7, the chip side: s on GDDR7, HBM3 and near-memory for the frozen object's traffic (WITNESS rows), the bridge reading, the BLOCKED rows, the batch NOT RUN
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary 85db138c1 over master acd67a116: docs/analysis/class-v6/1p5x/x7/README.md (X7's chip side, the s rows) and the batch adversary-20261009-x7 recorded at this manifest (NOT RUN, method model, cell adversary:x5-sweep); tools/1p5x stays on the branch.
2026-10-09 09:37:12 +00:00
igneum-labs
ebf95e9d9f Merge master acd67a116 into mhpow-b4 under the master-landing lock 2026-10-09 09:37:11 +00:00
igneum-labs
55e9e70d30 memory guard: the syncing band is 100 blocks and a unit in its first two minutes without an RPC answer is not counted (the seed's reopen restart at 10:32 UK was read as a second sync and the hand was refused once).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:36:15 +00:00
igneum-labs
468918c98e X2: run-prod-then-pairs.sh, the campaign script the README cites (the text as it ran on the pod)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:35:56 +00:00
igneum-labs
bd5e9cb203 X4 (1.5x): the registry batch beside the README for the steward (its cell is not in the map)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:35:50 +00:00
igneum-labs
acd67a1160 Merge igneum-1p5x-programme-pdf-docs a36f9863 into master (gate: green on 2af00493, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:35:50 +00:00
igneum-labs
a36f986364 Merge master 4fb77ea8d into igneum-1p5x-programme-pdf-docs under the master-landing lock 2026-10-09 09:35:47 +00:00
igneum-labs
8078c02399 1.5x X1: the batch names its evidence files (a directory citation is refused)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:34:41 +00:00
igneum-labs
4fb77ea8dd Merge x2-1p5x-landing ee5582a5 into master (gate: green on 12354ed3, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:34:33 +00:00
igneum-labs
ee5582a561 Merge master cb524ca6e into x2-1p5x-landing under the master-landing lock 2026-10-09 09:34:30 +00:00
igneum-labs
cb524ca6ed Merge mhpow-b2 bbaa1131 into master (gate: green on dcde61b9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:33:18 +00:00
igneum-labs
bbaa1131b8 Merge master 206e73f70 into mhpow-b2 under the master-landing lock 2026-10-09 09:33:15 +00:00
igneum-labs
d74bf8167b Counter ASIC 3.0 status: main's clock withdrawal and two words, the hidden Vast pods, the tracker at 37 of 101, PC 1 mining, the mini's worker fault read, the 2.0.3 app line and the DMG default, X7 dispatched, Track B's first results (B1 fixtures, B3 timing, B4's statement, B6's table), TV-02 final
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:31:05 +00:00
igneum-labs
4182e2be13 B6 (R15-10): the B1 lane's reference values (10:27 UK) in the verification budget table: n = 20, k = 64, 32-byte labels, three openings a challenge; proof bytes 45 + k(1 + 96(n + 1)) = 129,133 measured; the verifier's k(3n + 2) + 2k = 4,096 BLAKE2b calls; build-7's measured BLAKE2b rate 245 ns a call gives about 1.0 ms a proof cold on one core (0.1 percent of a core at 1 bps, 1 percent at 10 bps); and the row that decides the shape: the paper's Corollary-2 k of about 2.9e7 at n = 20 puts a proof near 56 GB, 200 times the 256 MiB message limit and 7.5 minutes a core to verify — the block-carried proof is BLOCKED on k (the B1 lane's row O-1). Every verdict NOT RUN
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:30:45 +00:00
igneum-labs
206e73f70e Merge build-1-guards a88c3a83 into master (gate: green on 27efd573, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 09:29:53 +00:00
igneum-labs
a88c3a836a Merge master 2a6fc6f41 into build-1-guards under the master-landing lock 2026-10-09 09:29:50 +00:00
igneum-labs
7eaaa9f257 mhpow B4: name the open rows of the loss table by their section 6 items
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:28:55 +00:00
igneum-labs
2a6fc6f411 Merge tv-04-security-budget fdec16ef into master (gate: green on b12ae3ae, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:28:45 +00:00
igneum-labs
fdec16efaf Merge master 0f6bbf0b5 into tv-04-security-budget under the master-landing lock 2026-10-09 09:28:41 +00:00
igneum-labs
9ffffc40c2 D02: the registry rows move with the README (batch tv-d02-20261009-02 supersedes -01)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:28:16 +00:00
igneum-labs
add70b655e Merge master into mhpow-b4: keep B2's and B4's export-exclude lines (rule 26)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:27:59 +00:00
igneum-labs
3eda463681 Merge master 0f6bbf0b5 into tv-d02 under the master-landing lock 2026-10-09 09:27:54 +00:00
igneum-labs
2af0049332 docs/plans/igneum-2.0-master/1p5x/research-plan: the typeset edition of the research programme (IGNEUM 2.0 / Hardware Research: 1.5x, 21 pages, 9 October 2026) beside the markdown, named in the README with its sha256
On main's word through the coordinator, documents only: the same twelve sections as the plan's markdown; the reading rule, typeset
from the 9 October plan, no new hardware result, proof audit or P04 certification. sha256 8bd4cf9fb4b0de4e9f888ce6a98456fd09ed49607ca8ff461691a53a6f128f09. No chain path; no served page.
2026-10-09 09:26:39 +00:00
igneum-labs
0f6bbf0b54 Merge ca3-coord-record 0c054a41 into master (gate: green on 19506c03, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:26:32 +00:00
igneum-labs
0c054a41de Merge master b0817ca23 into ca3-coord-record under the master-landing lock 2026-10-09 09:26:29 +00:00
igneum-labs
bc8cf9cc42 1.5x X1: the harness map page regenerated for the experiment:1p5x-x1 cell
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:26:26 +00:00
igneum-labs
adcb41922f Merge build/master into 1p5x-x4 (X4 landing)
# Conflicts:
#	tools/ci/export-exclude.txt
2026-10-09 09:26:01 +00:00
igneum-labs
12354ed3ab X2: the registry batch moves to tools/1p5x/x2 for the steward (method GPU, evidence by file); the landing writes no registry row
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:25:54 +00:00
igneum-labs
84a34569e7 X4 (1.5x): the replicate 4090 session (g 0.960 / 0.959 / 0.969, A/A 0.15 percent)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:25:43 +00:00
igneum-labs
b0817ca235 Merge class-v6-adversary-docs-6 c664ccae into master (gate: green on 09e1906f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:25:30 +00:00
igneum-labs
c664ccae20 Merge master e14e6c236 into class-v6-adversary-docs-6 under the master-landing lock 2026-10-09 09:25:27 +00:00
igneum-labs
dcde61b99c mhpow B2: re-cut to the B1 lane's encoding pins (unkeyed BLAKE2b-256, u64 indices, graph tag)
The B1 reference (R15-05) pinned the primitive's encoding at 10:2x UK; B2 adopts it whole: unkeyed
BLAKE2b with a 32-byte digest, lambda 256, one ASCII role byte per query kind (L, M, C, G; I stays B2's),
u64 LE integers, raw-label leaves with the LSB-at-root path, no path sharing, DRSample drawn from
'G' || graph_seed. The personalisation and the u32/u16 indices of the first cut are gone. Figures re-run on
build-9 (generator 7b8664ea, output 27bb414c); Appendix C now read and cited.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:25:23 +00:00
igneum-labs
e14e6c236e Merge tv-02-supply-replay 19e9c2a0 into master (gate: green on efe5fad4, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:24:16 +00:00
igneum-labs
19e9c2a02c Merge master e8b084c64 into tv-02-supply-replay under the master-landing lock 2026-10-09 09:24:13 +00:00
igneum-labs
e8b084c64f Merge mhpow-b2 15bbcf17 into master (gate: green on 7638774f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:23:06 +00:00
igneum-labs
15bbcf1746 Merge master 233110649 into mhpow-b2 under the master-landing lock 2026-10-09 09:22:56 +00:00
igneum-labs
2331106498 Merge queue-memory-rule c5650e67 into master (gate: green on f53e5058, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 09:21:50 +00:00
igneum-labs
c5650e67df Merge master 52ed677d4 into queue-memory-rule under the master-landing lock 2026-10-09 09:21:47 +00:00
igneum-labs
b12ae3ae9b TV-04 second cut: the registry row moves with its evidence (batch tv-04-20261009-02, superseding -01, NOT RUN, through tools/ci/test-record.mjs --record)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:21:05 +00:00
igneum-labs
13d0e1b5d8 Merge master 52ed677d4 into tv-04-security-budget under the master-landing lock 2026-10-09 09:20:44 +00:00
igneum-labs
4bb3c804ca D02: reconciled with TV-01's supply spec (32 rows exact), the paid model at 10 blocks/s, B1 and B4 closed
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:19:38 +00:00
igneum-labs
52ed677d4a Merge ci-tv01-mapcell 7dc1529a into master (gate: green on 7341f67a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:19:25 +00:00
igneum-labs
7dc1529add Merge master e9b6256e1 into ci-tv01-mapcell under the master-landing lock 2026-10-09 09:19:21 +00:00
igneum-labs
d27064242f mhpow B4 (R15-07): the composed accepted-proof energy statement, its losses and the encoded-state answer (NOT RUN)
Track B item B4, documents only. docs/analysis/mhpow/b4/README.md: the pROM model and the MTP/DRSample construction exactly as
Blocki-Smearsoll TCC 2025 (eprint 2025/1456, full PDF sha256 13c3646e...) states them, its theorems and constants with numbers
(Thm 4 to 7, Cor 1 to 3, Lemma 5, Fact 8), the composed three-term statement (hashing, transfers, retention) with the status of
each term, what the 2024 bandwidth paper (2018/221, 2a466b97...) and Ren-Devadas (2017/225) give, what is new, the reduction-loss
table (generic route at most 0.151 of honest energy at log2 N = 22; red-blue route at least 256/(1-rho) loss), R4's encoded-state
question as BLOCKED row B4-B07, the quantum sentence, ten BLOCKED rows and the obligations for B2 and B1 by row.
tools/mhpow/b4/params.py (closed-form arithmetic, standard library) ran on build-9; params.txt is its output; RUNS.md the runs;
registry-batch-b4.json one NOT RUN cell for the steward, not recorded. Research paths added to tools/ci/export-exclude.txt.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:18:47 +00:00
igneum-labs
89652f973f D02: section 9 wording
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:18:34 +00:00
igneum-labs
19506c03a7 Counter ASIC 3.0 status: RESET END (22 of 101 within ten, the three hubs one chain), build-1's OOM and the Caddy outage, the hub-1 archive done, TV-01's complete spec and TV-02's agreement, X0's amendment 5b (the board 2.35x at the knee, the die 7.8x), X1's, X2's and X4's GPU rows, B2's input spec, B4's papers, the clock fact
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:18:24 +00:00
igneum-labs
e9b6256e10 Merge b6-verification-budget 71327998 into master (gate: green on 71327998, recorded by tools/ci/pre-push.sh; landed on the box mirror): B6 (R15-10), the verification budget table, documents only
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:18:19 +00:00
igneum-labs
950e104e11 1.5x X1: fixed-window removal as the class v7 shape (+flat on 1p5x-x1-v7 a04b99391): the README with every row (census, live traces, cache-hit curves, GPU pairs, native correctness, generation), the tools, the test-map cell experiment:1p5x-x1 and the NOT RUN batch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:18:18 +00:00
igneum-labs
09e1906fa7 1.5x X0 amendment 5b: the frozen object's own numerator, the instruction count (the counted-op unit closed as the GPU's micro-op tally), the measured hits, stock and knee, both nodes, the wall term; the board 2.35x same-node at the knee, above 1.5x by 0.85x
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary 14939909a over master d7a1bcb24: the X0 README with amendment 5b, the X5 README with both pairs at both counts, multi-family-adversary.md's section 17; the cell adversary:x5-sweep on master's map; the batches adversary-20261009-x5 and adversary-20261009-placed-32lane recorded at this manifest (no decision changed); tools/1p5x and tools/chip-model/mf stay on the branch.
2026-10-09 09:17:27 +00:00
igneum-labs
27efd57303 build-1 guards (the coordinator, 9 October 2026, after the 09:54 OOM): the queue reader as a unit, a memory guard every minute (one fresh sync at a time by unit; free memory under 15 GB alerts), an edge check every five minutes (the workers page, the git host, /light; a failed caddy started again), Restart=always and the OOM order on caddy, cron, atd, rsyslog and the reader (last in line) and on the three sync units (first in line); install.sh runs on the box from the mirror.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:17:18 +00:00
igneum-labs
efe5fad437 TV-02 README: the TV-01 spec landed on master at fefb00d40 byte-identical to the copy B ran on (sha256 3ffdd308...), so R1 stands on the landed spec; R8 names the spec's C06 to C08 for the EVM ledger
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:17:12 +00:00
igneum-labs
e98db130e9 D02: the paid model and the exact reconciliation with TV-01's supply spec
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:17:06 +00:00
igneum-labs
cec5031b72 Merge ci-r15 af2fe220 into master (gate: green on aea0e375, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:17:00 +00:00
igneum-labs
af2fe22010 Merge master d7a1bcb24 into ci-r15 under the master-landing lock 2026-10-09 09:16:57 +00:00
igneum-labs
dd314b6e6c X2 (1.5x): serving-mode result compaction on the frozen control, equivalence and 4090 rows
The compaction is the CUDA worker's select pass already in db36d8060 (review B F10, default on);
no worker, consensus, generator or Cargo change. Equivalence: --readback select = --readback full =
the CPU references, byte for byte, on the three same-work contexts (every nonce of [0, 3 x 2^20) at
all-ones across the day switch, a 1,048,576-nonce fuzz set per context with the 8,192-nonce boundary
block, the 256/257 overflow edge, target 0 and the <= edge), the counter-reset fault flagged first.
4090 at stock, 4 ABBA pairs: rate +9.9 percent, g 0.971 against the full path, 1.0015 against the
kernel timer (the yardstick). Finding X2-F1: identical work twice in a row trips the stale-output
detector (exit 3) on both paths. Wall power BLOCKED, the knee NOT RUN, registry batch NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:16:23 +00:00
igneum-labs
d7a1bcb24c Merge tv-02-supply-replay 2fd7d3d3 into master (gate: green on 22a4f326, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:15:47 +00:00
igneum-labs
2fd7d3d327 Merge master dc22df3ff into tv-02-supply-replay under the master-landing lock 2026-10-09 09:15:44 +00:00
igneum-labs
7638774fc2 mhpow B2: the binding spec for the Track B work unit (instance layout, obligations O-01 to O-16)
The canonical instance input (328 bytes, work version 1, draft): network id, chain id, header and work
versions, the dataset policy digest, the program id, the epoch, era and day the frozen class carries, the
state root, the pre-PoW header hash (parents, coinbase root, DAA score, timestamp), the 64-bit nonce as trial
id, the graph parameters. The obligations read against Blocki and Smearsoll, eprint 2025/1456 (full PDF,
sha256 13c3646e): reuse answered per input; two lottery rules FAIL with counter-examples (sink re-roll,
free screening); the replacement, multi-instance, adaptive input, constants and energy BLOCKED to B4 and
the node lane. Figures from tools/mhpow/b2/b2_figures.py on build-9. Registry batch NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:15:09 +00:00
igneum-labs
f53e505811 build queue: the build-1 memory rule (one fresh sync at a time with its listener on loopback until within ten, one read node at most) and the reader's 90 percent memory fault, after the OOM of 9 October 2026.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:15:00 +00:00
igneum-labs
dc22df3ff4 Merge ca3-coord-record 34bad6a8 into master (gate: green on 6ebce745, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:14:44 +00:00
igneum-labs
34bad6a83c Merge master ea339095c into ca3-coord-record under the master-landing lock 2026-10-09 09:14:41 +00:00
igneum-labs
ea339095c3 Merge igneum-1p5x-research-plan-docs 522f9423 into master (gate: green on 0d316383, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:13:43 +00:00
igneum-labs
522f94238d Merge master 125e16c3d into igneum-1p5x-research-plan-docs under the master-landing lock 2026-10-09 09:13:40 +00:00
igneum-labs
7ee751ada7 TV-04 second cut: the run record
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:12:36 +00:00
igneum-labs
7341f67a37 A batch may carry the map cell it needs (map_cell_requested: added when absent, refused when it would change an existing cell or names an unknown case); TV-01's batch recorded with its cell token-value:tv-01 (NOT RUN in progress)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:12:32 +00:00
igneum-labs
1f28f11434 TV-04 second cut: regenerated on build-9 from a1912456
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:12:18 +00:00
igneum-labs
125e16c3d4 Merge page-canary 912faa25 into master (gate: green on 4d59b2b5, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 09:11:51 +00:00
igneum-labs
912faa25cf Merge master fefb00d40 into page-canary under the master-landing lock 2026-10-09 09:11:49 +00:00
igneum-labs
a1912456cc TV-04: the terminal year read as TV-01 states it (zero from the start of year 125)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:11:48 +00:00
igneum-labs
80d90e20a0 TV-04 second cut: the documents regenerated on build-9 from e1a35bb3 against the landed TV-01 spec (27 of 27 checks agree), the batch tv-04-20261009-02 superseding -01
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:11:33 +00:00
igneum-labs
7132799897 B6 (R15-10): the verification budget of a proof-carrying memory-work unit as a parameter table against the node's limits (documents only; the node lane, 9 October 2026, 10:1x UK): proof bytes per block, cold verification time on the hub-class box (build-7's measured single-core SHA-256 rate: 6.8 M 64-byte hashes a second) and on the minimum node (undefined, BLOCKED), invalid-proof amplification against the PoW strike guard (2 per hour), ledger N6 (3,600 s window, 600 s ban), the class v5 state wait and the fd class closed this morning, the pool's share check (one bound hash today, verify.rs 52), propagation against the 256 MiB message limit, the block time and the epoch wall; every B1 value a BLOCKED row named by its symbol; every verdict NOT RUN
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:11:26 +00:00
igneum-labs
f2b7b202ac the harness map page regenerated 2026-10-09 09:11:10 +00:00
igneum-labs
bf2e63a7c8 1.5x X0 and X5: the two consistent pairs (class v4 at 128 loads and the card 2.319; the frozen class v6 object at 256 loads and the card 4.011), the pair-B rows (the die 4.0x same-node the worst credible design), the B5 full-SRAM row on one reticle, X4's corrections in section 17
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary b54f8519c over master fefb00d40: the X0 and X5 documents, multi-family-adversary.md (section 17's X4 corrections), the cell adversary:x5-sweep on master's map and the batch adversary-20261009-x5 recorded at this manifest; tools/1p5x and tools/chip-model/mf stay on the branch.
2026-10-09 09:11:10 +00:00
igneum-labs
e1a35bb365 Merge branch 'master' of 188.40.146.49:/srv/igneum into tv-04-security-budget 2026-10-09 09:10:42 +00:00
igneum-labs
fefb00d40e Merge tv-01-supply-spec b7402e9a into master (gate: green on 92af6c89, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:09:52 +00:00
igneum-labs
b7402e9ac8 Merge master 4c84394e3 into tv-01-supply-spec under the master-landing lock 2026-10-09 09:09:49 +00:00
igneum-labs
22a4f32634 TV-02 on the TV-01 supply spec: B replays from the spec's own numbers and agrees with A to the integer on devnet-4 and mainnet and on both reorg fixtures
The spec (supply-spec.json at tv-01-supply-spec 92af6c89, sha256 3ffdd308...) is mapped to B's rules by
tv01_adapter.py, which refuses any rule it cannot map; B now reads a stated integer launch rate and Q32 step
multiplier. Byte-identical CSVs to A's (6ede4f4a..., 3cf7f426...), the 66 and 63 transitions, both fixtures equal to
the hand-written integers with the no-undo ledger refused, and A's terminal rows equal to the terminal supplies the
spec states. README: the spec rows, R1 to R4 updated (the spec states the genesis rule and the per-block order), R10
the mainnet genesis DAA score (C09). The registry batch carries the spec run.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:09:00 +00:00
igneum-labs
4c84394e35 Merge hash-registry-1 b0ec7fa0 into master (gate: green on 11fad85b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:08:50 +00:00
igneum-labs
b0ec7fa02a Merge master 197a7fe39 into hash-registry-1 under the master-landing lock 2026-10-09 09:08:46 +00:00
igneum-labs
6119101016 X4 (1.5x): the reg64c forms' equivalence verdicts, the 4090 pairs, the chip rows and the arithmetic; the differential, the pod script and the generators under tools/1p5x/x4; the registry batch NOT RUN
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 09:08:29 +00:00
igneum-labs
197a7fe39d Merge tv-02-supply-replay b87db306 into master (gate: green on b87db306, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:07:48 +00:00
igneum-labs
aea0e3751d The R15 suite of the acceptance registry: the ten packages of the 1.5x Research Programme (every one NOT RUN, the gate verbatim, the owner capability and artefact, the X and B lanes as cross-references), the two rules in the suite's note (WITNESS or BOUND on every chip figure; no raw hashes-per-second comparison without an approved equivalence); generated by tools/ci/r15-suite.mjs, regenerated at the merge, checked in the gate
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:07:39 +00:00
igneum-labs
6ebce7459e Counter ASIC 3.0 status: the founder's research plan and Track B fanned out (B1 to B6), X1's census, traces and hit curves (the window concentration 56 to 61 percent, not 72), X0's decider (class v6 costs the 5090 1.75x class v4) and its op-count band, X3's flat grid, X4's first GPU row, the stale-sink class closed on the moving chain, build-1's OOM, the Windows canary by KVM, the reset after wave two
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:06:47 +00:00
igneum-labs
2671566a9c TV-04: B-05 names every missing number
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:06:28 +00:00
igneum-labs
0d3163838e docs/plans/igneum-2.0-master/1p5x/research-plan: the Track B lanes B1 to B6 with owners and clocks as the coordinator names them, the Track B rules in the README's head, the lanes block in packages.json 2026-10-09 09:06:10 +00:00
igneum-labs
e922daaf52 TV-04: V* per unit of the missing capacity; the cost side in the result's meaning
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:06:04 +00:00
igneum-labs
2477aa7ab5 TV-04: the node lane's answers (10:06 UK): hub rate measured, the minimum hub count and committed maintenance BLOCKED by name, the devnet's three hubs and the build server as labelled partial rows; C10, C01, C12 confirmed by line, C04 for the founder
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:05:29 +00:00
igneum-labs
f4d0ac2428 docs/plans/igneum-2.0-master/1p5x/research-plan: IGNEUM, The 1.5x Research Programme (9 October 2026) with its arithmetic package, packages.json and README; the master's 1p5x line names both documents
On main's word through the coordinator, documents only: the plan (sha256 269ceaa5...), check_arithmetic.py, arithmetic_results.json
and manifest.json from the package (the zip's sha256 c873ac9d... recorded, the zip not landed), packages.json (the ten R15 packages
in machine-readable form for the registry's R15 suite, the X and B cross-references this landing's reading for the coordinator
to confirm), and the README (the two tracks and the gated third, witness versus bound, the 1.25x internal goal, the packages,
the stopping rules; the B lanes to be named). The plan claims no pass. No chain path; no served page.
2026-10-09 09:03:44 +00:00
igneum-labs
b87db3066a Merge master 76ee67d8f into tv-02-supply-replay under the master-landing lock 2026-10-09 09:02:19 +00:00
igneum-labs
76ee67d8fe Merge ca3-coord-record 70706d6b into master (gate: green on 00b3ed5e, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 09:01:25 +00:00
igneum-labs
70706d6b39 Merge master 8b1fc3815 into ca3-coord-record under the master-landing lock 2026-10-09 09:01:21 +00:00
igneum-labs
8b1fc38156 Merge ci-tv-d02 80a760ca into master (gate: green on 0e88a016, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 09:00:20 +00:00
igneum-labs
80a760ca47 Merge master 5fbafe632 into ci-tv-d02 under the master-landing lock 2026-10-09 09:00:16 +00:00
igneum-labs
11fad85ba7 test registry: the hash lane's batch 5 (X0 decider: class v6 over class v4 on one rented 5090, 1.78x to 1.84x joules per hash at stock)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 09:00:01 +00:00
igneum-labs
4d59b2b5a5 workers page and the build queue: a card with no report yet reads so (the Windows canary before its first post); build-7 shared by the node lane and the relay lane with the standing Windows canary VM as entry 11.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:59:22 +00:00
igneum-labs
5fbafe632d Merge canary-202 4b50eeda into master (gate: green on a4acf96d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:59:17 +00:00
igneum-labs
4b50eeda8a Merge master 9369f5e2e into canary-202 under the master-landing lock 2026-10-09 08:59:14 +00:00
igneum-labs
92af6c8901 TV-01 complete: the node lane's three lines, the litepaper re-pinned to master ef35a0d1, four node revisions anchored
C10 now names both 80/20 rules (the subsidy's 20% to the proving escrow; the tip's 80% to the miner alone, O-5.7
closed at zero) and the unmerged 90% proving-fee route; the litepaper's 'miner and provers' (lines 614, 622) is
superseded. C12 names the 1% tail as testnet-1's own approved genesis schedule (ledger E22), testnet-only. C01
records the site lane's rewrite at 57dfdbac4 beside the superseded sentence quoted at 2b65c985. Every cited node
line is anchored at a284380b, 5d53a591, bf60948a and 27f54124. The mainnet profile is named the contract. The Rust
dump program is kept as .rs.txt (it builds only inside the node tree, never in this repository).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:58:14 +00:00
igneum-labs
9369f5e2e1 Merge same-work-harness 3e5432d2 into master (gate: green on 86ce7ce5, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:57:42 +00:00
igneum-labs
3e5432d244 Merge master df71118c9 into same-work-harness under the master-landing lock 2026-10-09 08:57:10 +00:00
igneum-labs
df71118c93 Merge igneum-1p5x-brief-docs 4169b4b7 into master (gate: green on cc6ad7b5, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:56:08 +00:00
igneum-labs
4169b4b750 Merge master b222be3d3 into igneum-1p5x-brief-docs under the master-landing lock 2026-10-09 08:56:05 +00:00
igneum-labs
b222be3d3a Merge ci-records-per-run ab7e0c07 into master (gate: green on efbf6317, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:55:05 +00:00
igneum-labs
ab7e0c0738 Merge master ef35a0d1b into ci-records-per-run under the master-landing lock 2026-10-09 08:55:01 +00:00
igneum-labs
48fd4e048c workers page and the build queue (the coordinator, 9 October 2026 09:5x UK): a rig card reads "agent not reporting since <time>" until a report arrives through the intake; the queue names both owners on build-2 (the site lane and the adversary lane, neither ending the other's pid), the TV-02 lane on build-5, and main's 15-minute rule (an idle box unclaimed by its owner is marked open to any lane; 30 minutes idle is a red on the board).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:53:10 +00:00
igneum-labs
00b3ed5e81 Counter ASIC 3.0 status: the workers page published clean, the 09:49 per-box read and the idle-box rule, the seed and hand on the hubs' chain, main's Windows canary VM decision, the stale-sink fix read on the moving chain, X2's equivalence
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:53:04 +00:00
igneum-labs
98a556b19c /acceptance count: computed in the site build from the registry it already guards; the share text carries no count; pages.mjs no longer reads outside site/ (the master gate builds the site in a temporary copy of site/ alone, and the import broke it)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:52:46 +00:00
igneum-labs
437d561072 TV-04: the fleet lane's measured operator costs (09:50 UK) by class; V is the panel's cell
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:52:03 +00:00
igneum-labs
926c0f3335 TV-04: the cost side (USD cost inputs by role and class, missing inputs named), the coverage formula over V and the reference value V* (the coordinator's ruling, 10:0x UK), VR-04's sentence at the head
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:51:16 +00:00
igneum-labs
2f207c2056 Counter ASIC 3.0 status: main's boxes-first and house-rigs rulings, X0's reconciled r0 and X5's first rows (the SRAM die 2.44x retained), X1 cut (class v7 +flat), the Metal PASS, D02, the monetary conflicts answered, the PCs' state, the hand restart, the mini's reboot leg PASS on the moving chain, X4's equivalence, the Token Value re-clocks
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:50:47 +00:00
igneum-labs
2323986c66 Merge master ef35a0d1b into tv-01-supply-spec under the master-landing lock 2026-10-09 08:49:56 +00:00
igneum-labs
ef35a0d1bb Merge page-identity d21e8a5a into master (gate: green on 99f23006, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:48:52 +00:00
igneum-labs
d21e8a5a4d Merge master 03a13ceaa into page-identity under the master-landing lock 2026-10-09 08:48:48 +00:00
igneum-labs
bb508a9a19 TV-02: the registry batch moves beside the README (registry-batch-tv-02.json, the proposed cell native:tv-02) for the CI steward to record, as TV-04's did; the merge's replay refused a cell not yet on the map
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:48:29 +00:00
igneum-labs
a4acf96dcf Rule 33 record 1176efb9: the mini's reboot leg PASS (09:45 UK, back by itself in 71 s, every service under launchd, mining on the moving reference chain at 09:47); the tip feed and the collector under launchd; the batch re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:48:20 +00:00
igneum-labs
03a13ceaa4 Merge agent-watchdog 79b80c89 into master (gate: green on 56157f5d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:47:47 +00:00
igneum-labs
79b80c891f Merge master 02be991b9 into agent-watchdog under the master-landing lock 2026-10-09 08:47:43 +00:00
igneum-labs
02be991b90 Merge ci-tv04 948c9b92 into master (gate: green on 16eeb01d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:46:41 +00:00
igneum-labs
948c9b9242 Merge master 7b816c638 into ci-tv04 under the master-landing lock 2026-10-09 08:46:38 +00:00
igneum-labs
7b816c6380 Merge canary-202 d55f008b into master (gate: green on 65b76df6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:45:39 +00:00
igneum-labs
d55f008bf1 Merge master 2cdb61cd8 into canary-202 under the master-landing lock 2026-10-09 08:45:35 +00:00
igneum-labs
0e88a01644 TV-01, TV-03 and TV-04 on the D02 emission model cell (model:tv-d02-emission) and its batch tv-d02-20261009-01 recorded: NOT RUN in progress
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:45:24 +00:00
igneum-labs
efbf6317bd The recorder keeps records per (case, cell, run): the latest run is the cell's word, an older run stays as evidence, an older FAIL stands until a batch supersedes it by name (the same-work hand's class); the P01 batch re-recorded so its CUDA evidence returns to POW-01; the token-value generator's write line names the decisions' real statuses
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:44:53 +00:00
igneum-labs
2cdb61cd82 Merge ci-hashes-paths 34edde3c into master (gate: green on ac8c015c, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:44:37 +00:00
igneum-labs
34edde3cda Merge master 06eec5ad8 into ci-hashes-paths under the master-landing lock 2026-10-09 08:44:34 +00:00
igneum-labs
06eec5ad8a Merge tv-d02 6267787b into master (gate: green on a6165fbb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:43:38 +00:00
igneum-labs
86ce7ce5ee same-work: Metal PASS on all three phases of all three contexts (Apple M6, read back on build-1 09:41 UK); the six readers agree on every nonce, harness:same-work turns PASS for R2-F03-R02 and R03 (contexts 02 and 03); 01 stays NOT RUN for POW-01 with the P01 campaign evidence restored on its cell
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:42:45 +00:00
igneum-labs
85b653b3ba /acceptance: the build writes the registry's suite and case count into the page's metas and intro (262 cases in 20 suites), no hard-coded count left
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:41:26 +00:00
igneum-labs
f3f019e334 /acceptance renders the registry's 20 suites (VR, 40 rules; TV, 32 gates NOT RUN): a VR case's requirement and a TV case's procedure fill the steps list; the share text counts suites and cases from the registry (262 in 20); the release manifest under the served-identity guard: its six clock fields read UTC, no zone word in the served file, the OPS-03 cell re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:39:58 +00:00
igneum-labs
e1a910c7fc X4 (1.5x): byte-identical reg64c address-mix forms (direct, generated, prefix) behind --reg64-form and --reg64-cpu-form; the fold stays the definition and the default
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:39:54 +00:00
igneum-labs
56157f5d30 relay clients: the watchdog runs as a 10 s loop at logon; the service loop restarts the agent after 10 s
The founder's bar of 9 October 2026: a killed agent is back within 15 s. IgneumRelayWatchdogLogon now runs watchdog.ps1
-Loop (one check every 10 s for 55 minutes, one loop at a time), the five-minute IgneumRelayWatchdog task checks the
agent and starts the loop again when none runs, and igneum-agent-service.ps1 restarts the agent 10 s after any exit.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:39:48 +00:00
igneum-labs
4a1fcceb1b relay clients: the install clears a stale agent lock on start (ends old agent shells by pid)
9 October 2026, 09:0x UK, both PCs: an agent copy held the mutex but no longer polled (it sat waiting on an app a
task had relaunched), so igneum-agent.bat said "agent already running" and a hand was needed. install-agent.ps1
now ends every shell running igneum-agent.ps1 or igneum-agent-service.ps1 by its pid before it registers and starts
the task, so the bat and the watchdog's re-registration always start clean.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:38:01 +00:00
igneum-labs
6267787bbc Merge master 51edbe9ae into tv-d02 under the master-landing lock 2026-10-09 08:37:58 +00:00
igneum-labs
51edbe9ae4 Merge ci-identity-boxpath 0b22a1b0 into master (gate: green on 521c9465, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:36:55 +00:00
igneum-labs
0b22a1b0d6 Merge master ae48bc4c6 into ci-identity-boxpath under the master-landing lock 2026-10-09 08:36:52 +00:00
igneum-labs
7e7ccc190f TV-01: the genesis rule and the terminal fields TV-02 reads; C10 resolved by O-5.7; the registry batch kept beside the spec
Genesis is never rewarded (window.rs:177, coinbase.rs:139, genesis.rs:26), so block height h carries DAA score h - 1;
each profile now carries transition_count, last_paying_daa_score, last_paying_block_height and terminal_supply
(Devnet 4: 66 transitions, last paying block at height 4,102,488,000, terminal supply 3,963,038,999.610200483289816
IGN), and the checker refuses a spec whose terminal fields disagree. C10 (tip to provers) is resolved by spec 05
section 5.2's closed O-5.7. The batch moved out of tools/ci/batches/ because the test map has no token-value cell
for the replay; the CI steward records it.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:36:38 +00:00
igneum-labs
ac8c015cc5 served-identity-hashes: a path entry hashes its login only, never a generic path word (the build page's 'at desktop width' was refused); self-test in the gate
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:36:37 +00:00
igneum-labs
ae48bc4c67 Merge 770c7036b e1b4f0fc into master (gate: green on 770c7036, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:35:39 +00:00
igneum-labs
e1b4f0fcba Merge master 688904914 into 770c7036b under the master-landing lock 2026-10-09 08:35:35 +00:00
igneum-labs
99f2300628 workers page: no identity text in the page itself (the steward's served-identity guard, 9 October 2026): the Mac card reads the macOS build host, the two PCs read rig 1 and rig 2, the host is a dedicated box, and the machine-name word is gone from the CSS comments; the guard reads the page clean on build-1.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:34:53 +00:00
igneum-labs
cc6ad7b5b9 docs/plans/igneum-2.0-master/1p5x/README.md: the brief's README (the standing order, the matrix X0 to X6 with the owners and clocks of the founder's 09:4x fan-out as the coordinator names them, the permanent rule, the arithmetic, the window hypothesis, the controls, the landed copy's replacements with both sha256s) 2026-10-09 08:34:52 +00:00
igneum-labs
f0b9b4a5e9 TV-04: the per-block mainnet schedule at 18 decimals and 10 blocks a second, reconciled against the TV-01 spec when it is in the tree; BLOCKED rows follow its conflict register
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:34:35 +00:00
igneum-labs
b6bd4b193f TV-02: the supply replays agree to the integer on three network objects with the genesis rule written in; the words alone diverge at genesis
A (Rust, the node's issuance code at bf60948a, build-5) and B (Python from the rules in words, build-6), no shared
code: with rule set v0.1 EQUAL and byte-identical at all 591 rows (every transition's before/at/after, the terminal
and one step past) on devnet-4 (1 bps, 18 decimals), mainnet (10 bps, 18) and devnet (8), and on both hand-written
reorg fixtures, the no-undo ledger refused; 46,010,980,803 blocks replayed one by one in A, the node's two issuance
paths agreeing on every one. With the words alone (v0) the first row differs: genesis issues nothing in the node
(window.rs 176-179, coinbase.rs 139), so block h carries DAA score h - 1; the terminal total is unchanged,
3,963,038,999.610200483289816 IGN on devnet-4, 36,961,000.39 IGN under the cap. README with the method, the run
commands, the result rows and the open rows (TV-01 spec re-run, the genesis and per-block-order rules for the spec,
paid/burned/locked accounting); A's crate tests (3 green on build-5); the registry batch with TV-02 NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:33:38 +00:00
igneum-labs
688904914f Merge page-nopid d27e3740 into master (gate: green on c77ecbb8, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:33:25 +00:00
igneum-labs
d27e374062 Merge master 7f0d7d120 into page-nopid under the master-landing lock 2026-10-09 08:33:21 +00:00
igneum-labs
65b76df613 Rule 33 record 1176efb9: the recovery lines without process-id words (the served-site identity pattern)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:33:05 +00:00
igneum-labs
5a0f05660e relay clients: agent watchdog tasks (the agent outlives the engine's update, restart, quit and a reboot)
The founder's standing rule of 9 October 2026: no fleet or house machine may need a hand to recover. PC 1's relay
agent died at 09:08 UK because a signed job had started it as a child of the engine's job tree and the engine's own
update ended that tree. install-agent.ps1 now registers two more tasks beside IgneumRelayService: IgneumRelayWatchdog
every five minutes and IgneumRelayWatchdogLogon a minute after logon, both running watchdog.ps1, which starts the
service task when the agent's pid file names no live process and registers it again when the task is missing. The
agent is only ever started by the task scheduler. -NoWatchdog skips the two tasks; -Remove removes them. The client
zip carries watchdog.ps1.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:32:16 +00:00
igneum-labs
16eeb01dad TV-04 on the map (cell model:tv-04, the security-budget model) and its batch tv-04-20261009-01 recorded: NOT RUN in progress until the independent panel fills the role costs
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:32:07 +00:00
igneum-labs
799806a42b Rule 33 record 1176efb9: the mini's recovery legs on the mac block (the miner supervisor and the relay agent under launchd; the update-path and agent-kill legs PASS; the reboot leg NOT RUN: FileVault on, no auto-login, the founder's one hand); the batch re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:31:47 +00:00
igneum-labs
7f0d7d1202 Merge tv-04-security-budget 7f02f1b2 into master (gate: green on 06d1b90c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:30:19 +00:00
igneum-labs
7f02f1b2f3 Merge master 3de23ddeb into tv-04-security-budget under the master-landing lock 2026-10-09 08:30:17 +00:00
igneum-labs
3de23ddebd Merge ca3-coord-record 90996689 into master (gate: green on 496677e4, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:29:00 +00:00
igneum-labs
909966895e Merge master 2bd3841a1 into ca3-coord-record under the master-landing lock 2026-10-09 08:28:57 +00:00
igneum-labs
521c9465c3 served-identity-guard: the box form's default paths under /srv/builds/_identity (build-owned; /srv is root's with no sudo for the build user)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:28:48 +00:00
igneum-labs
d28777db76 docs/plans/igneum-2.0-master/token-value/README.md: the decisions D01 to D06 ratified by the founder on 9 October 2026, recorded against their tests before activation; the registry's decisions block at master 079afdea (the steward's ci-token-value batch) cited 2026-10-09 08:28:46 +00:00
igneum-labs
d4a40a91d5 Merge box/master 2bd3841a1 into igneum-1p5x-brief-docs 2026-10-09 08:28:46 +00:00
igneum-labs
129a5276cb docs/plans/igneum-2.0-master/1p5x: the founder's evidence and experiment brief for the 1.5x target (9 October 2026) with its README; one line in the master's README points at it
On main's word through the coordinator, documents only. The landed copy replaces the token "BST" (10 times) and the machine name
"PC 1" (once) inside the brief's quoted extracts so the identity gate passes on an exported path; the original's sha256
74ee073286d4a6e211723163c39d1e5afc52eb74cbfa99108b926a5e61d2ad67 is recorded in the README beside the landed copy's 13e0caaa26a774035c8ee461fdc842ecf18afaee27167eceaef4973c22a681b4. The matrix X0 to X6 carries owner and clock
columns to be named by the coordinator. The brief claims no pass. No chain path; no served page.
2026-10-09 08:28:21 +00:00
igneum-labs
a6165fbb4b D02: the same-cap emission comparison (Token Value Phase 0), generated on build-3
The node's emission rule at release-2.0.2-node a284380b replayed for the current
pacing (A), the volume's longer same-cap distribution (B, x2; x3 and x4 swept) and
the lane's smooth-glide alternative (C), years 1, 2, 5, 10, 20. The node's own
EmissionTable prints byte-identical rows; the outputs regenerate byte-identically.
No schedule picked (the founder: pending evidence). NOT RUN.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:28:02 +00:00
igneum-labs
2bd3841a1c Merge relay-blob-cap 41dc5735 into master (gate: green on 333869b3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:27:50 +00:00
igneum-labs
770c7036b7 The served-identity guard at the site build: downloads.json and release-manifest.json (/release.json) go through tools/ci/served-identity-guard.sh before the served tree is final, exit 1 (a hit) or 2 (no private list) stops the build; while the shared guard is not in the tree the build names the unguarded files and goes on; the deploy script stops on a failed build (its tail masked the exit code)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:27:47 +00:00
igneum-labs
41dc5735cd Merge master b3bb76241 into relay-blob-cap under the master-landing lock 2026-10-09 08:27:47 +00:00
igneum-labs
bfeddbeb7b D02: the registry batch sits in the docs folder for the steward
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:27:03 +00:00
igneum-labs
b3bb762413 Merge ci-served-identity f25a57ce into master (gate: green on 7d513436, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:26:27 +00:00
igneum-labs
f25a57ce09 Merge master eb23cc8d6 into ci-served-identity under the master-landing lock 2026-10-09 08:26:24 +00:00
igneum-labs
6720d629af TV-01 Phase 0: the supply spec (cap as the invariant under D01, two schedule profiles in exact integers, 13 litepaper-versus-code rows, 4 BLOCKED)
supply-spec.json and supply-spec.md under docs/plans/igneum-2.0-master/token-value/phase0/tv-01/; the generator
(tools/token-value/tv-01/gen-spec.py, anchored to every cited line at release-2.0.2-node a284380b and
release-2.0.3-node-k6 bf60948a, and equal on every field to the consensus code's own dump run on build-9);
the checker (tools/token-value/tv-01/check-spec.py: four known-failed cases first, then total + shortfall = cap
exactly); the registry batch tools/ci/batches/tv-01-20261009-01.json (TV-01 NOT RUN, for the CI steward).
Mainnet as compiled issues 3,963,038,999.610200467816224 IGN in all, 36,961,000.39 IGN under the cap, zero from
DAA 39,131,424,000. The litepaper's year-five tail-vote sentence is named superseded by D01. Documents and tests
only; nothing activates.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:25:53 +00:00
igneum-labs
eb23cc8d60 Merge page-collapse 2058f833 into master (gate: green on c333e7f5, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:25:31 +00:00
igneum-labs
2058f83321 Merge master 632b68102 into page-collapse under the master-landing lock 2026-10-09 08:25:28 +00:00
igneum-labs
cb28a1f572 D02: the node checkout sits at vendor/rusty-kaspa, where its path dependencies resolve
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:24:35 +00:00
igneum-labs
632b68102e Merge 57dfdbac4 64fe1132 into master (gate: green on 57dfdbac, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:23:50 +00:00
igneum-labs
64fe11326e Merge master 141267878 into 57dfdbac4 under the master-landing lock 2026-10-09 08:23:47 +00:00
igneum-labs
540d70b727 D02: the runner removes its example on any exit
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:23:12 +00:00
igneum-labs
c77ecbb8d3 workers page: no pid number on the page (the served-identity scrub, 9 October 2026): the job rows read kind, command and age; the mini and PC lines read the app, node and rate facts without pids.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:22:17 +00:00
igneum-labs
b8469d70bc D02: the runner finds cargo in a non-login shell
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:22:12 +00:00
igneum-labs
5d4a522744 TV-02: the two supply-replay implementations, the compare harness and the hand-written reorg fixtures, committed before any replay ran
Implementation A (tools/token-value/tv-02/replay-node): Rust, calls the node's own issuance code
(kaspa-consensus-core by path from vendor/igneum-node, bf60948a) per block, cross-checked against the node's
second path igneum::block_subsidy_units. Implementation B (replay-spec): standalone Python 3 from the rules in
words (rules-v0 from the litepaper and economics page; v0.1 adds the genesis rule the node lane cited), grouped
sums, no shared code. Fixtures: two reorgs (ramp end k=1 to 2, the first step k=2 to 3) with every expected
integer written by hand (closed forms evaluated with bc), the no-undo ledger as the known-failed case.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:21:28 +00:00
igneum-labs
06d1b90cdf TV-04: the run record (red, green, mutants, byte-identical generation, check)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:21:24 +00:00
igneum-labs
e71a971e2b D02: wording, file handles, the runner reads the rsynced node checkout
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:21:13 +00:00
igneum-labs
c2ffa91de4 TV-04: the generated document and CSVs (from 397be074 on build-9) and the registry batch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:21:05 +00:00
igneum-labs
496677e4e1 Counter ASIC 3.0 status: the chain continues at 09:18:05 (the first blocks past the cut on lp-05 and lp-06 from the mini's snapshot), the stage faults and the hand units stopped, the recipe v4 on its waves, the PCs on 2.0.2 public and the lab-build default, the queue live, the served-file red, the token suites in the registry, the 2.0.3 k7 line
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:21:04 +00:00
igneum-labs
333869b3e6 relay: blob upload cap 128 MB (a 2.0.2 Setup is 63.9 MB; the 50 MB client token refused it with a 403)
The relay's POST upload hands a Vercel Blob client token capped at MAX_BLOB. The Windows Setup grew past 50 MB with
2.0.2 (63,883,409 bytes), so both PC build jobs of 9 October 2026 ended at the blob PUT with 403 and the Setup could
not come back for the rule-33 canary. 128 MB keeps the one-file shape and the hour-long token.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:20:59 +00:00
igneum-labs
397be0746e TV-04: fee gap clamped at year 2 (no ramp), ceilings to six decimals, the batch beside the document
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:20:21 +00:00
igneum-labs
cf3d4337b4 D02: the generator and the README template
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:19:38 +00:00
igneum-labs
02ce7996d7 TV-04: the generator (deterministic, integers and fractions), mutants moved into the test
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:19:01 +00:00
igneum-labs
c333e7f57b workers page: the per-box detail panels collapsed by default (the founder, 9 October 2026): one compact row per box (name, OS, threads, load, the one-line status by pid, read age); the panel with the core bar and the dials opens on click or Enter, several at once, the open set kept per viewer in localStorage; the summary cards and everything else unchanged.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:18:47 +00:00
igneum-labs
7d51343646 The served-file identity guard: every served file built from reports or merges is refused at its publish step on an identity hit (the committed lists plus the private list on the Mac, or a hashed token list under a salt on a box, no name in clear), the refusal logged redacted; wired into publish-manifest.sh and publish-public.sh; the daily edge check; the box-form generator; self-tests
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:18:36 +00:00
igneum-labs
4174ee36bf Merge remote-tracking branch 'build/master' into tv-d02 2026-10-09 08:18:35 +00:00
igneum-labs
c4d4ada3a3 docs/ops/build-queue.md: the standing build queue for build-1 to build-9 (9 October 2026, the coordinator's order): one owner lane per box, the first ten entries with owner, box, pid file and clock, the kill and pid rules; the live copy is build-1:/srv/queue/build-queue.md, read every 30 minutes by the queue reader.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:18:00 +00:00
igneum-labs
1412678785 Merge ca3-coord-record 8f9604f6 into master (gate: green on bbe26ca9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:17:34 +00:00
igneum-labs
8f9604f666 Merge master fbf538041 into ca3-coord-record under the master-landing lock 2026-10-09 08:17:31 +00:00
igneum-labs
57dfdbac48 Token Value decisions ratified 9 October: the litepaper and economics page read the cap fixed with no tail emission and no vote that expands it under the pre-launch security-funding gate (D01), the schedule's pacing under comparison and not final (D02), every fee and burn route explicit with the 80/20 coinbase an emission allocation only and external-job charges not yet set (D04); the explorer pages' recovery lock never shown as final (D05); the leadership line cites D06; a ratified decision is a rule, not a promise of value
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:16:25 +00:00
igneum-labs
fbf538041e Merge workers-load-by-pid 3a3d9572 into master (gate: green on 53a4e844, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:16:07 +00:00
igneum-labs
3a3d9572d1 Merge master 079afdead into workers-load-by-pid under the master-landing lock 2026-10-09 08:16:04 +00:00
igneum-labs
8a3bb61766 TV-04: the inputs and the tests first, before the generator (the known-failed first run)
The ratified-rule properties (D01 cap, no assumed appreciation, zero external
jobs under D04, VR-08 conservation, no price anywhere, panel cells empty,
exact ceilings, byte-identical regeneration) and five mutants each must
catch. Runs on build-9 only, through run-on-box.sh, under a pid file.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:15:45 +00:00
igneum-labs
9ac0846d85 D02: the tests and the box runner first (the known-failed run precedes the generator)
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-09 08:14:04 +00:00
igneum-labs
079afdeadd Merge ci-token-value 312eb7e8 into master (gate: green on 168a2cf0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:13:51 +00:00
igneum-labs
312eb7e875 Merge master ee4de4321 into ci-token-value under the master-landing lock 2026-10-09 08:13:48 +00:00
igneum-labs
53a4e84440 workers page: load by pid per box (9 October 2026, the founder's order): collect.mjs lists every job from /proc beside the cargo builds (node, miner, prover, worker, suite, fuzz, harness, service, chip, archive; counts per kind, browsers counted only), the page renders the list on each box card and reads busy from it; the mini card carries its miner line (app version, node DAA and state, rate, last accepted block, node pid; "no miner report" when absent); the PC cards read their report age honestly (STALE over ten minutes) and show the intake report fields when a PC has posted one.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:13:33 +00:00
igneum-labs
ee4de43219 Merge cf8b20f04 66f6749d into master (gate: green on cf8b20f0, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 08:10:27 +00:00
igneum-labs
66f6749d45 Merge master 2b65c9851 into cf8b20f04 under the master-landing lock 2026-10-09 08:10:25 +00:00
igneum-labs
bbe26ca92b Counter ASIC 3.0 status: the snapshot on build-1 and the recipe v3's hubs stage (lp-05/06 on the mini's chain, the miner-gate fault fixed), the bf60948a IBD read, the PCs' install, the founder's 09:15 orders and the nine-box read, the Token Value ratification and the four Phase 0 lanes, the mini's collector, the hands ended
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:10:15 +00:00
igneum-labs
168a2cf089 The founder's ratification of the Token Value decisions (D01, D03, D05, D06 RATIFIED; D02, D04 RATIFIED WITH PARAMETER PENDING), each his word verbatim, through the recorder's decision form (a replayable note); the generator keeps a ratified decision at regeneration
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:07:06 +00:00
igneum-labs
00a1fe878a Merge remote-tracking branch 'box/master' into ci-token-value 2026-10-09 08:07:05 +00:00
igneum-labs
2b65c98511 Merge igneum-2.0-token-value-docs d9705de6 into master (gate: green on 601eeb0b, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 08:04:52 +00:00
igneum-labs
d9705de68e Merge master 1f371f02c into igneum-2.0-token-value-docs under the master-landing lock 2026-10-09 08:04:49 +00:00
igneum-labs
1f371f02c8 Merge ca3-coord-record 61fe8ea0 into master (gate: green on 9874c454, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 08:03:10 +00:00
igneum-labs
cf8b20f041 Token Value rule VR-30, scoped claims only: the ranking item on the litepaper, /claims, the ledger's C3 answer and the scorecard's leadership row carry "Designed to compete for leadership among GPU-first networks." until a ranking is measured; the miner levers raise the rate, not the fastest miner; the cap, the schedule, the tail and the fee routes read as the six pending monetary decisions D01 to D06 on the litepaper (header, emission, security after the subsidy: no tail coded beside the year-five vote, an unresolved tension) and the economics page
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:03:08 +00:00
igneum-labs
61fe8ea0e1 Merge master 7f41ba300 into ca3-coord-record under the master-landing lock 2026-10-09 08:03:07 +00:00
igneum-labs
245f0b975e The VR and TV suites of the acceptance registry from the token value rules and gates (40 rules PROPOSED requiring ratification, 32 gates NOT RUN with scope and inherited links), the decisions block D01 to D06 UNAPPROVED, the counting notes; generated by tools/ci/token-value-suite.mjs, regenerated at the merge, checked in the gate
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 08:01:02 +00:00
igneum-labs
601eeb0bab docs/plans/igneum-2.0-master/token-value: the Token Value and Network Leadership volume (1.0-proposed, snapshot 8 October 2026), the master's monetary companion, with its README; one line in the master's README points at it
On main's word through the coordinator, one documents-only commit: igneum-2.0-token-value.pdf, igneum-2.0-token-value-light.pdf,
rules-and-gates.json (40 VR rules, 32 TV gates, decisions D01 to D06, 47 sources, the page index), the sha256s in the README.
Status PROPOSED, no gate executed, every TV gate NOT RUN; the decisions read "pending" until signed; the registry rows are the
CI steward's batches, not this landing's. No chain path; no served page.
2026-10-09 07:58:04 +00:00
igneum-labs
7f41ba300f Merge 7ff62dd6af e8ddc9dc into master (gate: green on 7ff62dd6, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:56:50 +00:00
igneum-labs
e8ddc9dc6e Merge master d34e25684 into 7ff62dd6af under the master-landing lock 2026-10-09 07:56:47 +00:00
igneum-labs
9874c4546e Counter ASIC 3.0 status: the founder's word go continue (08:44 UK), the mini snapshot and the runner, hive-4 run 2 and hive-5 (the hive class closed: mining during the sync), the h-run.sh fix c7f43510 and its re-cut, the record's verdict FAIL and the freeze-file citation, the two 2.0.3 flows landings bf60948a, the two founder words, the archive order
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:55:39 +00:00
igneum-labs
7ff62dd6af /download and /miner: the devnet reset note above the 2.0.2 entry (reset this morning, a fresh install syncs once it completes, re-read at 10:30 UK); removed when the fleet's one-tip line and the fresh-install canary land
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:49:30 +00:00
igneum-labs
d34e256845 Merge 7605d6e17 9e70ea74 into master (gate: green on 7605d6e1, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:45:38 +00:00
igneum-labs
9e70ea748b Merge master 7d95aa4f9 into 7605d6e17 under the master-landing lock 2026-10-09 07:45:35 +00:00
igneum-labs
7d95aa4f92 Merge ci-record-verdict 8a63d0db into master (gate: green on 2aa8b662, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 07:43:10 +00:00
igneum-labs
8a63d0dbbe Merge master d14dc6bad into ci-record-verdict under the master-landing lock 2026-10-09 07:43:07 +00:00
igneum-labs
d14dc6bad5 Merge ca3-coord-record 9e71fa2e into master (gate: green on cc5d1a90, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:38:42 +00:00
igneum-labs
9e71fa2e9c Merge master 28856d0b9 into ca3-coord-record under the master-landing lock 2026-10-09 07:38:40 +00:00
igneum-labs
7605d6e17d /audit: the share-card open item closes (re-rendered on box 2, OG_VERSION 5)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:38:20 +00:00
igneum-labs
28856d0b9c Merge e88fa3f4f 2b506a30 into master (gate: green on e88fa3f4, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:37:10 +00:00
igneum-labs
2b506a3025 Merge master 9772a5daf into e88fa3f4f under the master-landing lock 2026-10-09 07:37:07 +00:00
igneum-labs
2aa8b66243 Merge remote-tracking branch 'box/master' into ci-record-verdict
# Conflicts:
#	docs/plans/igneum-2.0-test-registry.json
#	tools/ci/batches/canary-202-20261009-01.json
#	tools/ci/canary/1176efb9.json
2026-10-09 07:36:27 +00:00
igneum-labs
9772a5daf4 Merge c9dee6a75 2dd9f9db into master (gate: green on c9dee6a7, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:36:07 +00:00
igneum-labs
2dd9f9db08 Merge master 2acf00731 into c9dee6a75 under the master-landing lock 2026-10-09 07:36:04 +00:00
igneum-labs
2acf00731d Merge canary-202 9610239a into master (gate: green on 0b2d23e6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:35:03 +00:00
igneum-labs
9610239aa7 Merge master 589d5dd1f into canary-202 under the master-landing lock 2026-10-09 07:35:00 +00:00
igneum-labs
589d5dd1fa Merge class-v6-adversary-docs-5 b3511add into master (gate: green on fb18d3c1, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 07:32:30 +00:00
igneum-labs
b3511add39 Merge master 9e55729ec into class-v6-adversary-docs-5 under the master-landing lock 2026-10-09 07:32:27 +00:00
igneum-labs
cc5d1a9078 Counter ASIC 3.0 status: F0 signed by all three roles (9e55729ec), hive canary 3 FAIL at the chain's wall with the sync gate holding, the deciding box-dn3 read (the hive binary passes), hive canary 4 run 1 PASS under the raised limit, the dl split at the edge, ADV-01's routing fault, the h-run.sh fix taken
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:31:28 +00:00
igneum-labs
9e55729ec2 Merge f0-sign-protocol2 77d1f54d into master (gate: green on 77d1f54d, recorded by tools/ci/pre-push.sh; landed on the box mirror): the Protocol owner's signature on the F0 manifest
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:29:22 +00:00
igneum-labs
c0e18a699f Merge c49d804d2 eb3f8cce into master (gate: green on c49d804d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:28:25 +00:00
igneum-labs
e88fa3f4f1 Share cards re-rendered on box 2 (24 cards, wide and square; the explorer, swap, faucet and oracle cards no longer print the devnet number; acceptance, audit, docs, prize and tuning get their cards), OG_VERSION bumped; the site gate's run on c9dee6a7 recorded as evidence for the gate:pre-push cell (UX-08, GOV-06), no verdict word
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:28:23 +00:00
igneum-labs
a730a4fbd8 Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-09 07:28:23 +00:00
igneum-labs
eb3f8cce64 Merge master 833435e21 into c49d804d2 under the master-landing lock 2026-10-09 07:28:22 +00:00
igneum-labs
0b2d23e6f6 Rule 33 record 1176efb9: the record's own verdict FAIL (five of six blocks FAIL at sync; the mac block's PASS stays as its row for the Mac entry); the batch re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:27:48 +00:00
igneum-labs
69e1ee6820 Merge canary-202 23b6ee46 into master (gate: green on 783cc5a4, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:26:33 +00:00
igneum-labs
23b6ee4678 Merge master 0e6b6502b into canary-202 under the master-landing lock 2026-10-09 07:26:31 +00:00
igneum-labs
fb18d3c1ad Test registry: the adversary lane's batch adversary-20261009-placed-32lane re-recorded at manifest aaf3405b (the rows that name multi-family-adversary.md move with it; no decision changed, adversary:mf-placed stays in progress) 2026-10-09 07:25:55 +00:00
igneum-labs
9baa834874 multi-family adversary: the 32-lane full core's detailed routing did not converge (the fault and its log); the globally-routed row stands; adv-g's logs home
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary aaf3405b3 over master 0e6b6502b: the document whole; tools/chip-model/mf stays on the branch.
2026-10-09 07:25:55 +00:00
igneum-labs
8916c76983 Kit 2's rule-33 record reads verdict FAIL (a FAIL block fails the record; the check refuses a PASS over a FAIL block); F0's mining-class row cites the node fork's pow-freeze.txt and the 202 batches' rule-19 lines; GOV-01 and INT-07 move with their pages
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:25:00 +00:00
igneum-labs
c9dee6a75b publish-public: a platform missing from the manifest keeps its alias on the file the current vercel.json names while that file exists (a staggered publish dropped the Windows alias)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:24:40 +00:00
igneum-labs
77d1f54dfb F0 manifest: the Protocol owner's signature (the node lane, 9 October 2026, 08:2x UK): 326b1700 signed; the note says what the signature asserts (the digest be5f4068, the class fingerprint cbc5bd0a with the hash lane's 08:27 line, the signing id 2a1d6caab4c24564, kit 2's 5d53a591 as the roll's binary, c363ce90 as the 2.0.3 line) and what it does not (convergence, any PASS); merged beside the product owner's row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:22:44 +00:00
igneum-labs
0e6b6502b2 Merge f0-sign-adversary ad6d080e into master (gate: green on ed311288, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:22:30 +00:00
igneum-labs
ad6d080e52 Merge master 5d7aa6451 into f0-sign-adversary under the master-landing lock 2026-10-09 07:22:27 +00:00
igneum-labs
5d7aa64516 Merge a3ebe9ed0 a7cd94d0 into master (gate: green on a3ebe9ed, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:20:57 +00:00
igneum-labs
a7cd94d0eb Merge master 8170d98fb into a3ebe9ed0 under the master-landing lock 2026-10-09 07:20:54 +00:00
igneum-labs
8170d98fb8 Merge 8f00bfcdd fd0cf79e into master (gate: green on 8f00bfcd, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:20:04 +00:00
igneum-labs
fd0cf79e56 Merge master 8e1fa908c into 8f00bfcdd under the master-landing lock 2026-10-09 07:20:01 +00:00
igneum-labs
783cc5a450 Rule 33 record 1176efb9: hive-2, the lp-4090-43 kit-binary block and hive-3 (all FAIL at sync, 9 October 2026 04:2x to 08:1x UK; hive-3 on the sync-gate package 9998913f: the gate held the miners, 0 blocks mined, the wall now the chain's own fifth cut against the standing reference); the canary-202 batch re-recorded (INT-07 moves with the evidence)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:19:19 +00:00
igneum-labs
c49d804d2a publish-bin: the delta compares in the C locale on both ends (the Mac and the box sort differently, comm then read every file as new)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:19:08 +00:00
igneum-labs
8e1fa908c0 Merge ca3-coord-record 3d128443 into master (gate: green on db4b6d47, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:19:04 +00:00
igneum-labs
3d128443ab Merge master 17bf738c6 into ca3-coord-record under the master-landing lock 2026-10-09 07:19:01 +00:00
igneum-labs
17bf738c63 Merge ci-kill-widen cfc4f698 into master (gate: green on 8c8bfca0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 07:18:00 +00:00
igneum-labs
cfc4f69851 Merge master e42466717 into ci-kill-widen under the master-landing lock 2026-10-09 07:17:57 +00:00
igneum-labs
e42466717e Merge b68baee7e6 d7a2238a into master (gate: green on b68baee7, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:17:03 +00:00
igneum-labs
d7a2238a09 Merge master 010eb4a47 into b68baee7e6 under the master-landing lock 2026-10-09 07:17:00 +00:00
igneum-labs
ed31128854 Merge remote-tracking branch 'box/master' into f0-sign-adversary
# Conflicts:
#	docs/plans/igneum-2.0-f0-manifest.md
2026-10-09 07:15:58 +00:00
igneum-labs
010eb4a474 Merge f0-sign-product c0fa9003 into master (gate: green on 37312306, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:14:32 +00:00
igneum-labs
c0fa9003e5 Merge master db81258d0 into f0-sign-product under the master-landing lock 2026-10-09 07:14:29 +00:00
igneum-labs
a3ebe9ed0c publish-bin: the tar carries no AppleDouble entries (COPYFILE_DISABLE) and the store is swept of ._ files before a deploy
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:12:38 +00:00
igneum-labs
8f00bfcdd1 dl split: the bin project's production hostname is igneum-dl-bin.vercel.app (the project-team form of a Vercel hostname answers with the SSO redirect, the plain form is the production alias)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:11:34 +00:00
igneum-labs
8c8bfca0e7 INT-07's cell note brought up to kit 2's record (mac PASS, fleet FAIL, hive FAIL, no windows block); rule 6 lands with every owner's fix on master
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:10:42 +00:00
igneum-labs
db4b6d47f8 Counter ASIC 3.0 status: the steward's 07:58 board (NOT RUN 175, PASS 8, FAIL 7), F0's empty signatures table and main's signing order, the hash lane's class-pin line (the pow-freeze.txt citation fault), rule 6 of the kill-by-name check landed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:10:25 +00:00
igneum-labs
41e1cf1482 Merge remote-tracking branch 'box/master' into ci-kill-widen 2026-10-09 07:10:18 +00:00
igneum-labs
b68baee7e6 The dl split: the binaries of dl.igneum.network publish from build-1 as the Vercel project igneum-dl-bin only when a binary is new (tools/dl/publish-bin.sh, pid files on both ends, never a kill); the downloads project keeps the manifests, signatures, checksums and pages and rewrites every binary path to the bin project with the aliases pointing there directly; the three publishers call publish-bin --if-needed before their own deploy; README section
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:09:46 +00:00
igneum-labs
db81258d0f Merge hands-kill-by-pid 0c519d67 into master (gate: green on a1def26f, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 07:08:41 +00:00
igneum-labs
0c519d676d Merge master 2ec3f9eb9 into hands-kill-by-pid under the master-landing lock 2026-10-09 07:08:38 +00:00
igneum-labs
2371b61686 F0: the independent review owner's signature (the adversary lane) with the note on what it asserts and the two discrepancies named
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:08:20 +00:00
igneum-labs
3731230649 F0 signatures: the Product owner row (the shipper, 326b1700, 08:1x UK, 9 October 2026) and its note: what the signature asserts (the entries and kits named are the ones cut and read back by sha: the Mac entry published on the mini's PASS; the fleet kit on build-1; the Windows payload, the installer kit and the hive packages cut and unpublished) and what it does not (no convergence, no PASS beyond the mac block, no Windows or HiveOS entry, a fresh Mac install cannot join devnet-4 as it stands, the fee rules BLOCKED)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:07:19 +00:00
igneum-labs
2ec3f9eb9a Merge ca3-coord-record c29d6eea into master (gate: green on c29d6eea, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 07:05:12 +00:00
igneum-labs
a1def26fba move-hand.sh: the observer stop is by recorded pid file only (rule 6, 9 October 2026): the three Mac observer processes are stopped by $IGNEUM_OBSERVER_PID_DIR/<name>.pid (default /tmp/igneum-devnet/observer-pids), a process without a live pid file is not stopped and the line says so; the pgrep -f pattern loop is gone. Nothing else changed.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 07:01:55 +00:00
igneum-labs
c29d6eeadc Counter ASIC 3.0 status: the 08:00 UK read-back as sent to main (the live heal, the standing reference and the held reset, the home machines, the freeze, the board, the faults, the morning's default action)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 06:58:04 +00:00
igneum-labs
58a8ed8c43 Merge ca3-coord-record 0bbf737f into master (gate: green on 0bbf737f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 06:55:47 +00:00
igneum-labs
0bbf737f82 Counter ASIC 3.0 status: the morning reset recipe staged (both modes, A2 on the mini's snapshot), the stand's cause (a 2.0.0 hub cannot cross its own cut; the chain's continuation on dn3-q03), three state roots at one block and 2.0.2's determinism, the node lane's 07:45 read, the 07:45 lines (the relay lane, the shipper, the fleet lane)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 06:48:38 +00:00
igneum-labs
2064091a5d Merge ca3-coord-record 77b15c07 into master (gate: green on 77b15c07, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 05:41:33 +00:00
igneum-labs
77b15c0782 Counter ASIC 3.0 status: kit 6 and the 2.0.3-k6 kits, the mini holding the frozen reference, the OpenCL reader equal on all three contexts, the node lane's 06:30 word and the finality read (the stand is not finality's), the gate's 06:30 decision RESET HELD on 27 islands
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 05:34:24 +00:00
igneum-labs
d2ba7468b7 Merge same-work-harness 2cd1e854 into master (gate: green on 81879f87, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 05:16:46 +00:00
igneum-labs
2cd1e854fb Merge master 26336e02d into same-work-harness under the master-landing lock 2026-10-09 05:16:43 +00:00
igneum-labs
81879f8730 same-work 01: OpenCL PASS on all three phases on the first rig's RX 7600 (the frozen object across the day switch; the report read back on build-1 06:09 UK): OpenCL reads all three contexts equal to the CPU reference
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 05:09:37 +00:00
igneum-labs
26336e02d6 Merge ca3-coord-record b46d3105 into master (gate: green on 700d869a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 05:09:26 +00:00
igneum-labs
b46d3105a1 Merge master b46f0950c into ca3-coord-record under the master-landing lock 2026-10-09 05:09:23 +00:00
igneum-labs
b46f0950c1 Merge same-work-harness 1fe8d6e1 into master (gate: green on 1fe8d6e1, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 05:08:21 +00:00
igneum-labs
700d869a08 Counter ASIC 3.0 status: the reference stands by consensus (lp-04's conflicting finality certificate at index 677 at 05:45:03, the fd-leak death and seed-guard restart), the gate's 06:00 line (28 one-box islands, RESET HELD by the third condition), the same-work contexts 01 and 03
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 05:02:16 +00:00
igneum-labs
1fe8d6e1ab same-work 03: OpenCL PASS on all three phases on the first rig's RX 7600 (the live class v5 object across the day switch; the report read back on build-1 06:00 UK), five of six readers in agreement; 01: OpenCL take 1 a job fault, take 2 running
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 05:01:11 +00:00
igneum-labs
6eb36e3f16 Merge ca3-coord-record c2d516f6 into master (gate: green on 466a53ee, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 05:00:19 +00:00
igneum-labs
c2d516f60d Merge master c25c93250 into ca3-coord-record under the master-landing lock 2026-10-09 05:00:16 +00:00
igneum-labs
c25c93250a Merge same-work-harness c4d8436f into master (gate: green on c4d8436f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 04:56:51 +00:00
igneum-labs
466a53eed1 Counter ASIC 3.0 status: the gate v5 and v6 (lp-4090-43 deferred), the open-files read, the node lane's 06:00 line (kits 3 to 6, the 2.0.3 re-cut, the stale-sink class), the OpenCL same-work PASS, main's wordings, the reference standing at the epoch-13 cut since 05:45
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:53:11 +00:00
igneum-labs
c4d8436f7a same-work 02: OpenCL PASS on all three phases on the first rig's RX 7600 (the gen 6 worker, the day switch at 1572864 seen; the report read back on build-1 05:49 UK): five of six readers agree on every nonce; Metal is the sixth
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:49:42 +00:00
igneum-labs
0b265fc923 Merge ca3-coord-record c050f4db into master (gate: green on c050f4db, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 04:47:40 +00:00
igneum-labs
c050f4dba0 Counter ASIC 3.0 status: the two evidence kits and the hive sync gate 9998913f, the pods reconciled, the node lane's store read (the hubs hold and serve, the wall the hive package on lp-4090-43 alone), kits 3 to 5 and the 2.0.3 re-cut, the hive packages re-cut
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:40:30 +00:00
igneum-labs
738a39aedd Merge ca3-coord-record cc295698 into master (gate: green on e029ebea, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 04:35:09 +00:00
igneum-labs
cc29569862 Merge master d65414de2 into ca3-coord-record under the master-landing lock 2026-10-09 04:35:06 +00:00
igneum-labs
d65414de2e Merge same-work-harness b17d467f into master (gate: green on b17d467f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 04:34:04 +00:00
igneum-labs
e029ebeada Counter ASIC 3.0 status: main's word on the 06:30 reset, the gate v4 armed with override-on-pass, the hive class read as the run (h-run.sh mines before sync), main's hive fix ask for tonight, the two further evidence kits
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:27:17 +00:00
igneum-labs
b17d467f11 same-work: the 3090 PASS on all three phases of all three contexts (read back on build-1 05:00 to 05:14 UK), the CUDA cell on three cards per context; OpenCL take 2 on the first rig phase 1 PASS with the day-switch read on take 3; the runner and job faults named
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:26:48 +00:00
igneum-labs
6afa40f1d6 Merge ca3-coord-record 93d43c8c into master (gate: green on 93d43c8c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 04:25:26 +00:00
igneum-labs
93d43c8c81 Counter ASIC 3.0 status: the second hive canary and the gate v3, the mini at the reference tip mining on 2.0.2 (53-minute fresh sync through five cuts), the cap guard's restart and the shim's refusal, hive-2 FAIL with the hive build as the class, the kit-binary canary
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 04:18:16 +00:00
igneum-labs
9ad2992366 Merge ca3-coord-record c615beee into master (gate: green on 9bea27fc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:59:37 +00:00
igneum-labs
c615beeee7 Merge master a38e8c590 into ca3-coord-record under the master-landing lock 2026-10-09 03:59:34 +00:00
igneum-labs
a38e8c5908 Merge hash-registry-1 acbac23f into master (gate: green on acbac23f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:58:33 +00:00
igneum-labs
9bea27fc5c Counter ASIC 3.0 status and register: the mini's fresh sync past the first cut on kit 2's node (the hive wall a serving gap on the lp hubs), main's serving-gap ruling (the second hive canary, the 06:30 reset condition), layer 8 closed (row 18: the layer stays), the 2 GiB read
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:52:10 +00:00
igneum-labs
acbac23ff5 test registry: the hash lane's batch 4 (PC 1 knee rows: layer 8 stays in, the paired 2 GiB read)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:51:56 +00:00
igneum-labs
007a48c851 Merge ca3-coord-record 33a5f3da into master (gate: green on f4c6b37b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:48:43 +00:00
igneum-labs
33a5f3da80 Merge master 4c322391d into ca3-coord-record under the master-landing lock 2026-10-09 03:48:40 +00:00
igneum-labs
4c322391df Merge canary-202 c3c1d304 into master (gate: green on c3c1d304, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:47:40 +00:00
igneum-labs
f4c6b37b26 Counter ASIC 3.0 status: the fleet block landed on INT-07 (FAIL), the hive canary FAIL on the lost-proof relay (the reset held), the reference hubs' state-root split after the same cut block, main's rulings and the relay-class diagnostic
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:41:16 +00:00
igneum-labs
c3c1d30483 Rule 33 record 1176efb9: the hive block (lp-4090-43, FAIL at sync on the lost-proof loop at the first class v5 cut, 04:2x UK, 9 October 2026) and the re-shaped fleet block (no sync.feed object) beside the mac PASS; the canary-202 batch re-recorded with it (INT-07's row moves with the evidence)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:40:27 +00:00
igneum-labs
e5b05d55a0 merge master 2026-10-09 03:40:07 +00:00
igneum-labs
7c7d504ae0 Merge ca3-coord-record ea2bb20d into master (gate: green on 2d882ac7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:26:56 +00:00
igneum-labs
ea2bb20d15 Merge master b73a33b8a into ca3-coord-record under the master-landing lock 2026-10-09 03:26:53 +00:00
igneum-labs
b73a33b8a9 Merge ci-int07-fleet 910b0ed2 into master (gate: green on 910b0ed2, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 03:25:13 +00:00
igneum-labs
2d882ac73c Counter ASIC 3.0 status: the canary's class settled from its datadir line, the gate v2 armed on baseline 29, the mini's fresh-datadir reset, fix 3 = 09350682 and kit 3's evidence kit cut (23ef6f47), hub-1's disk kept by main's word, lp-4090-02's second fd death
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:19:46 +00:00
igneum-labs
910b0ed297 Kit 2's rule-33 record with the fleet block (FAIL at sync under fix 2's walk bound) and INT-07 moved with it (FAIL; the mac block PASS, hive and windows pending); F0's rule-33 row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:18:30 +00:00
igneum-labs
c4858ac9bd Merge master f12b24ca5 into canary-202 under the master-landing lock 2026-10-09 03:16:56 +00:00
igneum-labs
f12b24ca56 Merge ca3-coord-record 612a49a1 into master (gate: green on 612a49a1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 03:14:44 +00:00
igneum-labs
d540e669f2 Rule 33 record 1176efb9: the fleet datadir path as a home path (the identity grep)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:09:46 +00:00
igneum-labs
3a0109239a Rule 33 record 1176efb9: the fleet block note in UK time words (the identity grep forbids the zone abbreviation)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:08:23 +00:00
igneum-labs
612a49a189 Counter ASIC 3.0 status: the reference moved to lp-4090-04's chain (hub-1 diverged 03:46), kit 2's fleet canary FAIL at the walk bound and the roll held, the mini's second stall class, main's rulings on the gate refinement and the reset
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:07:31 +00:00
igneum-labs
4ad98bcef4 Rule 33 record 1176efb9: the fleet block (lp-4090-11, FAIL at sync, 04:04 UK, 9 October 2026) beside the mac block; a fresh 2.0.2 node walls at the reference chain's fifth cut under fix 2's walk bound (the kit ran clean on x86-64-v3); no fleet, hive or windows entry on this record
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 03:06:46 +00:00
igneum-labs
634d3272f8 Merge ca3-coord-record 9b2b857f into master (gate: green on 9b2b857f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 02:55:22 +00:00
igneum-labs
9b2b857f9b Counter ASIC 3.0 status: the 2.0.2 packages blocked on the packing guard and cut under the narrow blake3 acceptance (hive e475f3e0, Windows payload 6242bbe9, installer kit 34b77d28), the fleet kit's re-tar to de47da86 recorded once
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 02:48:09 +00:00
igneum-labs
cc17f9c3ba Merge ca3-coord-record 39cd9985 into master (gate: green on 39cd9985, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 02:29:46 +00:00
igneum-labs
39cd998555 Counter ASIC 3.0 status: kit 2's batch on master, the Mac entry live at 02:20, the hubs' open-file class, the mini's 18-minute stall cleared on its own, the duplicate build-server lane recorded once, the fleet kit cut at 03:18 and read back from build-1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 02:22:30 +00:00
igneum-labs
42d30ee01a Merge class-v6-adversary-docs-4 a9069ddf into master (gate: green on a9069ddf, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 01:47:36 +00:00
igneum-labs
a9069ddf5f multi-family adversary: the placed 32-lane 18-family core (9.54 pJ per lane-op, k 0.65 same-node), the estimate-to-SPEF calibration, the bank's cost by lane count, the 32-lane batch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary 7a9fa6148 over master a9bf2e855: the document whole, the batch adversary-20261009-placed-32lane recorded through tools/ci/test-record.mjs on master's registry copy; tools/chip-model/mf stays on the branch.
2026-10-09 01:41:05 +00:00
igneum-labs
a9bf2e8552 Merge ci-int07-kit2 4e7f90a6 into master (gate: green on 2e736f2d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 01:39:15 +00:00
igneum-labs
4e7f90a6ac Merge master 6d973e2a4 into ci-int07-kit2 under the master-landing lock 2026-10-09 01:39:12 +00:00
igneum-labs
6d973e2a42 Merge canary-202 85cb21f5 into master (gate: green on a2f276e6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 01:38:16 +00:00
igneum-labs
85cb21f551 Merge master a3fa52efb into canary-202 under the master-landing lock 2026-10-09 01:38:14 +00:00
igneum-labs
a3fa52efbd Merge de1f03389b 80ec82a6 into master (gate: green on de1f0338, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 01:34:42 +00:00
igneum-labs
80ec82a635 Merge master 9cd4e3e2b into de1f03389b under the master-landing lock 2026-10-09 01:34:39 +00:00
igneum-labs
2e736f2d24 INT-07 on kit 2's rule-33 record (the mac block PASS, one of four; NOT RUN in progress until the other three join); F0's rule-33 row; the identity grep covers the canary records and the owner's name in a host string; the recorder takes a cell's in_progress flag (only the legacy word RUNNING had set it)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 01:32:22 +00:00
igneum-labs
a2f276e6eb Rule 33 records: the mini's host line without the machine's local name (the owner's name stays out of the history; the steward's read, 9 October 2026 02:3x UK)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 01:31:05 +00:00
igneum-labs
9cd4e3e2b3 Merge canary-202 7d23e316 into master (gate: green on 7d23e316, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 01:28:43 +00:00
igneum-labs
de1f03389b 2.0.2 on Mac: the download index and the release manifest carry Igneum-Miner-2.0.2-5d53a591-1176efb9.dmg (sha256 66137cd8…, 46,002,244 bytes, min supported 2.0.1); Windows and HiveOS stay on 2.0.1 until their builds are cut; the download page's 2.0.2 note above the 2.0.1 one; the OPS-03 manifest cell re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 01:27:22 +00:00
igneum-labs
7d23e31639 Rule 33 records for 2.0.2: kit 2 (1176efb9, the mac block from the mini's fresh-install canary on Igneum-Miner-2.0.2-5d53a591-1176efb9.dmg: genesis to 16731 in 2016 s on hub-1's chain, 18 blocks in 5 min at 12.65 MH/s, 0 refusals, tip within ten of the feed, quit in 4 s; the Mac entry published on it at 02:20 UK, 9 October 2026) and kit 1 (5db25637, the fallback's mac block: 14189 in 1036 s, 16 blocks, 0 refusals, quit in 3 s; the entry unpublished). The fleet, hive and windows blocks for 1176efb9 follow from their own boxes.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 01:21:22 +00:00
igneum-labs
988e21680c Merge finality-native-runs bd4791a0 into master (gate: green on bd4791a0, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 01:02:16 +00:00
igneum-labs
bd4791a05d Merge master 146ccb936 into finality-native-runs under the master-landing lock 2026-10-09 00:55:40 +00:00
igneum-labs
146ccb9369 Merge docs-2.0.3-list 0861259d into master (gate: green on 01abd09f, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 00:49:25 +00:00
igneum-labs
0861259d90 Merge master 12773f4e9 into docs-2.0.3-list under the master-landing lock 2026-10-09 00:49:22 +00:00
igneum-labs
4e1eae54e1 The 2.0.3 reruns of rows 1b and 1c on the fixed node (finality-2.0.3-kind-and-conflict c8d22a85, 9 October 2026, 01:27 to 01:45 UK): the lock kind reads recovery on every node, two valid certificates at one index pause finality with reason conflict and no new lock above it; rows, files and the registry batch
Three runs on real nodes (igneumd a37f4b63 built from c8d22a85's code, build-5 and build-6, lease pool, pid watchers, zero restarts): 1b with e at 0.20 (A recovered at index 10 at 55.46 percent; that certificate reads lockKind recovery on A's, B's and C's nodes; 0 conflicts, 0 disagreement, all three at 24), 1b with e at 0.30 (the same at index 11, all three at 27), 1c (A and B recovered at index 11, two recovery certificates; after the heal both holders read "conflict: two valid certificates at index 11", finalityActive false, no lock installed above it; C followed A's chain, B's never reached it). Finding 1 and finding 2 of the native runs closed on the node. Batch fin-203-20261009T0127Z recorded (FIN-02, FIN-07 PASS on node:finality-realnode, manifest c8d22a85). Harness: v4.mjs records finalityActive per node; run-row.sh takes PAIR.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:47:43 +00:00
igneum-labs
12773f4e99 Merge ca3-coord-record c582c5ba into master (gate: green on c582c5ba, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-09 00:47:34 +00:00
igneum-labs
01abd09f25 The night of 8 to 9 October in the 2.0 plan (the split, kit 1 490ebcfe, kit 2 5d53a591 with the live heal, the 2.0.3 line and its open items) and finality-guarantees 6.6's joiner-under-a-lock sentence (the record store lane's patch)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:42:14 +00:00
igneum-labs
c582c5bacf Counter ASIC 3.0 status: the same-work test's three contexts on master, kit 1 named (490ebcfe) with the mini mining on 2.0.2 since 01:10, kit 2 re-composed and named (kit2b-line 5d53a591) with the dead island healed twice, the finality runs' note landed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:40:05 +00:00
igneum-labs
85a26058a5 Merge ci-202-kit2 31906fc6 into master (gate: green on 31906fc6, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 00:33:39 +00:00
igneum-labs
31906fc635 2.0.2 kit 2 pair gate: node 5d53a591 (fix 2 + the wedge fix) six node cells GREEN on build-4, pow and app GREEN on 77b5acc5 (no crate move to 1176efb9); batch 202-5d53a591-1176efb9; F0's pair row (kit 2 the roll, kit 1 re-cut the fallback)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:26:48 +00:00
igneum-labs
b22d4a9150 Merge ci-notes-stored 819884bd into master (gate: green on 04577e7a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 00:22:15 +00:00
igneum-labs
819884bda6 Merge master bfdca60ca into ci-notes-stored under the master-landing lock 2026-10-09 00:22:12 +00:00
igneum-labs
bfdca60ca4 Merge ci-canary-rules ff7e6e27 into master (gate: green on 31a54ad4, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 00:20:31 +00:00
igneum-labs
ff7e6e27d3 Merge master 810a06172 into ci-canary-rules under the master-landing lock 2026-10-09 00:20:28 +00:00
igneum-labs
810a061720 Merge 76cfdb9f81 7b047937 into master (gate: green on 76cfdb9f, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 00:16:11 +00:00
igneum-labs
7b047937a3 Merge master c387a57dd into 76cfdb9f81 under the master-landing lock 2026-10-09 00:16:09 +00:00
igneum-labs
04577e7a6d The recorder stores a cell's and a batch's note in the evidence record (every note written tonight had lived in the batch file alone); the recovery-certificate note as note files on FIN and REV so the replay keeps it
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:15:33 +00:00
igneum-labs
c387a57dd7 Merge ci-fin-note 2af8a94a into master (gate: green on 2af8a94a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-09 00:13:52 +00:00
igneum-labs
31a54ad469 canary-check: a mac block's shard may read n/a (no prover on Apple silicon), no other kind's; the tip is read against the feed line adjusted by its age at the block rate (within ten blocks); self-tests
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:13:44 +00:00
igneum-labs
76cfdb9f81 /acceptance rebuilt on the merged registry
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:08:52 +00:00
igneum-labs
fff42353ab Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-09 00:08:44 +00:00
igneum-labs
743f001702 Recovery lock, forming node only: the four-words note on the seven explorer pages and the block page's lock chip say the kind is the forming node's report on the current node line (a receiving node records an ordinary lock) until the 2.0.3 node line lands; the register's F04 row carries the same qualifier and the fix branch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:08:44 +00:00
igneum-labs
2af8a94a88 Registry: the dated recovery-certificate note on FIN-02, FIN-08 and the F04 closure rows (recovery kind correct on the forming node only until 2.0.3; conflicting-certificate reporting open); no decision changed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-09 00:06:50 +00:00
igneum-labs
e8d0b634f0 Merge finality-native-runs 32e23110 into master (gate: green on 9e851111, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-09 00:03:51 +00:00
igneum-labs
32e2311057 Merge master 2a9a3ea00 into finality-native-runs under the master-landing lock 2026-10-09 00:03:48 +00:00
igneum-labs
9e8511118d The native finality runs of 9 October 2026, section 6 (F01, the two-node cache-history case): PASS on real nodes at 00:41 UK on the cache-history-node pair c591e63b + harness-unsafe, the six runs recorded with their setup faults
Run 6 on build-5 (24 leased cores, zero restarts): the real proof's bytes under another block's statement refused as a cheap context refusal (no verifier run, nothing cached); the same bytes under the honest record verified once in consensus and paid exactly once on both honest nodes at the same chain block for the same wei; the invalid bytes verified once and refused again from the cache at a later carrier. H1's and H2's verdicts and paid maps identical. Runs 1 to 5 (the exec pool verifier Off on a node without the counters, a host pin that was not the node's, the harness-unsafe feature missing, the 8-core lease against the 600-block record window, a stale manifest beside the harness) are in the rows as the record of each fault, none the node's. Plan section 6 MEASURED; the batch note carries the result (F01's cell is the enforced lane's).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:57:05 +00:00
igneum-labs
2a9a3ea008 Merge ca3-coord-record 65c910a6 into master (gate: green on e52cb829, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 23:53:15 +00:00
igneum-labs
65c910a678 Merge master 3d9404873 into ca3-coord-record under the master-landing lock 2026-10-08 23:53:12 +00:00
igneum-labs
3d9404873f Merge same-work-harness b59db830 into master (gate: green on 180fa255, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 23:52:12 +00:00
igneum-labs
b59db83047 Merge master dd52dccb3 into same-work-harness under the master-landing lock 2026-10-08 23:52:09 +00:00
igneum-labs
dd52dccb3e Merge pool-int-rows 4f5c76ca into master (gate: green on 02d96fce, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 23:47:51 +00:00
igneum-labs
4f5c76cafe Merge master 2944efa47 into pool-int-rows under the master-landing lock 2026-10-08 23:47:48 +00:00
igneum-labs
e52cb82926 Counter ASIC 3.0 status: the kit 1 cut line, the wedge class named and fixed (5d53a591), both kits re-cut (490ebcfe, cf32be79), the mac canary FAIL on INT-07, the D1 record on master 0d94049bb, main's shape for the 08:00 read-back
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:45:38 +00:00
igneum-labs
180fa25584 same-work 03: the pool PASS on all three phases on the 2.0.2 kit as pinned (read back on build-1 00:39 UK): node x2, pool, CPU reference and two CUDA cards agree on every nonce of the live class v5 object across the day switch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:45:01 +00:00
igneum-labs
2944efa470 Merge same-work-harness 28826165 into master (gate: green on b3dfef4c, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 23:43:12 +00:00
igneum-labs
2882616598 Merge master 24ecbd7d1 into same-work-harness under the master-landing lock 2026-10-08 23:43:04 +00:00
igneum-labs
02d96fceb1 The pool's INT rows named in the map and recorded (the steward's form, 9 October 2026 00:3x UK): INT-03, INT-04 and INT-15 on the suite:pool cell with a coverage line each (the pool suite's intent, ledger and binding v2 tests on every 2.0.2 node sha named 8 to 9 October: 7cfa422a 53, f775c347 53, a284380b 54, d657e490 54, 94e4c6ba 54, 490ebcfe 54, cf32be79 54, all rc 0 on build-6; the live-network halves are the roll's), INT-16 on harness:same-work (the member-side re-check: the d1-pairing row PASS x3 on the class v6 object, the kit row PASS x3 on the class v5 object, the kit row on 02 BLOCKED by the V5 pins); the four ids out of the map's not_run block; the batch pool-int-20261009-01 (manifest 490ebcfe, method native, NOT RUN in progress with the evidence paths on build-1 and build-6, never PASS by inference; on an island, not a network for the 03 stream); the page regenerated
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:41:06 +00:00
igneum-labs
24ecbd7d11 Merge ci-202-kit1c 95843dc0 into master (gate: green on 95843dc0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 23:36:35 +00:00
igneum-labs
b3dfef4c68 same-work 03: the live class v5 object across the day switch: node PASS x3 on the release line (kit 1's pair 94e4c6ba) and on the D1 branch (cc23f9bd), CUDA PASS x3 on the 5090 and the 4090, the CPU references read back; the pool kit row running
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:35:51 +00:00
igneum-labs
95843dc093 2.0.2 kit 1 re-cut pair gate: node 490ebcfe (the wedge fix) six node cells GREEN on build-4, pow and app GREEN on 77b5acc5 (no crate move to 5db25637); batch 202-490ebcfe-5db25637; F0's pair and canary rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:29:37 +00:00
igneum-labs
9ac036cc7d Merge ci-202-kit1b 5a3e7e50 into master (gate: green on aef1969d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 23:23:36 +00:00
igneum-labs
5a3e7e5064 Merge master 1df98f6f7 into ci-202-kit1b under the master-landing lock 2026-10-08 23:23:33 +00:00
igneum-labs
1df98f6f75 Merge ca3-coord-record 70583117 into master (gate: green on 86ba35a1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 23:21:28 +00:00
igneum-labs
70583117a3 Merge master 0d94049bb into ca3-coord-record under the master-landing lock 2026-10-08 23:21:26 +00:00
igneum-labs
0d94049bb2 Merge d1-record 1254833b into master (gate: green on 36a0387c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 23:19:29 +00:00
igneum-labs
1254833b06 Merge master 7d62345a4 into d1-record under the master-landing lock 2026-10-08 23:19:26 +00:00
igneum-labs
aef1969d2f 2.0.2 kit 1 (final) pair gate: node 94e4c6ba six node cells GREEN on build-4, pow and app GREEN on 77b5acc5; the rule-33 mac canary FAIL on its sync line (kit 1 the fallback, kit 2 the roll); batch 202-94e4c6ba-870c0344; F0's pair and canary rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:16:55 +00:00
igneum-labs
86ba35a120 Igneum 2.0 register: D5 healed live at 00:12 UK on the fix-2 tree; Counter ASIC 3.0 status: kit 1 94e4c6ba green with a fresh node at hub-1's tip in 14 minutes, the live heal, kit 2's composition, the record-store lane done, the native finality runs landed, rule 6 built
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 23:14:17 +00:00
igneum-labs
7d62345a4a Merge fleet-sp1-pid-20261009 9618b6a0 into master (gate: green on 150fe70d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 22:58:04 +00:00
igneum-labs
9618b6a09b Merge master 5d57a74d0 into fleet-sp1-pid-20261009 under the master-landing lock 2026-10-08 22:58:01 +00:00
igneum-labs
5d57a74d07 Merge ca3-coord-record 3de77959 into master (gate: green on 05642204, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 22:54:30 +00:00
igneum-labs
3de779590a Merge master f9f423997 into ca3-coord-record under the master-landing lock 2026-10-08 22:54:27 +00:00
igneum-labs
f9f4239972 Merge finality-native-runs a8e0f423 into master (gate: green on 96a558eb, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 22:53:32 +00:00
igneum-labs
a8e0f4232f Merge master 3fc04d938 into finality-native-runs under the master-landing lock 2026-10-08 22:53:29 +00:00
igneum-labs
f1494e6de1 Merge remote-tracking branch 'box/hands-stop-by-pidfile' into ci-kill-widen 2026-10-08 22:52:36 +00:00
igneum-labs
150fe70d4d fleet: the SP1 server records its own pid; every server stop reads that file (the widened kill rule)
sp1-server-wrap.sh sits at home/.sp1/bin/sp1-gpu-server, writes /root/fleet/pids/sp1-server.pid and execs the binary beside it; lib/pidkill.sh's
kill_sock_owner becomes kill_pidfile sp1-server (no socket sweep); box-prover.py's kill_server reads the pid file only.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:51:26 +00:00
igneum-labs
c8489d4f1e The hand nodes' restart stops by pid file, never by a pattern listing (the kill rule's fourth instance, 8 October 2026, the steward's widened check): every node the script starts writes <appdir>.pid from the nohup child, stop() reads that file and nothing else (a node without a file is left running and said so), the running-now line lists the pid files' processes; no pgrep in the script
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:51:01 +00:00
igneum-labs
d237c56dd4 kill-by-name rule 6: a kill chosen by a pattern (kill fed by pgrep, lsof, fuser -k, an ss or netstat pipeline, xargs kill, a loop over a listing) is refused in every tracked script and job body; allowed: a recorded pid, the pid file, pkill -F, fleet-bg.sh stop, pgrep -P <recorded pid>; the socket-sweep fault as the class's fourth instance
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:50:56 +00:00
igneum-labs
0564220405 Counter ASIC 3.0 status: F0 signed on 326b1700, kit 1 corrected to d657e490 then 94e4c6ba (the body-sync class), the cut tip 870c0344, V6-07 and the cache-history case landed, main's correction on the superseded cut-tip line
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:47:16 +00:00
igneum-labs
36a0387c83 Merge master into d1-record for the D1 record landing
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:45:30 +00:00
igneum-labs
96a558ebcc The native finality runs of 9 October 2026 (plan sections 1 to 4 and 6): rule v4 on real nodes of the 2.0.2 line e189afb4 with the 60x file's windows, rows in sim/results_v2.md and the registry batch
Sections 1 to 4 MEASURED on build-5 and build-6 (22:35 to 23:15 UK) under the lease pool and pid watchers, the harness tools/finality-attacks/v4.mjs (the v3.mjs shape with three islands, an equivocating key, a leaving voter, a strip, a kept-datadir restart, a fresh node at the heal, the carried-certificate capture; lib/net.mjs gained the per-node EVM RPC port for the lock kind) and tools/finality-attacks/verifier-row.mjs (the shared Sepolia verifier and the same contract on anvil with the harness table). 1a PASS (every island pauses); 1b PASS on runs 2 and 3 (exactly the island above half of the anchored table recovers after a full window, the others pause and join its chain; run 1 drew the island under half by Poisson jitter and paused as the rule says); 1c the measured conflict of 6.5 (two recovery certificates, the anchored history untouched) with the plan's FAIL line hit: a recovery certificate reads lockKind "final" on every node that did not form it (finding 1, node change owed), and a node holding two certificates reports active and keeps locking (finding 2, 3.11.4); 1d PASS (pause only, the equivocator stripped at the heal); 2 PASS (the fresh node holds every pre-heal lock by carried certificates, the restarted node agrees, the pause ends within two intervals of the reconnect, four epoch boundaries inside the pause); 3a to 3d PASS on the node facts; 4 PASS (a recovery certificate fails closed on both verifiers). Section 6: the enforced lane's harness needs its cache-history-node pair (c591e63b) and the 0x51cd pin; runs 1 and 2 recorded with their cause, run 3 follows. Batch fin-native-20261008T2300Z recorded (FIN-02, FIN-07 PASS on node:finality-realnode; FIN-08 RUNNING).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:45:19 +00:00
igneum-labs
754a535daf Igneum 2.0 Deliverable 1, the record on the frozen candidate (c): e8773ff5 on class-v6-node-review, tree db36d8060, fingerprint 5f4d6dc6…, the signing object 2a1d6caab4c24564 at the chain-paired seed and state (F0 on master 6adf5f4a), the fallback 83bb8ea6; the gates as read back on build-1 (the six suites' counts, the pair's shas, the canary set, the census re-read and the signing program's trace, lane D 6.13, the same-work readers with the pool cell open); spec 01 version 0.3's object table on the same facts
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:45:19 +00:00
igneum-labs
3fc04d9383 Merge same-work-harness 1f7e58db into master (gate: green on 1f7e58db, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:37:47 +00:00
igneum-labs
1f7e58db7d same-work 01: the 4090 PASS on all three phases of the frozen object (read back on build-1 23:22 to 23:25 UK); the 3090's copy fault named on both rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:30:35 +00:00
igneum-labs
acd387e00c Merge same-work-harness 5dbcfd3a into master (gate: green on 8147b607, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:29:19 +00:00
igneum-labs
5dbcfd3ae7 Merge master 326b17001 into same-work-harness under the master-landing lock 2026-10-08 22:29:16 +00:00
igneum-labs
326b17001b Merge f0-signing a28b012c into master (gate: green on 8b2e4b7b, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:27:26 +00:00
igneum-labs
a28b012c01 Merge master 581359f16 into f0-signing under the master-landing lock 2026-10-08 22:27:23 +00:00
igneum-labs
581359f16d Merge ci-202-kit1 29ddc259 into master (gate: green on 15d629f0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:26:27 +00:00
igneum-labs
29ddc25909 Merge master 6adf5f4aa into ci-202-kit1 under the master-landing lock 2026-10-08 22:26:24 +00:00
igneum-labs
6adf5f4aa5 Merge ca3-coord-record 065e9b20 into master (gate: green on 72eb2d01, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 22:25:24 +00:00
igneum-labs
065e9b201c Merge master aaf13e93d into ca3-coord-record under the master-landing lock 2026-10-08 22:25:21 +00:00
igneum-labs
aaf13e93d8 Merge cache-history 3c08dd51 into master (gate: green on 3fc505a8, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 22:24:23 +00:00
igneum-labs
3c08dd5114 Merge master 1d8a8e597 into cache-history under the master-landing lock 2026-10-08 22:24:20 +00:00
igneum-labs
1d8a8e5976 Merge v607-floor-memory bad561f1 into master (gate: green on e047509c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 22:22:50 +00:00
igneum-labs
8147b60729 same-work: CUDA PASS on all three phases on the 5090 and the 4090 for context 02 and on the 5090 for context 01 (the frozen object's day switch seen), read back on build-1 23:09 to 23:20 UK
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:22:06 +00:00
igneum-labs
bad561f194 Merge master 9f99c3f0a into v607-floor-memory under the master-landing lock 2026-10-08 22:20:07 +00:00
igneum-labs
15d629f0df 2.0.2 kit 1 pair gate: node d657e490 on the key-succession pairing with the class v5 freeze, the kaspad check and five node suites GREEN on build-4; pow and app GREEN on 77b5acc5 (no crate move to 6b17f951); batch 202-d657e490-6b17f951
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:18:02 +00:00
igneum-labs
3fc505a800 The cache-history evidence: the carried rows' field is signer (the check reads clean)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:16:29 +00:00
igneum-labs
82a87ce28c The harnesses' carried rows name the record's vote key hash as signer (the secrets check reads any 64-hex beside the word key, keyHash included)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:15:56 +00:00
igneum-labs
852bd445e5 The harnesses' carried rows name the vote key hash as keyHash (the secrets check reads a 64-hex beside the word key as a secret; the value is the record's public key hash); the cache-history evidence edited to the same
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:15:10 +00:00
igneum-labs
72eb2d0140 Igneum 2.0 register: D1 FROZEN on candidate (c) at 23:17 UK; Counter ASIC 3.0 status: the freeze's inputs and decision, the seventeen-island census and main's rulings, fix (1) and fix (2) green, the 3,844 wall's real cause (P22's wire widening, reverted and returned gated), the lost-proof read, the same-work gate closed by evidence, the composition test, the chain-paired packs, GOV-03 PASS, the succession PASS with H and W, V6-07's rows, the cache-history PASS, the 2.0.2 cut tip
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:14:09 +00:00
igneum-labs
8b2e4b7b24 F0: the signing block (the class v6 freeze candidate 2a1d6caab4c24564 of db36d8060 at its pairing, the same-work and acceptance rows, the 2.0.2 pair gate, the prover row, the canary state, the network label); GOV-01 moves with the page
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:13:43 +00:00
igneum-labs
e047509cd1 V6-07: the batch in the steward's current form (method GPU, release identity, claim impact) recorded into the merged registry
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:13:20 +00:00
igneum-labs
9f99c3f0a5 Merge census-chainseed-trace 2dc26479 into master (gate: green on bdb06e88, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 22:12:37 +00:00
igneum-labs
2dc2647930 Merge master b319c1c09 into census-chainseed-trace under the master-landing lock 2026-10-08 22:12:34 +00:00
igneum-labs
03ba73516f Merge remote-tracking branch 'box/master' into v607-floor-memory
# Conflicts:
#	docs/plans/igneum-2.0-test-harness-map.md
#	docs/plans/igneum-2.0-test-registry.json
2026-10-08 22:12:32 +00:00
igneum-labs
b319c1c092 Merge ci-202-batch f15afb2f into master (gate: green on de0288c9, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:11:37 +00:00
igneum-labs
f15afb2fc5 Merge master ce69efa96 into ci-202-batch under the master-landing lock 2026-10-08 22:11:35 +00:00
igneum-labs
ce69efa963 Merge same-work-harness 28097e4c into master (gate: green on d1722a00, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 22:09:41 +00:00
igneum-labs
28097e4c27 Merge master 6134f51a6 into same-work-harness under the master-landing lock 2026-10-08 22:09:38 +00:00
igneum-labs
2eb3523536 Merge remote-tracking branch 'box/master' into cache-history
# Conflicts:
#	igneum-pow/src/accept.rs
#	igneum-pow/src/emit.rs
#	igneum-pow/src/generator.rs
#	igneum-pow/src/main.rs
#	igneum-pow/tests/packs.rs
2026-10-08 22:06:59 +00:00
igneum-labs
bdb06e88d0 Registry: census:class-v6 run census-v6-chainseed-trace-20261008-2305 (the chain-seed row with the signing program's window trace)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:04:43 +00:00
igneum-labs
de0288c929 2.0.2 pair gate: node a284380b on the key-succession pairing with the class v5 freeze, the kaspad check and five node suites GREEN on build-4; pow and app GREEN on 77b5acc5 (no crate move to 5f50afd1); batch 202-a284380b-5f50afd1 (the suites' cases NOT RUN in progress with the green logs, never PASS by inference)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:04:35 +00:00
igneum-labs
5584d806d5 Merge master 6134f51a6 into census-chainseed-trace under the master-landing lock 2026-10-08 22:04:15 +00:00
igneum-labs
d1722a00a8 same-work 02: CUDA phases 1 and 2 PASS on the 5090 and the 4090 (the day switch at 1572864 seen by a GPU reader), phase 3 rerunning on the fixed driver; the two driver faults in the note
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:02:08 +00:00
igneum-labs
8feca87dd7 p01-vectors: the pack the worker holds is read from its ready line and every other segment is prepared (phase 3 on a worker started on the day D pack refused every day D+1 job at 22:56 UK: missing 1,048,576, no disagreement); the self-test's phase 3 runs on a day D worker
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:02:08 +00:00
igneum-labs
89a1a022c5 same-work 02: docs/design/class-v5-stored-state.md (the node lane's fix-2 amendment, 6e3aabdd) moves with R2-F03-R02
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 22:00:56 +00:00
igneum-labs
f6300f1177 Merge remote-tracking branch 'box/class-v5-foreign-capture-doc' into same-work-harness 2026-10-08 22:00:56 +00:00
igneum-labs
6134f51a66 Merge same-work-harness 7494b3f2 into master (gate: green on 7494b3f2, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:59:19 +00:00
igneum-labs
6d8fb44830 V6-07: the harness map page regenerated for the rows:v607-floor-memory cell
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:58:37 +00:00
igneum-labs
dd9686640b Class v6 census: the window trace on the signing program 2a1d6caab4c24564 (per-site ratio 1.0026, 1.021x of the foldrw control on the item share)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:57:42 +00:00
igneum-labs
6e3aabddce Merge master 5114f6ce1 into class-v5-foreign-capture-doc under the master-landing lock 2026-10-08 21:56:49 +00:00
igneum-labs
2fd2e70fea Cache-history case: the verdict reads SP1 verifies (calls minus context refusals); a context refusal is a cheap pre-check, never cached, re-read at every carrier (read from the 22:34 UK run: paid once, the invalid bytes answered from the cache, the real proof verified once)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:51:52 +00:00
igneum-labs
7494b3f250 Merge remote-tracking branch 'box/master' into same-work-harness
# Conflicts:
#	docs/plans/igneum-2.0-test-registry.json
#	tools/ci/batches/same-work-20261008-02.json
2026-10-08 21:51:48 +00:00
igneum-labs
910b75e9e2 V6-07: the registry rows GPU-05, CAP-02, UX-02 from the V6-07 cell (partial coverage, RUNNING by the map's rule; island none), batch v607-floor-memory-20261008T2059Z
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:51:44 +00:00
igneum-labs
9aded49aa3 Class v5 stored state: the foreign-seed capture amendment (fix 2 of node 2.0.2, the HEAL lane, 8 October 2026). Section 8's row "a state the verifier cannot reach" becomes the bounded scratch execution of the foreign selected-parent chain (the retryable refusal never ended on igneum-devnet-4: 6 chains and 11 islands at the epoch-3 cut); section 2a.1 gains the rule that streams are keyed by block hash, several candidates per epoch, each with a capture's retention; section 2a.5 carries the two cost rows (one D per candidate stream; the grinding and DoS face with the bound, the one-in-flight rule and the PoW-first condition named as properties). Measured rows: without the fix the lighter node never left its chain in 300 s; with it, +20 s and one tip and seed from +60 s.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:50:10 +00:00
igneum-labs
5114f6ce19 Merge ci-registry-identity 7ee367a8 into master (gate: green on 84e360ea, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:49:20 +00:00
igneum-labs
7ee367a831 Merge master cebafdcdc into ci-registry-identity under the master-landing lock 2026-10-08 21:49:16 +00:00
igneum-labs
10056a0b2c V6-07: the host bisect names 15d8162e0 (FixtureEnv field without the guest re-pin) as the 0-bytes fault; amendments
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:49:15 +00:00
igneum-labs
9609e49c0d p01-vectors: the prepare handshake feeds day D jobs and polls the worker with a line a second until prepared (the worker loads a finished prepare only between stdin lines: the 22:26 to 22:47 UK deadlock on the 5090); the self-test's fake worker reports prepared on a later line, one case three lines late
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:49:07 +00:00
igneum-labs
984f86b4ea same-work 02: the pool D1-pairing reader PASS on all three phases (every nonce, the share verifier's path, the day switch at 1572864), read back on build-1 at 22:45 UK
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:46:14 +00:00
igneum-labs
6dbf092689 same-work: the batch notes and contexts name no rig short name (the acceptance page rule, 22:4x UK); statuses unchanged
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:43:02 +00:00
igneum-labs
84e360ea63 The zone word scrubbed from two more batch notes landed after the branch point (the served registry)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:42:28 +00:00
igneum-labs
cebafdcdc2 Merge vendor-spare b7b2d494 into master: the checkout clean spares vendor/ (a main-repo run took the worktree's vendor node tree, build-9 run114)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:42:19 +00:00
igneum-labs
89fa30954b Merge master 9b880f2d9 into ci-registry-identity under the master-landing lock 2026-10-08 21:41:02 +00:00
igneum-labs
9b880f2d9b Merge class-v6-family-gate 57ed1e95 into master (gate: green on 188586ea, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:39:59 +00:00
igneum-labs
57ed1e95a4 Merge master 97b4d5b41 into class-v6-family-gate under the master-landing lock 2026-10-08 21:39:56 +00:00
igneum-labs
97b4d5b412 Merge verdict-cache-fix 3e31a67a into master (gate: green on 71323e68, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 21:37:02 +00:00
igneum-labs
3e31a67a90 Merge master 6190cbe5b into verdict-cache-fix under the master-landing lock 2026-10-08 21:36:59 +00:00
igneum-labs
6190cbe5be Merge same-work-harness d51fd3aa into master (gate: green on 4e97e868, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:36:08 +00:00
igneum-labs
d51fd3aa99 Merge master 6e9828968 into same-work-harness under the master-landing lock 2026-10-08 21:36:05 +00:00
igneum-labs
6e98289681 Merge hash-registry-1 71006a55 into master (gate: green on 5815191a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:34:44 +00:00
igneum-labs
b7b2d49487 remote-run checkout: vendor/ spared by the clean (a main-repo crate run on a worktree took its vendor/igneum-node tree and target; the enforced lane's read on build-9, run114, 8 Oct 2026)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:34:13 +00:00
igneum-labs
e65081f28a The zone word scrubbed from two batch notes (the served registry); a landing stopped by its pid file releases the master-landing lock (INT and TERM)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:33:51 +00:00
igneum-labs
71006a55ac Merge master 85d928b5b into hash-registry-1 under the master-landing lock 2026-10-08 21:33:45 +00:00
igneum-labs
b442183143 Merge census-chainseed 23526068 into master (gate: green on 798f2dae, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:33:36 +00:00
igneum-labs
23526068f2 Merge master 85d928b5b into census-chainseed under the master-landing lock 2026-10-08 21:33:33 +00:00
igneum-labs
188586ea77 family gate: batch family-gate-20261008c records section 6.13 (the chain-seed draw at db36d8060) on the registry rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:33:32 +00:00
igneum-labs
e7acb8b5e0 Merge master 85d928b5b into ci-registry-identity under the master-landing lock 2026-10-08 21:32:02 +00:00
igneum-labs
85d928b5bd Merge host-format-guard 9d07e780 into master (gate: green on e9914bc6, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 21:30:57 +00:00
igneum-labs
71323e6849 Merge remote-tracking branch 'box/master' into verdict-cache-fix 2026-10-08 21:30:18 +00:00
igneum-labs
0a39d95a0e verdict-cache-fix: igneum-pow back to master's tree (the release-2.0.0 freeze pairing for box node builds had been staged by a checkout and rode into 99b83bbba; the spec read-back read it red)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:30:18 +00:00
igneum-labs
4e97e86809 Merge remote-tracking branch 'box/master' into same-work-harness
# Conflicts:
#	docs/plans/igneum-2.0-test-registry.json
2026-10-08 21:28:29 +00:00
igneum-labs
276ac5c1f4 same-work: the three batches (01 the frozen object, 02 the chain-seed object with the node cell PASS x3, 03 the live class v5 object) recorded through test-record; every cell labelled on an island, not a network
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:28:17 +00:00
igneum-labs
9d07e780a6 Merge master a1a0a4d06 into host-format-guard under the master-landing lock 2026-10-08 21:25:37 +00:00
igneum-labs
5815191af6 pairing row: UTC stamps (the identity grep forbids local-time zones in the export list)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:24:09 +00:00
igneum-labs
167ed663dd The identity grep covers the served registry's sources; the map's and three batch notes' rig names scrubbed; the island label (main's word): every record measured on the 2.0 devnet after 20:00 UK reads 'on an island, not a network', stamped at record time and by --label-islands at replay
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:23:28 +00:00
igneum-labs
798f2dae1a Class v6 census: the chain-seed draw 2a1d6caab4c24564 on the frozen object (the engine's pair: seed af89be5d, era genesis, day 20730, node1 state) through the (c''') rule and the attempts census, PASS; the block-hash-era draw beside it as the comparison; registry run census-v6-chainseed-20261008-2230
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:23:10 +00:00
igneum-labs
99b83bbbaf The succession case's evidence in the tree (docs/plans/proving-enforcement/succession-360-window-300-vcache-7.json); the batch names it (the registry's evidence rule: a PASS names a file at HEAD)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:23:06 +00:00
igneum-labs
a1a0a4d062 Merge lab-signing-20 ca181a48 into master (gate: green on c6b10d27, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 21:22:38 +00:00
igneum-labs
ca181a4825 Merge master bd06d4339 into lab-signing-20 under the master-landing lock 2026-10-08 21:22:35 +00:00
igneum-labs
ccc7970c00 Merge master bd06d4339 into verdict-cache-fix under the master-landing lock 2026-10-08 21:22:33 +00:00
igneum-labs
bd06d43396 Merge registry-ux06 37d22cff into master (gate: green on 2b2ee1dc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:21:37 +00:00
igneum-labs
37d22cffd1 Merge master b0818d882 into registry-ux06 under the master-landing lock 2026-10-08 21:21:34 +00:00
igneum-labs
c5ee1ec072 same-work: context 03 (the live chain's class v5 object 0x81fbfa3aa413173f at epoch 2) as read back on build-1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:21:17 +00:00
igneum-labs
388af50067 V6-07: the aggregate and chain floors at 8,500 MiB from the measured aggregation peak; the rows and their consequences
docs/analysis/floor-memory-profile-2026-10-08.md: the 3060 and 4060 rows on the default, unoverridden job path (the served 0317 host on the V6-07 server: 3060 shard 11.4 s at 7,601 MiB, the whole chain 27.4 s at an 8,306 MiB aggregation peak, both VERIFIED; 4060 shard 16.3 s at 7,504 MiB VERIFIED, the chain aborts at the aggregation's 486 MiB allocation on 176 MiB free), the host's profile and refusal rows (exit 78 under the floor and beside the miner on both cards, the miner unharmed), the recursion constant isolated (no change of the device peak), the known-failed first server, the master-host 0-bytes fault with its NOT RUN rows, and the consequences per card tier. memory_profile.rs: aggregate and chain floors 8,500 MiB (an 8 GB card proves shards and is refused the chain before setup), tests re-pinned; suite 7 passed on box 3.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:20:21 +00:00
igneum-labs
b0818d8823 Merge census-rows-live 2291fa50 into master (gate: green on c5c069ae, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:20:19 +00:00
igneum-labs
2291fa5021 Merge master 6816f8b69 into census-rows-live under the master-landing lock 2026-10-08 21:20:16 +00:00
igneum-labs
6816f8b69f Merge ca3-coord-record 28eb2af7 into master (gate: green on 7868be22, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:19:21 +00:00
igneum-labs
28eb2af7e8 Merge master c0398732e into ca3-coord-record under the master-landing lock 2026-10-08 21:19:18 +00:00
igneum-labs
e9914bc6c2 Merge remote-tracking branch 'box/master' into host-format-guard 2026-10-08 21:18:56 +00:00
igneum-labs
e30e89f5d5 host-format-guard: the duplicate gate check withdrawn (the steward's tools/ci/guest-format-check.sh landed for the class, 29dda1e7d); the host guard, the manifest provenance and the lock takeover stay
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:18:56 +00:00
igneum-labs
c0398732e3 Merge class-v6-kits 226ec124 into master (gate: green on e8608cbc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 21:18:18 +00:00
igneum-labs
7e739904ec family gate: 6.13 names the signing object's column (era edc4fa84) after the hash lane's 22:00 ruling
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:15:26 +00:00
igneum-labs
bf806eec76 Merge remote-tracking branch 'box/master' into verdict-cache-fix 2026-10-08 21:13:58 +00:00
igneum-labs
738bc64314 verdict-cache-fix: proving/igneum-prove/elf/ back to master's served pair (the 17:58 pair had ridden in with the harness commit by a staged checkout; the release-manifest check read it red)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:13:58 +00:00
igneum-labs
226ec12433 Merge master 29dda1e7d into class-v6-kits under the master-landing lock 2026-10-08 21:12:43 +00:00
igneum-labs
c5c069aef6 Class v6 census: the live-dataset census on the frozen object db36d8060 (Phase 1 item (j)): hl-v6-all 4de7b836cc40a4ea and sixteen chain seeds on the chain's dataset with the node1 leaves under header-bound init words, uniform inside every window to the Poisson floor, F8 form 0.999x of the window model; F06's live half LIVE on every register and load; the registry run census-v6-live-20261008-2210
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:12:34 +00:00
igneum-labs
67447144f3 build-remote's worktree lock: a waiter on the same Mac takes over a lock whose holder pid is dead (the dead-holder class: a build-remote killed by its pid never ran its EXIT trap and the box kept the lock for the 3 h rule; the fix node's build-7 chain waited an hour, 21:11 to 22:11 UK)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:11:55 +00:00
igneum-labs
29dda1e7db Merge ci-guest-format 687e8f97 into master (gate: green on c97eae06, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:11:46 +00:00
igneum-labs
687e8f978f Merge master b1856699e into ci-guest-format under the master-landing lock 2026-10-08 21:11:41 +00:00
igneum-labs
66be38ebd0 The host-format guard's test: a held pin still loads (id and verify work); the format check names the source commit
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:10:47 +00:00
igneum-labs
b1856699e5 Merge cae8635124 dedbc740 into master (gate: green on cae86351, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 21:10:40 +00:00
igneum-labs
dedbc740cb Merge master 67d594c02 into cae8635124 under the master-landing lock 2026-10-08 21:10:37 +00:00
igneum-labs
67d594c023 Merge class-v6-floor-k-docs-2 abce7a45 into master (gate: green on b40b86a8, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:09:38 +00:00
igneum-labs
abce7a4518 Merge master af98d3a85 into class-v6-floor-k-docs-2 under the master-landing lock 2026-10-08 21:09:34 +00:00
igneum-labs
c6b10d2782 Merge remote-tracking branch 'build/master' into lab-signing-20 2026-10-08 21:09:04 +00:00
igneum-labs
7868be22df Igneum 2.0 register: the D5 row's live line (the epoch cut as a partition, FAILED on 2.0.1, the fix software rolled); Counter ASIC 3.0 status: the first post-roll lock, the second fresh-install class, the freeze tree's pairing and the signing id 2a1d6caab4c24564, the chain-paired packs, the prover decision, GOV-03 PASS, the succession PASS with the H and W proposal, the night rule and Phase 1, the founder's 21:33 word, the four-chain split and main's ruling
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:09:00 +00:00
igneum-labs
2858a46d6c Key succession across a boundary on the F01/F02 fix node: PASS (six refusals on the right ground, nothing paid; batch enforced-proving-20261008-02 on the cell harness:proving-enforcement); the H and W proposal's last row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:06:40 +00:00
igneum-labs
0ca323498a Merge remote-tracking branch 'box/master' into verdict-cache-fix
# Conflicts:
#	tools/ci/export-exclude.txt
2026-10-08 21:06:28 +00:00
igneum-labs
057a723185 test registry: the hash lane's batch 3 (the pairing class: the chain-paired packs, the signing object's P01 reference, the export tool's pairing check)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:04:30 +00:00
igneum-labs
2b2ee1dcc7 Test registry: UX-06 FAIL on the over-u64 coinbase incident and PASS on the fixed miner's canary (per-case batches, rule 26)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:02:23 +00:00
igneum-labs
b40b86a8ca Merge box/master b4a55fc65 into class-v6-floor-k-docs-2 (the steward's b4a55fc6 under it; the repeat batch trimmed to floor lane 2's rows ADV-05 and ADV-06, method model; the registry master's with that batch recorded) 2026-10-08 21:02:08 +00:00
igneum-labs
c97eae06c9 Merge remote-tracking branch 'box/master' into ci-guest-format
# Conflicts:
#	docs/plans/igneum-2.0-test-registry.json
#	tools/ci/checks.txt
#	tools/ci/pre-push.sh
2026-10-08 21:02:04 +00:00
igneum-labs
487d89c4c7 Relay agent: the wait on a task is its own process with a cap, never -Wait (PC 2, 8 October 2026, 21:28 UK: a task that started Igneum Miner.exe held the agent for the app's whole life, because Start-Process -Wait waits for every descendant on the inherited console; the relay channel to PC 2 went silent for half an hour). Now WaitForExit(timeout_minutes, default 60) on the task's shell; a task past its cap is ended by its pid with a log line and exit 124, never by a name. Test known-failed first in relay/test/service.test.mjs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 21:01:54 +00:00
igneum-labs
af98d3a857 Merge workers-page-nine 838f5e8a into master (gate: green on 0a1fdacd, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 21:01:35 +00:00
igneum-labs
838f5e8a69 Merge master b4a55fc6 into workers-page-nine under the master-landing lock 2026-10-08 21:01:32 +00:00
igneum-labs
b4a55fc658 Merge ci-rule33-canary 5cb3f61e into master (gate: green on 5cb3f61e, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 21:00:33 +00:00
igneum-labs
e8608cbc96 registry: the REV suite rewritten by its generator (the merge gate's red: the recorder's write left the suites in another order; the kit's record on R2-F03-R02 kept)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:58:29 +00:00
igneum-labs
b219e3e38a family gate: section 6.13, the chain-seed draw at db36d8060 through the acceptance at both era inputs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:56:29 +00:00
igneum-labs
cae8635124 /acceptance: the share text and metas count the registry's 190 cases in 18 suites (INT beside REV), not the earlier 128 in 16
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:55:31 +00:00
igneum-labs
118717e359 Merge remote-tracking branch 'box/master' into same-work-harness
# Conflicts:
#	tools/ci/p01-vectors.py
2026-10-08 20:55:02 +00:00
igneum-labs
1e04c14318 Batches: the stale repeat shadow-k-20261008-rows-repeat removed (a stopped chain's commit; floor-k-20261008-rows-repeat is the one that stands, on floor lane 2's word) 2026-10-08 20:54:31 +00:00
igneum-labs
02c1fea18d The recorder drops a lifted reason-only record when a real cell lands and never counts it in the combined decision (R2-F03-R01 read NOT RUN beside its PASS cell); the F03 batch re-recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:53:54 +00:00
igneum-labs
5cb3f61ec6 Merge remote-tracking branch 'box/master' into ci-rule33-canary
# Conflicts:
#	docs/plans/igneum-2.0-test-harness-map.md
#	docs/plans/igneum-2.0-test-registry.json
#	tools/ci/batches/kills-20261008.json
#	tools/ci/test-map.json
2026-10-08 20:53:44 +00:00
igneum-labs
4a6f17ebfc Merge remote-tracking branch 'box/master' into ci-guest-format 2026-10-08 20:53:19 +00:00
igneum-labs
47d9f50903 /prize: the disclosure prize's terms (a placed or measured adversarial implementation beating the served bracket, or a reproduced shortcut; not confirmations, synthesis-only results, outside-budget work or excluded classes; judged in-house, the finding served either way); the phrase leaves the served forbidden list on the founder's word of 8 October; the audit's prize row and the three closed open items; the og prize sub line within 80
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:53:08 +00:00
igneum-labs
0a1fdacd4b route-spill check: the unreachable-box probe points at port 1 (ssh URI), so a gate run on a build box reads it as down
On a box sshd answers on 127.0.0.1:22 and a forwarded agent logs in, so the bare address returned a slot line and the
gate was red on every box run while green on the Mac. The probe still exercises the same /bin/bash path through lib.sh.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:52:14 +00:00
igneum-labs
3be399f67b The host-format class (8 October 2026, 22:0x UK): the manifest names the pinned pair's source commit and guest input format; a host of another format refuses to build inputs for the pair; the gate reads the held state
The V6-07 sub-lane measured a host built from master writing guest input format 3 to the pinned 5 October guests (format 1) and reading "public values are 0 bytes, expected 328" on a 3060 and a 4060; the 0317 host built at the pin's source f503f491e proves the same shard in 14.1 s. Master's proving crate has carried inputs the pinned pair cannot read since the D4 flag landed without its pin (c693cb7c4), then stages 1 and 2 and the format tag.

By construction: proving/igneum-prove/elf/manifest.json carries source_commit (f503f491e9 for the served pair) and guest_input_format (1; absent reads as 1). Manifest::check_input_format refuses a host whose GUEST_INPUT_FORMAT differs, naming the source commit to build the prover from; the host runs it before every mode that builds a guest input (aggregate, chain, the fixture modes), not for id or the verify modes, so a held pin still answers --mode id and verifies proofs. Known-failed test: another format refuses with the source commit named; a manifest naming none is format 1; the embedded manifest either matches the code or Pinned::load's callers refuse. tools/ci/guest-format-pin-check.sh (self-tested three ways, in the gate): a code format that differs from the pinned pair's is red unless the manifest names the pair's source commit, the held state, in which the kit's prover is built from that commit, never from the tree.

The 2.0.2 kits ship the served 0317 pair built at f503f491e (the shipper's rule tonight); the host that writes the layout the manifest names rides 2.0.3 with a card-measured proof.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:52:05 +00:00
igneum-labs
bf3be0f0cb Merge ci-f03-manifest 8242849d into master (gate: green on aa29c4bc, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:51:07 +00:00
igneum-labs
8242849d8a Merge master a60586e20 into ci-f03-manifest under the master-landing lock 2026-10-08 20:51:04 +00:00
igneum-labs
f521c4fcfd Merge commit 'a60586e20' into site-2.0-followup 2026-10-08 20:50:48 +00:00
igneum-labs
cf1f3803ca registry: OPS-03 manifest cell recorded with a real evidence path
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:50:48 +00:00
igneum-labs
891bda580c The guest input format moves with the pinned guests: a GUEST_INPUT_FORMAT bump without a change under proving/igneum-prove/elf/ is refused at the merge; the gate reads the elf manifest's guest_input_format against the source constant (a pre-provenance pin is a named line); self-tests
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:50:45 +00:00
igneum-labs
f1b2dd2981 same-work: the two job contexts (01 the frozen object 0x4de7b836cc40a4ea, 02 the chain-seed object 0x2a1d6caab4c24564) as read back on build-1 at 21:49 UK
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:50:37 +00:00
igneum-labs
1d41ecc687 Merge master 4066512f into site-2.0-followup (registry: OPS-03 manifest row re-recorded)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:50:25 +00:00
igneum-labs
9e5d7da1ce V6-07: one floor patch; the canonical copy carried no grow_for_main and built a server that overflows its key buffer at prove
proving/prover-floor/sp1-gpu-6.8.1-floor.patch and tools/fleet/floor.patch are now byte-equal to tools/fleet/floor-v5.patch (the complete patch: the key buffer grown for the main traces, the pool release threshold, the stage hook on a panic). Measured 8 October 2026 20:5x UK: the server built from the old canonical copy (floor-build.py's input; sha 75d0b4be) panicked at sp1-gpu/crates/jagged_tracegen/src/lib.rs:240 "range end index 37428736 out of range for slice of length 36700160" on the first recursion prove (the RTX 4060, chain mode); the server built from floor-v5 (db37c38b) proves. box-setup.sh re-pinned to the one sha.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:49:20 +00:00
igneum-labs
a60586e203 Merge pool-registry 462dfd97 into master (gate: green on 8ab851ce, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:48:42 +00:00
igneum-labs
462dfd97fa Merge master 4066512f4 into pool-registry under the master-landing lock 2026-10-08 20:48:39 +00:00
igneum-labs
b4545723b6 Test registry: the rows that name shadow-k.md moved by the repeat batch floor-k-20261008-rows-repeat (ADV-05, ADV-06 floor lane 2's on its word, method model; POW-03, POW-07 the steward's; no decision changed) 2026-10-08 20:46:23 +00:00
igneum-labs
5069844e8e Merge box/master 4066512f4 into class-v6-floor-k-docs-2 (rule 26: master's map, page and registry taken) 2026-10-08 20:46:22 +00:00
igneum-labs
de6f034f51 Rule 33: the fresh-install canary record (tools/ci/canary/<sha>.json, one file per sha with an artefacts list) and its check; publish-manifest.sh and publish-public.sh refuse an entry whose sha has no PASS record for its own artefact; the canary cell under INT-07 (BLOCKED tonight); the merge replays modified batches too (the kills re-record reaches master's rows); the identity words out of the map
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:46:09 +00:00
igneum-labs
7eb0bce671 Test registry: the rows that name shadow-k.md moved by the repeat batch shadow-k-20261008-rows-repeat at this landing (no decision changed; named per owner) 2026-10-08 20:45:54 +00:00
igneum-labs
022810e775 Merge box/master 4066512f4 into class-v6-floor-k-docs-2 (rule 26: master's map, page and registry taken) 2026-10-08 20:45:54 +00:00
igneum-labs
4066512f4d Merge finality-native-plan acd2f5ba into master (gate: green on 6932d4c3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:44:35 +00:00
igneum-labs
acd2f5baa5 Merge master f2668bf98 into finality-native-plan under the master-landing lock 2026-10-08 20:44:32 +00:00
igneum-labs
20075d2989 registry: R2-F03-R02 leaves the map's not-run table now that the kit's cell names it; recorded RUNNING
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:44:26 +00:00
igneum-labs
54009b5408 same-work: the P01 driver prepares the day D+1 pair before the first job across the boundary (prepare, prepared, prepare-failed and a prepare-0 worker in the self-test); the spec page carried for the readers until ci-f03-manifest lands
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:44:19 +00:00
igneum-labs
4f7b4292f0 registry: the kit batch cites paths only in its evidence field (the page, zip 4, the emulation log on build-1) with the reading in a note; recorded RUNNING on R2-F03-R02
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:44:04 +00:00
igneum-labs
aa29c4bc5d REV and INT generators keep evidence_records, blocked_on and method_recorded on regeneration (a regenerated suite dropped every recorded cell; self-tests assert they survive)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:52 +00:00
igneum-labs
4cb5a53033 registry: the kit's cell names master's case id R2-F03-R02 (REV-F03-2 renamed on master) and the batch carries its method (GPU); re-recorded, the map page regenerated
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:47 +00:00
igneum-labs
f2668bf98e Merge ca3-coord-record ae14a248 into master (gate: green on 8d4a9abf, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 20:43:33 +00:00
igneum-labs
ae14a248e5 Merge master 536c3c26e into ca3-coord-record under the master-landing lock 2026-10-08 20:43:30 +00:00
igneum-labs
1233ff9252 Merge build/master 9cfaadbe7 into class-v6-kits (master's registry, harness map and gate-remote.sh taken; the kit's batch kit-class-v6-20261008-01 re-recorded on master's registry and the map page regenerated)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:21 +00:00
igneum-labs
4787bd0d51 Workers page: one card per entry of the merged boxes[] (nine boxes), the Mac mini card, the main site icon set, no per-box feed map
The page drew build-1 to build-3 only: a hardcoded three-entry feed map fed the cards while merge-workers.mjs on build-1
already carried nine boxes. The map and its live-feed loader are gone; every card comes from the merged workers.json.
build-3 reads "down since 16:40 UK, Hetzner switch fault" when its feed is absent or stale; a box with no builds log yet
reads "provisioning, first build logged when the sources land". The MacBook card says nothing builds there except the one
DMG and the mini carries macOS binaries from tonight; igneum-mini (the Mac build box, M6) has a server row and a card that
read "no report yet" until its collector pushes. The head carries site/index.html icon links (the ember mark as an SVG
data URI, favicon.ico, favicon-32.png, icon-192/512, apple-touch-icon.png).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:14 +00:00
igneum-labs
735072dfd3 F03 batch: GOV-01 cites the fork's freeze file as a box path (the recorder's tree rule)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:07 +00:00
igneum-labs
ca7c20adce Merge build/class-v6 db36d8060 into class-v6-kits (the hash lane's V6-02 re-export and its green suite: emit.rs, generator.rs, tests/v6fold.rs; the merge gate's three v6fold reds)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:43:06 +00:00
igneum-labs
3e488a6ae7 shadow-k: the placed gated 64-register window core (9.45 pJ per lane-op ASAP7, k 0.77 at the lock at N3; the board 2.0x node-for-node, 2.45x a node ahead; the window's placed residual +0.23 of k)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 86e5b0fb2 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:29 +00:00
igneum-labs
3a85cd8298 chip-model: delete the simulation traces after each power report (a full pod disk killed four runs)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 14d4f3a32 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:29 +00:00
igneum-labs
c69e0ce6a5 shadow-k: the placed gated 32-register base (6.7 pJ per lane-op ASAP7, the board 2.4x node-for-node and 2.8x a node ahead at the lock), the 8 KB scratch row (104 pJ per read at N3, k 0.074 against the L2 hit)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 07029f7ee (86e5b0fb24) for the box mirror master
2026-10-08 20:42:29 +00:00
igneum-labs
17e9fa28cf shadow-k: the mixed-resource lane's FP32 units routed (6.6 to 7.1 pJ per op ASAP7 as an upper bound, k 0.63 to 0.68 at the lock at N3)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 089546fb1 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:29 +00:00
igneum-labs
aa4ef20448 shadow-k: the time-multiplexed core built (8.8 pJ, not the lever), the connected-state variant on the gated window core (6.3 pJ per lane-op, k 0.51 at the lock at N3), the lanes' agreement on the window's cost
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 08447ca97 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:28 +00:00
igneum-labs
a64bf24c74 shadow-k: the adversary's gated rows (4.5 and 6.2 pJ per lane-op ASAP7; the window's residual +0.13 of k), the placed ungated base (11.3 pJ), the ICG simulation model
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 9737ffb26 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:28 +00:00
igneum-labs
544b126e0e shadow-k: the window's measured GPU side (no spill, 83 and 67 percent occupancy, at most 5 percent per load); the time-multiplexed core, the connected-state draw, the simplified FP32 units and the pod mode
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 26844fde7 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:28 +00:00
igneum-labs
b4bf487dd0 shadow-k: the adversary's 64-register core (the live-state analysis: 95 percent of the window necessary across every wait under the fold-reads-all rule; the state's cheaper forms modelled; the gated rows pending), the gated variants' configs, livestate.py
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of f1ddf0b39 (86e5b0fb24) for the box mirror master
2026-10-08 20:42:27 +00:00
igneum-labs
536c3c26e9 Merge ux-01-batch-2 09ecdcd7 into master (gate: green on 3846f469, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:42:25 +00:00
igneum-labs
09ecdcd7d3 Merge master 9cfaadbe7 into ux-01-batch-2 under the master-landing lock 2026-10-08 20:42:22 +00:00
igneum-labs
fde300abc8 Key succession on the live object: the H and W proposal with the fast-time evidence (Phase 1 item d, for the 08:00 read-back; W one epoch of 3,600 DAA, H the first epoch boundary an epoch after a clean 24-hour run; pin C as the next pair, the served pair as prior)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:41:31 +00:00
igneum-labs
8ab851ce26 registry: pool batch 03 at a43dbc6c with its evidence page docs/analysis/pool/pool-pair-2026-10-08.md (UX-05 vote-key PASS in the crate; the devnet-4 live pair NOT RUN, its wrong_hash an unsynced node's unsettled class v5 state, not a generator skew; the guard on pool-2.0; two 2.0 gaps closed)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:41:26 +00:00
igneum-labs
9cfaadbe7a Merge class-v6-adversary-docs-3 5d9b47cb into master (gate: green on c29dcef3, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:41:20 +00:00
igneum-labs
5d9b47cb76 Merge master 98a4aafdc into class-v6-adversary-docs-3 under the master-landing lock 2026-10-08 20:41:17 +00:00
igneum-labs
e9ab272d3f build.mjs: the devnet scrub's word boundary written as a regex escape, not a control character
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:41:05 +00:00
igneum-labs
141697b34f build.mjs: the acceptance inject's call closed (the scrub comment had swallowed the inject's file argument)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:40:36 +00:00
igneum-labs
98a4aafdc2 Merge fleet-pidkill-20261008 a4ab1a96 into master (gate: green on 62afa712, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:40:06 +00:00
igneum-labs
a4ab1a969a Merge master b2a241f6c into fleet-pidkill-20261008 under the master-landing lock 2026-10-08 20:40:03 +00:00
igneum-labs
735879441c Fast-time two-node cache-history case (review B F01, Phase 1 item c): a proof's bytes refused once for context pay later as their own record from the cached facts with no second verify; invalid bytes are refused again from the cache
Three local nodes at fast time; the real proof is one of the chain's own blocks, exported from H1, cut by igneum-prove-export and proven compressed by igneum-prove-host on the box's CPU inside the run, so its statement is H1's native one. Verdict: paid once; H1's verifies.run grew by exactly 2 (the real proof, the invalid bytes); cacheAnswers by at least 2; the context refusal read; the invalid bytes refused again with no new verify. Needs the node's verifies counters (verdict-cache-fix-node, the status JSON) and node and host on the same pair.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:39:40 +00:00
igneum-labs
b2a241f6c5 Merge class-v6-family-gate 8d2c5fd2 into master (gate: green on 9f7aacbb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 20:38:55 +00:00
igneum-labs
8d2c5fd2ae Merge master d078291b1 into class-v6-family-gate under the master-landing lock 2026-10-08 20:38:52 +00:00
igneum-labs
d078291b1b Merge ship-docs-rule33 125242d2 into master (gate: green on e0d071a8, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 20:37:53 +00:00
igneum-labs
125242d299 Merge master 31cc3d1bf into ship-docs-rule33 under the master-landing lock 2026-10-08 20:37:50 +00:00
igneum-labs
3846f469a4 Merge remote-tracking branch 'build/master' into ux-01-batch-2 2026-10-08 20:35:25 +00:00
igneum-labs
6932d4c317 The native finality runs of 9 October 2026: the 40/40/20 case past the window with equivocation (F04), the pause-only alternative with backfill, missing history and the old keys returning, authority succession and strip, restart, certificate arrival order, seed boundaries, the inter-chain verifier on a recovery lock (I03), V6-09's cold verification on the minimum validator, and the two-node cache-history test (F01); boxes and clocks
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:34:46 +00:00
igneum-labs
c13fd2a10c Fast-time proving enforcement, succession mode: the rejoin keeps the attacker's miner running and waits up to 600 s (a paused miner never rejoined in 300 s, twice at 21:2x UK)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:34:34 +00:00
igneum-labs
c29dcef333 Batch adversary-20261008-placed-8lane: adversary:d2b's evidence cited at the document (section 13); the mf results file stays on the branch until it lands (the recorder's tree rule since 7d64dfdc); the batch recorded on master's registry 2026-10-08 20:32:56 +00:00
igneum-labs
62afa71232 fleet: every stop goes through a pid file; pkill and killall are gone from the live tree
The founder's word (20:21 BST 8 Oct 2026): pkill and killall refuse by construction on every box and pod (exit 97). lib/pidkill.sh
(kill_pidfile, kill_children by parent pid, kill_sock_owner through ss -xlp) is the shared form; box-prover.py finds the SP1 server by
the pid owning its socket; lib/box.py, box-kill.sh, kill-node.sh, the rig scripts (box-ember, box-rig, box-matrix, box-floor-v5),
lib/standing.py and publish-2-move.py stop by pid files; box-dn3.sh writes node, miner-loop and miner pids and uses pidkill;
fleet-puller.sh and dn3-kill.sh call fleet-stop.sh. Seventeen devnet-2-era scripts that only ever stopped by name move to
tools/fleet/retired/ with a README.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:32:25 +00:00
igneum-labs
fd232a513d Merge box/master 7d64dfdca into class-v6-adversary-docs-3 (rule 26: master's map, page and registry taken; the adversary cells re-added with ADV-05; the batch recorded) 2026-10-08 20:32:17 +00:00
igneum-labs
31cc3d1bfc Merge pool-guard-docs e09652d8 into master (gate: green on a3aaea60, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:32:07 +00:00
igneum-labs
e09652d816 Merge master 7d64dfdca into pool-guard-docs under the master-landing lock 2026-10-08 20:32:03 +00:00
igneum-labs
8d4a9abf79 Counter ASIC 3.0 status: the freeze tree 1a938abe4 and the review verdicts, the hash lane's acceptance fault and its fix, the first fixed-miner block and the roll's stages, the house ban and the 3847 stall, the pool pair's corrected cause, lock 270's fractions, V6-08 and P22 landed, the F03 and evidence-class landings, the night rule
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:31:57 +00:00
igneum-labs
9f7aacbb7f Class v6 family gate, 6.12: the pairing read back at the final class-v6 sha 1a938abe4 (both pack ids equal to the ac86d7910 read); master merged (the steward's evidence rule: a new evidence file lands free)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:31:48 +00:00
igneum-labs
5e3775576c Merge remote-tracking branch 'build/master' into class-v6-family-gate 2026-10-08 20:31:47 +00:00
igneum-labs
1c10a52d53 /acceptance: the registry's rig and devnet names scrubbed on the served page and the runtime reply (the identity list; the INT suite's case text named a rig)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:31:20 +00:00
igneum-labs
e0d071a861 Release rules 17 and 18: no entry without a fresh-install canary on the live network (rule 33); a class gets a fix clock inside the hour
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:30:02 +00:00
igneum-labs
7d64dfdca4 Merge ci-evidence-added 5edc4971 into master (gate: green on 8e07b66f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:29:58 +00:00
igneum-labs
5edc497133 Merge master b500c68e5 into ci-evidence-added under the master-landing lock 2026-10-08 20:29:55 +00:00
igneum-labs
f466cf310c UX-01 batch: the harness map page regenerated from master's map plus the pc:install-update cell (the gate's page check; the registry stays master's for the landing's replay)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:28:23 +00:00
igneum-labs
097ef101a2 Merge remote-tracking branch 'build/master' into ux-01-batch-2 2026-10-08 20:28:19 +00:00
igneum-labs
12faf45f8c F03: harness:release-manifest and harness:same-work cells on the map; R2-F03-R01 PASS on release-2.0.1 01baa863 (every component builds from the manifest on build-4); the F0 page names the final tip
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:27:37 +00:00
igneum-labs
80a90155da class v6 kit: the harness map page regenerated for the kit's cell (the merge gate's red); arc-v6-bench.ps1 reads the generator 6 kit from the fresh dir fetch-class-v6-kit-20261008-g6 (a fetch into the old dir left zip 2's files on PC 2)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:25:47 +00:00
igneum-labs
a3aaea6008 Pool record: the devnet-4 pair's class (no job on an unsynced node's state) in docs/plans/pool.md 11a and the test map's suite:pool coverage (state_provider::tests::an_unsynced_node_hands_the_pool_no_state_and_no_job; 58700c4c on release-2.0.2, a43dbc6c on pool-2.0, 52 of 52 on build-6, known-failed first against the 3642cc34 provider); the freeze read-back (igneum-pow/src tree 93c36844 on every 2.0.x line)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:25:03 +00:00
igneum-labs
3670f84aee Merge box/master b500c68e5 into class-v6-adversary-docs-3 (rule 26: master's map, page and registry taken; the adversary cells re-added with ADV-05; the batch recorded) 2026-10-08 20:23:20 +00:00
igneum-labs
5e8721164b Batch adversary-20261008-placed-8lane: method model on both cells (the lane's word, 21:3x UK); ADV-05 joins adversary:mf-placed as RUNNING in the map at the sync 2026-10-08 20:23:18 +00:00
igneum-labs
8e07b66fad Evidence rules: a new evidence file lands free (rule 2 binds modified and deleted files); the recorder refuses a missing or directory tree path at record time; the kills batch cites the two experiments' own files, not the class-v6 directory
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:23:03 +00:00
igneum-labs
b500c68e5c Merge p22-stage-2 2d5509a9 into master (gate: green on 2d5509a9, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:21:13 +00:00
igneum-labs
8e17a32d5a UX-01 batch: method team-reported (the recorder's rule since 83177aca: never conflated)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:20:58 +00:00
igneum-labs
32cf9e534c Test registry: UX-01 RUNNING as a batch for the merge tool to replay (tools/ci/batches/ux-01-20261008-win-2.0.0.json on manifest f49904fe; the cell pc:install-update in tools/ci/test-map.json for UX-01 (team-run evidence only; the P10 study NOT RUN until unaffiliated participants are recruited), UX-07 (the install classes) and OPS-03 (the update path's read-back); the evidence file docs/plans/evidence/UX-01-20261008.md with the read-back lines so far). The registry and the map page are not in this commit: the landing replays the batch onto master's registry and the page follows the steward's regeneration (rule 26 refused four landings that carried them)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:20:36 +00:00
igneum-labs
cd4a58d4cf Merge master 1dd05f020 into class-v6-family-gate under the master-landing lock 2026-10-08 20:20:04 +00:00
igneum-labs
1dd05f020a Merge amd-intel-energy-registry-docs 78a124eb into master (gate: green on c64f84b0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:18:52 +00:00
igneum-labs
db36d8060b class-v6: program.h's load and byte defines keep their exact text (the pinned packs byte for byte); the executed-count note is a line of its own on the window packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:18:49 +00:00
igneum-labs
78a124eb3e Merge master 9fd1d6c68 into amd-intel-energy-registry-docs under the master-landing lock 2026-10-08 20:18:49 +00:00
igneum-labs
9fd1d6c687 Merge class-v5 742ffcb4 into master (gate: green on 742ffcb4, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 20:16:41 +00:00
igneum-labs
b10634d3a0 Fast-time proving enforcement, succession mode: the attacker's miner is paused for the rejoin (its one thread kept the dead chain ahead for over 150 s at 20:12 UK; the after-window record went unread) and restarted after; the rejoin waits up to 300 s
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:15:18 +00:00
igneum-labs
742ffcb4e1 class v5 design page: the Arc job staged but held on the dl host, the kit's registry cell
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:14:11 +00:00
igneum-labs
23d035a166 Merge build/master into class-v6-family-gate: the CI steward's family-gate cell and batch taken as master has them; this landing's batch family-gate-20261008b moves the rows with their evidence; 6.12's subset census at 64 of 64 (0 hot sets, 0 over 1.2x)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:13:17 +00:00
igneum-labs
635d5e12e4 Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 20:12:49 +00:00
igneum-labs
377758b2a6 /acceptance rebuilt from the merged registry 2026-10-08 20:12:26 +00:00
igneum-labs
e0da6e4075 Merge remote-tracking branch 'box/master' into site-2.0-followup
# Conflicts:
#	docs/plans/igneum-2.0-test-registry.json
2026-10-08 20:12:26 +00:00
igneum-labs
c64f84b0fb Merge box/master 7891dd541 into amd-intel-energy-registry-docs (rule 26: master's map, page and registry taken; the lane's cells bench:amd-intel-energy re-added; batches re-recorded) 2026-10-08 20:12:15 +00:00
igneum-labs
a062ab239b GPU-03 AMD and Intel cells: the test-map cell bench:amd-intel-energy (GPU-03, partial) and its batch amd-intel-energy-20261008-01 (method GPU, NOT RUN in progress, evidence docs/analysis/class-v6/amd-intel-energy.md on master a49870ac), the harness map page regenerated; the registry write is the per-cell recorder replay at the merge, not hand-edited (the batch file from amd-intel-energy-registry c4bcd1c59; the map cell and page follow in the sync) 2026-10-08 20:12:14 +00:00
igneum-labs
e3d4abd22a Merge box/master 7891dd541 into class-v6-adversary-docs-3 (rule 26: master's map, page and registry taken; the lane's cells adversary:mf-placed adversary:d2b re-added; batches re-recorded) 2026-10-08 20:12:11 +00:00
igneum-labs
c4dfed3dac registry: the class v6 kit's cross-platform fingerprint cell (kit:class-v6-fingerprints) answers REV-F03-2's worker half; batch kit-class-v6-20261008-01 writes RUNNING (CPU, CUDA 4090, Metal, Apple OpenCL equal on the generator 6 packs; the PC rows and the node and pool halves open)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:11:52 +00:00
igneum-labs
c0608a28be Merge v608-proving-tasks 10575e1e into master (gate: green on 10575e1e, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:11:49 +00:00
igneum-labs
7db54dcbad Merge remote-tracking branch 'box/master' into ci-f03-manifest
# Conflicts:
#	tools/ci/README.md
#	tools/ci/checks.txt
#	tools/ci/pre-push.sh
2026-10-08 20:11:35 +00:00
igneum-labs
7891dd5418 Merge ci-int-suite 9e5047bc into master (gate: green on f199ead1, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:10:25 +00:00
igneum-labs
9e5047bc6a Merge master 1b03d65cf into ci-int-suite under the master-landing lock 2026-10-08 20:10:21 +00:00
igneum-labs
d615914998 ECO-05's sentence made exact (the second sustaining world on the RX 7600's modelled efficiency point, the metered row due in the morning; the verdict FAIL either way) on the litepaper, the economics page and the facts row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:09:38 +00:00
igneum-labs
2d5509a926 Merge remote-tracking branch 'box/master' into p22-stage-2
# Conflicts:
#	proving/igneum-prove/host/src/bin/pin.rs
#	tools/ci/export-exclude.txt
2026-10-08 20:07:50 +00:00
igneum-labs
1b03d65cfa Merge 89be94880 89be9488 into master (gate: green on 89be9488, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:07:46 +00:00
igneum-labs
93fb1a4f53 Merge floor-eco-record-02 6a4efc39 into master (gate: green on 6a4efc39, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:07:38 +00:00
igneum-labs
b0e2497e9c class v5 design page: both full gates GREEN on box 2, the master merges pushed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:07:33 +00:00
igneum-labs
195897117d Merge worker-select-pass 145e9ee3 into master (gate: green on 145e9ee3, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 20:07:26 +00:00
igneum-labs
3f6f9d36de Merge key-succession-pin-tool 84b64111 into master (gate: green on 84b64111, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 20:06:05 +00:00
igneum-labs
c134c2ba77 Class v6 family gate, 6.12: the final tree (class-v6 ac86d7910, the packs' draw read back equal on both ids) through the acceptance under the harness's predicate and the crate's own, which agree on 678095100's fix (r 0.144 and 0.137 at width 4, 0 exhausted in 6,000 eras, the floors at 0 to 0.5 percent, the fold's half of the bit-R class): PASS; the registry batch at manifest ac86d7910, method native
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:05:56 +00:00
igneum-labs
d033df2d16 multi-family adversary: section 17 bound restated on the connected-state class's own shape (the prefix form 8 nJ per hash; the bracket moves at most 0.02x)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of class-v6-adversary bb8cf8c30 over master 413880473: the document whole, the batch adversary-20261008-placed-8lane recorded through tools/ci/test-record.mjs on master's registry copy, the two map cells added to master's map, the harness page regenerated; tools/chip-model/mf stays on the branch.
2026-10-08 20:04:15 +00:00
igneum-labs
548a508f57 The 2.0.1 Windows entry on the index and the manifest (2.0.1 on every platform; 2.0.0 withdrawn, the line under the release note), OPS-03's row moved with it through the recorder
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:04:01 +00:00
igneum-labs
f199ead158 P01 part A, the CUDA half complete: four packs on three cards, twelve runs, zero disagreements
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:03:26 +00:00
igneum-labs
a2e1f8c239 Merge ca3-coord-record d3909f2f into master (gate: green on d3909f2f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 20:03:23 +00:00
igneum-labs
952cdc240a V6-10: pin C held off master on p22-stage-2-pin (056a5cb74); proving/igneum-prove/elf/ back to master's served pair for the stages' landing (the 2.0.1 kits embed master's elf/ and their start check refuses another top pair)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:02:11 +00:00
igneum-labs
a13c1e7709 pre-push: the F03 check line's stray trailing quote removed (the bash -c string never closed; the check was red on its own syntax)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:01:46 +00:00
igneum-labs
6a4efc39ea ECO-05 batch 02 on the RX 7600's class v6 cell (15.79 MH/s measured, the knee 5.4 modelled; the metered knee is batch 03) and the B580's class v6 cell (11.0 measured, watts estimated): one more sustainable world (10R at 0.10, by 1.6 percent on the 7600's entry), 0 of 108 cells pass the envelope, RUN FAIL unchanged; the driver's override hook carried; the cubes and the registry rows recorded at manifest 89bef9af
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 20:00:11 +00:00
igneum-labs
4138804732 Merge hash-registry-1 c8706d64 into master (gate: green on c8706d64, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:59:34 +00:00
igneum-labs
53f1b24596 class-v6: V6-02 re-done: the executed load and byte counters (loads_per_hash_executed, bytes_per_hash_executed) are read by the emitters alone; the acceptance and the draw read the drawn count as before (the first form, 00c7e2dc3, routed the executed count into the acceptance and moved every reg64 verdict: hl-v6-all drew 0x1626c5853aa84261 instead of 0x4de7b836cc40a4ea, found by the re-export's read-back)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:59:06 +00:00
igneum-labs
056a5cb74b V6-10: the repin note with every row read back (three deterministic builds, the id read-back on two boxes, the old and new fee mode compressed proofs VERIFIED under the new pair, the node equality replay, the RPC flag class)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:58:48 +00:00
igneum-labs
f29382aeb3 Merge pool-review-b-docs 85edf042 into master (gate: green on 85edf042, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:58:33 +00:00
igneum-labs
dad3727121 gate-remote.sh: ci mode on box 2 (the box carries the overlap browser; local mode on a box reads two environment reds)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:57:49 +00:00
igneum-labs
8a73b694fb gate-remote.sh: ci mode on box 2 (the box carries the overlap browser; local mode on a box reads two environment reds)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:57:49 +00:00
igneum-labs
89be94880a The 2.0.1 Mac and HiveOS entries on the index and the manifest with OPS-03's row through the recorder (site:manifest, NOT RUN in progress); the reference population and the cost per accepted unit of work served on the litepaper and the facts page (floor lane 3's table on master at 4cb82734); the box master merged
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:57:25 +00:00
igneum-labs
b234c2063e Fast-time proving enforcement, succession mode: the second record waits the full phase; the clocks that fit two records per phase (360 floor, 300 window)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:56:47 +00:00
igneum-labs
d3909f2f9a Counter ASIC 3.0 status: the kit on the post-review packs (four of six), F05 with both sides, V6-10's repinned ids, the research lane's 21:00 copy on master 4cb82734, the census lane closed with its cell PASS, the 21:00 copy's third refusal under the evidence rule
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:56:25 +00:00
igneum-labs
bbcf0c06ba V6-10: the new fee mode's fixture from the D4 node 930b6322 (proving_payment_activation_daa 0, build-8 fast time, block 149; the exporter replayed 149 segments with every state root equal to the node's)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:55:50 +00:00
igneum-labs
ea3ca1faea class v5 design page: the freeze wording for the class v6 kit, the master merges and the full gates
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:55:47 +00:00
igneum-labs
f9f6176f95 Test map: the site:manifest cell (OPS-03, partial coverage: the manifest regenerates from its sources; the separation is the node suites') so a manifest regeneration moves its row through the recorder
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:55:44 +00:00
igneum-labs
10575e1e11 V6-08 build, the fleet side: box-prover.py posts each claim as a lease (igneum_claimSegment) and skips a refusal, the chain-health backpressure gate (blocked, re-executing, discontinuous, lagging, stalled, finality paused, unreachable), TASK=segment|shard|auto with one-shard tasks under the segment line and MAX_SHARDS, the preflight (host and export sha256 against the shipped manifest, --mode id against the node's pinned pair, ldd, nvidia-smi, exit 4 naming the file), the fourth outcome abandoned (lease, restart) and the flow line; prover-outcomes.py reports abandoned, the kind column and the conservation identity per kind; both self-tests known-failed first, the gate runs box-prover's
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:55:43 +00:00
igneum-labs
89bef9af81 Merge ca3-coord-record fbcdb12d into master (gate: green on fbcdb12d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:55:15 +00:00
igneum-labs
4cb827345c Merge counter-asic-4-docs-3 ad2133c6 into master (gate: green on ad2133c6, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:55:03 +00:00
igneum-labs
89c0f8f9c8 docs/build/compatibility.md held at master's copy (its label moves with its registry row EVM-01, the reference-apps lane's)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:38 +00:00
igneum-labs
0372cdca31 class v6 kit: gate-remote.sh runs the full gate over the kit tree on a build box (the class-v5 script)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:31 +00:00
igneum-labs
fef3a90773 p01-vectors: the job-context form (--job-context, --phase 1|2|3): each phase on its range and pack, phase 2 split at the boundary nonce with the boundary block in the evidence, a boundary outside phase 2 refused
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:28 +00:00
igneum-labs
0e279adcb0 V6-07: the host's row from the lesser of the engine's grant and its free reading; prover-floor.md names the free-memory rule
The window lane's engine half (reviewb-202 4fcdedad) grants a fixed proof budget beside the miner (7,532 MiB plus 10 percent) while the card's free figure can be under it (a 12 GB card beside the 6.1 GiB miner: 6,159 MiB free), so memory_profile::lease_reading takes the lesser of IGNEUM_PROVE_MEM_BUDGET_MB and IGNEUM_PROVE_MEM_FREE_MB when both are set; test lease_takes_the_lesser_of_grant_and_free. Suite on box 3: 7 passed.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:26 +00:00
igneum-labs
b2a55b69d0 The manifest and the download index held at master's copies for this landing (the 2.0.1 entries move with their registry row OPS-03 through the recorder, on the next landing)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:21 +00:00
igneum-labs
fe1a0804c7 Merge build/master 94889a656 into class-v6-kits (the counter-asic-4 code revert 867dbfe8 landed; the frozen class-v6 tree on master)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:20 +00:00
igneum-labs
83b0d16808 class v5: gate-remote.sh runs the full gate (tools/ci/pre-push.sh) over the worktree on a build box, the kits-remote shape
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:54:13 +00:00
igneum-labs
e7f67d0106 Merge census-registry-v6 49941c9d into master (gate: green on 49941c9d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:54:05 +00:00
igneum-labs
94da2c09c5 Merge build/master 94889a656 into class-v5 (the counter-asic-4 code revert 867dbfe8 landed; the frozen class-v6 tree on master)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:53:27 +00:00
igneum-labs
145e9ee3fd F10 rows, I05 epoch tag, I06 pack geometry rule across the three hosts
Rows: docs/analysis/review-2026-10-08-b/f10/rows.md with the pod rows (5090: steady
70.4 MH/s select against 63.7 full, 86.2 against 88.7 J per 2^24 batch; 3090 at the
card's clock 30.1 against 27.6, 184.6 against 197.9 J; the 3090 pod's power cap at
210 MHz named per run; ptxas 92 and 87 registers, no spills) beside the kernel timer,
the emulation and loader logs, the mini's geometry and serve logs. serve-bench.sh reads
a kit pack's seeds from program.h, execs the worker in its coproc (the recorded pid
and the CPU seconds are the worker's).

I05: every worker's found line carries a fifth field, the epoch the hash was computed
under (16 hex): CUDA and OpenCL from the pair, Metal from the job; select-check.sh and
serve-check.sh assert it, the swap case with pack B's epoch. The miner reads four or
more fields.

I06 (gate INT-10): one normative geometry rule. packfile.h reads the word count at
64 bits and refuses a count above 2^32 - 1 and a log2 that is not the floor of log2 of
the count; proto-metal/main.swift gains packGeometry with the same rules and refusal
words, sizes the day's dataset from the exact word count before any Metal work, and
--geometry-check <vectors> [pack dir...]. emu/geometry-vectors.txt is the shared
conformance file (ds55, ds85, ds115, the power-of-two sizes, wrong count or log2,
overflowing counts, missing leaves, leaves on a v2 pack): 19 vectors green in C on
build-7 (packfile-test.sh) and in Swift on the mini, with the two checked-in packs.

Record: cells harness:cuda-select-check (ROT-01, POW-01 partial) and
harness:pack-geometry (POW-02 partial); batch f10-worker-20261008.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:53:24 +00:00
igneum-labs
b9385ddb0d release-manifest-check: a proving manifest's source_commit must be an ancestor of the tree's HEAD (V6-10 provenance); no source_commit is a note
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:52:57 +00:00
igneum-labs
85edf04217 Pool review B record (documents and the registry batch only): docs/plans/pool.md section 11 (F12, F13, INT-04, INT-15 closed by construction on pool-review-b 786e09cc: what was, what is, the regressions, the consequences per tier), spec 09 section 9.3 (the frame bound while reading; binding v2, the exact bytes; welcome, authorize, authorized fields; the job row carries master's vote_key_hash and the pool line's seed fields together), the test map's suite:pool cell and the batch pool-review-b-20261008-01 (51 of 51 on build-6 against successor-2.0.1 515ba674, cargo check green against the manifest's node 7cfa422a; evidence build-1:/srv/artefacts/tas/pool-review-b-20261008-01/). The code lands on the release tree (the coordinator's ruling, 20:5x UK): the pool line sits 581 commits off master with conflicts in app, workflows and tools, and master's igneum-pow fingerprint a65e4c5a differs from the freeze's cbc5bd0a, so the pool crate builds from release-2.0.1 or the pool line, never from master's own igneum-pow (F03)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:52:09 +00:00
igneum-labs
c8706d6468 test registry: the hash lane's batch 2 (the fleet's F05 rows on the post-review object as bench:fleet-pods evidence; suite:pow on the review-fix tree)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:51:34 +00:00
igneum-labs
d0e0941cd3 class v5 design page: the re-export is metadata only (fingerprints final on the platforms read), the fourth-zip rule, PC 1's rows the morning's
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:51:31 +00:00
igneum-labs
24674906be class-v6: the fold test parses the plain class string (an era class's name is not a parse form)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:50:17 +00:00
igneum-labs
41781aace6 class v5 design page: the generator 6 all pack's CPU emulation reading counted (four of six)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:49:56 +00:00
igneum-labs
1799534bf8 Fast-time proving enforcement, succession mode: the two shapes of each phase on two blocks with a rejoin between (one record per carrier)
Read from the fix node's run of 20:29 UK (and the pre-fix run of 18:49, which read the complementary half): the attacker's carrier dies with its refusal, so of two records forged on one block only the first was ever carried and the verdict counted one shape per phase. forgeSuccession forges the prior-pair shape, waits half the phase, rejoins the honest tip, forges the next-pair shape on a fresh block and waits the other half; the phase's refusals then carry both. forge() takes the shape set ('p', 'n', 'pn'); floor mode is unchanged.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:49:47 +00:00
igneum-labs
72a5dbbbad V6-10: the guests re-pinned from the committed tree c744daa26 (deterministic across three builds on build-1), the manifest carrying source commit, input format 3 and the live pair as prior
Shard 0x51cd8cba314a32b60fac393949a4571714da6d6656717d286011601b2a163fe7 (elf sha256 0ce9e351...), aggregator 0x05b395ec238f67406084f8a449d400f64c87dc62151daebf66695864727ded8a (elf sha256 3ef25e3f...); vks 0dbb6605... and 074eb906.... Three builds (A: overlay tree, B: a clean target dir two minutes later, C: the committed tree with the elf output dir removed) gave identical bytes. The prior block is the live pair 0x2b1a81cb... / 0x474678f3... (the 17:58 UK re-pin's pair never activated and is skipped); elf/prior holds its files from key-succession-pin. docs/analysis/v6-10-guest-repin-2026-10-08.md carries the rows.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:48:52 +00:00
igneum-labs
da602c33d8 class v5 design page: the class v6 kit's CUDA 4090 read of the generator 6 packs (three platforms equal on each)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:48:15 +00:00
igneum-labs
c1151022fd V6-07: the floor's limits from FREE memory, the small-card threshold 2^26, two recursion budgets, a pinned memory profile per workload in the host
Master review R1 residual V6-07 (the floor patch picked limits from total VRAM, defaulted small cards to 2^27 where the passing rows used 2^26, and returned one recursion constant in both branches).

- proving/prover-floor/sp1-gpu-6.8.1-floor.patch (and the fleet's two copies, box-setup.sh re-pinned): gpu_memory_gb() reads the device's FREE memory once per process (OnceLock; SP1_GPU_MEMORY_BUDGET_GB when the host leases it), never the total; the small tier's element threshold is 2^26 (the alone-comp-26-v1 rows of 6 October on the 3060, 3080, 4060, 4060 Ti, 4070, 5070 and the 8 October proof_alone rows on the 3060 at 7,525 MiB and the 4060 at 7,532 MiB); recursion_trace_allocation_for_budget returns upstream's 2^27 on the 24 GB tier and RECURSION_TRACE_ALLOCATION_SMALL = 2^26 + 2^25 under it (a recursion key or shard uses 90,177,536 elements); floor_tests pin the small tier and that the two branches differ; the FLOOR opts line carries free_mib and total_mib.
- host/src/memory_profile.rs: the pinned table (full, 24gb, 16gb, small by free MiB; floors per workload shard, aggregate, chain) with tests pinning every value; the row is chosen from the engine's lease (IGNEUM_PROVE_MEM_BUDGET_MB, else IGNEUM_PROVE_MEM_FREE_MB, with IGNEUM_PROVE_DEVICE, IGNEUM_PROVE_WORKLOAD, IGNEUM_PROVE_DEADLINE_S: the app lane's device coordinator interface) or, with no engine, from nvidia-smi memory.free on the device; applied to the floor server by environment before the SP1 client spawns it; a hand override is kept and named; under the floor the host refuses with one line and exit 78 before any setup.
- tools/fleet/box-prover.py: the default path names its workload (IGNEUM_PROVE_WORKLOAD=chain, IGNEUM_PROVE_DEVICE) and closes a refused segment as cancelled/memory.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:47:49 +00:00
igneum-labs
ad2133c6eb Test registry: floor lane 3's batch eco05-20261008-01b (ECO-05 FAIL, ECO-01 and ECO-08 RUNNING at manifest 24883757; the rows move with their evidence files carried by this landing; the same run as batch 01, no result changed), recorded on the lane's word
The registry's evidence rule 2: eco-05-results.md and sim/economy/coexist/README.md change in this landing, so the rows that name
them as evidence move in the same diff, by their owner's batch through tools/ci/test-record.mjs.
2026-10-08 19:47:37 +00:00
igneum-labs
49941c9d36 Registry: census:class-v6 PASS (run census-v6-20261008-2034: the freeze's object hl-v6-all 4de7b836cc40a4ea at class-v6 9415e9c89 through the sub-version 3 harness; evidence docs/analysis/class-v6/census-packs.md sections 0 to 7)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:47:22 +00:00
igneum-labs
4b079e7c87 Merge the box master before the relanding (the download buttons from the refreshed index: the 2.0.1 Mac and HiveOS entries; the manifest's versions with them)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:47:14 +00:00
igneum-labs
fbcdb12da0 Counter ASIC 3.0 status: the STOP read back by every lane, the roll's first stage and the first fixed-miner block, P01 part A complete on the CUDA cards, F05's GPU rows, the census (c''') PASS on the freeze's pack, the D1 state, the key-succession landing re-shaped, the rule v4 rows on master, the steward's registry corrections, the master pin diff, the workers page read from the edge (a coordinator fault once)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:47:07 +00:00
igneum-labs
9fa5c83209 Merge box/master 94889a656 into counter-asic-4-docs-3 (rule 26 again: master's map, page and registry taken, the lane's cell re-added, the batch re-recorded) 2026-10-08 19:46:35 +00:00
igneum-labs
94889a6561 Merge reference-apps-f04 4e954be8 into master (gate: green on 4e954be8, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:46:20 +00:00
igneum-labs
d99478d39c class v5 design page: the class v6 kit's post-review (generator 6) packs, the third zip 735e1411, the Metal worker lift, the Mac readings (two platforms equal on each pack)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:45:24 +00:00
igneum-labs
c744daa260 V6-10: the hand-flagged new-fee-mode fixture is withdrawn (its plan's shard roots were the old mode's; the new-mode row comes from a block exported by the D4 node 930b6322 instead)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:45:22 +00:00
igneum-labs
d820a21f0d Merge class-v6-census-packs-docs-3 13b4b42f into master (gate: green on 13b4b42f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:45:10 +00:00
igneum-labs
6b53b14af0 class v6 kit: the PC job scripts expect the post-review (generator 6) packs' fingerprints, the Mac's Metal and Apple OpenCL reading (all pack e8f4f3289c6ee1fc, partner 6ce3dc344a613500); the third zip packs-class-v6-20261008T194045Z.zip
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:43:45 +00:00
igneum-labs
b6b4dc08ad The master-landing lock: one holder on build-1 for the whole landing, master merged into the branch under it, the merge stamped as the union of two gated parents
merge-to-master.sh takes /srv/builds/_locks/master-landing on build-1 (an atomic mkdir with the holder's pid, host, branch and start; waiters poll every 10 s in order up to a 20-minute cap; a holder older than the cap is reaped; released on exit, a kill by pid file included) for the whole landing. Under the lock, when master is ahead of the branch, the script merges master into the branch itself (the registry rebuilt from master's copy with the branch's batches and notes replayed, the map merged structurally, the page regenerated, the suites regenerated) and stamps that merge as the union of the branch's green stamp and master's own landing, so the push takes the light gate; a landing can no longer be refused for a master that moved, and lanes wait in the queue instead of racing (six landings lost ten minutes each in the hour before, main through the coordinator). Self-tests: the lock is taken with its holder line and released, a stale holder is reaped and the lock retaken, a fresh holder is waited for up to the cap, and the branch-side merge carries master's rows and cells plus the branch's.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:43:37 +00:00
igneum-labs
5df21add1d V6-10: the new fee mode fixture's expected roots from the host's native run with the flag on (run74, build-2)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:43:19 +00:00
igneum-labs
052cf9fb18 Merge fin-v4-rows 1cb3e890 into master (gate: green on 1cb3e890, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:43:19 +00:00
igneum-labs
658e63d5f8 Merge lab-signing-20 19d21812 into master (gate: green on 19d21812, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:41:47 +00:00
igneum-labs
319fa42343 V6-10 (review B): a versioned guest input format checked first by both guests; the manifest names its source commit and input format; fee rounding, duplicate payment and format tests; the new fee mode's fixture
ShardInput.format and AggInput.format are the first field of every guest input, GUEST_INPUT_FORMAT = 3 (1 proving v0, 2 the D4 flag and the stage 1 inputs, 3 the stage 2 carried fixtures); shard_statement and aggregate refuse another format before anything else; every host site stamps it. igneum-prove-pin writes source_commit (IGNEUM_PIN_SOURCE_COMMIT or git HEAD) and guest_input_format into the manifest and carries a prior pair over unless --no-prior. Tests (host suite): known-failed first, another format refused by both guests; the proving payment split sums to the charge with the odd wei to the burn over 2,000 charges and the u128 edge; a duplicate, a paid-before and an invalid carried record pay nothing inside the guest's derivation. fixtures/fees-v1-shards2-payment-on.json: the same block with proving_payment_to_pool on (the new fee mode's proof input; the node equality row is owed with the D4 node). Suites green on build-2 (run69).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:41:04 +00:00
igneum-labs
4bad929e71 class-v6: the fold test reads the class name's suffix order (fold inside rw) and parses both spellings
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:40:56 +00:00
igneum-labs
84b6411159 Merge master into key-succession-pin-tool (the pin tool's half only: elf/prior/ as a copy of the served pair, the manifest without a prior block; the real pin 0d0184e9c stays on key-succession-pin for tomorrow's H)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:40:50 +00:00
igneum-labs
19d21812f1 Merge remote-tracking branch 'build/master' into lab-signing-20 2026-10-08 19:40:19 +00:00
igneum-labs
b51ce846af V6-08 design: proving task protection (leases, backpressure gate, shard-sized tasks, bounded transport, preflight, flow conservation), docs/design/proving-task-protection.md
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:39:22 +00:00
igneum-labs
6cdd8dccdd class v6 kit: the Metal worker runs generator 6 as it runs class v5 (packClassOf 6 = v6, the state-leaf rules on both classes, as packfile.h 5f21d1165); the kit's packfile-test names the checked-in class v5 pack as its known-good (the generator 6 all pack failed that check by construction in the third build)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:39:22 +00:00
igneum-labs
35bfd5ce95 P01 part A: hl-v6-all (the class v6 D1 object) a million vectors with zero disagreement on the 5090, 4090 and 3090
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:39:14 +00:00
igneum-labs
5683c392ca Merge box/master 57592dbeb into counter-asic-4-docs-3 (rule 26: master's map, harness page and registry taken, the lane's cell harness:economics-model re-added and the batch eco-d4-20261008-01 re-recorded; the export list both ways) 2026-10-08 19:39:06 +00:00
igneum-labs
4e954be8c0 Merge build/master into reference-apps: master's steward files carried, the reference-apps cells and batches re-recorded, pages rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:38:55 +00:00
igneum-labs
13b4b42f19 Class v6 census: the post-review object's (c''') read (hl-v6-all 4de7b836cc40a4ea, generator 6, PASS: the rule with the floor, 256 of 256 at r 0.129, the window trace standing), with the 8cf53d5f2 read beside it
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of b0712487f (b0712487f6) for the box mirror master
2026-10-08 19:38:32 +00:00
igneum-labs
c0fd811463 Class v6 census: the x16 address rows for the four chain seeds; hl-v6-rw's harness outputs from build-3 (back at 19:48 UK)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of bf666e2d2 (b0712487f6) for the box mirror master
2026-10-08 19:38:31 +00:00
igneum-labs
3c6b2dea9d Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of e375bccf3 (b0712487f6) for the box mirror master
2026-10-08 19:38:31 +00:00
igneum-labs
2ddb72aa75 Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of abf7711a4 (b0712487f6) for the box mirror master
2026-10-08 19:38:31 +00:00
igneum-labs
8207f7534e Class v6 census: the x16 address rows for the four chain seeds; hl-v6-rw's harness outputs from build-3 (back at 19:48 UK)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 258606e56 (b0712487f6) for the box mirror master
2026-10-08 19:38:31 +00:00
igneum-labs
8fa614da28 Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 90c57eafc (b0712487f6) for the box mirror master
2026-10-08 19:38:30 +00:00
igneum-labs
3e84124fb2 Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of d0dfcd777 (b0712487f6) for the box mirror master
2026-10-08 19:38:30 +00:00
igneum-labs
0b5b661a41 P01 part A, run p01-20261008-01: hl-v5-win a million vectors with zero disagreement on the 5090, 4090 and 3090 (POW-01 in progress; the v6 packs, OpenCL and Metal remain)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:36:19 +00:00
igneum-labs
23cac34c77 Research lane D's family-gate cell and batch (POW-02, ROT-07, ROT-08 partial; recorded by the steward at the lane's ask)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:35:58 +00:00
igneum-labs
1cb3e890b7 Registry batch: FIN-08 through the finality-sim cell (RUNNING, the real-node rows joined to the simulator's; the combined-boundary runs are tomorrow's plan), so sim/results_v2.md and its rows move together
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:35:40 +00:00
igneum-labs
4079c3ff9c Merge remote-tracking branch 'build/master' into class-v6 2026-10-08 19:35:20 +00:00
igneum-labs
e877993409 Class v6 family gate: 6.11 lands documents-only (master's test map, registry and harness-map page untouched; the harness cell and its batch go to the CI steward, the page's generator owner, to land with the next regeneration)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:35:17 +00:00
igneum-labs
6b0bc3aee4 The merge normalises master's registry copy on every landing; --check refuses a row outside the four decisions
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:35:04 +00:00
igneum-labs
00c7e2dc32 class-v6: review B's V6-02: loads_per_hash and bytes_per_hash report the executed schedule (256 loads under the window) with the drawn count beside them and an agreement assert; the v6fold pairs draw both sides under the v6 rules (the fold and layer 8 off pairs)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:35:01 +00:00
igneum-labs
d9ce5ab3f3 Merge build/class-v6 5f21d1165 into class-v6-kits (the pack reader runs generator 6; the post-review packs)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:34:47 +00:00
igneum-labs
8481e2f5fd publish-manifest.sh: the --no-nudge arm the nudge commit named (the edit that carried it had aborted; the test read it missing)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:34:22 +00:00
igneum-labs
00bbec04aa The registry rebuilt on master 1bca7b68: normalised to the four decisions, the kills as FAIL, REV with the master ids, INT with V6-12, the notes
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:34:17 +00:00
igneum-labs
8972f86cb8 Merge master 1bca7b68 2026-10-08 19:34:12 +00:00
igneum-labs
1c63bb042c The master's status discipline in the writer: four decisions, the p.139 record, the four approvals, several records per case; the REV ids from the master; INT-07's V6-12; the two kills as FAIL
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:34:09 +00:00
igneum-labs
5f21d11652 proto-cuda/nvrtc/packfile.h: the pack reader runs generator 6 (class v6) as it runs class v5 (the shadow block and the state leaves required); the kit workers refused the re-exported packs with 'not a generator version this worker runs'
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:33:17 +00:00
igneum-labs
35cb870464 2.0.2: a manifest publish nudges every relay machine to check at once (the shipper's order, 8 October 2026: the engine's manifest check is hourly today, ten minutes from 2.0.2, and the mini took the 2.0.1 entry only when its api/update/check was called by hand). publish-manifest.sh --deploy ends by posting packaging/ota/update-check.ps1 as a relay run to every machine under ~/.config/igneum/relay-machines (--no-nudge skips it; an unreachable machine is one line, never a failure); the script asks the local engine through its own api/update/check with the token from app.url, waits 45 s and reads back what it staged (RESULT UPDATE-CHECK asked version=... manifest=... state=...); it installs, quits, pauses or resumes nothing (the engine's own path installs at its next safe moment and the MINING-ON relay run reads the apply). Also: publish-jobs.sh's edition read is safe under set -e (the pre-push publish-jobs check's sandboxed add had failed on it). Test known-failed first in relay/test/clients.test.mjs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:33:15 +00:00
igneum-labs
57592dbeb5 Merge worker-select-pass 190b97c7 into master (gate: green on 190b97c7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:33:11 +00:00
igneum-labs
1bca7b685f Merge ci-rev-suite c172affe into master (gate: green on c172affe, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:32:51 +00:00
igneum-labs
69944c0949 release-manifest-check: the V6-12 block (signature, lockfile hashes, binaries, devices and drivers, the prover patch, memory thresholds, tuner identity) read as notes; INT-07 reads BLOCKED until it is filled
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:32:48 +00:00
igneum-labs
c7234d6cc7 Litepaper: the corrected loads-per-hash accounting (256 dependent reads under the class v6 object, 128 before; bytes per hash, the schedule and the memory model each figure names; review B's V6-02, the hash lane)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:32:40 +00:00
igneum-labs
adf8500ef2 Merge remote-tracking branch 'build/master' into reference-apps-f04 2026-10-08 19:32:33 +00:00
igneum-labs
f22685b139 Class v6: the genesis dataset size DECIDED at 4 GiB (the founder's word at 20:00 UK, FROZEN as class_v6_dataset_steps [(0, 4096 MiB)]); change (3) and the served policy sentence as decided; the chip line's a-node-ahead end 3.3x with the floor marked
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of counter-asic-4 248837578 over master 39bddf6a6 (the 21:00 landing): the design and analysis documents, spec 05 and 06 (06 and the export list three-way merged), sim/economy/coexist (python, JSON, TSV), the map cell harness:economics-model added to master's map, the batch eco-d4-20261008-01 recorded through tools/ci/test-record.mjs on master's registry copy; nothing under igneum-pow, proto-cuda or the apps; the branch itself unmerged.
2026-10-08 19:31:58 +00:00
igneum-labs
bc1879b4e6 Merge ca3-coord-record aa8212c2 into master (gate: green on aa8212c2, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:31:30 +00:00
igneum-labs
0188bb071e The master's wording: the three boundaries with 'automatically' (every page and the pins), the ranking ceiling in the master's words (no present-tense rank; what an independently substantiated pass would and would not support), the proving record served as a disrupted record, not a benchmark
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:30:45 +00:00
igneum-labs
c0e43ec600 Merge dex-devnet3 20340c16 into master (gate: green on 20340c16, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:30:29 +00:00
igneum-labs
a49870acaa Merge amd-intel-energy-docs c1b7426e into master (gate: green on c1b7426e, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:29:11 +00:00
igneum-labs
9233f76e61 Registry: the node lane's rule v4 real-node run (fin-v4-realnode-20261008T2025Z on 12424341) onto FIN-02 and FIN-07 through test-record.mjs; the evidence under sim/finality-attacks-results/
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:28:51 +00:00
igneum-labs
96d2a1a4cf test-record: a batch cell may narrow its write to named cases ("cases": [...]) so one case's incident never writes a cell's other cases
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:28:07 +00:00
igneum-labs
0edde9f46a The deploy script records its own pid before it starts and refuses a second run (the one Mac-side publish path); the chip per-tier line in the three-row form with the placed 32-lane floor and P04 FAIL at both ends; the decided dataset clause verbatim
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:28:03 +00:00
igneum-labs
63bc0f5f38 Class v6 family gate: the harness cell on master's current test map, the page regenerated from it, the batch replayed (rule 26 and the page check)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:27:57 +00:00
igneum-labs
b67b8964bc Merge outcome-ledger b881f791 into master (gate: green on b881f791, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:27:43 +00:00
igneum-labs
f2c4aa82ab The founder's word by construction: the kit ISA check, kill-by-name rule 5 and the no-kill shim, the cut batch's read-back
tools/ci/kit-isa-check.sh disassembles every executable of a kit (objdump) and is red on any AVX-512 encoding (a zmm register, an EVEX opmask, an EVEX-only mnemonic); self-tested with a fake objdump; in the gate as a self-test, in merge-to-master.sh over any executable a landing adds under packaging/kits or bin, and for the shipper's cut gate over the kit. kill-by-name-check.sh rule 5: a pgrep -f or pkill -f pattern passes only when anchored on the exact command line (^/full/path or ^command), the bracket form, a variable, -x or -F; a bare path, a log name or a word is red; the tree reads clean under it. tools/ci/no-kill-shim/{pkill,killall} exit 97 with the pid-file rule when first in PATH (the one line for a shell rc is in the file; the founder's own shell is his to change). test-record.mjs refuses a batch that declares a cut without the binary's build-N:/srv path, its commit string read back equal to the manifest sha, and the kit check's clean line.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:27:43 +00:00
igneum-labs
0fb1fc6062 Merge master-2.0-landing-l 2668157a into master (gate: green on 2668157a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:26:45 +00:00
igneum-labs
1993e03209 build-from-manifest: vendor/igneum-node-exec is a second checkout at the node sha, never a link (an overlay ships directories only)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:26:30 +00:00
igneum-labs
b13d734a11 Rule v4 harness, the reruns on the fixed node (12424341, HEAL 400): the pause-only run resumes after the heal (the node fault closed), the recovery run locks exactly the side above half (54.62 percent this time; 51.26 the other way in the first run), split70 as before; the seven result files in sim/finality-attacks-results/
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:26:24 +00:00
igneum-labs
190b97c734 CUDA worker serve-bench: keep the coproc pid past its exit, IGNEUM_PID_DIR for the fleet pid directory
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:26:17 +00:00
igneum-labs
52dfa85028 CUDA worker: the select pass (review B F10), ported from the OpenCL worker
The serving loop read 8 bytes per nonce back over the bus (128 MiB per 2^24-nonce
dispatch) and scanned them on the host under the GPU mutex. Now a tiny
igneum_select kernel, compiled once by NVRTC with no pack involved, writes the hits
(index, hash word) behind an atomic counter plus 34 sentinel words, and the host
reads back a few hundred bytes; the found lines come in nonce order from the sorted
hits, the hash word printed is the kernel's own out[i]. A chunk with more than 256
hits falls back to the full read of that chunk. The sentinels feed the stale-output
detector the OpenCL worker has (an unchanged signature across two chunks exits 3).
--readback full or IGNEUM_READBACK=full keeps the old path; a select pass that fails
to build falls back to it with an info line. The ready line carries "readback
select|full"; a transfers line per 200 jobs and at quit gives the per-chunk budget.
No hash changes: the bound kernel and its result layout are untouched.

The emulation backend learns the select kernel (module S, a host loop in reverse
index order so the sort is exercised). emu/select-check.sh, called from emu/test.sh,
compares select with the full read line for line, known-failed first
(IGNEUM_READBACK_FAULT_TEST skips the counter reset): zero hits, partial hits,
the all-hit overflow with its full fallbacks, a 96-nonce tail with a 32-lane
launch, the high-32 rollover, two queued jobs, hits then a zero chunk, a mismatch
error then a job. Green on build-7 (2255 found lines, 10 jobs, 2 fallbacks).
serve-bench.sh is the serving-mode measurement (production and steady numbers
beside the kernel timer).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:26:17 +00:00
igneum-labs
e8313a6ef6 Merge master into fin-v4-rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:25:55 +00:00
igneum-labs
a5c5670e7b Merge branch 'ci-rev-suite' into ci-int-suite 2026-10-08 19:25:53 +00:00
igneum-labs
c172affeab merge-to-master: the harness page regenerates after the registry rebuild, never from a copy with conflict markers (the REV landing's 20:24 loss); fixture extended
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:25:37 +00:00
igneum-labs
255ce1dd72 class-v6: the export's file order as the pinned packs carry it (identity.json second, kernels before the headers); the era pack test lists identity.json beside the pinned files
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:24:57 +00:00
igneum-labs
15350922f1 Merge wallet-recovery-20 3cc9d478 into master (gate: green on 3cc9d478, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:24:57 +00:00
igneum-labs
cb818bad18 F14 pinned and the founder's kill-by-name refusal in the relay agent (8 October 2026). The agent runs a task only beside an engine whose api/state reads edition "lab", product "Igneum Miner Lab" and channel "igneum-2.0-devnet-lab" (the window lane's reviewb-202 ef3c8402 strings); an engine with no such field is pre-2.0.2 and runs as before. publish-jobs.sh refuses an add to a target whose latest IGNEUM-APP header reads edition=public (tools/logs.mjs --header <id8>, new: the machine's latest app header line). The founder's word at 20:21 UK ("STOP all these mess ups", the fourth kill-by-name breach that day), by construction: Check-Task refuses a task body that ends a process by its name (Stop-Process -Name, taskkill /IM, Get-Process -Name | Stop-Process, pkill, killall) with exit 77 and the matched line; a pid is the only way. Tests known-failed first in relay/test/service.test.mjs (the shapes built from pieces so the tree's own kill-by-name check reads no kill)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:24:55 +00:00
igneum-labs
8381cf5a06 Merge build/master into reference-apps: master's steward files carried, the reference-apps cells and batches re-recorded, pages rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:23:35 +00:00
igneum-labs
aa8212c2a2 CLAUDE.md: the founder's STOP by construction (8 October 2026, 20:21 UK: pkill and killall refuse, fleet binaries only from the shipper's kit, one deploy script from the Mac, a slip reported once); Counter ASIC 3.0 status: the 20:2x lines (the AMD/Intel lane's branch, ADV-07 placed, the joint table's third row, lock 270's exact fractions, the founder's STOP)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:23:34 +00:00
igneum-labs
39bddf6a61 Merge pool-registry 07a36020 into master (gate: green on 07a36020, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:22:31 +00:00
igneum-labs
c1b7426e73 AMD and Intel energy on class v6 (GPU-03 AMD and Intel cells, ECO-05 named cause): per 32 bits of bus the AMD and Intel cards burn the 5090s watts but do 0.21x to 0.47x its random reads; the window costs the RX 7600 and the Arc B580 no rate per unit of work; the B580 class v6 rows (11.01 MH/s, fingerprints equal, watts unreadable unelevated); hash-identical kernel candidates ranked (0 to about 10 percent); the RX 7600 metered knee owed to a queued PC 1 job
Documents only: docs/analysis/class-v6/amd-intel-energy.md and docs/analysis/class-v6/amd-intel-energy/ (the three job scripts, the Level Zero sampler source, the offline-compile prelude and ISA summary).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Documents-only replay of c9e32b256 (c9e32b256a) for the box mirror master
2026-10-08 19:21:27 +00:00
igneum-labs
c20db4be82 Merge audit-f7 b8443e85 into master (gate: green on b8443e85, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:21:10 +00:00
igneum-labs
746d90455c The INT suite (the master edition's 18 integration gates), the counting note, REC-01's closure evidence as notes, and INT-17 as a rule of the writer
tools/ci/int-suite.mjs writes the INT suite from docs/plans/igneum-2.0-master/traceability.json's integration_gates (the requirement verbatim as title and accept, source R1, NOT RUN, the owner per the coordinator's crosswalk) and regenerates at the merge like REV; the master's counting note is a registry-level note ("128 original test cases, 18 additional integration gates, 44 updated-stack closure requirements. These sets overlap and are not 190 independent tests."); REC-01's closure evidence (rule v4 on 12424341's line, mode recovery by the founder's ruling, both real-node lines PASS, FIN-02 PASS at b24f28d69) is a dated note on FIN and on INT for INT-05 and INT-06, RUNNING until the beyond-window healing case runs natively. INT-17 in test-record.mjs: a batch cell that declares prereqs with any oracle, pinned keys or real-proof fixture missing is written BLOCKED with the missing ones named, never PASS; self-tested both ways.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:21:08 +00:00
igneum-labs
20340c16f9 Merge remote-tracking branch 'build/master' into dex-devnet3 2026-10-08 19:20:32 +00:00
igneum-labs
7ed22e60ac P22 stage 2: the stages design document reads what shipped (fixture shape, the split inside the guest, the commitment and its vector, the statement offsets, what the proof says and does not say)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:20:28 +00:00
igneum-labs
f0b8f1aa33 Merge remote-tracking branch 'box/master' into p22-stage-2 2026-10-08 19:20:28 +00:00
igneum-labs
4fbeb0625f Class v6 family gate: master's copies of the harness-map page and the registry verbatim (rule 26); the family-gate batch replays onto the registry at the merge
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:20:21 +00:00
igneum-labs
2668157aa5 Merge remote-tracking branch 'box/master' into master-2.0-landing-l 2026-10-08 19:19:42 +00:00
igneum-labs
b881f7913f The proving outcome ledger (review B F08): every claimed job ends in one outcome; the report reads paid completions, missed deadlines and wasted work by cause
tools/fleet/box-prover.py point 6: each claimed segment is an eligible job and closes once as paid, expired (unpaid, held_expired) or cancelled (disk, export, cut, chain, timeout, shards, statement, sign, refused), active until then; the row carries outcome, cause, deadline, margin at the claim, seconds spent (wasted unless paid) and the deadline miss; the state carries the counters and the wasted seconds by cause; every close is a RESULT outcome line, the run ends with a RESULT ledger line.

tools/fleet/prover-outcomes.py: the report over state files and logs (a log from before the ledger is reconstructed from its RESULT lines; a state row wins over a log row): outcomes, paid completions (segments, shards, IGN, median end to end, median time to pay, median margin), missed deadlines by cause with the median miss (never negative, none on a stale tip), wasted work by cause, throughput per hour and the paid share of the seconds spent, the open jobs. --self-test to known numbers (known-failed first), run by the gate. tools/fleet/night.py sums the fleet's counters into its hourly row. docs/analysis/proving-outcome-ledger.md: the definitions and how to read the three ratios.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:19:39 +00:00
igneum-labs
0b9cf9be46 Merge ca3-coord-record c7e74a05 into master (gate: green on c7e74a05, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:19:25 +00:00
igneum-labs
2c49d453fc build-from-manifest: the exec link line quoted
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:19:08 +00:00
igneum-labs
d0a2edf506 Workers page: the Mac mini's row (no report yet until its relay id), the MacBook card says the one DMG only, a box without sources reads provisioning
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:19:03 +00:00
igneum-labs
3ec6ed9971 class-v6: the pack tests read identity.json as the thirteenth export file beside the pinned twelve (the era, v5, reg64 and file-list tests); the A04 test reads a class v4 program (the shadow is class v4's)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:18:44 +00:00
igneum-labs
30c471ec0d Merge the box master 025cc046 (/acceptance rebuilt from master's registry) 2026-10-08 19:18:27 +00:00
igneum-labs
a2384733fa Merge remote-tracking branch 'box/master' into site-2.0-followup
# Conflicts:
#	site/acceptance.html
2026-10-08 19:18:22 +00:00
igneum-labs
ab08918b18 build-from-manifest: the proving workspace's vendor/igneum-node-exec placed beside vendor/igneum-node
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:18:03 +00:00
igneum-labs
2b227a15c6 Chip text: the per-tier line carries the placed 32-lane floor (the complete machine 1.5x to 2.1x on the same node, 1.8x to 2.4x a node ahead; the hybrid 1.9x to 2.6x and 2.4x to 3.2x); the board-alone figures and the served sentence unchanged
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:17:40 +00:00
igneum-labs
b9d942b8d3 P22 stage 2 (the guest side): the shard proof commits to the derivation it ran, the carried records as fixtures (docs/design/consensus-proof-stages.md stage 2)
CarriedFixture {record, shards, pool_credit, segment_daa, paid_before, valid, v1_active, aggregator_share_bps}; derive_payouts runs the node's split natively inside the guest; derivation_commitment (keccak over the fixture list, vector 0xe824944e49f90e9dc7734ae5764b1413f9a29407f7b399ea26d6087a14a95baa) closes ShardOutput and BlockOutput (lengths 360 to 392, 372 to 404). The aggregator carries the commitment out unchanged. Host and exporter emit the fixtures from the node's carried records. Guest suites green on build-7 (run56).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:17:22 +00:00
igneum-labs
3cc9d47810 The wallet's History row: a recovery lock reads "finalised (recovery lock)", never plain final (review B F04, the founder's ruling)
The node lane's lockKind word for a transaction under a recovery lock ("finalised by a recovery lock") reads on the
row as "finalised (recovery lock)" with the why: the surviving majority's lock after a long pause, not a certified
checkpoint, not yet verified here. Known-failed first on build-2 (the word fell through to the label); 22 wallet UI
tests green. Until the node carries the field the pause word stands (wallet-words-20).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:17:13 +00:00
igneum-labs
118dfdbb52 Merge master; the REV suite, the batch and the notes re-applied on master's registry 2026-10-08 19:16:31 +00:00
igneum-labs
a836e2dd18 Merge remote-tracking branch 'build/master' into reference-apps-f04 2026-10-08 19:16:04 +00:00
igneum-labs
714fc79e7d The registry's structural transforms replay at the merge like batches: the REV generator and the notes; a NOT RUN row is stamped only on change
merge-to-master.sh rebuilds the registry from master's copy whenever a landing carries any transform, then regenerates the REV suite from the merged tree's findings and dispatch (review-suite.mjs --write), replays every added batch, and replays every added note file (tools/ci/notes/<id>.json, {suite, text}, through test-record.mjs --note-file), then regenerates the harness page from the structurally merged map. The founder's two rulings ride as note files. test-record.mjs stamps a NOT RUN row only when its status or reason changes (every landing had been colliding on 39 untouched rows, the reference-apps lane's finding).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:16:03 +00:00
igneum-labs
1bfaf0a508 Reference apps F04 in the acceptance layer: run ra-20261008T1915-ver recorded, VER-05 in its own cell
The verification rows re-run on the 2.0 devnet with the lock-state code: VER-03, VER-04, VER-06, VER-08 pass (coverage names
the F04 cases), VER-01 and VER-02 FAIL by design, VER-05 FAIL on this run because the public read node now reports
startedFrom snapshot (the reader on build-1 is still from genesis); VER-05 moves to harness:reference-apps-ver-availability
so its verdict never drags the other rows. Recorded through test-record.mjs; the harness map page regenerated.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:15:55 +00:00
igneum-labs
07a3602065 test map: suite:pool (UX-05 and UX-04 partial coverage); batch pool-2.0-20261008-01 RUNNING at 72cc306e8; the harness page regenerated on master's map
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:15:13 +00:00
igneum-labs
4bde1f6fb2 Merge build/master into reference-apps-f04, pages rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:14:58 +00:00
igneum-labs
3cbaa58b84 Merge remote-tracking branch 'build/master' into reference-apps-f04 2026-10-08 19:14:58 +00:00
igneum-labs
025cc046d7 Merge registry-ux-shipper-2 f1b0c820 into master (gate: green on f1b0c820, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:14:43 +00:00
igneum-labs
3f93f71010 IGNEUM 2.0 Complete Master Edition: the reference, traceability register, R1 review and evidence companion
Documents only. The master (292 pages) governs where it differs from the
plan PDF or the RTF; 18 INT gates and 44 R2 closure requirements become
suites INT and REV in the acceptance registry (CI steward).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:14:26 +00:00
igneum-labs
3d70a3af52 Merge reference-apps ad6dac7c into master (gate: green on ad6dac7c, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:13:21 +00:00
igneum-labs
61871cdada The cross-backend same-work test specified (F03, Review B): one job context, six readers, three phases around a day rotation, bit-for-bit agreement
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:13:16 +00:00
igneum-labs
b8443e858b The window audit records F7 to F9: review B's F14, F07 and F04 as built for v2.0.2 (the founder's rulings of 19:57 BST)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:13:13 +00:00
igneum-labs
5cfb48898b Merge remote-tracking branch 'build/master' into dex-devnet3 2026-10-08 19:12:12 +00:00
igneum-labs
c7e74a05ce Igneum 2.0 register: main's layer 8 wording on the D2 row; Counter ASIC 3.0 status: the F05 pricing, the first lock after the outage (270 at 19:51:37), lane D's second chain-path fault and the 6.11 PASS, the final tree ac86d7910, review B on master, the F01 fix and its live reproduction, FIN-02 the first PASS, GOV-03's first row, main's two questions answered
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:11:40 +00:00
igneum-labs
ba2e402f34 F03 (Review B): the release manifest's check and the build-from-manifest script
tools/ci/release-manifest-check.sh: on a release branch that carries packaging/release-manifest.json, every component's own pin must equal it (the Windows node-source pin, the proving manifest's elf and vk sha256s and the files' hashes on disk, the node fork's freeze fingerprint, the pool's vendored node checkout at the manifest's node sha, no redefined EpochSeeds in the pool); a tree without a manifest is not a release and passes with a line. tools/ci/build-from-manifest.sh puts the node fork at the manifest's node sha under vendor/igneum-node (the pool's path dependency, so the shadow_reps seam closes by a build against the pinned node) and checks kaspad with igneum-pow (rule 19 proves the generator), igneum-miner, the pool, the app and the prove host on a box at gate priority, then the pin check. The 2.0.1 manifest itself lands on release-2.0.1.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:10:51 +00:00
igneum-labs
b20c9eb143 The dataset policy decided on the facts row and the Mine pages too (4 GiB at genesis, 8 October 2026)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:10:28 +00:00
igneum-labs
1e7ce8470c Merge p02-fleet-pods-20261008-01 eaed5eee into master (gate: green on eaed5eee, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:10:14 +00:00
igneum-labs
9f7b5c8bd0 The dataset policy decided (the founder's word at 20:05 UK, 4 GiB at genesis; the curve and the 2 GiB and 5.5 GiB reasons kept beside it; later steps at 5 percent) on the litepaper, the facts row, the Mine pages and the manifest; the board clause corrected (six of seven at any hardware price, the fleet-cost condition every design fails)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:09:57 +00:00
igneum-labs
b455074d63 Merge build/master into class-v6-family-gate (rule 26: master's copies of the harness map and the registry, the family-gate batch re-recorded on them)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:09:56 +00:00
igneum-labs
c450730c5c Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 19:09:56 +00:00
igneum-labs
20e9db0787 F14: the relay agent's lab refusal under test (relay/test/service.test.mjs: App-Product, the refusal in the task path, an older engine allowed)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:09:19 +00:00
igneum-labs
945dcae1ca Merge ca3-coord-record ee93c8a8 into master (gate: green on ee93c8a8, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 19:08:11 +00:00
igneum-labs
60d684cd89 F14, the relay and publisher half (the founder's ruling, 8 October 2026, 19:57 UK: the public miner carries no remote execution; the fleet runs the lab build under its own signing root, separate from the OTA key). publish-manifest.sh: the key follows the channel (igneum-2.0-devnet-lab signs with ~/.config/igneum/lab-signing/lab-signing-key, --lab names it; every other channel the OTA key; a channel naming a lab that is not the lab channel is refused); publish-jobs.sh: --channel lab|public picks the root, anything else refused. igneum-agent.ps1: App-Product reads api/state .product and Lab-Refusal refuses every task beside a public engine ("Igneum Miner"), an engine without the field (pre-2.0.2) runs as before. Release rule 16 names the split (feature lab, channel igneum-2.0-devnet-lab, product "Igneum Miner Lab", the lab kits, the per-PC exes wrapping the lab Setup, the lab root). Known-failed first: the publishers' cross refusals, relay/test/service.test.mjs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:07:34 +00:00
igneum-labs
703f9389c9 The REV suite: Review B's 44 required regressions in the acceptance registry, and the founder's two rulings as notes
tools/ci/review-suite.mjs writes the REV suite from docs/analysis/review-2026-10-08-b/findings.json and dispatch.md: one case per required regression (REV-F01-1 onward), the regression line verbatim as title and accept, status NOT RUN, the owner lane from the dispatch table, the finding id and priority carried as fields; every unmapped case gets a NOT RUN reason in tools/ci/test-map.json naming its owner lane; the gate's check refuses a registry whose REV suite drifts from the findings. The founder's 19:57 rulings on F04 (the recovery lock kept, always labelled recovery) and F14 (the public miner from 2.0.2 without remote jobs; the lab build for our fleet) are dated notes on the FIN, UX and OPS suites through test-record.mjs --note, and resolved fields in F0. The harness page is regenerated.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:07:23 +00:00
igneum-labs
5bc1f52f26 Merge master (Review B) 2026-10-08 19:06:33 +00:00
igneum-labs
f1b0c82069 UX evidence: the over-u64 coinbase incident (incident-u64-coinbase-2026-10-08) for UX-06, the registry row to follow by a per-case batch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:06:13 +00:00
igneum-labs
2e886d2f6c The 2.0.1 pair recorded (7cfa422a + ee0c2e11), F0 re-pinned with the founder's two rulings, and four gate tools from Review B's night
Batch 201-7cfa422a-ee0c2e11: node 7cfa422a (the miner base-unit fix, amended after 777214af's self-recursive connect failed to compile under the steward's read) green on the kaspad check and five suites on build-4 over the key-succession pairing; miner cut tip ee0c2e11 (crate identical to 011b89e4) green on pow and app on build-2. F0 names those pins and records the founder's 19:57 rulings on F04 (the recovery lock kept and always labelled recovery) and F14 (the public miner from 2.0.2 without remote jobs; the lab build for our fleet) as resolved. Tools: proof-rule-bypass-check.sh (F02: the test bypass cannot reach a release build; a cell of the node matrix from now, red until the proving lane's change lands); test-map-merge.py and the page regeneration at the merge (two lanes' cells no longer collide as text); push_race in merge-to-master.sh (a push that lost master's compare-and-swap retries without re-running the hook; twelve tries); review-suite.mjs (the REV suite generated from a review's findings and dispatch, written in the next commit once Review B is on master); test-record.mjs --note (a dated note on a suite, never an accept text).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:06:04 +00:00
igneum-labs
76340cfb21 class-v6: the program_classes test counts class v6 (generator 6 is a class now; 7 is none)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:05:31 +00:00
igneum-labs
ad6dac7c4c Merge build/master into reference-apps: master's steward files carried, the reference-apps cells and batches re-recorded, pages rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:04:55 +00:00
igneum-labs
4dd8d1816e Merge review-b-landing-l 432b1b4d into master (gate: green on 432b1b4d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 19:04:43 +00:00
igneum-labs
ad8be04ae6 class-v6: review B's F05 measurement text: igneum-pow export --reg64-prefix writes the CUDA kernels with the reg64 chain in its closed prefix form (S the running xor of the rotated registers, updated after every base and shadow write; a load's source r[s] ^ ror(P_s, 1) ^ S ^ P_s ^ a[s]); the same hash and vectors, OpenCL and Metal keep the fold; a tool switch, no object change
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:04:30 +00:00
igneum-labs
011cdcb328 Merge enforced-proving c74ac60b into master (gate: green on c74ac60b, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:03:30 +00:00
igneum-labs
61b691db28 Merge remote-tracking branch 'build/master' into dex-devnet3 2026-10-08 19:03:13 +00:00
igneum-labs
eaed5eeebf registry: P02 retail cohort on the rented pods (bench:fleet-pods RUNNING, six CUDA cells)
GPU-01, GPU-03 and POW-08 take run_status RUNNING with the evidence rows on build-1 under /srv/artefacts/tas/p02-rows; PASS waits on the AMD cells, the 1080 Ti cell and the re-exported v6 packs.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:02:51 +00:00
igneum-labs
e6da0cc3ef Class v6 family gate, 6.11: the post-review object (class-v6 8cf53d5f2, mx8+sh256x27+state+reg64c+nowin+fold+rw) through the acceptance: PASS under the full rule (r 0.15, 0 exhausted, the floors at 0.07 to 0.23 percent, the fold halving the bit-R class); the second predicate finding (a width-4 class is not the class v4 shape to the crate's own predicate because of mix: the chain's path runs the v2 parts only, r 0.05, the accepted draw under the floor), a freeze condition; attack-f8 valid on the mirror's subset only (96 of 96 mismatches on the fold and reg64c, stated); the registry write-back: harness:family-gate mapped to POW-02, ROT-07, ROT-08 as partial coverage, the batch recorded
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:02:10 +00:00
igneum-labs
678095100d class-v6: the acceptance's class v4 shape predicate and the draw's source rule set the era's drawn width aside (lane D's second finding: a multi-width era wrote the drawn width into mix and fell to the class v2 parts); test: the shape holds at every width of the family
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:02:00 +00:00
igneum-labs
e8cbb46563 Merge jobs-restart-guard 996ed34d into master (gate: green on 996ed34d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 19:00:59 +00:00
igneum-labs
b414ecc5d7 class-v6: the mixer determinism test skips identity.json beside the pinned pack (A06's thirteenth file)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:00:46 +00:00
igneum-labs
9e689c3051 Reference apps F04: the one-file verifier rebuilt on the box from the lock-state source; the oracle README names the refused recovery locks
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:00:18 +00:00
igneum-labs
81d6c4376b class-v6: review B's F03 and F05 (8 October 2026). F03: ProgramClass::V6 in the canonical enum, GENERATOR_VERSION_V6 = 6, V6_CLASS = mx8+sh256x27+state+reg64c+fold+rw (layer 8 off the fifth flag); every class carrying a v6 flag draws as generator 6 under an era, the packs read program_class "v6", the pack check treats v6 as a state class; class v5 and below untouched. F05: the reg64 full-chain address source in closed form (verify::reg64_address_source: r[s] ^ ror(P_s, 1) ^ (S ^ P_s ^ a[s]) with a[k] = rotl(r[k], (63 - k) mod 32)) proven equal to the reference fold on every source register over 256 drawn register states and a real update sequence, the known-failed one-rotation-off form disagreeing; the verifier keeps the fold as the definition.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 19:00:05 +00:00
igneum-labs
ee93c8a889 Igneum 2.0 register: review B's thirteen rows (F04 and F14 the founder's rulings; the 20:0x coverage); Counter ASIC 3.0 status: the pool seat's early item, the 19:4x lines (the miner base-unit root cause, the hubs' memory caps, the three object candidates on the live line, P22 stage 1, F0), the 20:00 words and read-back, review B, the founder's two rulings, the roll correction
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:59:38 +00:00
igneum-labs
b24f28d694 Merge finality-boundary 31012d0b into master (gate: green on 31012d0b, recorded by tools/ci/pre-push.sh; landed on the build mirror under the exception declared by main: finality-boundary registry write-back 2 (the steward's split cell, 19:46 UK): tools/ci/batches/fin-boundary-20261008-02.json and the registry only; no .rs, Cargo or build file) 2026-10-08 18:59:16 +00:00
igneum-labs
bd39a7c18a Reference apps, Review B F04: a recovery lock is never presented as a final lock
The light service maps the node's lockKind (igneum_getFinalityCheckpoints, 2.0.2 line) to lock_state beside every certificate
it answers with; core.js reads it as one step on /light and /receipt, refuses an unknown kind and a receipt that claims final
under a reported recovery lock; the pages print "recovery lock, not final" on the result, the receipt file carries lock_state,
the one-file verifier prints it; the shared terms block defines the recovery lock; /oracle says recovery locks are not accepted
by the Sepolia verifiers (two-thirds rule only, so every stored root passed the final rule). Node and browser negative cases
added. On a node before the field nothing changes.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:58:50 +00:00
igneum-labs
de3ea90fe1 class-v6: A06's kernel hashes move to identity.json (a thirteenth pack file: program id, class, generator, day, dataset bytes, the BLAKE2b-256 of every kernel text) so every pinned pack's twelve files stay byte for byte; the tests skip it in the pinned comparison and count thirteen
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:56:10 +00:00
igneum-labs
e5c5a134f9 Bridge doc: recovery locks (F04) fail closed on the verifier, which reads only weight against the installed table and knows no lock kind
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:55:15 +00:00
igneum-labs
4dd069f613 Merge build/master into reference-apps: master's registry, map and harness page carried, the reference-apps cells and batches re-recorded through the steward's form
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:53:59 +00:00
igneum-labs
c74ac60b7a Merge box master b4856f6c into enforced-proving (the proving cell on master's map, the page regenerated, the batch replayed)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:53:57 +00:00
igneum-labs
996ed34d32 publish-jobs: restart --what app is refused unless --allow-app-restart (PC 1, 6 October 2026 19:10Z and 8 October 14:50Z: on a 0.3.x engine the restart kind leaves a relaunch helper racing the window host for the single instance; it lost both times, the app down for hours with the whole queue behind it; the fix, the host's ladder with no helper, is v2.0.0's restart-kind-20). The flag is the publisher's word that the target's last upload reads 2.0.0 or later; the node and miners restarts are unchanged. Known-failed first: the shape that hit PC 1 now exits 2 with the reason
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:53:39 +00:00
igneum-labs
432b1b4d74 Merge remote-tracking branch 'box/master' into review-b-landing-l 2026-10-08 18:53:16 +00:00
igneum-labs
31012d0b3c Test registry: FIN-02 PASS on harness:finality-sim-fin02 (batch fin-boundary-20261008-02): the simulator half of the accept text met in sim/results_v2.md Rule v4 (the 40/40/20 fixture, the boundary splits, the pause valid, zero conflicting final certificates within the declared bound); the real-node half stays node:finality-realnode
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:52:43 +00:00
igneum-labs
b4856f6cab Merge ci-batch-4 654f999f into master (gate: green on 654f999f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 18:51:09 +00:00
igneum-labs
7424d1d398 Fast-time proving enforcement, the succession mode read from its first both-pairs run: the proof floor at 0 as on devnet-4, the two real proofs per epoch as the signal, the reasons read from the relay's flow-error line, the attacker rejoining the honest tip before each forge (its carrier dies with its refusal)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:49:44 +00:00
igneum-labs
eef4cc4455 Review B (8 Oct 2026): second external review, findings, reproduction pack, dispatch
Documents only. Fourteen findings F01 to F14 with forty-four regressions,
dispatched by lane in dispatch.md; the regressions become suite REV in the
acceptance registry (CI steward).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:49:43 +00:00
igneum-labs
29fafab012 Merge df1eeff59 df1eeff5 into master (gate: green on df1eeff5, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:48:32 +00:00
igneum-labs
1826c917ef Reference apps in the acceptance layer: three harness cells and two run batches recorded through the steward's form
The map gains harness:reference-apps-compat (EVM-02 to EVM-06, partial coverage named per case), harness:reference-apps-ver
(VER-03 to VER-06 and VER-08) and harness:reference-apps-ver-trust-anchor (VER-01 and VER-02, FAIL by design and disclosed).
Batches ra-20261008T1744-evm (22 of 22 rows on the 2.0 devnet, node 4cdcc488) and ra-20261008T1746-ver (evidence per case
under tools/reference-apps/ver/evidence) are recorded with node tools/ci/test-record.mjs --record; the harness map page is
regenerated; the registry rows move with their evidence (site/lc/verify-receipt.js rebuilt in this landing).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:46:28 +00:00
igneum-labs
4e3f4b9cf5 Merge box master fd966646 into enforced-proving (the test map rebuilt on master's copy with the proving cell; the registry from master's copy with the batch replayed; the page regenerated)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:46:16 +00:00
igneum-labs
654f999f33 Registry batches: the 2.0.1 literal run (ef0f2ed8 + 2826f37e) and F0's GOV-01 row; the finality cells split
Run 201-ef0f2ed8-2826f37e: node ef0f2ed8 (291ee6ae plus the 2.0.1 version bump) on the key-succession pairing, kaspad check and the five node-side suites green on build-4; the miner cut tip 2826f37e (app crate identical to 2ea7b43f), pow and app green on build-2; evidence at build-1:/srv/artefacts/tas/201-ef0f2ed8-2826f37e/. GOV-01's row takes F0 (docs/plans/igneum-2.0-f0-manifest.md) as its evidence through the batch f0-manifest-20261008-b (the earlier f0 batch landed before the replay existed and never recorded). The map splits the finality cells at the finality lane's ask: harness:finality-sim keeps FIN-08 (the model side), harness:finality-sim-fin02 carries FIN-02's simulator half, node:finality-realnode carries the node lane's real-node lines for FIN-02 and FIN-07.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:44:31 +00:00
igneum-labs
ee0c07d27b Workers page: the push reads every box with a host file, build-1 to build-9 (boxes 4 to 9 joined tonight)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:42:17 +00:00
igneum-labs
fd96664647 Merge ci-f0-manifest 2083ed6f into master (gate: green on 2083ed6f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 18:41:56 +00:00
igneum-labs
df1eeff597 Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 18:41:55 +00:00
igneum-labs
5f235294db Chip text: the reconciled per-tier line for the DRAM board (the two chip models agree after placement: 1.5x to 1.8x as a machine, 2.0x to 2.4x for the board alone on the same node; 1.8x to 2.1x and 2.45x to 2.8x a node ahead) replaces the single core-only line
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:41:42 +00:00
igneum-labs
e0f9b69ecd Merge hash-registry-1 cda49bef into master (gate: green on cda49bef, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:41:01 +00:00
igneum-labs
e72718f6e2 P22 stage 1 (the guest side): shard 0's public values commit to the rewards, the pool credit and the payouts it applied; the aggregator carries the commitment out (docs/design/consensus-proof-stages.md; ZKP-04 and ZKP-08, the proof side)
ShardOutput.inputs (328 to 360 bytes) and BlockOutput.inputs (340 to 372): keccak over the inputs list in order (inputs_commitment, the vector 0x911a87e4... pinned here and in the node); every shard but the first carries zero and the aggregator asserts it. Known-failed first: fee_switch_tests::the_inputs_commitment_binds_the_rewards_and_payouts_through_shard_0_and_the_aggregator (shard 0 commits, the others are zero, the aggregator carries it out, other rewards commit to another value). Suites on build-2 at 19:06 UK: core 8, host 11 passed. The ELF and the program ids are NOT re-pinned here; the stage ships through a key succession.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:40:16 +00:00
igneum-labs
3683ba8617 Merge floor-eco-record b622d535 into master (gate: green on b622d535, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:39:55 +00:00
igneum-labs
978e5f559c Merge remote-tracking branch 'box/master' into enforced-proving 2026-10-08 18:38:50 +00:00
igneum-labs
750959df70 Consensus proof stages: what the code already gives stage 2 (the carried records and the paid map on the segment record, the exporter's carried block, the per-shard split functions)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:38:49 +00:00
igneum-labs
c7453ea0d9 Merge finality-boundary c8152a58 into master (gate: green on c8152a58, recorded by tools/ci/pre-push.sh; landed on the build mirror under the exception declared by main: finality-boundary registry write-back (the CI steward's form, 19:30 UK): tools/ci/batches/fin-boundary-20261008.json and the registry only; no .rs, Cargo or build file) 2026-10-08 18:38:45 +00:00
igneum-labs
88893a0fc3 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 18:37:57 +00:00
igneum-labs
5ac2d96916 Merge commit 'f8fcfa813' into site-2.0-followup
# Conflicts:
#	site/index.html
2026-10-08 18:37:56 +00:00
igneum-labs
a5b28f0f1f Workers page: the five gauges on one row at desktop width and a clean stack on a phone (flex with growth; a wrapped tile fills its row, no empty cell drawn)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:37:37 +00:00
igneum-labs
38829ab2b4 Merge audit-f6 b91163fe into master (gate: green on b91163fe, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:37:35 +00:00
igneum-labs
f8fcfa813a Home: one-line headings, the statement under the downloads, a quick-scan landing, the phone bar and the footer rows aligned
The founder's home pass (8 October 2026). Section headings shortened to one line at 390 and 1440 (What 2.0 delivers.,
The people on it.); the hero line fits one line at 1440 and keeps two at 390 (25 px; one line would need 13 px). The
one-click statement moves under the download buttons as one line. The miner rows cut to the scan shape with the claim
and window sentences verbatim and the chip detail behind /litepaper#chip-model; the deliverables table stays. The phone
bar keeps the toggle, Download and the burger together on the right at one size; the footer's icons (Discord, source,
Reddit, email) and its four download pills each sit in one row.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:37:00 +00:00
igneum-labs
a0531096e2 Income page: the TEAM-REPORTED label on the card rows written in the generator, the page regenerated from it (the gate's income check reads the generator)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:36:04 +00:00
igneum-labs
51ae16fe49 Chip text: the whole-machine sentence stands (1.5x to 3.1x; 1.5x to 2.3x on the GPU's own node) with the core-only line beside it (2.8x and 2.4x, placed and routed, plus or minus 15 percent) and the standard's P04 target as approved; the two-source range withdrawn (the coordinator's word: the rows measure different things)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:35:36 +00:00
igneum-labs
cda49bef76 test registry: the hash lane's batch 1 (tools/ci/batches/hash-lane-20261008-batch1.json: bench:pc1-packs, bench:pc1-amd, bench:fleet-pods, census:class-v6, suite:pow as RUNNING with their evidence rows under docs/analysis/class-v6/rows)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:33:08 +00:00
igneum-labs
3e73be0b50 Merge ca3-coord-record 85699625 into master (gate: green on 85699625, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:32:53 +00:00
igneum-labs
f0c8ea910d igneum-pow hash-bound --count: one warp per 32 nonces (the P01 campaign's million-vector files in minutes; the per-nonce form hashed the whole group per nonce)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:32:44 +00:00
igneum-labs
2083ed6f0c F0, the release and assurance manifest: the pins read tonight, main's four rulings, the unresolved-field register, the signing block
docs/plans/igneum-2.0-f0-manifest.md is the fixture F0 every case pins to: the identity pins as the steward read them on 8 October 2026 (the miner cut tip 2ea7b43f, the node roll sha ef0f2ed8, igneum-devnet-4, the object digest be5f4068, the class v5 freeze and its fingerprint, the roles and kits), the four fields main ruled on at 19:3x (P07's workload W as the pilot plan's shape; P00 and P08's fault model and thresholds as the finality spec's own at 19e96548e; P10's study NOT RUN until unaffiliated participants are recruited, never a staff run; P02's AMD cells the 9070 XT and RX 7600 on PC 1, PARTIAL until a rented AMD cell exists), an unresolved-field register with owners and defaults, and the signing block for 23:30. GOV-01's row (through the batch f0-manifest-20261008, replayed at the merge) adds the manifest to its evidence path and stays RUNNING until the signatures are in.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:32:20 +00:00
igneum-labs
b622d5357b ECO-05 recorded through the acceptance layer: map cells model:eco05 (ECO-05, full coverage of the frozen register) and model:coexist-fixtures (ECO-01, ECO-08 partial); batch eco05-20261008-01 at manifest 80178b3b: ECO-05 FAIL with its evidence, ECO-01 and ECO-08 RUNNING; ECO-01 and ECO-05 out of not_run; the page regenerated
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:32:20 +00:00
igneum-labs
c8152a585d Test registry: FIN-02 and FIN-08 recorded RUNNING by the finality boundary lane (batch fin-boundary-20261008, cell harness:finality-sim, evidence sim/results_v2.md, manifest 19e96548e); PASS waits on the F4 fault-network run and the independent review, FIN-08's model checking is not the simulator's
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:32:17 +00:00
igneum-labs
64149e21f8 Acceptance map: the proving enforcement cell (harness:proving-enforcement: the enforced_* and succession_* suites and the fast-time crossings) answering ZKP-01, 02, 03, 04, 05, 08 and EVM-08 with partial coverage named; the run batch enforced-proving-20261008-01 recorded (RUNNING, manifest 417c4a57, the crossing's result file on build-2)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:31:42 +00:00
igneum-labs
dc31baf163 built pages after the master merge 2026-10-08 18:30:53 +00:00
igneum-labs
6459c55cc3 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 18:30:53 +00:00
igneum-labs
b91163fe2b The window audit records F6: a node with no peers holds the worker, never a worker fault (the founder, 19:25 BST, v2.0.2)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:30:31 +00:00
igneum-labs
2d2ea50670 Chip text: the two placed-and-routed models disagree, so the served sentence carries their range (a DRAM-board machine 1.5x to 2.4x on the same node, 1.8x to 2.8x a node ahead; two sources named, MODELLED, no chip measured) until the 21:00 reconciliation
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:29:39 +00:00
igneum-labs
83177aca73 Merge ci-batch-3 9c91fee1 into master (gate: green on 9c91fee1, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 18:28:32 +00:00
igneum-labs
eb5b39ccdf Merge the box master (the reference-apps lane's compatibility rows taken whole) 2026-10-08 18:28:26 +00:00
igneum-labs
80972d6ec0 /acceptance: the header carries the standard's form of the decision (APPROVED AS PROPOSED), never the approver's own sentence from the registry's word field
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:28:10 +00:00
igneum-labs
85699625dd Igneum 2.0 gap table (the standard's profiles against today's values, main's word on the four F0 fields); Counter ASIC 3.0 status: the 19:0x to 19:3x lines (A05 and A03 closed, the chain-path acceptance fault found by lane D, the three object candidates, the batch replay, build-7/8/9, the coverage line, the freeze ruling)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:25:37 +00:00
igneum-labs
f0b2f5dbd4 built pages after the master merge 2026-10-08 18:23:55 +00:00
igneum-labs
ef489fdd68 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 18:23:55 +00:00
igneum-labs
955fac1a19 The reference apps on the Igneum 2.0 devnet: the verifier's placement check takes the DAA-seconds rule (checkpoint i at DAA 30 (i - 1) from a genesis anchor, finality.rs daa_target; devnet-4 runs it from DAA 0, so its certificates sit under 30 i in blue score), the homepage card shares it; /light verifies a devnet-4 balance (chain block 3743 under checkpoint 246, 4 trie nodes) and /receipt a devnet-4 transaction (checkpoint 241), every negative case refused on both devnets' fixtures; the oracle takes the coinbase amount width as a constructor immutable and is redeployed for devnet-4 (0x06c12c0c…, 16 bytes), certificate 249 verified by the devnet-4 verifier and chain block 3815's root stored, provenBalance equal to eth_getProof; the offline verifier rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:23:53 +00:00
igneum-labs
2bab73471a Merge registry-ux-shipper 8f4bc2b1 into master (gate: green on 8f4bc2b1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:22:19 +00:00
igneum-labs
9c91fee1fa A registry landing carries its batches and the merge replays them onto master's copy; tonight's three batches ride it
The acceptance registry is a hot file: three landings in a row lost rule 26's race to another lane's rows during their own seven-minute gate. Now a registry landing carries its run batches as tools/ci/batches/<run id>.json (the files test-record.mjs --record took); merge-to-master.sh, for a branch that added batch files, lets rule 26 pass the registry path (the branch's copy is never what lands), and in the merge worktree takes master's copy of the registry, replays every added batch through the recorder (idempotent), commits the merge and runs the evidence rules on the merged result before the push. Self-test: a fixture where master gained a row after the branch point and the branch carries a batch; the merge lands with both rows. The batches: 200-417c4a57-b2 (the 2.0.1 gate, 30 cases RUNNING), review-harness-20261008T180034Z (POW-01's cross-check, all four anchor groups agree), p01-partb-20261008-01 (POW-06, three parsers, zero panics); the map gains crosscheck:review-harness and part B's command and coverage.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:21:59 +00:00
igneum-labs
fec4f58a2b Merge pool-registry 6d527d69 into master (gate: green on 6d527d69, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 18:21:26 +00:00
igneum-labs
03b3806ea8 Merge ci-rules-only 37da13a3 into master (gate: green on 37da13a3, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 18:20:21 +00:00
igneum-labs
80773c55aa Merge reference-apps 31f8e643 into master (gate: green on 31f8e643, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:19:36 +00:00
igneum-labs
8cf53d5f23 class-v6: the acceptance's class v4 shape predicate and the draw's source rule set the window and layer 8 off aside (lane D's finding: a +nowin or +reg64c program was judged by the class v2 parts on the chain's path); test: every v6 flag keeps the shape and the attempt cap
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:19:16 +00:00
igneum-labs
49732a4a24 Merge dex-devnet3 4c08d5ab into master (gate: green on 4c08d5ab, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:18:02 +00:00
igneum-labs
4da1c76f68 Merge class-v6-census-packs-docs-2 6aee2d5c into master (gate: green on 6aee2d5c, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 18:17:23 +00:00
igneum-labs
ac8f8c9854 Merge commit 'ab4ee3b7d' into site-2.0-followup 2026-10-08 18:15:34 +00:00
igneum-labs
ab4ee3b7da site: fix the 2.0 audit's open items and add /docs
Pre-2.0 ledger ids pointed at 2.0 entries or dropped (M32 to D3, E19 to A7,
M4 to C1, P1/P3 to D5; E20, F7, M12 dropped); the dataset row and sentences
read the served dataset policy; engineering-log citations name
docs/bench-log.md; the node1-dn3 source notes gone; the earlier devnet named
in governance; the four words on /address, /proving and /scenes; the tx fee
sentence matches economics; provenance's SP1 sentence reads the current fact;
receipt capitals and the unlabelled timing dropped; the lock tile reads active
and total weight; TEAM-REPORTED labels on app, income, compatibility, build,
light and the dev fee row. New /docs page listing the 2.0 documents by their
master paths, wired into the build, nav, nav check, sitemap, capture and og.
docs/site/audit-2.0.md moves each fixed item into "What was rewritten".

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:14:51 +00:00
igneum-labs
8f4bc2b13a Merge master into registry-ux-shipper; the shipper's four cases over master's copy (rule 26)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:14:44 +00:00
igneum-labs
6d527d699b registry: POW-05 reviewed (binding review section 5a, master 38a29345); merged onto master's copy under rule 26
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:13:19 +00:00
igneum-labs
37da13a3f7 The gate manifest regenerated
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:13:16 +00:00
igneum-labs
273de87b2e The registry's evidence rules in the gate: a PASS carries existing evidence, evidence moves with its row, stale evidence never reads PASS, a run_status needs the approval
tools/ci/registry-evidence-check.sh runs in merge-to-master.sh after rule 26: (1) a landing that sets a case's run_status to PASS must name an evidence_path that exists, in the tree at the landing or on a build box over ssh (a box that does not answer is a line, not a refusal); (2) a landing that changes a file under docs/analysis/ or a path a registry row names without moving that row's updated field is refused (GOV-04: the row and its evidence move together); (3) a PASS whose evidence record pins another manifest than the registry's pinned_manifest_sha is refused (GOV-08: stale evidence reads NOT RUN); (4) a run_status written while the registry carries no approval block is refused (GOV-02: thresholds before results). Self-test on a fixture repo covers each rule both ways.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:13:13 +00:00
igneum-labs
31f8e6435d Test registry: this lane's run fields inserted into the approved registry textually (master's bytes untouched, rule 26); the read service serialises coinbase amounts at the 2.0 devnet's 16-byte wire width (18 decimals), so /receipt verifies on igneum-devnet-4 (checkpoint 241, 719 headers); the devnet-4 fixtures
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:12:30 +00:00
igneum-labs
4c08d5abd0 Bridge: the 2.0 devnet's voter table and checkpoints 241 and 242 verified and recorded on the igneum-devnet-4 Sepolia verifier (installTable 0xc2568a7a, 0x2102dae6, 0x61b5d581); docs/contracts/sepolia.json
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:11:22 +00:00
igneum-labs
5d6cfac39b Igneum 2.0 Deliverable 1, the record (candidate): docs/spec/01-lottery-hash.md to version 0.3 (1.0 the frozen object by digest, 1.4.8 generator 6, 1.8.7 and 1.13.4 the dataset policy under the freeze, 1.16 the parameters the freeze fixes with version 0.2's prototype table kept as 1.16.5, 1.17 the class v6 vectors Open with their clock) and the D1 record under docs/plans/igneum-2.0.md's D1 heading; the object candidate dab9259f on class-v6-node, main's default dataset policy (4 GiB from genesis), the review's nine findings pending their owners' verdicts in the freeze file
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:11:21 +00:00
igneum-labs
6aee2d5c33 Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of b10fe1351 (b10fe1351dea53344acfa5b764d8215dc77480f3) for the box mirror master
2026-10-08 18:11:09 +00:00
igneum-labs
e78156b813 Merge build/master into reference-apps (the approved registry carried byte for byte with this lane's run fields inserted; master's nav on every rebuilt page)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:10:59 +00:00
igneum-labs
14600f4d6f Merge build-server 8a893576 into master: the deploy script after the devnet-4 re-point (index hero, explorer-stats keyed on the live network, checkpoint shape check, LIVE_NETWORK default igneum-devnet-4) and the checkpoint no-certificate reason with live_daa
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:10:57 +00:00
igneum-labs
b30966dfc8 Facts: finality active on the Igneum 2.0 devnet from checkpoint 241 (19:08 UK, 115 minutes after block one, 78 percent of active weight), TEAM-REPORTED, case FIN-01; the box master merged
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:10:56 +00:00
igneum-labs
d3ee22788a Merge ca3-coord-record 1d84a77c into master (gate: green on 1d84a77c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:09:15 +00:00
igneum-labs
9a484534ed Merge enforced-proving 53c6ffc3 into master (gate: green on 53c6ffc3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:06:45 +00:00
igneum-labs
ef615ecff9 class-v6: blake2b_256 reached through its own module; the pack-reader fuzz skips a file the pack does not carry
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:06:01 +00:00
igneum-labs
68964de817 registry: POW-05 reviewed (binding review section 5a, master 38a29345); fields under rule 26
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:05:49 +00:00
igneum-labs
e2aeada4fb Fast-time proving enforcement: --drop-keys for a node line behind master's 60x file (OverrideParams refuses an unknown field; the D4 pin's key stays on its own branch)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:05:44 +00:00
igneum-labs
38a29345e7 Merge binding-review 92d49692 into master (gate: green on 92d49692, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 18:03:43 +00:00
igneum-labs
f72a4ef054 class-v6: the external review's findings (docs/analysis/review-2026-10-08, 8 October 2026), fixed by construction where they apply: A02 every class carrying a v6 flag reserves five non-load slots as shuffles over the five lane dimensions in a drawn order (LoadClass::is_v6; the id carries v6draw/); A08 a v6 mad never names its destination as its second source; A06 program.json carries the BLAKE2b-256 of every kernel text (kernel_blake2b256); A07 the verifier's group alignment, tails and low-32 rollover under test; A04 a zeroing shadow fails acceptance under test (the acceptance executes the shadow since sub-version 3); and the fuzz's finding: bind::unhex panicked on a multi-byte character inside the text, now a refusal on bytes.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:03:38 +00:00
igneum-labs
a09b457ac8 Merge master into registry-ux-shipper (rule 26: master's registry lines carried)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:02:23 +00:00
igneum-labs
10d4fa42cd Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 18:02:23 +00:00
igneum-labs
03bbeed45d Merge 509b41af0 509b41af into master (gate: green on 509b41af, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 18:02:19 +00:00
igneum-labs
1d84a77c52 Igneum 2.0 register: the nine review rows (A01 to A09, main's dispatch) and the 19:0x coverage; the registry's times read UK on master's current copy (the enforced-proving and steward rows kept); Counter ASIC 3.0 status: the registry approved and on master, ECO-05's FAIL under P12 and main's three rulings, build-5 green as a Cloud ccx53, the 18:57 kill by name and its re-runs, the pairing rule for 291ee6ae, the lanes' clocks
Rule 26: the registry edit is the time strings only (BST to UK) on master's copy as it stands after a7a47a64a and 7b7a2b1c; nothing of any lane's fields is dropped.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:02:10 +00:00
igneum-labs
4930820f38 Merge class-v6-family-gate 79557f4c into master (gate: green on 79557f4c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:01:23 +00:00
igneum-labs
53c6ffc3a7 The consensus proof in stages (P22, ZKP-04 and ZKP-08's proof side): the inputs commitment in code (stage 1), the payouts derived inside the aggregator from records checked natively (stage 2), the rewards from consensus data the guest verifies (stage 3) with the facts the header would have to commit to; every stage ships through a key succession
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 18:00:40 +00:00
igneum-labs
19e96548e7 Merge finality-boundary e56e3268 into master (gate: green on e56e3268, recorded by tools/ci/pre-push.sh; landed on the build mirror under the exception declared by main: finality-boundary amendment e56e3268d (the coordinator's word 18:5x BST): docs/spec/finality-guarantees.md only; no .rs, Cargo or build file) 2026-10-08 18:00:03 +00:00
igneum-labs
a7a47a64aa Merge enforced-proving e3d298cf into master (gate: green on e3d298cf, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:59:10 +00:00
igneum-labs
0fb6a83a6d Merge review-2026-10-08-docs ed90d1db into master (gate: green on ed90d1db, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:58:21 +00:00
igneum-labs
610c02b016 Rule v4 harness on real nodes: the four runs on bee41b5e into sim/results_v2.md (v3 known-failed, v4 pause with the node fault it read, v4 recovery as designed, split70), and v3.mjs's split50 pass line keyed on the recovery switch (finality-guarantees.md 6.7)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:58:08 +00:00
igneum-labs
2be82da7bd class v5 design page: the Arc job's kit-missing fault (the fetch targeted PC 1) and the re-post at PC 2
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:57:50 +00:00
igneum-labs
7b7a2b1cbb Merge ci-test-map-2 d0ac272a into master (gate: green on d0ac272a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:56:57 +00:00
igneum-labs
92d49692ca docs/analysis: binding review section 5a, the external review's A05 (FNV initialisation, the 64-bit fold): the argument, five measured lines, no change for 2.0, the class-version shape if one is wanted
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:55:49 +00:00
igneum-labs
4de9db88bb Merge build/master into reference-apps (registry fields re-merged) 2026-10-08 17:55:29 +00:00
igneum-labs
509b41af0b Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 17:55:19 +00:00
igneum-labs
cc0d85f912 Test registry: the shipper's four cases in the file's own format (26 lines moved, nothing else)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:55:06 +00:00
igneum-labs
79557f4ccd Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 5c6b07015 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 5c6b07015
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:54:46 +00:00
igneum-labs
723e02ac05 Test registry: the shipper's UX cases (UX-02, UX-03, UX-07 RUNNING; UX-06 pending the 01:30 run) with their evidence record (rule 26: fields merged, never replaced)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:53:55 +00:00
igneum-labs
7697af0271 Merge pool-wire-2.0 a7e43ee9 into master (gate: green on a7e43ee9, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 17:53:34 +00:00
igneum-labs
73239cd06f ECO-05 in the research lane's revised words (the sixteen worlds, the one passing world, the failure regions, what moves it, published for reproduction) with its labels, on the litepaper, the facts row and /economics
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:53:10 +00:00
igneum-labs
e3d298cffb Test registry: the enforced-proving lane's run rows on the approved copy (ZKP-01, 03, 04, 05, 08 RUNNING on the 8 October evidence; ZKP-02 and EVM-08 RUNNING on key-succession-node 291ee6ae; the P22 and pin dependencies named per row)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:53:07 +00:00
igneum-labs
6e770f39af ECO-05 served as FAIL under the approved P12 envelope (main's ruling): the sentence beside the coexistence reading on the litepaper and the facts row with the corrected-R label line, and on /economics in the standard's words with the one passing world, the failure regions and what moves it
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:52:50 +00:00
igneum-labs
e154836c0f Revert "Revert "ECO-05 reported as found beside the coexistence result (the standard's new-entry test FAIL on a frozen register, its labels and files) on the litepaper and the facts row""
This reverts commit 119072380a.
2026-10-08 17:52:50 +00:00
igneum-labs
0c72718114 /acceptance: the registry's times read UK on the served page and in the runtime reply (the zone name is a forbidden string on a served page)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:52:23 +00:00
igneum-labs
ed90d1db36 docs/analysis/review-2026-10-08: the external algorithm review's evidence pack (evidence.md, results.json, harness.zip), 8 October 2026
The three files as they stand in the Mac checkout at 18:51 BST, on the coordinator's word, one documents-only commit:
evidence.md (45 KB), results.json (82 KB, parses; the delivered results), harness.zip (43 KB: a C and Python reproduction
harness, twelve files, data beside the evidence and not repository code). No chain path; the pack names no founder and no box.
2026-10-08 17:52:21 +00:00
igneum-labs
0035b0f5d5 Merge the box master 2130fa1d (the approved registry); /acceptance rebuilt from it 2026-10-08 17:51:46 +00:00
igneum-labs
7365636d0f Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 17:51:45 +00:00
igneum-labs
119072380a Revert "ECO-05 reported as found beside the coexistence result (the standard's new-entry test FAIL on a frozen register, its labels and files) on the litepaper and the facts row"
This reverts commit a218ce6d4d.
2026-10-08 17:51:44 +00:00
igneum-labs
e56e3268d1 finality-guarantees.md: the two-thirds anchored test never lapses (6.2 item 1, after the node lane's harness finding acd9d067); the even split's jitter fact (7 item 4); the harness pass line per variant (6.7)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:51:41 +00:00
igneum-labs
d0ac272a5f Merge remote-tracking branch 'box/master' into ci-test-map-2 2026-10-08 17:50:33 +00:00
igneum-labs
fe5c274dbc class v5 design page: the class v6 kit's Arc job repointed at c98a42c2e (PC 2 job run-20261008-174916)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:49:35 +00:00
igneum-labs
2130fa1d6d Merge ca3-coord-record 10126092 into master (gate: green on 10126092, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:48:54 +00:00
igneum-labs
c6136a92f9 /tuning: the sitemap, capture and share hooks and the link from /miner
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:47:34 +00:00
igneum-labs
17fc7e1d03 Merge build/master into reference-apps (registry fields re-merged) 2026-10-08 17:47:27 +00:00
igneum-labs
95f540ef53 Test registry: the EVM and VER suites' first automated runs on the Igneum 2.0 devnet (run fields merged under rule 26, owner_lane reference-apps): EVM-02 to EVM-06 PASS (22 compatibility rows, run ra-20261008T1744-evm, two EVM-02 rows added: another chain id refused, a replay refused), EVM-01 PARTIAL and EVM-07 NOT RUN with their dependencies and clocks; VER-03 to VER-06 and VER-08 PASS, VER-01 and VER-02 FAIL by design and disclosed (node-supplied voter table, statement in place of the proof), VER-07 the wallet lane's; the VER runner tools/reference-apps/ver/run.mjs with its evidence files; the write-back script
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:47:26 +00:00
igneum-labs
5c0b0bffe9 /tuning: the hash lane's docs/build/tuning.md served under the Mine group (the knee rule, the priors and ladders, the per-class defaults, the worker flags, the compiler settings, the fingerprint check), linked from /miner; a rig is described, never numbered, on the served copy
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:47:19 +00:00
igneum-labs
47935f9285 Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 17:46:49 +00:00
igneum-labs
a218ce6d4d ECO-05 reported as found beside the coexistence result (the standard's new-entry test FAIL on a frozen register, its labels and files) on the litepaper and the facts row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:46:25 +00:00
igneum-labs
a7e43ee9b8 spec 09: the wire shape for the vote-key commitment (Igneum 2.0): job and share carry vote_key_hash, share_result gains code vote_key, 9.4.1 item 1 reads the job's key, 9.8 item 5 checks it first
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:45:46 +00:00
igneum-labs
b917b99295 Merge tuning-doc-1 344bddf8 into master (gate: green on 344bddf8, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:43:54 +00:00
igneum-labs
7a471b7026 Merge remote-tracking branch 'box/master' into ci-test-map-2 2026-10-08 17:43:40 +00:00
igneum-labs
c7de53fa3a Oracle page: the deployed contract's chain named the earlier devnet, no number; the gate manifest regenerated for the acceptance render test
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:42:55 +00:00
igneum-labs
22c4d120b3 Merge the acceptance page (3f95c6fd) into the 2.0 lane branch: /acceptance from the Test and Acceptance Standard's registry with its runtime endpoint, the case ids on the facts rows, the nav, sitemap, capture and share hooks united with the audit page's
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:42:28 +00:00
igneum-labs
1012609277 Igneum 2.0 Test and Acceptance Standard 1.0 (the founder's, 73 pages, 128 cases in 16 suites) landed with its registry APPROVED AS PROPOSED on 8 October 2026 (P13 DEFERRED by the founder): every case owned by a lane with the live fields (run_status, owner_lane, evidence_path, run_id), 63 RUNNING with tonight's evidence records, 64 NOT RUN, 1 DEFERRED; the register gains the case ids on every row and the standard's pass criteria
Rule 26: docs/plans/igneum-2.0-test-registry.json replaces the landing hand's PROPOSED copy (df5eaada) on purpose, the founder having approved the standard as proposed at 18:2x; the case set is unchanged (128 in 16 suites), the approval block and the live fields are added, nothing of master's text is dropped. The register keeps master's 104 rows (081727ebc) and adds the Cases column.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:41:34 +00:00
igneum-labs
cea3c1b39c class-v6: the window's liveness rule is wired into the acceptance behind the reg64 flag (the arithmetic-only window refused at its first dead register, the full chain and every other class unchanged); the test reads it through accept::check
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:41:05 +00:00
igneum-labs
3f95c6fdef /acceptance: the Test and Acceptance Standard 1.0, case by case, rendered from docs/plans/igneum-2.0-test-registry.json
The page shows each of the 128 cases in 16 suites as it is run, in the standard's words (NOT RUN, RUNNING, PASS, FAIL,
BLOCKED, DEFERRED): a header with the approval line and a thin segmented count bar (never a percentage), G0 and the five
gates G1 to G5 plus the three named gates as cards whose state follows the standard's rule, one section per suite with an
expandable row per case (setup, steps, accept, required evidence, the run's evidence record when present), the profiles
(approved as proposed, P13 deferred, the P04 line read as a FAIL to work against), the fixtures, and the closing notes.

site/lib/acceptance-render.mjs is the one renderer: build.mjs imports it for the build-time page and prints the same functions
into the page's inline script, which polls /api/acceptance (site/api/acceptance.mjs: the registry from git.igneum.network
master, cached 60 s, ok:false with status 200 on failure) and re-renders in place when a case state or source_sha256 moves.
Hooks: the Learn panel, the nav check, the sitemap, capture.sh, the og card row, a lead link on /scorecard, the facts rows 1
to 7 name the case that will prove each. The never-served check strips the plan's own marked never-served list. Node tests
(known-failed first) run in the gate; the registry and the standard text land with the page.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:40:41 +00:00
igneum-labs
51548665e4 Merge enforced-proving daa80874 into master (gate: green on daa80874, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:40:34 +00:00
igneum-labs
c75b770279 The dataset policy's closing clause on the coordinator's ruling (the genesis size the founder's decision on the adversary-against-commodity scoring, the lane's recommendation 4 GiB, later steps at 5 percent), PROPOSED until the word; the 5.5 GiB row's 12 GB tier cell
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:40:25 +00:00
igneum-labs
db0d01f43a The test map takes the hash lane's bench cells, and P01 part A's driver lands with its self-test
tools/ci/test-map.json gains bench:pc1-packs (GPU-02, GPU-03, GPU-05, POW-08 on PC 1's 5090), bench:pc1-amd (GPU-01, GPU-05 on the RX 7600), bench:fleet-pods (GPU-01, GPU-03, POW-08 on the rented cards), census:class-v6 (POW-02), POW-07 under suite:pow (the FP32 branch unreachable on master) and UX-08's published-tuning half; GPU-04 and GPU-07 read NOT RUN with the Devnet 3 off order as the reason; the harness map page is regenerated. tools/ci/p01-vectors.py is P01 part A as the hash lane shaped it: the real worker driven with pool.rs's job lines at an all-pass target, every found hash diffed against the CPU reference list, the evidence JSON with the counts, the first ten disagreements, the pack and program ids, the device line and the manifest sha; exit 1 on any disagreement or unanswered nonce; self-tested with a fake worker (clean PASS, one wrong hash FAIL naming the nonce, one unanswered nonce FAIL naming it).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:39:50 +00:00
igneum-labs
a3b383331e Download page: what changed in 2.0.1, in the shipper's words, under the buttons (the index refresh follows the last 2.0.1 entry on the dl host)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:39:48 +00:00
igneum-labs
09dc418000 POW-01 and POW-02, the malformed-input half: igneum-pow/tests/fuzz_parsers.rs (10,000 mutations each of the class string, the hex and era strings, the IGSD1 state stream; a panic fails) and proto-cuda/nvrtc/packfile-fuzz.c (10,000 mutated pack files through pf_load, never a crash)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:39:45 +00:00
igneum-labs
1566f1cb5a The energy-against-size curve beside the pending dataset policy (1, 2, 4, 5.5 GiB at stock and at the lock, the exclusions by memory, the SRAM tickets; every cell labelled) on the litepaper, cited by the facts row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:38:57 +00:00
igneum-labs
541bd1c72f The dataset policy serves no size as decided (the genesis size is the founder's decision, pending; the costs by size measured; later steps under the standard's 5 percent rule) on the litepaper, the facts row, the Mine pages and the manifest
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:37:52 +00:00
igneum-labs
344bddf85b docs/build/tuning.md: the register row on tuning (the knee rule with the 5090, 5080, 9070 XT and 7600 rows, the priors and the ladders, the tiers, the per-class defaults, the worker's flags and their costs, the compiler settings and register budgets, the variant catalogue, the fingerprint check)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:37:04 +00:00
igneum-labs
2fd9c162be Merge wallet-words-20 472d40d7 into master (gate: green on 472d40d7, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:36:23 +00:00
igneum-labs
28acd0acb6 Key succession, the main side: elf/prior/ (a copy of the current pair until a re-pin moves the old one there; the node reads it only when the manifest names prior), the 60x file's four succession fields, the fast-time harness's succession mode (--succession, --window, --next-ids, --next-proof: the refusal reasons across the height are the signal)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:36:03 +00:00
igneum-labs
65996a382c The acceptance layer: the test harness map, its page, and the recorder that writes runs into the registry
tools/ci/test-map.json maps every automated case of the Test and Acceptance Standard's registry to the cell that runs it (the seven crate suites of the release matrix, the pre-push gate, the freeze check, the fast-time harness, the finality simulator, the P01 vectors and parser-malformed harnesses as they land), each cell with its command, box class and fixtures (F0 onward), each case with what the cell proves and what remains; 31 of 109 automated cases map tonight, 78 read NOT RUN with the reason. tools/ci/test-map-doc.mjs writes docs/plans/igneum-2.0-test-harness-map.md from the JSON (--check in the gate refuses a stale page). tools/ci/test-record.mjs --check refuses an unmapped automated case without a reason or an unknown id; --record <batch> writes run_status, run_id, evidence_path, updated and the evidence record (cell, manifest sha, coverage) to the mapped cases only, leaves every accept text byte-identical (the self-test diffs them), gives an unmapped automated case NOT RUN with its reason and a manual case nothing. Rule: a mapped cell's green writes RUNNING; PASS only when coverage is full and the evidence file exists; never PASS by inference.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:35:45 +00:00
igneum-labs
bfdd4a23aa Merge 1b6a7c988 1b6a7c98 into master (gate: green on 1b6a7c98, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:35:00 +00:00
igneum-labs
1a9de1b36d Key succession, the pin tool's half: elf/prior/ and the manifest's prior and succession blocks, the host embedding both pairs, the release-manifest check comparing both
docs/design/key-succession.md (the enforced-proving lane, 8 October 2026): the
object names the prior pair, a next pair, an activation height H and a window
W; the node embeds both pairs and verifies under the pair a proof claims when
that pair is accepted at the carrier's DAA (the node branch key-succession-node
on the fork carries that side).

The pin tool (igneum-prove-pin): a pin over an existing elf/ moves the four
files it holds to elf/prior/ and writes the manifest's `prior` block (the same
per-program fields plus the pinned_at of that pair) and a `succession` block
naming both pairs' ids; the top-level shard and aggregator stay the newest
pair; at most two pairs live (a pin over an elf/ that already carries prior/
replaces prior/); `--no-prior` keeps today's shape. The host (pinned.rs)
embeds elf/prior/'s four files, checks them against the `prior` block when the
manifest carries one and derives the prior ids from the keys (Pinned::prior,
PriorKeys), checks the `succession` block's four ids against both pairs, and
builds unchanged on a tree whose manifest names no `prior` (every tree now
carries elf/prior/ as a copy of the current pair, so the include_bytes
compile; the in-process verifier reads `prior` as absent). The release
manifest check refuses a served manifest whose `prior`, `succession`,
succession_daa or succession_window_daa differ from elf/manifest.json's, and
a `prior` present on one side only.

The node reads H, W and the next ids from its object, never from the manifest;
`succession` is for the served manifest and its check. The first real pin (the
live pair 0x2b1a81cb…/0x474678f3… into prior/, the re-pinned
0x282dcfce…/0x3fd721e8… on top) runs when main names H.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:34:55 +00:00
igneum-labs
ca4cb251c9 The dataset policy on the paired mapping control (4 to 5.5 GiB 12 to 14 percent over 1 GiB at the lock, over the 5 percent budget of P03; the dataset starts at 2 GiB, PROPOSED, decision pending; 4 GiB and the 5.5 GiB schedule the costed alternatives) on the litepaper, the facts row, the Mine pages and the manifest
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:34:51 +00:00
igneum-labs
daa808743e Merge remote-tracking branch 'box/master' into enforced-proving 2026-10-08 17:34:34 +00:00
igneum-labs
d6f098f0e8 Enforced proving spec: the fast-time harness's key-succession mode (section 8)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:34:24 +00:00
igneum-labs
df5eaada28 Merge igneum-2.0-test-standard-docs dd4c34e9 into master (gate: green on dd4c34e9, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:29:46 +00:00
igneum-labs
1b6a7c9880 Merge commit 'd6d252b5b' into site-2.0-followup 2026-10-08 17:29:19 +00:00
igneum-labs
ac8843f566 Publish the 2.0 evidence set on the public mirror (main's word): coexistence-model.md, operator-simulation.md, connected-state.md, coexist-rows.md and the class v6 design record leave the export-exclude list, the lane records and logs stay excluded; the zone word redacted in connected-state.md; the mirror-follows-master note beside every evidence column
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:29:00 +00:00
igneum-labs
d6d252b5bd Site audit 2.0: docs/site/audit-2.0.md served at /audit, one line per served page (34, with the audit itself) and one sub-row per litepaper section (19): what the reset changed, what was rewritten, what still carries pre-2.0 copy, the label of each claim, what is open
The markdown loop in site/build.mjs takes paths under docs/ (build/build.md, build/grants.md, build/compatibility.md, site/audit-2.0.md); /audit joins the Learn panel (both lists), the nav-check groups, the sitemap, the capture routes and the og cards.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:28:45 +00:00
igneum-labs
80bfaaba81 Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 17:28:14 +00:00
igneum-labs
472d40d70f The wallet's History row: a block under a locked checkpoint is finalised even in a pause; the window audit records the founder's v2.0.1 calls
docs/spec/finality-guarantees.md section 9: one vocabulary, included, executed, proven, finalised; the network's pause
is the network's word, never a transaction's. The wallet's History row read the node's "finality not active" word for a
transaction under a locked checkpoint while finality was paused; it reads "finalised" now, with the pause in the why
("under a locked checkpoint, not yet verified here; finality is paused on the network above it"). Known-failed first on
build-2 (view.test.mjs: the row's word and the vocabulary set); 21 wallet UI tests green.

docs/design/app-audit-2026-10-08.md gains section 7: the founder's reversals and additions for v2.0.1 (the Cards tab
back, the first-block card once per address, the four words, one positioning line, the watchdog's waiting words), each
with where it lands (branch cards-201 on release-2.0.1; this branch for the wallet).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:27:45 +00:00
igneum-labs
b5ddcbbb3c Merge reference-apps 195c5352 into master (gate: green on 195c5352, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:27:09 +00:00
igneum-labs
0e57ff834f Merge class-v6-family-gate 83652b68 into master (gate: green on 83652b68, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:26:17 +00:00
igneum-labs
29a111999e Merge ca3-coord-record 081727eb into master (gate: green on 081727eb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:25:23 +00:00
igneum-labs
e18d5dd84d Merge enforced-proving 988ab54d into master (gate: green on 988ab54d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:24:12 +00:00
igneum-labs
303341ca55 The dataset policy's AMD clause (an 8 GB AMD card under 3 percent of rate, the measured RX 7600 row) on the litepaper and the facts row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:24:10 +00:00
igneum-labs
dd4c34e945 docs/plans: the Igneum 2.0 test standard (the founder's PDF, its text, and the test registry: 128 cases in 16 suites, profiles P00 to P16, fixtures), 8 October 2026
The three files as they stand in the Mac checkout at 18:23 BST, on the coordinator's word, one documents-only commit:
igneum-2.0-test-standard.pdf (392 KB), igneum-2.0-test-standard.txt (its text), igneum-2.0-test-registry.json (205 KB; data, not
code: the registry the suites are read from, parses). No chain path.
2026-10-08 17:23:47 +00:00
igneum-labs
cff5288bdf Merge 5f127a9d0 5f127a9d into master (gate: green on 5f127a9d, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:22:47 +00:00
igneum-labs
9a2971c9b6 Merge explorer-dn3 9385b9ed into master (gate: green on 9385b9ed, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:22:00 +00:00
igneum-labs
fdc9557c05 class v5 design page: the class v6 kit's RX 7600 read (both packs equal; six platforms on the all pack)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:21:44 +00:00
igneum-labs
83652b680d Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 3d086fac9 for the layer-8-off acceptance
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:20:45 +00:00
igneum-labs
195c5352cb Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 17:20:42 +00:00
igneum-labs
b902b8bec1 Reference apps on the 2.0 devnet before its first lock: the pages and the read service answer "no finality certificate yet; the first lock comes when the weight window fills at DAA 7,200" with the live DAA; the light client and the service refuse any certificate or proof whose network string is not the release manifest's network.id; /oracle labels the devnet-4 verifier "table installs at the first lock"
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:20:42 +00:00
igneum-labs
442f278207 Merge binding-review 9e522113 into master (gate: green on 9e522113, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 17:19:14 +00:00
igneum-labs
7c113d4145 Merge reference-apps 7a58ab25 into master (gate: green on 7a58ab25, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:18:22 +00:00
igneum-labs
081727ebcf Igneum 2.0 register: the key-succession row (104), the reference population landed, the formal memory model in flight, the node's four-state RPC and manifest landed; Counter ASIC 3.0 status: the founder's completeness and no-straying orders, the register, the ten missed pins' owners, the 2.0.1 queue complete, the re-pin ruling, the kit at five platforms, the 32-lane synthesis row, the capacity order (build-5, the pods)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:17:41 +00:00
igneum-labs
6f355b16b6 Merge build-server cff31427 into master: /api/checkpoint serves the live chain only (the public site answered the finality test fixture as igneum-devnet-7); the deploy's checkpoint check keys on the live network; LIVE_NETWORK defaults to igneum-devnet-4; observer wei columns numeric
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:16:38 +00:00
igneum-labs
5c6b07015f class-v6: the v4 source rule sets the nowin flag aside as it does fold and rw (the known-failed test read a different load source under +nowin)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:16:16 +00:00
igneum-labs
988ab54dcf Key succession: a re-pin of the proving programs as a scheduled transition (docs/design/key-succession.md; the coordinator's ruling of 8 October 2026, 18:1x UK)
The object names a prior pair, a next pair, an activation height and a window; below the height only the prior pair verifies and pays, in the window either, after it only the next; the node embeds both pairs (elf/ and elf/prior/), the body rule, the payment rule and the native segment statement read one floor, the daemon refuses to start without every pair the object accepts at the tip, the manifests carry both pairs and the height; never on every object, in the digest once set. Tests known-failed first (the seven refusals on both sides of the height) and the fast-time case across it; the node branch by 18:00 UK on 9 October 2026.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:15:56 +00:00
igneum-labs
c6af580343 Merge class-v6-connected-docs-2 fe7bd9fc into master (gate: green on fe7bd9fc, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:15:34 +00:00
igneum-labs
9385b9ed62 Merge remote-tracking branch 'build/master' into explorer-dn3 2026-10-08 17:14:57 +00:00
igneum-labs
955eb89434 Merge class-v6-census-packs-docs 1cccae2d into master (gate: green on 1cccae2d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:14:33 +00:00
igneum-labs
5f127a9d0d Home page to the reference: the positioning line as the sub-line, the plan's four-deliverable table with the evidence label and file beside each row, the three boundaries in one line, the honest status line in the ladder's words; the miner row reads as paid work, never a guaranteed income
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:14:18 +00:00
igneum-labs
c693cb7c4f Merge proving-payment-guest-src 08ad83fe into master (gate: green on 08ad83fe, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:13:45 +00:00
igneum-labs
84bcdda8fc Merge igneum-2.0-register-docs 6b29a893 into master (gate: green on 6b29a893, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:13:00 +00:00
igneum-labs
d0c851a468 class v5 design page: the class v6 kit row names the PC script fault (one-pack leaves check, gfx1201) and its fix at class-v6-kits c98a42c2e
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:12:58 +00:00
igneum-labs
a8db391f8d Finality wording on the live strip and the explorer: not yet active until the weight window fills at DAA 7,200, the live DAA beside it (no clock served)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:12:40 +00:00
igneum-labs
9e5221139f docs/analysis: binding review of template, nonce, work and result (Igneum 2.0 register row): the chain of bindings from the code, the twelve reuse paths with their cost and rule, the measured lines, five open questions (epoch-seed VDF not in the node line, the day keyed on the timestamp)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:11:56 +00:00
igneum-labs
983cffc22e Merge enforced-proving b12323ef into master (gate: green on b12323ef, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 17:10:37 +00:00
igneum-labs
511253ad40 class v6 kit: the PC job scripts check each kit pack's own leaves.bin (the class v5 script's one-pack check stopped the 7600 job before the device list) and the AMD match is the RX 7600's gfx1102
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:09:29 +00:00
igneum-labs
cae205ea1d Explorer API: network_label from the node's network name with the plan's map (igneum-devnet-4 reads "the Igneum 2.0 devnet", any other suffix "the Igneum devnet N"; the site moved to the dn4_ tables while the label stayed Devnet 3)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:09:03 +00:00
igneum-labs
1cccae2dbc Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 25098c1a2 (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
2026-10-08 17:08:39 +00:00
igneum-labs
1ef134c680 Class v6 census, the pack harness: the F8 seed sample is p18 to p33 (outside the known-failed set)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of a229b3095 (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
2026-10-08 17:08:37 +00:00
igneum-labs
d9132b1c35 Class v6 census, the pack harness: the per-pack launcher (pack-run.sh), the verdict sheet (pack-summ.py), the census script with state and era hex
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 982302d0e (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
2026-10-08 17:08:37 +00:00
igneum-labs
df9e06fb99 Class v6 census, the pack harness: the sitestats command (per-site distinct ratio, bucket sigma, index-bit sigma of a pack's program) and the harness-gated accept walk; the attack-pass lane's f8 tool (class v5, state leaves) with --load-class for a class string; the census script's state and era-hex arguments
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 3b0ac575d (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master; left on the branch: igneum-pow/src/main.rs tools/attack/f8-uniform/src/main.rs
2026-10-08 17:08:36 +00:00
igneum-labs
7a58ab25ac built pages after the master merge 2026-10-08 17:07:53 +00:00
igneum-labs
1d0bf5928b Merge build/master into reference-apps (mine kept) 2026-10-08 17:07:53 +00:00
igneum-labs
8b14be9ed1 Merge dex-devnet3 42269ede into master (gate: green on 42269ede, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:07:33 +00:00
igneum-labs
6b29a893fe Igneum 2.0 register: one numbered row per pin (103) with the plan page, the owner lane, the clock, the status and the evidence; the plan with the ten pins the finish line missed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Landed from ca3-coord-record c1aa45bde on the founder's order through the research-landing hand: igneum-2.0-register.md whole. docs/plans/igneum-2.0.md stays master's copy under rule 26: the branch's plan-file change was the finish-line sections already on master from the checkout and the removal of the finality lane's D5 block, which stays.
2026-10-08 17:07:04 +00:00
igneum-labs
026d6e023b class-v6: D2 experiment "layer 8 off" (the coordinator's order, 8 October 2026, 18:12 UK; a research class behind "+nowin"): the era layout's window-layer draw removed, every load site reads the whole dataset (win = 0, off = 0); the stream still consumes the two window draws per instruction so the base program's instructions and the shadow are the class's without the flag; the id carries nowin/; "+nowin" parses in any order with the other suffixes and names back inside +fold/+rw. Test: tests/v6fold.rs nowin_removes_the_window_layer_and_nothing_else.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:06:34 +00:00
igneum-labs
a2592d881d Merge igneum-2.0-plan-docs-2 fb706d42 into master (gate: green on fb706d42, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:06:04 +00:00
igneum-labs
ee14e83f43 The dataset policy served PROPOSED, decision pending (a first step proposed at 4 GiB; the 5.5 GiB rows the costed alternative) on the litepaper, the facts row, the Mine pages and the manifest
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:05:37 +00:00
igneum-labs
b8c2140e4e Merge remote-tracking branch 'box/master' into site-2.0-followup 2026-10-08 17:05:17 +00:00
igneum-labs
b12323ef4d Enforced proving: the register row for negative test six's proof side (derivation inside the aggregator guest, P22 stage 3), clock 18:00 UK 9 October 2026
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:04:36 +00:00
igneum-labs
08ad83fe68 Shard guest sources with the D4 split, the ELF pin left at the served release's ids (the re-pinned elf/ rides the node 2.0.1 and miner v2.0.1 paired cut)
The served release manifest is kept equal to proving/igneum-prove/elf/manifest.json by tools/ci/release-manifest-check.mjs, and the running release (v2.0.0) verifies under the old pair, so the new ids (0x282dcfce..., 0x3fd721e8...) land with the paired cut, not before: proving-payment-guest d681c1c65 on the box mirror holds the re-pinned files. This commit lands the sources, the exporter flag and the known-failed test; every existing fixture reproduces its roots with the flag off, so the old ELF stays a faithful pin of what the devnet runs.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:03:38 +00:00
igneum-labs
05feae8822 class v5 design page: the class v6 kit's 5090 reads (both packs equal; the window's cost per hash and per joule)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:03:27 +00:00
igneum-labs
1e7de00bdb The 32-lane bracket beside the per-machine line (same node 1.5x to 2.1x, a node ahead 1.8x to 2.6x, MODELLED); the live strip and the explorer say finality not yet active with the first lock expected about 23:00 UK until the first lock exists, paused only after one
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:02:49 +00:00
igneum-labs
892c27c6f1 built pages after the master merge 2026-10-08 17:01:09 +00:00
igneum-labs
ad0c5ad988 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 17:01:09 +00:00
igneum-labs
3b54f32f9b /oracle: the igneum-devnet-4 verifier (0x874D8Be5…) set on the devnet-4 oracle; its table installs at the chain's first lock (about 23:00 on 8 October)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:01:08 +00:00
igneum-labs
42269edefb Bridge: the igneum-devnet-4 verifier on Sepolia at 0x874D8Be5385474414aeb69EE4AB8374DA34b8c1F (Igneum 2.0 devnet, chain id 4465; table at the first lock); docs/contracts/sepolia.json
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:00:45 +00:00
igneum-labs
fb706d427b docs/plans/igneum-2.0.md: "The finish line" and "Pins the finish line missed" (the plan file from the Mac checkout, 8 October 2026, 18:0x BST), merged onto master's copy
Rule 26: the same file master holds, merged not replaced: a three-way merge of the checkout's file over master's copy with the
31fe2804 landing as the base; the finality lane's D5 partition-row block (fafbddd5) stays, the two new sections are added, 22 lines,
no deletions. Documents only.
2026-10-08 17:00:13 +00:00
igneum-labs
67190b8afd Bridge: the Install script (voter table and optional certificate onto an already deployed verifier; for a chain whose table is read at its first lock, igneum-devnet-4)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:57:34 +00:00
igneum-labs
fe7bd9fc43 Connected state: the PC 1 lock row (the window +1.6 percent of energy per hash at the 1,300 lock, +5.9 unlocked; the score re-read at x 1.016: 1.08x node-for-node, 1.07x a node ahead; the verdict unchanged)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of dd9e114c3 (dd9e114c3a) for the box mirror master
2026-10-08 16:57:26 +00:00
igneum-labs
83a6430d23 Oracle for the 2.0 devnet on Sepolia (0xbb345004…, statements with chain id 4465, on the shared verifier); /oracle says the shared verifier's installed table is Devnet 3's until devnet-4's lands
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:54:21 +00:00
igneum-labs
259bba08f4 Merge box master e6d353bd into proving-payment-guest (the 60x file lists both switches)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:53:17 +00:00
igneum-labs
d681c1c659 Shard guest re-pinned with the D4 proving-payment split: shard program id 0x282dcfce483565a358268a6228b32beb1c48f4ee58095950364f9e5e6f5122b4, aggregator id 0x3fd721e8482357780fd55904101cbdc316a5a7ec07c0dac47040696d57a328bd (pin-guests.sh on build-1, SP1 6.8.1, 17:49 UK; the host pinned tests 10 passed)
Every prover and verifier moves to a host and a node built from this elf/ together; an object that pins these ids under verifier_in_consensus takes the node release that embeds them. proving_payment_activation_daa stays at never until an object pins this shard id.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:49:41 +00:00
igneum-labs
15d8162e03 Shard guest: the D4 proving-payment split mirrored behind FixtureEnv::proving_payment_to_pool (known-failed first; the ELF and program id not yet re-pinned)
The guest core applies the node's split at both charge sites (proving_payment_split, the same arithmetic as igneum_exec::executor): off, the whole proving charge burns as every existing fixture recorded; on, 90 percent of pgas used x f_p is credited to PROVING_POOL_ADDRESS and 10 percent burns. The flag is serde-default false, so every fixture written before it reads unchanged and reproduces its roots; the exporter reads it from the node's segment JSON (provingPaymentToPool, proving-payment 930b6322 of the fork). Test: host fee_switch_tests::the_proving_payment_flag_moves_90_percent_of_the_charge_to_the_pool (off: the recorded roots and the subsidy credit alone in the escrow; on: 90 percent of the charges in the escrow, another post-root, the proving work unchanged); fee-switch tests 5 passed on build-2 at 17:44 UK. The guest ELF, verifying key and program id in elf/ are NOT re-pinned by this commit: until pin-guests.sh runs on the new sources and the object pins the new id, proving_payment_activation_daa stays at never on every object.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:45:03 +00:00
igneum-labs
0e6dbe8cd0 class v5 design page: the class v6 kit's second zip (098e64c3, the window texts in) on the row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:26:08 +00:00
igneum-labs
05f04430be class v5 design page: the class v6 all pack reads equal on Metal and Apple OpenCL with the window texts (four of six platforms at 59e6708e46f1e87c)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:24:13 +00:00
igneum-labs
76cf0b684d class v6 kit: the PC job scripts expect the CUDA reference 59e6708e46f1e87c on the all pack now that the window's OpenCL text exists (the second zip)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:22:08 +00:00
igneum-labs
2c9188f113 Merge remote-tracking branch 'build/class-v6' into class-v6-kits 2026-10-08 16:22:08 +00:00
igneum-labs
20ed9276be class v5 design page: the class v6 kit row (the zip 2c56bd06 from the class-v6 merge, the reads so far per pack and platform, the all pack's Mac refusals by the stub, the window texts owed, the ds55 form not in the pack)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:12:36 +00:00
igneum-labs
f62ce7e4c9 class v6 kit: the PC job scripts (the AMD and the Arc hosts on the partner hl-v6-foldrw, expected 5a6ad122a71a888f; the all pack's OpenCL refusal line as the record)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:07:38 +00:00
igneum-labs
e30f3fe3ae Fast-time 60x file: proving_payment_activation_daa listed (never)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:01:21 +00:00
igneum-labs
c73722d7d6 Merge remote-tracking branch 'build/class-v6' into class-v6-kits 2026-10-08 16:01:11 +00:00
igneum-labs
a7b4799b35 class v6 kit (8 October 2026): the Metal hosts size the dataset by the ds55 words and items defines (packbench and the worker's pack path; a power-of-two pack reads unchanged: hl-v6-fold f6c34aa6e87bf211 on both builds), the kit's box script for the all-together pack and its known-failed partner, the runner's script switch
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:23:59 +00:00
igneum-labs
912835ba64 class v6 kit: the two-pack emulation runner builds each orientation in its own dir
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:18:03 +00:00
igneum-labs
e6e6c69302 class v6 kit: the two-pack emulation runner (the known-failed shape: the plain-address pack and the fold pack of one seed read two ids and two fingerprints on the worker's own kernel text)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:17:09 +00:00
igneum-labs
4907565f0f Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 13:49:16 +00:00
igneum-labs
48b548ef5e class v5 design page: the Intel row moves to its fingerprint (the Arc B580 reads 82b19cbde8557ea5 on the rebuilt kit; the rotate fold was the whole fault; six platforms equal)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:49:15 +00:00
igneum-labs
24f9cb33ea Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 13:18:20 +00:00
igneum-labs
1c610c94c4 class v5 harness: the attempt-3 read's standalone path (--a3-only, --a3-known-failed) and the runner's stdout line; the check's live EQUAL on the rebuilt pair and the known-failed DIFFER on the page with the logs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:18:19 +00:00
igneum-labs
fa07d2212c class v5 harness runner: the attempt-3 seed's inputs travel to the box with the harness
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:09:48 +00:00
igneum-labs
cd23554835 class v5 harness: the pairing rule's fixed attempt-3 seed read on every run (kaspa-pow program-id beside the run's CLI, attempt and id against the record; an unreadable side fails the check); the seed's inputs pinned under the harness dir; the page row
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:09:23 +00:00
igneum-labs
9e84c33af2 class v5 design page: the pin's FAIL seed re-read (the freeze draws 1f1cf82877f46ee6 at attempt 3; both FAIL ids were foreign crates; the seeded attempt-3 case next)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:01:28 +00:00
igneum-labs
d1a0db4db3 Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 12:57:31 +00:00
igneum-labs
3cfa8cd9f5 class v5 design page: the pairing read-back on the rebuilt 0.3.25 pair (PASS, id for id on epochs 8 to 10 against the freeze CLI at exactly e4534d19; no attempt-3 seed in the run, the seeded case next), the logs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:57:30 +00:00
igneum-labs
5277dc8f8d class v5 design page: the 0.3.25 pin's pairing STOP (the attempt-3 seed divergence, the embedded crate path), the pairing rule's attempt-3 line, the read-back plan
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:36:47 +00:00
igneum-labs
9d9378024d class v5 harness: POW_BIN points the CLI id read at another igneum-pow build (the freeze CLI for a pairing read-back)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:36:23 +00:00
1372 changed files with 290968 additions and 1757 deletions

View file

@ -141,7 +141,11 @@ var View = (function () {
case 'executed': return { word: 'executed', tone: 'ink', why: 'in ' + blk };
case 'proven': return { word: 'proven', tone: 'ink', why: 'in ' + blk + ', proof paid' };
case 'finalised': return { word: 'finalised', tone: 'ink', why: 'under a locked checkpoint, not yet verified here' };
case 'finality not active': return { word: 'finality not active', tone: 'ink', why: 'under a locked checkpoint; finality is paused on the network' };
// section 9 of docs/spec/finality-guarantees.md: a block under a locked checkpoint is finalised even while the network's
// finality is paused; the pause is the network's word, never a transaction's
case 'finality not active': return { word: 'finalised', tone: 'ink', why: 'under a locked checkpoint, not yet verified here; finality is paused on the network above it' };
// review B F04: a recovery lock is labelled "recovery", never plain "final" (the node lane's lockKind word)
case 'finalised by a recovery lock': return { word: 'finalised (recovery lock)', tone: 'ink', why: 'under a recovery lock: the surviving majority’s lock after a long pause, not a certified checkpoint; not yet verified here' };
case 'unknown': return { word: 'pending', tone: '', why: 'not in any block the node holds' };
}
if (e.finality === 'in_block') return { word: 'included', tone: '', why: 'in ' + blk };

View file

@ -103,7 +103,14 @@ test('one state word per row: the wallet\'s verified final wins, failed from the
assert.deepEqual(V.stateWord(e, 'proven'), { word: 'proven', tone: 'ink', why: 'in block 140,262, proof paid' });
// the node says finalised but this wallet has not verified the certificate: the word, not the molten tone
assert.deepEqual(V.stateWord(e, 'finalised'), { word: 'finalised', tone: 'ink', why: 'under a locked checkpoint, not yet verified here' });
assert.deepEqual(V.stateWord(e, 'finality not active'), { word: 'finality not active', tone: 'ink', why: 'under a locked checkpoint; finality is paused on the network' });
// section 9 of docs/spec/finality-guarantees.md (8 October 2026): a block under a locked checkpoint is finalised even while
// the network's finality is paused; the pause is the network's state word, never a transaction's. Known-failed first: the
// node's "finality not active" word was shown on the row.
assert.deepEqual(V.stateWord(e, 'finality not active'), { word: 'finalised', tone: 'ink', why: 'under a locked checkpoint, not yet verified here; finality is paused on the network above it' });
// review B F04 (the founder, 8 October 2026): a recovery lock is labelled "recovery", never plain "final": the node's word
// for a transaction under one (the node lane's lockKind) reads on the row as finalised by a recovery lock. Known-failed
// first: the word fell through to the label.
assert.deepEqual(V.stateWord(e, 'finalised by a recovery lock'), { word: 'finalised (recovery lock)', tone: 'ink', why: 'under a recovery lock: the surviving majority’s lock after a long pause, not a certified checkpoint; not yet verified here' });
assert.equal(V.stateWord(e, 'unknown').word, 'pending');
// no node word yet (the public RPC, or not asked): the wallet's label
assert.deepEqual(V.stateWord(e, ''), { word: 'included', tone: '', why: 'in block 140,262' });
@ -114,8 +121,8 @@ test('one state word per row: the wallet\'s verified final wins, failed from the
assert.deepEqual(V.stateWord(r, ''), { word: 'executed', tone: 'ink', why: 'in block 140,201' });
assert.equal(V.stateWord(entry({ hash: 'proving-1-0', kind: 'proving', finality: 'final', checkpoint: 9 }), '').word, 'finalised');
// never a stronger word than the chain's: the words the row can show are exactly the node's plus failed
const words = new Set(['pending', 'included', 'executed', 'proven', 'finalised', 'finality not active', 'failed']);
for (const w of ['pending', 'included', 'executed', 'proven', 'finalised', 'finality not active', 'unknown', '']) assert.ok(words.has(V.stateWord(e, w).word), w);
const words = new Set(['pending', 'included', 'executed', 'proven', 'finalised', 'finalised (recovery lock)', 'failed']);
for (const w of ['pending', 'included', 'executed', 'proven', 'finalised', 'finality not active', 'finalised by a recovery lock', 'unknown', '']) assert.ok(words.has(V.stateWord(e, w).word), w);
});
test('the row model: kind word, who, sign, amount, the rows that need the node\'s word', () => {

View file

@ -0,0 +1,37 @@
// SPDX-License-Identifier: MIT
pragma solidity ^0.8.24;
import {Vm, VM_ADDRESS} from "../test/Vm.sol";
import {IgneumCertificateVerifier} from "../src/IgneumCertificateVerifier.sol";
/// Installs (or replaces) the voter table on an already deployed verifier (BRIDGE_VERIFIER) from the vectors file in
/// BRIDGE_TABLE_JSON (a gen.mjs table or chain output: keys, weights, index) and, when the file carries a certificate
/// (bitmap, signature), submits it. The deployer key comes from BRIDGE_DEPLOYER_KEY in the environment, never printed.
/// Used for a chain whose table is read at its first lock, after the contract itself was deployed (8 October 2026,
/// igneum-devnet-4: the contract first, the table when the weight window filled).
///
/// BRIDGE_VERIFIER=0x.. BRIDGE_TABLE_JSON=test/vectors/dn4-table.json forge script script/Install.s.sol:Install --rpc-url sepolia --broadcast --sig "run()"
contract Install {
Vm constant vm = Vm(VM_ADDRESS);
function run() external {
uint256 key = vm.envUint("BRIDGE_DEPLOYER_KEY");
IgneumCertificateVerifier v = IgneumCertificateVerifier(vm.envAddress("BRIDGE_VERIFIER"));
string memory j = vm.readFile(vm.envOr("BRIDGE_TABLE_JSON", "test/vectors/dn4-table.json"));
bytes[] memory keys = vm.parseJsonBytesArray(j, ".keys");
uint256[] memory w = vm.parseJsonUintArray(j, ".weights");
bytes memory packed;
uint64[] memory weights = new uint64[](w.length);
for (uint256 i = 0; i < keys.length; i++) {
packed = abi.encodePacked(packed, keys[i]);
weights[i] = uint64(w[i]);
}
uint64 index = uint64(vm.parseJsonUint(j, ".index"));
vm.startBroadcast(key);
v.installTable(index, packed, weights);
if (vm.keyExistsJson(j, ".bitmap")) {
v.submitCertificate(index, vm.parseJsonBytes32(j, ".checkpoint"), vm.parseJsonBytes(j, ".bitmap"), vm.parseJsonBytes(j, ".signature"));
}
vm.stopBroadcast();
}
}

View file

@ -0,0 +1,249 @@
# Binding review: template, nonce, work and result (October 2026)
Igneum 2.0 register row (plan p. 10, missed pins): "Cryptographic review of the template, nonce, work and result
binding: no expensive intermediate reused across cheap winning attempts." Adversarial seat, 8 October 2026 (evening,
UK), with the hash lane for the generator's side. Sources: the crate (`igneum-pow` at the mirror's master 494fb981),
the fork's node line (`release-2.0.0-node` 9fc9f42a on the box mirror; the Mac's vendor copy is the 7 October master
and is not used where the two differ), spec 01, 02, 04 and 09, and the attack pass of 7 to 8 October
(`docs/analysis/attack-pass-2026-10.md`, rows F3, F8, F9, F1 and their records). Every number is either from a
record named beside it or marked Designed. No consensus code is changed by this document.
The question in one line: for every quantity that is expensive to compute, which inputs is it a function of, and
can a miner hold it fixed while it varies something cheap that still produces distinct winning attempts? A "winning
attempt" is a 64-bit lane hash at or below the target for a header the chain accepts.
## 1. What the hash commits to, from the code
### 1.1 The chain of bindings
| Step | Function of | Where | Cost |
|---|---|---|---|
| The pre-PoW hash `H` | every header field but the nonce: version, parents (every level), `hash_merkle_root`, `accepted_id_merkle_root`, `utxo_commitment`, timestamp, bits, `daa_score`, `blue_score`, `blue_work`, `pruning_point`, `vote_key_hash`; the nonce field zeroed | fork `consensus/core/src/hashing/header.rs:7` (`hash_override_nonce_time(header, 0, header.timestamp)`), `consensus/pow/src/igneum.rs:115` (`header_prehash`) | one BLAKE2b over about 200 bytes per template |
| The init words `I[0..7]` | `seed_words_from_bytes("igneum-block/" || H || nonce_hi_le32)` | `igneum-pow/src/bind.rs:48` (`block_init_bytes`, 49 bytes), `:57` | four FNV-1a-64 passes over 49 bytes per `(H, nonce_hi)`: about 200 integer ops |
| The lane registers at start | `r[i] = splitmix32((n XOR I[i]) + 0x9e3779b9 (i + 1)) XOR I[(i + 1) AND 7]` for lane nonce `n` (the low 32 bits of the header nonce) | `verify.rs:570` (`interpret_warp_core`); spec 1.6 | 8 splitmix32 per lane |
| The program | the epoch seed: on the node line, the hash of the last selected-chain block below `epoch x 3,600 - 600` on the header's own selected-parent chain (`pow_epoch_seed_score`, `epoch_seed`), attempt by attempt through acceptance (spec 1.4.6.6); the era seed from the era VDF (spec 4.4) | fork `consensus/core/src/igneum.rs:343`, `consensus/src/pipeline/header_processor/processor.rs:365` (release-2.0.0-node); `generator.rs`, `accept.rs` | once per epoch per node: the draw plus acceptance, about 1.8 core-s per candidate at (c'') and (c''') (attack pass, F9 lane (d)), 3.2 candidates per seed |
| The dataset | the day key `seed_words_from_bytes("igneum-day/" || day_le64)` with `day = header.timestamp_ms / 86,400,000` (class v5 adds the epoch's state leaves) | `bind.rs:62`, fork `pre_ghostdag_validation.rs:147` (`day: day_index(header.timestamp)`); spec 1.8 | once per day per node: the 256 MiB cache fill (175 ms on one core) and, for a miner, the 1 to 2 GiB dataset |
| One lane hash | the program applied to the 32 lanes of the aligned group `n AND NOT 31`, 8 iterations of 64 base instructions plus the 256-instruction shadow block 27 times, 16 loads per iteration reading `dataset[load_index(x)]`, the output fold over `r0..r7` | `verify.rs:555` to `:654` | 55,296 instructions and 128 dependent dataset reads per lane; the warp is the unit |
| The verdict | `hash_bound(H, nonce) <= target64(bits)`, `target64` the top 64 bits of the 256-bit target | `bind.rs:128`, `igneum.rs:120`, `:173` | one 64-bit compare |
So a winning attempt is a function of `(H, nonce_hi, n, program(e), dataset(day), target)`, and every one of `H`,
`e` (through `daa_score` and the parents, both in `H`) and `day` (through the timestamp, in `H`) is under proof of
work. The expensive quantities are three: the program (per epoch), the dataset (per day), and the hash itself (per
warp). The cheap variables are the nonce's two halves and anything in the template the miner may change.
### 1.2 What is in the template that a miner may change, and what each change costs
| Field | Who sets it | Freedom | What changes downstream |
|---|---|---|---|
| nonce, low 32 bits (`n`) | the worker | 2^32 per `I`, iterated 32 at a time | the lane registers only; the warp's 32 lanes are hashed together |
| nonce, high 32 bits | the miner (`main.rs:565`, a random `hi`, incremented when the lane space wraps) | 2^32 per template | `I`, hence every register of every lane: a new warp space |
| timestamp | the miner, within Kaspa's bounds (10 s future tolerance, above the sampled past median) | about 10 s of milliseconds, 10,000 values | `H`, hence `I`; and the DAY at a day boundary (1.4) |
| the coinbase and transactions | the miner (mode A or C) or the pool | unbounded | `hash_merkle_root`, hence `H` |
| parents | the miner, among known tips within the merge bound | a few | `H`, `daa_score`, `blue_work`, `blue_score`, and the epoch seed if the selected parent's chain differs below the seed score |
| `vote_key_hash` | the member's client (spec 9.4.1 item 1) | one per key the miner holds | `H` |
| bits, `daa_score`, `blue_score`, `blue_work`, `pruning_point`, `accepted_id_merkle_root`, `utxo_commitment` | the node from the parents | none | |
Every one of these is an "extra nonce": it changes `H`, so `I`, so every register from the first instruction. None
of them is free of the hash: a template change costs the whole warp again.
## 2. The nonce's place in the chain and the warp as the unit
The lane nonce enters once, at register initialisation, XORed with each init word before splitmix32 (`verify.rs:570`).
Nothing later reads the nonce. So the hash of lane `n` is the composition `fold(program^8(init(n, I)))` and the only
state shared across lanes is what `shfl` moves (lane `l` reads lane `l XOR mask`), which couples the 32 lanes of the
aligned group into one computation. The consequences:
- A warp's 32 hashes are 32 attempts for the price of 32 lanes of work; no lane's result is reusable for another
nonce because every register of every lane starts from the nonce.
- The high half of the nonce is one `I` per 2^32 lanes. A miner that changes `nonce_hi` pays one FNV over 49 bytes
(about 200 ops, `bind.rs:48`) and gets a fresh warp space; it does not need to, since 2^32 lane nonces at 141.8
MH/s on an RTX 5090 (attack pass F9, the card row) is 30 s of work per `I`, 30 templates' worth at 1 block per
second. The crate's own test `bind::bound_hash_properties` pins that two `nonce_hi` values give different warps
under one `H` and that the lane hash depends on `H` (the fork's engine test pins the timestamp, `igneum.rs:237`).
- The pool's share check recomputes `hash_bound(job.prehash, nonce)` for the claimed nonce (`pool/src/verify.rs:52`),
so a share binds the whole template through `H`; a nonce under another template "hashes differently and is
refused as a wrong hash" (the crate's test `the same nonce on another template`, `verify.rs:101`).
## 3. What the 256 loads and the shadow block compute from
### 3.1 The loads
Each of the 16 load sites per iteration (128 per hash) reads `dataset[load_index(era, site, x)]` where `x` is the
source register's value in that lane at that instruction (`verify.rs:759`): `idx = x AND MASK` without an era, or
`rotl(x M, R)` masked into the site's window under an era (`load_index`, `:18`). The address is therefore a function
of the lane's register state, which from the first instruction is a function of `(I, n)` and, after the first load,
of dataset words too. The attack pass measured the part that is a function of `(I, n)` alone (F9, sub-row (c), taint
analysis `init_determined_sites`): on the devnet epoch-0 program the loads at instructions 7, 8, 9, 10 and 31 of
iteration 0; over 2,000 seeds 1 to 7 sites per program, median 3, always in iteration 0 only. Everything after the
first dataset word is data-dependent.
The 256 loads of a hash's "working set" are the 128 reads of its own lane plus the reads the warp's other lanes
make, and they are distinct per hash by construction: the acceptance rule refuses a program whose site reads fewer
than 120 distinct addresses per hash on average (`MIN_DISTINCT_SUM`, spec 1.4.6.4), whose 32 lanes compute one
address at any site (`LaneConstantSite`), whose site's distinct-index ratio over 2^20 evaluations falls under 0.98
(class v4, (c'')) or 0.995 (class v5, (c''')).
### 3.2 The shadow block
The shadow block is 256 ALU instructions from the ten non-load families (`generator.rs:413`), applied 27 times after
instruction 63 of every iteration with the iteration's `sel` (`r0` at the iteration's start; `verify.rs:609`,
`:631`). It has no loads. Its input is the lane's eight registers at that point and `sel`; its output is the
registers for the next iteration. It is therefore a per-lane function of the lane's state, with `shfl` coupling
lanes inside it as in the base block. Nothing in it is shared across nonces, iterations or templates: the same block
applied 27 times to a different register state each time. The attack pass's F1 row measured what an honest compiler
can remove from it (at most 4.688 percent of its instructions on the frozen class v5 tip at 10^5 programs, two
programs at 5.078 percent in the 2.2 x 10^5 partial, both at the honest-compiler parity the ruling AP-F1-1 names), so
the block's cost per application is fixed to within that margin for every implementer.
## 4. Where a result could be reused, each with its cost and the rule or the finding
The seven places an expensive intermediate could be shared across cheap attempts, in the order a miner would try
them. "Rule" names what forbids the reuse or makes it worthless; "cost" is what the reuse would save against what it
costs.
| # | Reuse | What is shared | Across what | Cost to the attacker | Rule or finding |
|---|---|---|---|---|---|
| R1 | The dataset | the day's 1 to 2 GiB and its 256 MiB cache | every hash of the day, every miner | nothing: this is the design (the memory-hard dataset is the shared intermediate on purpose) | Intended. The question is whether a SMALLER shared structure serves: the hot set (R5) and partial storage (R6) |
| R2 | The compiled program | the epoch's kernel | every hash of the epoch, every miner | nothing: intended; one compile per epoch per card | Intended. A miner that grinds the epoch seed to get a favourable program is R7 |
| R3 | The init words `I` | one FNV result | 2^32 lane nonces | nothing to gain: `I` costs about 200 ops and a warp costs 1.8 million lane-instructions (F9's count) | No rule needed; the ratio is 10^-4 |
| R4 | The register prefix before the first load | the first instructions of iteration 0, a function of `(I, n)` | nothing: `n` is per lane, so there is no second attempt with the same prefix | zero reuse: each lane's prefix is its own | Bound by construction (spec 1.6: the nonce enters every register) |
| R5 | A hot set of items | a few MB that serves a large share of reads | every hash of the epoch | the attack pass's F8 and F9 (b): at the frozen tip no program's top 0.1 percent of items carries more than 0.23 percent of reads (256 seeds, 245 within 1.2x of the window model), hot-set verdict clear on every seed; the exemplar that reads 3.35 percent (class v4 seed 100767) is refused by (c''') | AP-F8-1: the residue is a quarter-bit bucket concentration at one narrow-window site, named by mechanism, no cacheable hot set; the per-site largest-bucket bound is a next class's item |
| R6 | A partial dataset or cache | a stored fraction `f` of the cache lines, the rest recomputed | every hash | F3: every cache line costs exactly `j + 1` block evaluations from nothing (0 of 1,024 lines under the bound), the storage-against-recompute curve at f = 1/8 is 3.17 ops per read optimal against the 3.5 the funding note assumed, and a partial-cache chip is worse than the full mirror at every f below 1 | F3 PASS; the chip edge is the latency ladder's business, not a binding hole |
| R7 | The epoch seed | the program of epoch `e + 1` | every hash of that epoch | a miner who produces the seed block (the last selected-chain block below `3,600 (e + 1) - 600`) picks among the candidate blocks it can produce; each candidate costs a full block's work, and the 600-score lead gives every miner the same 10 minutes to compile; under the devnet stand-in there is no VDF on the epoch seed (spec 4.3 Designed, the era VDF Implemented) | Spec 4.3 (the 1,200-s lead and the 600-s VDF) is the rule; on the node line the lead is 600 and the VDF is not in the node. The grind's value is bounded by the program-to-program variance of hash rate: the attack pass's F8 and F1 rows put every accepted program within a few percent of the mean on the card (the per-program spread is the F10 ladder's reading), so a candidate block burned to pick a 2 percent better program is a bad trade at any hashrate under 50 percent. Finding, minor: the VDF of 4.3 is the stated defence and is not implemented; the lead alone does not stop the pick. Routed to the Counter ASIC lane's D1 list as a 2.0 item (6) |
| R8 | The day | the dataset of day `d` | every hash of the day | the day is keyed on the header TIMESTAMP (`pre_ghostdag_validation.rs:147`), which the miner sets within about 10 s; at a day boundary a miner may hash on either day's dataset for about 10 s, and a verifier must hold both caches across the boundary (the engine's `note_chain_day`, `:139`, builds the next in the background) | No gain: both datasets are full datasets. Observation: spec 1.12 keys the day on DAA score and the node keys it on the timestamp; one of the two texts moves (6) |
| R9 | The attempt chain | the acceptance work of attempts 0 to k-1 | every node and miner of the epoch | nothing to a miner: attempts are deterministic from the seed; a miner cannot choose the attempt. A verifier's cost is the row below | No rule needed |
| R10 | The warp | one hash computation | 32 nonces | intended: the 32 lanes are 32 attempts for 32 lanes of work, coupled by `shfl` so no lane is computable alone | Intended (spec 1.9). The verifier dedupes items within a warp (`verify.rs`, the 4,096 derivations bound); a miner that finds warps whose loads coincide is F9 (c): one coalesced pair per 3,400 tries is worth 0.2 percent of one warp and costs 2.4 hashes of search; five sites fully coalesced would be worth 43 percent and has probability 2^-115 per draw |
| R11 | The template | one `H` | 2^64 nonces | intended; a template change is a new `H` and costs nothing but one BLAKE2b; it buys nothing, since the nonce space under one `H` is 2^64 | No rule needed |
| R12 | The vote key | one `vote_key_hash` | every block of the key | a miner with many keys hashes under one `H` per key; keys are free (spec 03 W6) and weight is blocks, so more keys is more templates, not more hashes per hash | No gain; the pool design document (pool-vote-key-commitment.md) covers the pool case |
The cheapest reuse that survives as a gain is R10's coalesced pair at 0.2 percent of one warp per 2.4 hashes of
search, which is a loss, and R5's quarter-bit bucket, which is under the window model's own spread. No path was found
by which an intermediate computed once serves a second winning attempt at less than the honest cost of that attempt.
## 5. Known-failed tests and measured lines
| Test | Known-pass | Known-fail | Where | Result |
|---|---|---|---|---|
| The lane hash depends on `H` and on `nonce_hi` | two headers differ in one field: different warps | the same `(H, nonce_hi)`: the same warp, bit for bit | `igneum-pow/src/bind.rs`, `bound_hash_properties`, `bound_vectors`; the fork's `igneum.rs:200` smoke test (timestamp bound, `:237`) | see the run line below |
| A nonce on another template is refused | the pool's check against its own job | the same nonce on another template: `wrong_hash` | `pool/src/verify.rs:101`, `the same nonce on another template hashes differently` | in the pool crate's suite (pool.md section 4) |
| A stateless hasher is wrong on every class v5 item | the dataset built with the leaves | the dataset built without them: every item differs | `igneum-pow/src/state.rs:200`, `a_stateless_hasher_is_wrong_on_every_item` | see the run line below |
| No cache line costs less than `j + 1` | the real chain | a flattened chain (the F3 harness's known-fail) | `docs/analysis/attack-pass/f3-cache.md`, the two firings | PASS, 7 October |
| No hot set on the frozen tip | the window-model control | a planted hot site (F8's known-fail) | `f8-uniform.md` sections (d) and (e) | PASS, 61 of 64 and 245 of 256 within 1.2x |
| Init-determined sites are in iteration 0 only | the taint trace | a program with a load whose address never absorbs a word (F9's planted case) | `f9-grind.md` sub-row (c) | 1 to 7 sites, iteration 0 only, 2,000 seeds |
Run line (box 2 through `tools/build-remote.sh`, `cargo test --release -p igneum-pow -- bind::
state::a_stateless_hasher_is_wrong_on_every_item`): 8 October 2026, 19:0x UK, box 2 (igneum-build-2) through `tools/build-remote.sh --box 2`, the crate at the mirror's master 494fb981: `bind::tests::bound_hash_properties` ok, `bound_vectors` ok, `init_bytes_layout` ok, `day_bytes_layout` ok, `pow256_and_target64` ok, `closed_form_bound_also_works` ok (6 passed, 0 failed, 0.43 s); `state::tests::a_stateless_hasher_is_wrong_on_every_item` ok (1 passed, 0 failed, 2.15 s). The pool crate's `the same nonce on another template hashes differently` and the fork engine's timestamp-bound test are in their crates' suites (pool.md section 4; `igneum.rs:200`), not re-run here.
## 5a. Finding A05 of the external review: the FNV initialisation and the 64-bit fold
The external review's finding A05 (`docs/analysis/review-2026-10-08/evidence.md`): the seed and the header-bound
initialisation are four salted FNV-1a-64 passes with a final mix (`seed.rs:37`, `bind.rs:57`), the final state
reduces by rotated XOR to 64 bits placed in the top 64 bits of the 256-bit proof-of-work value (`verify.rs:649`,
`bind.rs:76`), FNV is non-cryptographic by its own specification, and ProgPoW's keccak-f800 at both ends of a cheap
inner mix is the pattern to measure against. Two questions: can one expensive intermediate be reused across cheaper
attempts through the initialisation or the fold, and is the binding to job and nonce complete. The argument, then
the measured lines, then what a change would be if one were wanted.
### 5a.1 What the initialisation has to do, and what it does not
ProgPoW's keccak at the start exists because its inner mix is a fixed structure for a 50-block period and a hasher
must not be able to choose or correlate its inputs cheaply; the keccak at the end exists because the inner mix is
not a cryptographic function and its output must not be shaped. Igneum's initialisation does not carry that burden
alone, for three reasons that are in the code:
1. The attacker does not choose the FNV input. The 49 input bytes are the tag, `H` and `nonce_hi` (`bind.rs:48`). `H`
is a BLAKE2b-256 over the template (the chain's `BlockHash`, `hashing/header.rs:7`); the only way to change it is
to change a header field, which gives a fresh 256-bit value the attacker cannot steer. The attacker's whole
freedom at the FNV input is the 32 bits of `nonce_hi` under a fixed `H`.
2. FNV-1a with the final mix gives no control over its output beyond brute force over those 32 bits. Each pass is
`h = (h XOR byte) x P` over the bytes, then `h ^= h >> 33; h *= C; h ^= h >> 33`. The mix is a bijection, so a
target output pins the pre-mix state; the last four bytes of the chain are then four steps `s_{k+1} = (s_k XOR
b_k) x P`, each inverted by `b_k = (s_{k+1} x P^-1) XOR s_k`, which must land in 0..255: probability 2^-56 per
byte for a random target. So hitting a chosen 64-bit pass output costs the full 2^64 and hitting a chosen 32-bit
word of `I` costs 2^32, the brute-force figures. The measured control line below reads this at the byte scale:
256 tries of `nonce_hi` hit a chosen byte of `I[7]` at the random rate.
3. What a weak initialisation would give is an `I` correlated across `nonce_hi` values or across templates, so that
the prefix of the program (the init-determined loads of F9, 1 to 7 sites in iteration 0) could be shared. The
avalanche lines below read 128 of 256 bits flipped per input bit, with the min and max inside the binomial's
range; no two of 2^18 `nonce_hi` values under one `H` share an `I`, nor a single 64-bit pass.
The non-cryptographic property FNV lacks, preimage resistance against a chosen input, is not used: nothing in the
chain asks that `I` be hard to invert, only that it be a near-uniform function of `(H, nonce_hi)` that the attacker
cannot steer, and the steering is bounded by BLAKE2b on one side and by 32 bits on the other.
### 5a.2 The fold
The fold is linear over GF(2): `lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21)`, `hi = r4 ^ rotl(r5,9) ^
rotl(r6,18) ^ rotl(r7,27)`, and the verdict reads `hash <= target64` with `hash = hi || lo` (`bind.rs:83`,
`target64_from_le256`). What a hasher would want from a linear fold is to shape the top bits of `hi` cheaply at the
end. Three facts close that:
- Nothing cheap varies at the end. The nonce enters once, at initialisation (section 2); the last instructions
before the fold are the shadow block's 27th application in iteration 7, pure ALU on the lane's eight registers,
and every register at that point is a function of the whole program over the dataset words the lane read. There
is no second cheap input to vary after the expensive part; the warp is recomputed from the start for every nonce.
- The top 64 bits need `r4..r7` in full and those depend on `r0..r3` throughout the program (every register is the
`dst` of an injecting write, part (b), and the draw's source rule keeps the dataflow fresh, part (a')), so no
register is skippable.
- The fold's output is tested per program: part (c) of acceptance refuses a program whose output bits' ones-count
over 2,048 hashes falls outside 1,024 plus or minus 136 (`OutputBias`, `accept.rs:68`, 6 sigma), and F8's
cross-hash histogram rows read the 64-bit outputs uniform at 2^24 nonces on every accepted seed. A program whose
final state left the fold biased is refused before it is the epoch's program.
Where ProgPoW needs keccak at the end is that its mix is fixed and public for a period, so an output-shaping
structure could be found once and used for 50 blocks; Igneum's program is a fresh random draw per epoch that is
itself tested for output bias, so the fold's linearity has no fixed structure to exploit. Against a hasher that
tries anyway: the cost of computing `r4..r7` is the hash, and the comparison is one 64-bit compare after it.
### 5a.3 Is the binding to job and nonce complete
A job is `(prehash, target64, share_target64, nonce_start, nonce_count)` (spec 9.5); a share is a nonce under that
prehash. The lane hash is `fold(program(init(n, I(H, nonce_hi))))` with `H` the template's pre-PoW hash, so a share
commits to every header field (the coinbase and the transactions through `hash_merkle_root`, the key through
`vote_key_hash`, the epoch through `daa_score` and the parents, the day through the timestamp) and to both halves of
the nonce. Two nonces give two warps (`bound_hash_properties`); two templates give two `I` (the fork's timestamp
test); a nonce moved to another template fails as `wrong_hash` (the pool's test). Nothing in the computation reads
anything outside `(H, nonce, program, dataset)`, so there is no unbound input a hasher could hold fixed. The 2.0
wire shape adds the key to the job and share lines (spec 09 at master 2e9b3e73) for the pool's evidence, not for the
binding, which the prehash already carries.
### 5a.4 Measured lines (8 October 2026, 19:5x UK, the spec-exact replica `a05/fnv.py` on the Mac, integer arithmetic, seconds of CPU)
| Line | Known-pass | Known-fail | Result |
|---|---|---|---|
| The replica is the spec's function | `seed_words("igneum-genesis")` equals the spec 1.3.1 vector `67a9a7be 1a155b25 fddfb732 4b5af2e8 c55caf33 a27c13b7 06628a48 03852469` | the replica without the final mix must differ | OK; FIRED (differs) |
| Avalanche over `nonce_hi` (one random bit flipped, 20,000 trials) | | | mean 128.02 of 256 bits, min 94, max 160 (binomial expectation 128, sd 8) |
| Avalanche over `H` (one random bit flipped, 20,000 trials) | | | mean 128.01 of 256 bits, min 96, max 158 |
| Collisions over 2^18 `nonce_hi` values under one `H` | | | 0 equal `I` (256 bits), 0 equal pass-0 outputs (64 bits; birthday expectation 1.9e-9) |
| Control: a chosen value for the top byte of `I[7]` reached by one of 256 `nonce_hi` tries, 2,000 trials | | | 1,280 of 2,000 (0.640) against the random expectation 0.633 |
The crate's own lines of section 5 stand beside these (`bound_hash_properties`, `bound_vectors`, the timestamp
test, the pool's `wrong_hash` test).
### 5a.5 Verdict and what a change would be
Verdict: the argument holds; no attack. The initialisation is a near-uniform, unsteerable function of a BLAKE2b
hash and 32 free bits, the fold follows a per-epoch random program that acceptance tests for output bias, and the
binding to the job and both nonce halves is complete through the prehash. No consensus change is named for 2.0.
If main wants the ProgPoW shape regardless, the change is a class version, not a patch, because every vector moves:
| Change | What it buys | Cost | Vectors |
|---|---|---|---|
| Init: `I = BLAKE2b-256("igneum-block/" || H || nonce_hi)` as eight words (`blake2b.rs` exists in the crate) | a cryptographic initialisation by its own specification; no change to the argument above | one BLAKE2b per `nonce_hi` per warp space, about 1 microsecond on a CPU core, nothing on the card (the init is a kernel argument) | every pack's vectors, the acceptance stream (`"igneum-accept/"` is FNV too), the day key, the program seed: a new generator version with a new vector set and a new frozen object |
| Finalisation: BLAKE2b over the 256-bit final state before the fold | removes the fold's linearity as a question | one BLAKE2b per hash on the card, about 2 to 5 percent of hash rate (Designed, unmeasured; ProgPoW pays keccak-f800 per hash) | the same new version |
The seat's recommendation is neither for 2.0: the measured lines and the argument close A05 as written, and the
cost of the second row is paid by every honest card for every hash. The first row is cheap and could ride the next
class version whenever one is cut for another reason; it is named here so the decision is main's, with the vectors
as the price.
## 6. Open questions, named for main
| Id | Question | What closes it |
|---|---|---|
| B1 | The epoch-seed VDF (spec 4.3, 600 s of delay on the seed block's hash) is Designed and not in the node line; the era VDF is. Without it the seed-block producer picks among the candidates it can afford to burn (R7). Is the epoch VDF a 2.0 item, or does the measured program-to-program hash-rate spread (the F10 ladder's reading) close it as not worth a block? | A ruling, with the F10 spread as the number |
| B2 | The day is keyed on the header timestamp in the node (`day_index(header.timestamp)`) and on DAA score in spec 1.12 (R8). Which text moves? The timestamp key makes the day boundary a miner's choice within 10 s and costs the verifier two caches across it; the DAA key makes it a function of the past alone | A ruling; a one-line spec or code change |
| B3 | `seed_source` and `proof_ref` (spec 2.4, fork point a5) are not in the node line's header; the epoch seed is bound through `daa_score` and the parents instead, which is sufficient for binding but leaves the spec's field table ahead of the code | The spec's table marked to the code, or the fields added when the chunked proving protocol needs `proof_ref` |
| B4 | A verifier syncing from genesis derives every epoch's program (the draw plus acceptance, about 6 core-s per epoch at 3.2 candidates): about 15 core-hours per year of chain on one core, parallel across epochs | The IBD cost measured on the node line with the memo (`epoch_seed_memo`) and a per-epoch program cache; a number, not a rule |
| B5 | R10's coalesced-pair search (F9 (c)) is measured as a loss on the RTX 5090; it is not measured on a card whose load completes per lane rather than per warp (an AMD wave64 under the local-memory exchange) | One run of the F9 `grind` per-warp table on a 9070 XT |

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# The int8-dominated class and the ARX-only class: a research record (9 October 2026, CLOSED)
RESEARCH RECORD ONLY. The founder asked at 11:0x UK for "the int8-dominated class"; main closed the build at 11:1x UK
(the coordinator's line: "the int8 class build is CLOSED now ... the frozen v6 stays the algorithm"). This page records
what was cut before the stop, so nobody has to redo it. Nothing here activates. The census, the kit, the GPU self-test,
the J/hash rows and the OpenCL and Metal runs were NOT RUN. The card's measured int8 and ARX microkernel rows are the
hash lane's, on the pods.
## What was cut
| Item | Value |
|---|---|
| Branch, sha | `1p5x-int8` on the box mirror (build-1:/srv/igneum.git), `0592e48e8fbbf37ebb162915b35294dc21fb19a7`, on X1's `a99de07cd` (on the frozen tree `1a938abe4`) |
| igneum-pow/src fingerprint | `9e8fb3c4b987f9b149ab0d9eb3efc8bcc401fe99faad84e7b1a62e6ac897352f` (recipe `cd igneum-pow && find src -type f \| LC_ALL=C sort \| xargs shasum -a 256 \| shasum -a 256`); the frozen `5f4d6dc6...` is untouched at `1a938abe4` |
| The op | `Op::Dp4a`: `d = d + dot4_u8(a, b)` mod 2^32, `dot4_u8` = the sum of the four unsigned byte products (at most 260,100), the form of `docs/analysis/int8-matrix-family.md` section 2.1. CUDA `__dp4a` on unsigned operands (PTX `dp4a.u32.u32`); OpenCL and Metal the exact integer helper `dot4_u8`; the CPU reference `verify::dot4_u8`. Integer only: no rounding mode or fast-math switch can move a bit. `src2 != dst` by construction (the A08 rule's twin) so the op is a bijection in `d`. Injection is by the accumulator (an add), not by xor: an xor of `d` with a function of `d` is not a bijection, and the add uses the MAC's own accumulate |
| The flag | `LoadClass::fam8` (1 to 4), class suffixes `+int8w50r32`, `+int8w75r32`, `+int8w90r32`, `+arxr16`, `+arxr32`, program-id literal `fam8/` with the table row and the load slots; the re-weight table is off (rw 0), no A02 shuffle reservation (no shfl exists); generator 6 pack shape; the CLI `export ... --program-class v6 --era-hex <era> --fam8 <suffix>` |
| The tables (`FAM8_WEIGHTS`, sum 100, the base program and the shadow block both) | int8w50: dp4a 46, add 11, sub 11, xor 11, rotl 11, rotr 10; int8w75: dp4a 72, then 6, 6, 6, 5, 5; int8w90: dp4a 89, then 3, 2, 2, 2, 2; arx: add, sub, xor, rotl, rotr at 20 each; mul, mulhi, mad, or, shfl at 0 everywhere |
| The energy weighting | the record's 5090 microbench (`docs/analysis/counter-asic-4-research.md`): an ARX op 11.3 pJ (measured); a dp4a instruction 13.1 pJ (APPROXIMATE: 11.3 times the `__dp4a` step-cost ratio 1.16 of the family probe in `docs/bench-log.md`, a time ratio taken as the energy ratio, since no dp4a energy row exists). Count share for energy share s: (s / 13.1) / (s / 13.1 + (1 - s) / 11.3), so 46.3, 72.2 and 88.6 percent |
| Reads per hash | `load_slots x 8 iterations x 2` (the reg64 window runs every instruction twice): r32 = 2 load slots, r16 = 1, over the same 4 GiB dataset (the frozen object reads 256) |
## The five programs on the signing pair (epoch seed af89be5d..., era 0:edc4fa84..., day 20730, node1 state, 4 GiB)
Exported on build-9 with the branch's binary at 10:01 to 10:07 UTC. Every export printed `OVERALL: PASS (pack written)`,
which covers the CPU reference's own vectors and the cache FNV (448274a57f508cbc). The logs are under `rows/`.
| Class string | Program id | Attempt | Base-program op mix (64 instructions) | kernel.cu blake2b-256 | CPU vector, warp 0, lane 0 |
|---|---|---|---|---|---|
| mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w50r32 | e74e5ed6b9686781 | 0 | dp4a 20, add 13, rotl 9, sub 8, rotr 6, xor 6, load 2 | 7bf3072b... | see rows/export-int8w50r32.txt |
| mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w75r32 | 445765984996028a | 0 | dp4a 44, xor 5, rotr 4, sub 4, add 3, rotl 2, load 2 | 76c23add... | rows/export-int8w75r32.txt |
| mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w90r32 | 0d438354ca69b247 | 0 | dp4a 55, rotr 2, sub 2, add 1, rotl 1, xor 1, load 2 | 0913390e... | rows/export-int8w90r32.txt |
| mx8-erad810f22d+sh256x27+state+reg64c+fold+arxr16 | ffc2516557f356be | 0 | add 17, rotr 17, rotl 11, sub 10, xor 8, load 1 | cbfcb244... | rows/export-arxr16.txt |
| mx8-erad810f22d+sh256x27+state+reg64c+fold+arxr32 | ad3b3faaf6ac1ad6 | 1 | xor 16, rotl 15, add 12, sub 11, rotr 8, load 2 | 11cc0bfc... | rows/export-arxr32.txt |
The packs stay on build-9 at /srv/builds/int8/packs-out/ (not copied to build-1; no kit was cut).
## State at the stop, and the rows NOT RUN
| Row | State |
|---|---|
| `cargo check --all-targets` and the release build on build-9 | clean (the binary that exported the packs) |
| The pow suite with `tests/fam8.rs` | NOT RUN (stopped by main's ruling before it started) |
| The CUDA emulation `--check` (the shim gained `__dp4a`) | NOT RUN |
| The CUDA emitter's bit-exact self-test on a card (fk-int8-5090a was handed at 11:05 UK) | NOT RUN: the pod was released unused |
| OpenCL and Metal bit-exactness | NOT RUN |
| The census instruments (hot set, bit bias, exhaustion, the family predicate) | NOT RUN; acceptance on the signing pair took attempt 0 or 1 for all five, the only reading |
| J/hash, rate, memory share on the 5090 and 4090 | NOT RUN here (the hash lane's microkernel rows are the data) |
| Registry | `tools/ci/batches/1p5x-int8-20261009-01.json`, NOT RUN |
Two open design points, if the class is ever re-opened: the dp4a energy is an approximation (a measured dp4a row on
the card settles it), and dropping from 256 to 32 or 16 reads per hash changes the memory share of the hash by an order
of magnitude, so each class needs its own dataset-floor reading before any comparison with the frozen object.

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# 2026-10-09T10:02:30Z host igneum-build-9 cmd: ./bin-int8-wip export --out packs-out/arxr16 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state node1-state.igsd1 --dataset-log2 30 --fam8 arxr16
state stream node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/arxr16
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 0 program id ffc2516557f356be, loads/hash 8; epoch built in 4111.4 ms
op mix: add=17 rotr=17 rotl=11 sub=10 xor=8 load=1; class mx8-erad810f22d+sh256x27+state+reg64c+fold+arxr16, 32 bytes/hash, widths (1,4,16 words) [1, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/arxr16/program.json (57080 bytes)
wrote packs-out/arxr16/identity.json (999 bytes)
wrote packs-out/arxr16/vectors.json (6458 bytes)
wrote packs-out/arxr16/kernel.cu (33724 bytes)
wrote packs-out/arxr16/kernel.cl (41561 bytes)
wrote packs-out/arxr16/program.h (7302 bytes)
wrote packs-out/arxr16/vectors.h (5942 bytes)
wrote packs-out/arxr16/program.metal (29712 bytes)
wrote packs-out/arxr16/program_bound.metal (29864 bytes)
wrote packs-out/arxr16/kernel_bound.cu (31499 bytes)
wrote packs-out/arxr16/kernel_bound.cl (70738 bytes)
wrote packs-out/arxr16/memhard.h (7369 bytes)
wrote packs-out/arxr16/memhard.metal (7258 bytes)
vector warp base 0: lane0 83009d56db7af885 lane31 0e2fbfa86964174e
vector warp base 4096: lane0 84d2a1811e44ad82 lane31 2bb0af48de71546a
vector warp base 1000000: lane0 935efac70dceb4b5 lane31 2686973018dc3407
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T10:02:35Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T10:02:30Z host igneum-build-9 cmd: ./bin-int8-wip export --out packs-out/arxr32 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state node1-state.igsd1 --dataset-log2 30 --fam8 arxr32
state stream node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/arxr32
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 1 program id ad3b3faaf6ac1ad6, loads/hash 16; epoch built in 5607.4 ms
op mix: xor=16 rotl=15 add=12 sub=11 rotr=8 load=2; class mx8-erad810f22d+sh256x27+state+reg64c+fold+arxr32, 64 bytes/hash, widths (1,4,16 words) [2, 0, 0]
seed words 0xe60ed2a2 0x883319ea 0x6b6aa4f7 0xc4c7864e 0x5d7f9712 0x6027eee6 0x37f56d14 0x9555c104
wrote packs-out/arxr32/program.json (57042 bytes)
wrote packs-out/arxr32/identity.json (999 bytes)
wrote packs-out/arxr32/vectors.json (6458 bytes)
wrote packs-out/arxr32/kernel.cu (36687 bytes)
wrote packs-out/arxr32/kernel.cl (44524 bytes)
wrote packs-out/arxr32/program.h (7310 bytes)
wrote packs-out/arxr32/vectors.h (5942 bytes)
wrote packs-out/arxr32/program.metal (32681 bytes)
wrote packs-out/arxr32/program_bound.metal (32833 bytes)
wrote packs-out/arxr32/kernel_bound.cu (34462 bytes)
wrote packs-out/arxr32/kernel_bound.cl (76664 bytes)
wrote packs-out/arxr32/memhard.h (7369 bytes)
wrote packs-out/arxr32/memhard.metal (7258 bytes)
vector warp base 0: lane0 9580077ff8ede4e9 lane31 c860805edb3d7d65
vector warp base 4096: lane0 7027129cabee388c lane31 2dd26ee19f07cbd1
vector warp base 1000000: lane0 b7ff12a5456933bd lane31 81065cdec0efecca
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T10:02:36Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T10:02:30Z host igneum-build-9 cmd: ./bin-int8-wip export --out packs-out/int8w50r32 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state node1-state.igsd1 --dataset-log2 30 --fam8 int8w50r32
state stream node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/int8w50r32
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 0 program id e74e5ed6b9686781, loads/hash 16; epoch built in 5308.1 ms
op mix: dp4a=20 add=13 rotl=9 sub=8 rotr=6 xor=6 load=2; class mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w50r32, 64 bytes/hash, widths (1,4,16 words) [2, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/int8w50r32/program.json (57160 bytes)
wrote packs-out/int8w50r32/identity.json (1003 bytes)
wrote packs-out/int8w50r32/vectors.json (6458 bytes)
wrote packs-out/int8w50r32/kernel.cu (44831 bytes)
wrote packs-out/int8w50r32/kernel.cl (45596 bytes)
wrote packs-out/int8w50r32/program.h (7328 bytes)
wrote packs-out/int8w50r32/vectors.h (5942 bytes)
wrote packs-out/int8w50r32/program.metal (33696 bytes)
wrote packs-out/int8w50r32/program_bound.metal (33848 bytes)
wrote packs-out/int8w50r32/kernel_bound.cu (42606 bytes)
wrote packs-out/int8w50r32/kernel_bound.cl (78520 bytes)
wrote packs-out/int8w50r32/memhard.h (7369 bytes)
wrote packs-out/int8w50r32/memhard.metal (7258 bytes)
vector warp base 0: lane0 7613fbd09ebad410 lane31 8258dbc8c1d8bca6
vector warp base 4096: lane0 1626c89572860ca0 lane31 bdb50545527f7a86
vector warp base 1000000: lane0 70228df867a63fb8 lane31 63056f4571a34b41
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T10:02:36Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T10:02:30Z host igneum-build-9 cmd: ./bin-int8-wip export --out packs-out/int8w75r32 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state node1-state.igsd1 --dataset-log2 30 --fam8 int8w75r32
state stream node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/int8w75r32
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 0 program id 445765984996028a, loads/hash 16; epoch built in 6283.8 ms
op mix: dp4a=44 xor=5 rotr=4 sub=4 add=3 load=2 rotl=2; class mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w75r32, 64 bytes/hash, widths (1,4,16 words) [2, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/int8w75r32/program.json (57221 bytes)
wrote packs-out/int8w75r32/identity.json (1003 bytes)
wrote packs-out/int8w75r32/vectors.json (6458 bytes)
wrote packs-out/int8w75r32/kernel.cu (49376 bytes)
wrote packs-out/int8w75r32/kernel.cl (44621 bytes)
wrote packs-out/int8w75r32/program.h (7326 bytes)
wrote packs-out/int8w75r32/vectors.h (5942 bytes)
wrote packs-out/int8w75r32/program.metal (32615 bytes)
wrote packs-out/int8w75r32/program_bound.metal (32767 bytes)
wrote packs-out/int8w75r32/kernel_bound.cu (47151 bytes)
wrote packs-out/int8w75r32/kernel_bound.cl (76570 bytes)
wrote packs-out/int8w75r32/memhard.h (7369 bytes)
wrote packs-out/int8w75r32/memhard.metal (7258 bytes)
vector warp base 0: lane0 0682338b74a04c37 lane31 46a7253171090557
vector warp base 4096: lane0 0b2de8e8d48c9a85 lane31 e7120f2f5c688b5d
vector warp base 1000000: lane0 0356246b8a19b8b2 lane31 ccc92e7507e700f1
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T10:02:37Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T10:02:30Z host igneum-build-9 cmd: ./bin-int8-wip export --out packs-out/int8w90r32 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state node1-state.igsd1 --dataset-log2 30 --fam8 int8w90r32
state stream node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/int8w90r32
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 0 program id 0d438354ca69b247, loads/hash 16; epoch built in 6384.4 ms
op mix: dp4a=55 load=2 rotr=2 sub=2 add=1 rotl=1 xor=1; class mx8-erad810f22d+sh256x27+state+reg64c+fold+int8w90r32, 64 bytes/hash, widths (1,4,16 words) [2, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/int8w90r32/program.json (57255 bytes)
wrote packs-out/int8w90r32/identity.json (1003 bytes)
wrote packs-out/int8w90r32/vectors.json (6458 bytes)
wrote packs-out/int8w90r32/kernel.cu (51966 bytes)
wrote packs-out/int8w90r32/kernel.cl (44221 bytes)
wrote packs-out/int8w90r32/program.h (7322 bytes)
wrote packs-out/int8w90r32/vectors.h (5942 bytes)
wrote packs-out/int8w90r32/program.metal (32161 bytes)
wrote packs-out/int8w90r32/program_bound.metal (32313 bytes)
wrote packs-out/int8w90r32/kernel_bound.cu (49741 bytes)
wrote packs-out/int8w90r32/kernel_bound.cl (75770 bytes)
wrote packs-out/int8w90r32/memhard.h (7369 bytes)
wrote packs-out/int8w90r32/memhard.metal (7258 bytes)
vector warp base 0: lane0 0efd4800328caf38 lane31 08b4e0d27bcc35f6
vector warp base 4096: lane0 2fdb239b2e6cf15b lane31 1bff9b5abb29d044
vector warp base 1000000: lane0 2bea1236f6fb35a1 lane31 ae8a005b17a4b664
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T10:02:37Z rc 0

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@ -0,0 +1,425 @@
<!-- the landed copy of the lab's interface (scratchpad/lab/INTERFACE.md on the LAB lane's Mac); the landed table is table.md beside it; both move on master at every real result -->
# The 1.5x laboratory interface (LAB, 9 October 2026, set 11:5x UK; every lane reads this before its first row)
Scope: the one evaluation every control and candidate goes through, the interfaces between the five lanes (LAB, CONTROLS,
SEARCH, ADVERSARY, COHORT), the score, the rejection filters, the regression set, the row and batch forms, the report rule.
The charter (scratchpad/lab/CHARTER.md) sits above this file; nothing here relaxes it. The landed copy is
docs/analysis/class-v6/1p5x/lab/README.md on the box mirror's master; the live table is scratchpad/lab/TABLE.md.
## 0. The objects and their ids
- A candidate is an executable specification: a generator tree sha (the program class), a pack set (program.json ids, the
class string, the fingerprints), a CPU reference, a CUDA kernel (OpenCL and Metal where the cohort needs them), a resource
line (dataset bytes, reads per hash, read width, the working set at that width, state bytes per instance, instructions per
hash in BOTH conventions, cold-verification cost per unit), and an id: controls `ctl-v6`, `ctl-progpow-094`, `ctl-fishhash`,
`ctl-coop-arx`; search candidates `cand-<nn>`.
- The frozen v6 control (`ctl-v6`): tree 1a938abe4 (branch class-v6, source fingerprint 5f4d6dc6…), signing object
2a1d6caab4c24564 AT 2^30 WORDS = 4 GiB (dataset policy 70a6c703): the pack x1-ctrl-ds30.tgz 7606c13d (its read-only twin
x1-ctrl-ds30-readonly.tgz 7629ed95) under build-1:/srv/artefacts/lab/controls/frozen-v6/ (CONTROLS, 12:2x UK on main's
correction), run by the l8off kit's worker (kit c20999d1…, CUDA worker 218ca414… Windows / 9bfcf728… Linux) or the gen-6 Linux
worker 804a6f7f…; 256 random reads per hash over 4 GiB, 62,120 ALU instructions per hash (102,612 in the counted-op
convention), layer 8 ON. The 1 GiB research pairing hl-v6-all 0x9d40978601a7df2a (kernel fingerprint 59e6708e46f1e87c) serves
the fingerprint cross-check row only; no 1 GiB figure is ever a cohort row of ctl-v6.
- The work unit is energy per ACCEPTED work. For v6 and like-for-like candidates: joules per hash at equal difficulty. For a
changed work unit (ProgPoW, FishHash, any proof-carrying unit): an accepted-work equivalence (lottery contribution per unit at
an equal security budget) written by CONTROLS or SEARCH and approved by LAB before any number is served; raw hashes per
second are never compared across algorithms. The comparison is always the ratio WITHIN an algorithm (its GPU energy over its
own redesigned specialist's).
## 1. The measurement recipe (COHORT lane)
The hash lane's recipe (build-1:/srv/artefacts/1p5x/gpu-row-recipe.md, sha cbab453c) is the instrument; this section adds the
lab's rules. Every figure's software, pack, card, clock and boundary are pinned in the row.
1. The instrument: the kit's own worker `--bench --pack <dir> --batches 250 --batch-log2 24 --block-warps 1 --device 0`; the
pack self-test `check=PASS` or the row is the finding; the worker and the kit zip named by sha256; the fingerprint (FNV-1a 64
of the 2^24 outputs at base nonce 0) equal on every platform and at every state before a rate row is read.
2. Power: `nvidia-smi --query-gpu=timestamp,power.draw,clocks.sm,clocks.mem,temperature.gpu,utilization.gpu,power.draw.instant,power.draw.average --format=csv,noheader -l 1`
for the whole run; watts = the mean of power.draw from 8 s in to the end of the timed dispatches; idle NOT subtracted;
board power as the card reports it. Rate = the worker's own `mhs=`. nJ per hash = W / MH/s x 1,000.
3. Wall where a pod allows: a pod that exposes a host-side reading (a metered PDU, the provider's node-level meter) records it
beside the board figure as `wall_w` and the ratio is computed on both. No rented pod of ours exposes one today, so the wall
column reads BLOCKED and the machine-term allowance of X0 section 4.4 (about +10 percent on the card's figure: a PSU at 92
percent and the host share, approximate) is printed as a labelled third column, never applied silently to the board figure.
4. States: stock on every rented pod (a container that refuses `-lgc` says so in the row). The knee where a lock holds (the
5090 at `-lgc 0,1300`, the 5080 at `-lgc 0,1100`); the house rigs are BLOCKED for every lane, so knee rows exist today only
in the record (the frozen v6 on the house 5090: 4,011 nJ at the lock, 5,842 at stock, job report 05f00bd8…) and on any rented
pod that permits the lock (try it; keep the refusal line).
5. The cohort, measured from the FIRST candidate: RTX 5090, 4090, 3090, 5080 (rented); the AMD tier (RX 7600 or the nearest
RDNA card the market has) and the Intel tier (Arc B580 or the nearest) through the OpenCL kits. A tier with no reachable card
reads NOT RUN with "no card reachable" and the score reads NOT RUN; the scope is never narrowed quietly.
6. The pair rule: the candidate and the frozen v6 control in the same job, on the same card, at the same state, back to back;
deltas as percent of the pair; absolutes never compared across sessions (the 13 percent enclosure-swap caveat on the first
rig stands).
7. The read-only twin (the memory share f): the same kernel with the arithmetic short-circuited and the dataset reads kept (the
same read count and width, the address stream reproduced from the candidate's own address generator or a recorded trace),
paced to the full kernel's rate (the same dispatch cadence, throttled to match), same session, same card, same state.
f = J_twin / J_full. Both rows carry W and MH/s. The twin's fingerprint is not expected to match (it is not the function); its
address stream is checked against the full kernel's trace (the first 4,096 addresses equal) and the check is in the row.
8. Repeats: three timed runs per cell; the row carries the median and the spread (max minus min, percent of the median); a
spread over 3 percent repeats the cell.
9. The row: `RESULT lab cand=<id> ctl=<id> card=<model> pod=<fleet id> driver=<ver> kit=<sha8> worker=<sha8> pack=<program id>
class=<class string> state=stock|lock<MHz> mhs=<x> watts=<mean> watts_instant=<mean> watts_average=<mean>
wall_w=<x|BLOCKED> nj_per_hash=<x> nj_twin=<x|none> f=<x|none> fingerprint=<16 hex> check=PASS|FAIL twin_addr=PASS|FAIL|none
spread_pct=<x> utc=<start>..<end>`, the worker's own RESULT line beside it verbatim; the nvidia-smi samples in the job folder;
the folder tarred to build-1:/srv/artefacts/lab/<cand id>/<pod>/ with SHA256SUMS; rows.jsonl beside it with the same fields.
11. Power-capped pods (COHORT's finding, 12:17 UK): on a host whose card runs at a vendor power cap the twin reads f near 1 and is
meaningless (the card spends the saved ALU power on clock and reads the same watts), so f is read only on uncapped cards; the
gate refuses capped hosts for the f cells; a capped row stands as a named capped row (`cap_state=capped` and the cap in the
row) and its f is credible only where the card did not reach its cap (watts under the cap in the row). Every rented pod today
refuses `-lgc`, so every cohort row is stock and the knee rows are the house record's until a pod that locks is found.
10. The P03 cost line per candidate and card: rate and joules per accepted work as percent of the paired frozen v6 at the same
state (the budget: at most 5 percent joules and 2 percent throughput for a like-for-like change, read at the knee where a
lock exists, else at stock).
## 2. The adversary interface (ADVERSARY lane): what comes back per candidate
1. The input from LAB (the X5 section 5 trace shape, extended): `{"cand": "<id>", "tree": "<sha>", "ops_per_hash":
{"instructions": N, "counted": Nc, "by_family": {...}}, "loads_per_hash": L, "read_bytes": W, "dataset_bytes": D,
"state_bytes": S, "hit": {"0.01": h, "0.05": h, "0.10": h, "0.25": h, "0.50": h, "0.75": h, "1.00": 1.0}, "policies":
["static", "trained", "adaptive"], "gpu_nj": {"5090": {"stock": x, "knee": x}, "4090": {...}, ...}}`. SEARCH or CONTROLS
supplies the counts and the item histogram (the attack-f8 histogram over the candidate's own nonces); COHORT supplies gpu_nj.
2. The output per candidate: `scratchpad/lab/adv/<cand id>.json` and the lane's README under
docs/analysis/class-v6/1p5x/lab/adv/<cand id>/. One row per design, the design set never smaller than: the pure DRAM board
(GDDR7), the hybrids at 0.25, 0.50 and 0.75 stored, the full SRAM die (one N2 reticle), recomputation, HBM3 (one stack),
near-memory (the hash unit beside the bank), and every architecture improvement the lane finds (fused operations, register
organisations, shared instruction storage, specialised arrays, a systolic int8 array wherever the candidate has MACs, memory
fractions, recomputation, alternative scheduling). Each row: `{"design": ..., "node": "N5"|"N3", "nj_per_work": {"low": ..,
"nominal": .., "high": ..}, "label": "WITNESS"|"BOUND", "convention": "instruction"|"counted", "complete_machine": true,
"machine_terms": "board.py <sha>", "hit_used": .., "sustained_rate_mhs": .., "machine_w": .., "capex_usd": .., "usd_per_mhs":
.., "credible": true|false, "sources": [<shas>], "witness_note": "placed"|"synthesised"|"modelled"}`. The lane's model files by
sha (tools/chip-model/mf/results/table.csv, tools/1p5x/x5/sweep.py, tools/chip-model/mf/flow/board.py).
3. The lowest credible specialist energy: a_same = the minimum nominal over the credible rows at N5 (low and high carried);
a_ahead = the same at N3. Credible = capital per MH/s under ten times the card's (X5's rule) AND a complete machine. A BOUND
row is used only as a justified lower bound L with its assumptions named; a WITNESS row is used as E_D and every ratio from
it is labelled WITNESS (E* at or under E_D).
4. The convention: the instruction count is the default (the units fault, REG-07); a counted-op row is carried beside it, never
alone.
5. Every improvement found goes into the adversarial set with a version (`adv-set v1`, `v2`, ...) and its UTC stamp; LAB re-scores
every earlier candidate on the new set and the table names the set each score used. The strongest known specialists are kept
throughout (the plan's stopping rule 7).
6. Per candidate the lane also returns the family sentence: for each family in the candidate's mix, the cheapest permitted unit
and its pJ per op against the card's (the family table of record: ARX 1.25 to 1.3x, mul 2x, mulhi and shfl 5x, int8 MAC about
7x against an array, random reads about 13x).
## 3. The score (LAB)
1. The cells: for every cohort card c at each state s with a row, and each node n in {same, ahead}: R(c, s, n) = G(c, s) / a(n),
G the measured board-power joules per accepted work (the wall column and the +10 percent machine-term column computed
beside it, labelled, never mixed into R).
2. The score = the MAXIMUM of R over every cell (the worst comparison), with its band: score = max G / a_nominal;
score_high = max G / a_low (the adversary's optimistic end); score_low = max G / a_high. The band is printed with the score.
3. The target: a score at or under 1.5 at the nominal AND at score_high is the only reading that counts as under; the internal
design goal is 1.25 nominal (the guardband: 1.25 x 1.05 / 0.90 = 1.458).
4. Missing cells: a cohort card, state or node without a row makes the score NOT RUN; a partial figure is printed as "partial
over {cells}" and never as the score.
5. Within an algorithm: a control's score is its GPU energy over its own redesigned specialist; the controls and candidates are
compared on their scores, never on hashes. If every control reads poorly under the model, LAB investigates (optimistic old
claims, a stronger adversary, a miscalibrated model) and writes the finding; never the convenient reading.
6. The table's vocabulary: NOT RUN, BLOCKED (with the owner), REJECTED (a filter or a regression test, the reason named), FAIL
(a measured score over 1.5 at the nominal), SCREEN (a simulator's or model's score, no measurement yet), MEASURED (the cohort
rows and the adversary rows in). PASS is never written by any lane (X6's blind run and the panel).
## 4. The rejection filters (before any score; any one rejects, the reason printed on the table)
- F1 correctness: bit-exact fingerprints across the CPU reference, CUDA and OpenCL (Metal where present) at every state; the
pack self-test PASS; for a proof-carrying unit, a verifier that accepts every GPU output and refuses every known-failed fixture.
- F2 verification budget: cold verification of one accepted unit on one CPU core at or under the frozen v6's; proof bytes,
invalid-proof amplification, pool share checking and propagation inside the fleet's node limits (R15-10; B6's table on master
1ab735be9 is the reference). A unit with no measured cold-verification row is NOT RUN, not rejected.
- F3 practical generation: deterministic generation from the epoch seed on every platform; the pack exportable by the kit lane's
recipe (the cross-build on build-1 at the x86-64-v3 baseline); generation time at or under the frozen class's at the epoch
boundary.
- F4 the honest-GPU cost limits (P03): a like-for-like change pays at most 5 percent joules per accepted work and 2 percent
throughput against the paired frozen v6 (the knee where a lock exists); a changed work definition carries its comparison
contract and the budget applies to the equivalent unit. No padding that costs ordinary miners more than it costs the chip: a
candidate whose GPU energy rises by more than its specialist's is rejected by the mixture lemma before measurement.
- F5 nothing but joules: attestation, quotas, proving revenue, resale, chip cost and rotation count for nothing in R (they may
sit in a separate economics column, never in the score).
- F6 the resource line stated: dataset bytes, the working set at the candidate's read width, state bytes per instance; the full
SRAM, hybrid and recompute designs stay in the set after every change; where the working set fits one reticle the die is
scored first.
## 5. The regression set (every failure of 8 and 9 October as a test)
A candidate that repeats a failed mechanism under a new name fails the test and is REJECTED; re-entry only with a written
statement of what differs materially from the failure mechanism, read by LAB before any row.
| Test | The failure of record | The test on a candidate |
|---|---|---|
| REG-01 connected state | 8 Oct, KILL: the adversary's clock-gated register file; the window width was the one robust knob (+0.14 k at the lock); the cs64 research class | a candidate whose lever is state kept live between reads, or liveness, is scored against the clock-gated register-file row; no credit for "the chip must keep the state powered" |
| REG-02 mixed FP32 | 8 Oct, KILL: +15 to 26 percent card energy for +7 percent chip edge (FP32 FMA k 0.4 to 0.5) | any FP32 or masked-float family in the mix reads the FP32 k from the family table; a mix whose card cost rises more than the chip's fails F4 |
| REG-03 window removal (X1) | 9 Oct: g 0.98 to 1.00 on four cards; the hottest half serves 0.56 (signing) to 0.61 (mean), not 0.72; a half store still serves 0.50 (H(q) at or above q/N); the windows buy nothing for the board or the die; the hybrid's a capped at 1.14 to 1.29 | a candidate whose lever is address flattening, permutation or "no hot set" is screened by the static-cache bound: the hybrid rows at hit = q/N are its best case and the die serves every read whatever the distribution |
| REG-04 int8 mixes (X8) | 9 Oct: against a systolic array (0.30 pJ per MAC, 0.10 to 0.60) every int8 mix at 10, 50 and 90 percent raises the ratio (the board 2.4x to 2.7x, the die 8x to 14x); dp4a-only (1.54x at 90 percent) is not the adversary's cheapest unit | any tensor, MAC or dot-product family puts the systolic array in the adversary set; a row against dp4a alone is refused |
| REG-05 the scattered-read ARX point (X8b) | 9 Oct: ARX-only at 32 per-lane scattered reads 3.55x same node / 4.38x a node ahead (dollars 11.2x); at 16 reads 3.85x / 4.92x: fewer scattered reads raised the ratio | a candidate that changes only the count of per-lane scattered reads is screened by R = 1 / ((1 - f) / 1.3 + f / 13); a new mechanism needs the cooperative shape (lanes on one fetched entry, every byte consumed, the arithmetic feeding the next address) |
| REG-06 the memory-route verdict (X7) | 9 Oct: f = 0.853 on the 4090 at stock (8,091 nJ against the twin's 6,899); s = 12.8 (GDDR7 board), 22 (HBM3), 39 (beside the bank) per read; r = s / f; no read-dominated design reaches 1.5x at any f | a candidate whose claim is "more read-dominated" or "more bytes" is screened by the bridge r = 1 / (f / s + (1 - f) / c) with X7's s and the candidate's own f; the term it must change is the card's cost per read (27 nJ all-in on the 4090 at stock; 14 all-in and 8.7 marginal on the 5090 at its knee), not the count |
| REG-07 the units fault | 9 Oct 11:4x UK: a "counted op" is the GPU's 1.83 micro-op tally; the shadow is 55,296 instructions; the placed rows multiplied 102,612 counted ops by a per-instruction chip energy and overstated the chip's shadow by 1.85x | every adversary row names its convention; the instruction count is the default; a counted-op row without the instruction row beside it is refused; every candidate's op count is reported in both conventions |
| REG-08 layer 8 off | register row 18, closed 04:49 UK 9 Oct: off at the knee costs the card 5.7 percent of rate and 3.6 to 5.7 percent of joules; the chip side gains 4 percent at the mean hit | the layer stays ON in every control row; a candidate that removes it carries its own pair row |
Also of record (X0, the decider): the frozen v6 costs the card 1.78x to 1.84x class v4's joules per hash at stock (twice the reads
for 9 to 10 percent more ALU) and the chip's memory term doubles while its shadow holds. Every ratio is read on ITS OWN pair
(chip and card on the same program), never spliced across programs or snapshots.
## 6. The candidate table (scratchpad/lab/TABLE.md)
Columns: candidate id; kind; tree and pack ids; the resource line (SEARCH or CONTROLS); the cohort rows per card (stock nJ, knee
nJ, f, spread; wall BLOCKED or the figure); the adversary rows (a_same, a_ahead, the lowest credible design, the adv-set
version); the worst score with its band; status; the next move with its owner and clock. LAB writes the table; the lanes send
rows; the table is current within ten minutes of a row.
## 7. The report rule
- A lane reports to LAB and to main on a real change only: a measured row read back, an adversary row set, a rejection, a fault
with its cause and clock. Never a status note. The form: one line, UK time from `date`, the figure, what it means on the score,
the evidence path.
- LAB's line to main at every real result: a control's ratio, a candidate's score, an adversary improvement that re-ranks, a
fault. The first full line: the frozen v6's worst-cohort score.
- A slip once, with its cause and the new clock. Nothing on the devnet is touched; no founder input is ever asked for; builds and
runs on the boxes and rented pods only; kills by recorded pid after reading the pid's command line.
## 8. The registry and the landings
- Suite R15; the lab's cell `lab:candidate` (cases R15-01, R15-08, R15-09); every row NOT RUN until read by the panel (X6 blind).
The batch form (tools/ci/batches/lab-<date>-<nn>.json, as the recorder takes it): run_id, manifest_sha = the candidate's tree
(the frozen control 1a938abe4), method GPU for card rows and model for chip rows, evidence_dir, release_identity with
network_object "none: ...", cells `[{cell: "lab:candidate", cases, status, in_progress, method, evidence, note, claim_impact}]`;
recorded with `node tools/ci/test-record.mjs --record <batch>`.
- The landing: a worktree off build/master; `tools/ci/pre-push.sh` (the full gate on the branch); `MERGE_REMOTE=build
tools/ci/merge-to-master.sh` (the box mirror, under the master-landing lock on build-1); read back with
`git fetch build master` and the file's sha on the mirror. Documents under docs/analysis/class-v6/1p5x/lab/; a lane's rows under
docs/analysis/class-v6/1p5x/lab/<lane>/<cand id>/; artefacts under build-1:/srv/artefacts/lab/<cand id>/.
- Clocks: this file 12:15 UK; the frozen v6's worst-cohort score when COHORT's and ADVERSARY's rows are in (by 13:4x UK); every
later candidate scored within one hour of its last row.
## 8a. X10, the full-sector fold candidate (the founder's third review, 11:5x UK; main's digest scratchpad/lab/review-3-x10.md)
The working scope from now, by default, until the founder says otherwise: the ENERGY CLAIM is the same-node board only (a
programmable core plus a GDDR controller, the same process node as the reference GPU, the dataset in external DRAM, no on-package
store larger than a cache); the SRAM or HBM die and every node-ahead chip stay in the table as COEXISTENCE rows, labelled out of
the energy claim (ticket, fleet cost, margin). Every other rule of this file holds; the score column for X10 carries the board
column as the claim and the die and node-ahead columns beside it.
The object (`cand-x10`), built exactly as reviewed, one object fixed at genesis, no shadow ladder: a chain of DEPENDENT 32-byte
sector loads from the 4 GiB dataset, the address of load n a function of the bytes of load n - 1; all 32 bytes folded into the
lane state with 32-bit integer MAD, XOR and shifts; between loads a fixed mix of 32-bit integer MAD, shifts and bitwise ops, a
64-register window retained across every rotation, a 32-lane shuffle at least every four arithmetic ops; no 64-bit multiply, no
division, no wide permute, no matmul; the read count = the largest count whose joules per hash on the locked 5090 is within 10
percent of the frozen v6's, the search starting at 64 loads (2 KiB useful traffic), cut before any width is added; the low address
bits folded before every era boundary; a draw refused if any fraction of the set takes more than its size share of loads (the
0.995 acceptance floor pointed at this address-share test); hourly program and weekly era draws stay (a versatility tax, outside
the energy model); the 180-day family epoch out until the bracket has passed; the verifier one warp under 10 ms on the reference
core.
Two facts of record conflict with the reviewer's premises; X10 is the measurement that settles them, never an argument: (1) the
board reads 2.35x same node at the knee after X0's corrections (1.90 to 2.65), not the 1.5 to 1.6x of X0's first reading, so the
"remaining tenth" is 0.85x on the corrected figure; (2) X7's s = 12.8 on the chip's own GDDR7 board for the same traffic (the card
about 27 nJ per random read all-in against about 2 nJ for the burst) says the card's read-path fabric, not the DRAM burst, is the
dominant term. The reviewer's answer is the full-sector fold (8x the useful bytes per read, 8x fewer reads for the same traffic);
whether that moves the card's cost per useful byte toward the chip's is what X10 measures.
The assignments (earliest clocks; one line per real result to LAB and main):
| Lane | X10 work | Clock UK |
|---|---|---|
| CONTROLS | the readwidth fact of record: does the frozen v6 read 4 bytes of a 32-byte sector or fold the whole sector (the readwidth row, by sha); the card's measured energy per 32-byte random sector read at the knee and at stock on the 5090 and the 4090 by X7's read-only-twin method, and the same with every byte of the sector folded (the ALU-fold cost), as a paired same-session row set | the readwidth fact 12:30; the sector rows 14:00 |
| SEARCH | X10 exactly as specified above: CPU reference + CUDA kernel (bit-exact), 64 dependent 32-byte loads to start, the read count set by the 10 percent budget on the locked 5090 (a rented pod that holds the lock, else the house record's pair convention stated), the address-share test at the 0.995 floor, the verifier timed under 10 ms; the trace JSON of section 2.1 (both conventions) to ADVERSARY; the kit to COHORT through the kit lane's recipe | the kernel and reference 14:00; the kit and the trace 14:30 |
| ADVERSARY | the same-node board on X10 under the reviewer's model rule (external GDDR, same node, the cache hit rate = cache size over 4 GiB, no stable hot set), the ENERGY SPLIT published (memory, ALU, the fixed-function tax) and not only the ratio, under BOTH conventions (ours: the cheapest programmable core; ProgPoW's: a chip that keeps a GPU-class datapath); the die and the node-ahead rows beside it as coexistence rows, labelled out of the energy claim; the same split on the frozen v6 for the pair | the v6 split 13:30; the X10 board rows within one hour of SEARCH's trace |
| COHORT | the frozen denominator: the locked 5090 and 5080 (a rented pod that holds the lock, else stock with the lock refusal in the row), a 4090, one AMD card when rentable (NOT RUN with the reason until then), on the frozen v6 and on X10, same session pairs, the read-only twin on both; the 10 percent cross-vendor budget line (FAIL if the AMD card or the 4090 pays more than 10 percent over the budget against v6) | the v6 denominator rows 12:3x (in flight); the X10 rows within one hour of the kit |
| LAB | the verdict line: the board at or under 1.5 on every denominator card, or the number it reads and which term (memory, ALU, tax) holds it above; FAIL CLOSED per the review (above 1.5 after the burst change: stop; no added arithmetic, no family rotation, no set growth); the PASS condition is never written by the lab (the board column at or under 1.5 on every card, the memory share of card energy at least half, the verifier under 10 ms, the GPU-cost budget held, then the coexistence rerun: the panel reads it) | within one hour of the last X10 row |
The twin for X10: the dependent-address chain is kept by construction (the fold of each sector into the next address stays; the
rest of the ALU mix is dropped), so the twin's address stream equals the full kernel's and `twin_addr` reads `by construction
<kernel sha>` without a trace instrument; the same ruling covers ctl-v6 (the X7 twin, kernel 93a6a5ce): `twin_addr=none` is accepted
on the control rows and no instrument is built before the first candidate.
### 8a.1 X10 facts of record (12:2x UK)
- The readwidth fact (CONTROLS): the frozen v6 reads ONE 32-bit word per load site and never folds the sector. Proof lines in the
l8off kit's packs/hl-v6-all (program.json 9eec9e325a820c16, program.h bfd9230e231ffb2c, kernel_bound.cu 77cabb0602ee7ad5):
program.h `IGNEUM_LOADS_PER_HASH 128`, `IGNEUM_WIDE_LOADS_PER_HASH 0`, `IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 }`; kernel_bound.cu
line 115 a 4-byte `ds[...]` xor into one register; the reg64c mirror repeats each site: 256 executed loads per hash, 1,024 bytes
consumed of the 8,192 bytes of 32-byte sectors the memory system moves. The read-width rows of record (the first rig's 5090 at the
1,300 lock, 8 Oct): W = 4 words 2.29 uJ per hash, W = 8 2.55 (+11 percent), W = 16 4.09 (+78 percent). So X10's premise (the
card moves a sector and consumes 4 bytes of it) is true of record, and folding the sector costs the card's ALU (+11 percent at
8 words on that row).
- The fault of record in the Sector reference as written (SEARCH): the sector index reads lane registers 0 and 1; the fold writes
dst = (load x 8 + k) & 63, so registers 0 and 1 are rewritten only every eighth load; 7 of every 8 loads re-read the same sector
(every fixture's lane-0 trace: two fresh addresses, then six repeats); about 16 distinct dependent sector addresses per lane-hash;
the other 102 loads are L1 or L2 hits on the card and free on a chip. The author's split (memory 35 / fold 55 / tax 10) and the
10 percent budget rest on 118 real misses. Evidence scratchpad/lab/x10-sector/cuda/fixtures.txt (columns 5 to 12), hash.ts lines
95 to 112. RULING: cand-x10 is built and measured bit-exact to the reference as written (its own row, labelled "16 real misses");
cand-x10b is main's ratified address rule (load n reads the two registers the previous load's fold wrote last; zero repeats in
every trace), measured beside it; both kits under build-1:/srv/artefacts/lab/cand-x10/kit/ (sector.cu 16417ce6, run-x10.sh;
VARIANT=x10b for the corrected one) and cand-x10b/. The CUDA kernel is bit-exact with the reference on all 18 fixtures (a rented
4090, 11:11 UTC; 112 registers, no spills).
- The accepted-work contract for X10, APPROVED by LAB: the lottery unit is the warp digest; the column comparable to the frozen
v6's joules per hash is joules per LANE-WORK (per digest over 32); both are printed on every row; the P03 budget and every ratio
are read per lane-work; the ratio is unit-independent while both sides use the same unit; the security-budget line (energy per
lottery draw at an equal target) is printed beside it per the units rule (8c.2).
- The first X10 rows (SEARCH, a rented 4090 at stock, SCREEN until COHORT's paired rows): 118 loads 810 to 845 nJ per lane-work
(25.9 to 27.0 uJ per digest) at 264 to 275 W; 64 loads 567 nJ per lane-work at 294 W; a tenth of v6's 8,091 nJ on the same card
class, which is the cache hits of the fault, not a design gain.
## 8b. The coexistence table (the founder, 12:0x UK; the scoreboard's headline beside the energy ratio; ADVERSARY's job, due with the controls this afternoon)
The outcome the founder has set is COEXISTENCE: GPU owners remain competitive, no lasting overwhelming supplier advantage, no
emergency intervention. So every control and candidate carries a coexistence table next to its score, built by ADVERSARY with the
placed core and the X8b dollar method, every number a WITNESS with its source, the fleet size and the design-cost assumption
stated on the row, no raw hashes. Rows per adversary: the same-node DRAM board, the stored-half hybrid, the N2 SRAM die, the
node-ahead board. Columns:
1. Energy edge at the knee: the card's nJ per hash over the chip's (the complete machine), with the band.
2. Chip capital per MH/s in USD: the die (the placed core's mm2 at the node x the claimed wafer cost and yield), the memory (4 GiB
of GDDR7, USD 320 of devices of record, or the SRAM at USD 250 per GiB claimed), the board and assembly (USD 200 of record), the
design cost (the mask set and the design team, the sum stated) spread over a stated fleet (machines and MH/s); against the card's
USD per MH/s on the SAME object (15.7 of record on the X8b row; 30.6 on the frozen v6 at the knee in adv-set v1): both pairs
stated.
3. The GPU owner's electricity-only cost per hash at three prices, USD 0.05, 0.10 and 0.15 per kWh, in USD per TH (nJ per hash x
price per kWh / 3,600; the card is sunk).
4. The chip's all-in cost per hash at the same three prices, USD per TH: its electricity (its nJ per hash x the price) plus its
capital per MH/s amortised over a stated life (months, straight line, the chip's sustained MH/s) plus the design-cost share; the
life and the fleet stated on the row.
5. The verdict per row and per price: does the chip's all-in cost per hash fall BELOW the GPU owner's electricity-only cost per hash?
yes = the GPU owner is pushed out; no = coexistence holds. The row prints the margin (chip all-in over GPU electricity-only) so a
reader sees how far from the line it sits.
The table's file: scratchpad/lab/adv/<cand id>-coexistence.json beside the design rows (the same keys as the columns above, one
object per adversary row with its assumptions) and the lane's README section; LAB carries the four verdict cells (one per
adversary row at USD 0.10) on TABLE.md beside the score, the full table in the landed README.
## 8c. Scoreboard rulings (the founder's fourth and fifth reviews, through main, 12:5x and 13:1x by main's clock; binding on every served or committed sentence)
1. Labels: every ratio names its adversary (the same-node DRAM board, the stored-half hybrid, the N2 SRAM die, the node-ahead
board), its column (energy, capital, cost ratio), its clock state (knee or stock), the card and the set version; never a blended
figure.
2. The coexistence table's last column is "cost ratio" (the chip's all-in cost per TH over the GPU owner's electricity-only cost
per TH), never "margin". A revenue column: the block reward times the token price under growing, flat and falling scenarios, as
revenue per accepted work in each algorithm's OWN units (the units rule, CONTROLS), never raw terahashes across algorithms.
3. "All three tested tariffs" (USD 0.05, 0.10, 0.15 per kWh), never "every electricity price"; the tariff at which the two curves
meet is stated per row (the reviewer's linear read on ctl-v6's board row: about USD 0.33 per kWh).
4. "No fleet size reaches break-even" appears only with its fleet, amortisation and revenue rows shown.
5. Two phases per adversary (board, hybrid, die), with the development cost both recoverable and sunk. Phase A, before investment:
can the maker recover its spend under growing, flat and falling demand with realistic hardware sales. Phase B, after investment
with the spend sunk: the ongoing cost per TH on both sides (the chip's electricity, hosting and maintenance itemised: of the
chip's USD 0.265 per TH at ten cents about 0.043 is electricity, the other 0.222 itemised as capital, design or recurring), the
realised contribution against revenue, who exits first as difficulty rises, GPU participation and supplier concentration over
time.
6. The SRAM die stays a live opponent in both phases; where it is called implausible the row names the assumption that fails.
7. The NEW-BUYER column: a new card's capital plus electricity against the chip's, per tier, with the indifference point; under
each growth schedule with the chip's memory capital scaling with the set (4, 8, 16 GiB) against a card buyer who already holds
16 to 32 GB, and the set size at which the chip's capital per MH/s meets the card's. The USED-CARD column: a 4090 and a 3090 at
today's used prices (source stated), resale retained at 24 months, the chip's resale zero after a program-draw change. No
sentence about supplier advantage appears before the new-buyer column exists; ADVERSARY's first result (12:1x): the new buyer
picks the chip on every row and tier (the board 0.24x to 0.43x a new card's all-in at ten cents; the die 0.04x; indifference at
USD 9.7 per MH/s on the 5090 knee, 10.5 on the 5080, 5.4 on the 5090 stock, 2.6 on the 4090; the only hold the project share
below about 13,500 boards sold).
8. The card's random-read headroom (COHORT with CONTROLS; the lab's most important physical row, the only lever on phase B): the
achieved sector reads per second on v6 (rate x 256) per cohort card against that card's random-activation bound from its memory
timing (channels, banks, tRC) and against the chip's 148 MH/s on the same memory kind; if the card sits well under its bound the
miner-side lever is more loads in flight per core (software pipelining across lane-hashes, occupancy, batch shape) and SEARCH
cuts a worker variant that measures it: a faster card at the same price is the direct answer to the chip's USD 14 per MH/s.
9. The approved wording, verbatim, until the two-phase rows exist: "The current model finds that existing GPU electricity costs
are below the assessed DRAM-board specialist's all-in costs at the tested tariffs and stated lifetime assumptions. This supports
a conditional entry-deterrence result. It does not yet establish post-deployment competitiveness, viable GPU replacement or new
entry, or coexistence against the modelled SRAM fleet at sufficient scale. Those outcomes remain separately assessed."
Withdrawn everywhere: "the winning outcome is met", "only one design decision remains", "no lasting supplier advantage", "no
other GPU chain has this written down" (the last needs a comparative review of what other chains publish: a row of the table,
NOT RUN until done). The sentence the rows support today: a DRAM-board chip can be built and does not undercut a card its owner
already has; the store-on-die chip is the residual, held by the growth schedule.
10. The 4 GiB proving cap defined precisely on the record: which of the mining state, the proof-generation allocation, the
verifier requirement or the advertised hardware profile it limits (CONTROLS states it from the proving manifest and the record;
ADVERSARY the economics).
11. (the sixth review, 12:3x UK) The revenue column splits revenue by hardware: a GPU earns the mining share plus the proving
share of the block reward (the ratified split from the Token Value volume on master, D01 to D06 and TV-04, taken from the
documents by path and sha, never invented), a hash chip the mining share only; phase B (spend sunk) is recomputed with that
split for the board, the hybrid and the die, with the proving share at which the chip's operating advantage over the GPU
disappears at ten cents; the row is labelled NOT LIVE until a shipped package runs a prover (today the HiveOS package mines
only; proving turns on at 24 GB) and a shipping row is open for it (TABLE.md, the shipping row: which packages prove today
at what VRAM and by what switch, the 24 GB threshold and whether a 16 GB card can prove a smaller instance, the share of the
live cohort that can prove; a HiveOS prover a named 2.0.3.1 item beside snapshot sync). The phase B row states the
assumption that all proving stays on the GPU cohort, with the sentence: a chip maker who fields GPUs to prove is a GPU miner
with a sidecar. ADVERSARY's first result (545f3f8a0): the proving share at which the chip's operating advantage disappears at
ten cents is 9 percent for the board, 13 for the hybrid, 20 for the die, against the ratified 20.
14. The 8e "4 GiB fault" is corrected (12:4x UK, once): every cohort cell ran the live 4 GiB object (the self-test's dataset word
1,073,741,823 on every cell; dataset_words on every row); CONTROLS' 13.16 MH/s was its worker build 804a6f7f at 20 x 2^22, not
the object; the decider names the instrument difference; the 4 GiB rule (every row names its dataset words) stands.
12. (the sixth review) The per-epoch tuple rotation (bytes folded per line, register-window depth, shuffle distance, chosen from a
committed list and published one epoch early) is costed by ADVERSARY as versatility tax on the programmable core (what it
adds to the chip's shadow and what it costs the card) beside the hourly and weekly draws, and is NOT scored as a defence
against the programmable adversary; the lab's measured X10 verdict (31 against 31.6 nJ per read, 5.8x against 5.4x on the same
4090) is the answer to the review's rule 2 and the growth rows the answer to its rule 3.
13. A SCREEN cell under 1.5 (the first: cand-x10 at 520k ALU on set v3, 1.03x with the card assumed equal to v6) is never served
as a result; it is a measurement order (SEARCH builds the point, COHORT measures it paired with v6, the P03 line decides
before the ratio).
Owners: ADVERSARY 2 to 7, 10's economics, 11 and 12; CONTROLS the units rule and 10's definition; COHORT 8 with CONTROLS; LAB the
wording, the layout and the labels.
## 8d. The founder's lab bundle (14:00 UK with the measured controls)
build-1:/srv/artefacts/lab/founder-bundle-<stamp>.zip, built by /srv/artefacts/lab/make-bundle.sh (no identity text: no names,
logins, rig names or the zone word; the script greps every text file and refuses on a hit): the interface, the scoreboard with the
coexistence table and its assumptions, the adversarial set v2 design notes and the placed rows, the frozen-v6 control kit with the
4 GiB packs and sidecars, the cohort rows, the controls' rows, the X10 record; the path and sha256 to main.
## 8e. The 4 GiB rule and the post-deployment lever (main, 12:3x UK)
CONTROLS measured the live 4 GiB signing object (x1-ctrl-ds30, 2^30 words) at 13.16 MH/s on a rented 4090 at stock against 31.28
for the 1 GiB research pack on the same card and session (3.4 against 7.9 G dataset reads per second on the same memory). Rules:
(1) the 4 GiB figure is the one every scoreboard row carries from now; every 1 GiB row is relabelled research and is never a cohort
cell; (2) the decider (COHORT, one session per card: the 1 GiB pack, the 4 GiB pack, both twins, ABBA, the dataset words on every
row), then the cause read directly (the worker's occupancy and loads in flight at 4 GiB from its RESULT line; CONTROLS' pure-read
kernel at 1, 2 and 4 GiB in steps against the card's page size and L2 TLB coverage; the layer-8 window shape over 2^30 words),
then the first worker-side fix the cause names (SEARCH: larger pages or a different allocation, more independent lane-hashes in
flight per warp, a window shape that keeps the page set hot), measured as a pair against the frozen worker on the same card with a
bit-exact fingerprint, the gain in MH/s per card and the new nJ per hash; (3) one line to main at the decider, one at the cause,
one at the first fix pair. Recovering the loss halves every card's USD per MH/s at no gain to the chip: it is the phase B lever.
## 8f. The ledger order (the founder, 12:5x UK; binding; the deliverables reordered)
The primary objective within five hours: the statement "Someone can build a chip, but ordinary GPU owners remain competitive,
the supplier cannot obtain a lasting overwhelming advantage, and the network does not depend on emergency intervention to survive"
made true and verifiable. The lab's lanes feed the GPU NETWORK LEDGER (the LEDGER lane a101aa8329d1e82bf assembles; it does not
re-measure) FIRST: (1) every live GPU chain measured the same way on the same rented 4090 and 5090 in one session each (Igneum v6
at 4 GiB, KAWPOW via ProgPoW 0.9.4 at the live DAG, FishHash, Etchash via the pinned chfast hashimoto at ETC's current DAG,
Autolykos2 if the in-house rule and the clock allow), the set v3 board ratio and the ProgPoW-premise ratio per chain, the two-phase
rows with each chain's actual reward split (only Igneum pays provers), and the E9 Pro calibration line (ADVERSARY models the one
real chip against Etchash; the gap to its public rate and power is the model's calibration, stated); (2) the proving row flips
LIVE on the PROVING LIVE lane's on-chain evidence (af561127dc1bc7044, one full epoch of paid rows, by 16:00; today's read: 663 paid
v1 segment records to 30 keys on Devnet 4, payments paused since the hub roll, the cause under fix); (3) the comparative-review row
(what other chains publish about their resistance, verbatim with source) so the ledger's claim is checkable; (4) the hash candidate
search continues fail-closed at lower priority (the 520k-ALU point and the headroom row close their records; no new families).
Clocks: the ledger table on the record 15:30, the kit 16:30, the page 17:30. Every row MEASURED or WITNESS with its source;
"pending" never blank; the BUILD STEWARD a3d365ef4a3a107a4 fills any idle box the lab names. The ledger's registry cell:
ledger:cross-chain beside lab:candidate on R15-09, NOT RUN until the kit's rows reproduce; its paths: the scoreboard table.md and
README.md at the box master's sha at 15:00, the conventions on the ctl-v6 and ctl-progpow-094 rows. Correction to 8c.11: the
32 GB prototype-shard clause is Devnet 1's; on Devnet 4 (fees_v1_activation_daa 0) a 24 GB NVIDIA card proves the v1 shard and
aggregates beside its miner now; the 16 GB tier holds no shard.
## 8g. The "no emergency intervention" row (main, 13:1x UK; measured behaviour of record)
The statement's third clause ("the network does not depend on emergency intervention to survive") is carried on the scoreboard as
a measured row, never an argument: Devnet 4 runs finality rule v3 (the frozen table expiring at lock DAA + 7,200); finality has
been paused since lock 1980; the roll restores signing weight; the first new lock is expected 15:30 to 17:00 UK; through the pause
the chain ran on PoW, nothing certified reversed, and proving was unaffected once the finality gate on provers was lifted. The vote
key is label-derived (no key file; a fresh datadir keeps it). The row flips from "paused, chain on PoW" to "locked" on the hub's
first new lock line; the ledger page cites it with the DAA and the UK time.
The LAB stays on watch until the ledger page lands (17:30 UK): the scoreboard and table current as COHORT's five-chain session,
ADVERSARY's ledger rows, the proving epoch record (16:00) and the comparative review (15:30) land; make-bundle.sh re-run for the
14:00 edition and at 17:30 with the ledger rows, each edition's path and sha to main.
## 9. The lane briefs, one line each
- CONTROLS: the four controls as rows of the table: `ctl-v6` from the record and re-measured on the cohort; `ctl-progpow-094`
built from the official 0.9.4 source with its test vectors (kawpowminer master a proxy only); `ctl-fishhash` from Iron Fish's
implementation; `ctl-coop-arx` (the CUDA kernel and CPU reference by 14:00 UK); each with its own optimised GPU implementation
and its accepted-work equivalence contract; the traces (op counts in both conventions, the item histogram) to ADVERSARY and
the kits to COHORT.
- SEARCH: candidates as executable specifications with explicit resource limits over arithmetic composition, dependency
structure, state layout, lane cooperation, memory-transaction shape and work granularity; each through F1 to F6 and REG-01 to
REG-08 on the simulator before a kit is cut (a SCREEN score); the top of the SCREEN ranking to COHORT and ADVERSARY as kits
and traces.
- ADVERSARY: section 2 per candidate; the set versioned; every earlier candidate retested on each new set.
- COHORT: section 1 per candidate on the full cohort from the first candidate; the rows to build-1:/srv/artefacts/lab/; the P03
lines.

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# Proving live on Devnet 4: the on-chain record (9 October 2026)
The 1.5x scoreboard's phase B row reads "a GPU earns the proving share of the block reward and a hash chip cannot". This page is the evidence that the proving share is paid on the live devnet to GPUs proving beside their miners, read from the chain and nothing else. One epoch is 3,600 DAA; Devnet 4's DAA runs at 1.0 per second (63,577 at 11:59:15Z to 63,902 at 12:04:30Z), so an epoch is one hour.
## The rule being exercised, by file and line (node 27f54124, the 2.0.3 line)
| what | where |
|---|---|
| 20 percent of every block subsidy to the proving pool, 80 to the producer | consensus/core/src/igneum.rs:44 (`PROVING_POOL_SHARE_PERCENT`), :87 (`proving_pool_share`) |
| a carried record pays its shard part of the pool credit to the record's payout address when valid, verified and first | igneum/exec/src/proving.rs:551 (`carried_payouts`) |
| a v1 segment (8 chain blocks, 8 shards + one aggregation) pays as one record, 1,000 bps of the credit to the aggregator | consensus/core/src/proving.rs:638 (`split_pool_credit`); igneum/exec/src/proving.rs `segment_status` Proven |
| fees v1 from DAA 0 on the devnet (the shard is the calibrated v1 size, 30,000 pgas, never the prototype) | consensus/core/src/config/params.rs:2307 (`DEVNET_PARAMS.fees_v1_activation_daa: 0`); the node reports `fees.v1ActivationDaa 0`, `shardBudget 0x7530` |
| what a prover reads and submits | `igneum_getProvingStatus`, `igneum_getAssignedShards`, `igneum_submitProofRecord`, `igneum_submitSegmentRecord`, `igneum_getSegmentRecords` (igneum/exec/src/rpc.rs:1342, :1443, :1628) |
## What proves today
The fleet's prover stack on rented RunPod and Vast boxes: `tools/fleet/box-prover.py` (one loop per box, beside the box's kit-2 miner, MINER=none so the miner is never paused) driving the served 0317 prover pair (`igneum-prove-host` sha256 71bc2438…, `igneum-prove-export` 263bf4ce…, SP1 6.8.1, shard program id 0x2b1a81cb…, aggregator id 0x474678f3…, the pair the node pins) and the SP1 GPU server. The same binaries are what the 2.0.3.1 HiveOS package wraps; the Mac and Windows apps carry the same prover, on by default at 23,552 MiB or more (app/igneum-app/src/provedefault.rs:23-24). Cards: RTX 4090 (24,564 MiB), RTX 3090 (24,576), L40S and RTX 6000 Ada (48 GB) as aggregators. Measured on a 4090 beside its miner: one 8-block segment in 117 to 185 s end to end (shards 48 to 52 s, aggregation 57 to 61 s), peak 13,523 to 14,899 MiB; a 16 GB card cannot hold the shard (the LAB's floor rows).
## Baseline before the restart (read 11:50:22Z, lp-4090-02's node, chain id 4465, executed tip 31,719, DAA 62,833)
| counter | value |
|---|---|
| paid v1 segment records since genesis | 663 = 653.93 IGN |
| distinct prover keys paid | 30 (median 4 segments a key, maximum 230) |
| payout addresses | 3 (the fleet's wallets) |
| paid v0 shard records (the pre-segment path) | 6,474 = 7,196 IGN |
| proving pool balance | 27,706 IGN |
| carried records refused as duplicates ("segment already paid") | 952 of 2,199 carried |
| carried records refused as late ("unproven", after the 600 DAA deadline) | 461 |
Evidence file: build-1:/srv/artefacts/proving-live/prov-ledger-4465-tip31719-115022Z.json (sha256 bd3f53c18c3ffa20354ea62ade9fd5e7a5794202a71c3c369a5be71484f7143a), every segment from genesis with its paid row and carried records.
Why payments had stopped at 11:15Z: Devnet 4's finality paused at 11:15:57Z under the hub roll (signing weight 4 to 25 percent of the frozen table), and every fleet prover gates on a finality pause (the 8 October build claims only below the finality-settled block; the V6-08 build holds after 600 s). The gate is the prover's own policy; payment never depended on finality (`carried_payouts`). The provers were restarted as generation 2 at 11:59Z with the gate lifted and the chain paid again from 12:02Z.
## The epoch of evidence (12:02Z to EPOCH_END)
EPOCH_TABLE
## The sentence the row carries
EPOCH_SENTENCE
## Access to proving work (main's question of 13:1x UK)
Segments are allocated by first valid record: 8 assignees per shard drawn from the keys in the record window hold a 10 DAA exclusive window (consensus/core/src/proving.rs:26, :30, :255, :305), after which any key may prove and the first valid record carried is paid; no stake, no queue; leases are off on the live nodes. A newcomer competes equally from its first record; a prover on a synced node claims within one 15-second pass (lp-4090-02 claimed 15 s after its restart). With about 227 segments an hour on this devnet and 120 to 185 s a proof, 8 to 11 provers saturate the work and every prover past that dilutes the fixed 20 percent as 1/N; about a third of carried records today are duplicate proofs. The rule change is docs/design/proving-claim-order.md (node change after 2.0.3; nothing on the chain today).

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# The SEARCH lane of the 1.5x laboratory (9 October 2026): the constrained workload search, its candidates and its rows
The lab's charter (scratchpad/lab/CHARTER.md) and interface (docs/analysis/class-v6/1p5x/lab/README.md) sit above this file.
Nothing here is a PASS; every chip figure is a WITNESS on the adversarial set named beside it; every card figure names its
card, state, pod and pack. Branch `lab-search` (off `1p5x-int8` on the frozen tree 1a938abe4), tools under `tools/lab/`.
## 1. The system
| Part | What it is | Where |
|---|---|---|
| The knobs | arithmetic composition (a weight table over add, sub, xor, rotl, rotr, mul, mulhi, mad, shfl, dp4a; the ARX families, int8 MAC and FP32 FMA allowed, mul, mulhi and shfl as explicit points), dependency structure (the drawn chain, reg64c's interleave, `+ilp2`, `+ilp4`), state layout (8 or 64 registers per lane), lane cooperation (scattered per-lane entries; the warp-coalesced entry modelled only), memory-transaction shape (entry 4 to 64 bytes realisable, 128 to 1,024 modelled; reads per hash 16 to 256; the dataset 2 to 8 GiB), work granularity (the shadow block 64 to 1,024 instructions x 4 to 108 passes) | `tools/lab/search/labsearch.py` |
| The executable specification | a class string on the lab tree plus `params.env` (the limits: the verifier 10 ms on the F6 proxy, the dataset at or under 8 GiB for the 16 GB floor, P03 overhead at or under 5 percent, registers under 96, 16,384 to 340,000 instructions per unit) and `trace.json` in the adversary's section 2.1 form | `candidates/cand-NN/` |
| The generator flags the search needed | `+labw<20 hex>[r<reads>]` (a generic non-load table, the reads per hash on the fam8 load-slot rule), `+ilp<2 or 4>` (the eight registers as independent banks: W chains per lane; 8 is refused, one register per bank has no bijection), `+flat` parsing outside a fam8 suffix; the program id binds every flag | `igneum-pow/src/generator.rs`, `igneum-pow/tests/labsearch.rs` |
| The cost model | the card: a throughput model per tier and state (the measured twins: the 4090 at stock 24.9 nJ per dependent read above idle and 21.2 pJ per instruction; the 5090 at the knee 12.0 nJ and 11.8 pJ on the drawn chain against 6.2 on an ILP-4 chain; the 3090 and 5080 rows PROVISIONAL from the class v4-shape rows), the per-unit fixed work, the coalesced entry at the streaming cost; the chip: the X5 machine (memory at its sustained rate or the SRAM die's power bound, the core sized to the ops, PSU, VRM, fan, host share) on the family table of the adversarial set in force (v0 the placed core; v2 ADVERSARY's fused units with a per-design scale fitted so the frozen object reads v2's own rows) | `calib.json` |
| The score | the worst cell over the cohort (5090 knee and stock, 4090 stock, 3090 stock, 5080 knee and stock) against the lowest credible specialist (board, HBM3, near-memory, N2 die, stored-half hybrid; capex under 10x the card's USD per MH/s), with the band; since 11:5x the BOARD cell first (the energy claim's scope) and the die beside it | `labsearch.py score` |
| The regression tests | REG-01 to REG-07 as predicates on the knob vector, by name (connected state; mixed FP32; window removal alone; int8 at or above 10 percent; scattered ARX at or under 32 reads; scattered reads above 256; the units fault) | `regression.json` |
| The box side | the census (8 chain-shaped seeds through the class's own acceptance rule, attempts and exhaustion) and the pack export on the signing pair (epoch af89be5d, era edc4fa84, day 20730, node1's state, 2^28 words for screening and 2^30 for a handed candidate), SHA256SUMS per candidate | `run-candidates.sh`, build-9:/srv/builds/lab-search/ |
| The card side | the paired row (ABBA against the frozen control in one session, the gen-6 worker, 250 x 2^24, the sampler rule, PAIR lines with USD per MH/s at a street price) and the headroom sweep (the worker's loads-in-flight knobs beside its memprobe) | `pair-bench.sh`, `headroom.sh` |
## 2. The candidates staged (build-1:/srv/artefacts/lab/)
| Set | Candidates | Ranking | Census | Self-test (F1) |
|---|---|---|---|---|
| batch 1 (adv-set v0 top ten) | cand-01 to cand-10: ARX-only at 48 to 64 reads, 170k to 340k instructions, w4/w16/w32/w64 entries | candidates/ranking-batch1-v0.md, -v2.md | 8 of 8 on every one | PASS 10 of 10 (rented 4090, gen-6 worker --check, 11:43 UTC) |
| batch 2 (adv-set v2 top ten on the labw and ilp knobs) | cand-11 to cand-20: MAD-heavy `+labw...+ilp4+flat` draws at 256 reads, two ARX-only points | candidates/ranking-batch2-v2.md | 8 of 8 on nine; cand-17 0 of 8 (exhausted, REJECTED on practical generation) | queued |
| the merged v2 ranking | the twenty on one table by the board cell | candidates/ranking-merged-v2.md | | |
| the ILP-wide redraw of the frozen program | cand-ilp4, cand-ilp2 (the same ops, the same 256 reads and shadow, the registers in 4 or 2 banks; 4 GiB signing pair) | the frozen object's cells | attempt 2 and 0 | PASS |
| X10 "Sector" (the founder's reference) | cand-x10 (as written) and cand-x10b (main's ratified address rule), cand-x10 variant alu-520k | ADVERSARY's cand-x10-*.json | the reference's own acceptance floor | bit-exact on 18 and 18 and 9 fixtures |
| the frozen v6 controls | controls/frozen-v6/headroom/ (variant 1), controls/frozen-v6/fix-4gib/v6x2-ds30 (two lane-hashes per thread, `interleave2.py`) | | | PASS |
## 3. The findings of record (12:0x to 13:0x UK)
1. On the frozen tree's realisable space no scattered-read design screens under 3.7x on the worst cell on set v0 and none under 2.4x on the board cell at the 5090 knee on set v2 (the frozen object 2.66x there); the mixture lemma holds on every set: a candidate moves the ratio only through a family the adversary prices near the card's, and on v2 that family is mad (2.9x), so the top of the v2 ranking is MAD-heavy ILP-4 draws (cand-14 2.42x board at the 5090 knee, 5.20x on the provisional 3090 stock row).
2. The ILP-wide redraw, measured (4090 stock, in-session ABBA, spread 0.00): rate +0.00 percent, joules -0.64 percent (ilp4) and +0.00 (ilp2). The card is on its dependent-read ceiling (30.697 MH/s x 256 = 7.86 G reads/s) with the ALU in the reads' shadow; a cheaper instruction stream cannot raise the rate on v6.
3. X10 "Sector" as written re-reads the same sector 7 loads in 8 (the address reads registers 0 and 1, rewritten by the fold every eighth load): about 16 real misses per lane-hash; 827 nJ per lane-work on the 4090 at stock is a cache artefact of the fault, not a design gain (LAB's ruling). cand-x10b (every load a fresh miss): 3,653 nJ per lane-work at 118 loads, 31.0 nJ per dependent read against v6's 31.6, the card at its read ceiling, 5.8x on ADVERSARY's v2 board row against v6's 5.4x on the same card: the full-sector fold buys nothing on the ratio (REG-06).
4. The 4090's read headroom (variant 1): fifteen cells of block-warps x batch size flat within 0.2 percent at 7.85 to 7.86 G reads/s; the memprobe's dependent 4-byte chase at 1 GiB saturates at 8.06 to 8.15 G loads/s from 65k to 4.2M lanes in flight and with 8 independent loads per lane: the live object at 4 GiB runs at 97 percent of the card's activation bound; larger pages are not available (cuMemGetAllocationGranularity 2 MiB minimum and recommended on driver 12.8).
## 4. The rows of 13:0x to 13:2x UK (the same rented 4090 at stock; the pod destroyed at 12:24 UTC)
| Row | Figure | Reading |
|---|---|---|
| v6x2 (two lane-hashes per thread, interleave2.py) against the frozen control, ABBA | 30.697 against 30.697 MH/s (+0.00 percent), 8,574 against 8,615 nJ per hash (-0.47 percent), the fingerprint equal (b1f90e91cadb15b6) | 8c.8 closed: with the fifteen loads-in-flight cells flat at 7.85 to 7.86 G reads/s and the memprobe's 8.1 G/s ceiling, the 4090 is at its bound; no worker variant raises its rate per dollar on v6 |
| cand-x10b at 64 loads | 122.2 M lane-works/s at 243.5 and 246.8 W: 1,993 and 2,020 nJ per lane-work (63.8 and 64.7 uJ per digest), 31.1 nJ per read | the same read ceiling as at 118 loads; the sector fold rides free |
| cand-x10 variant alu-520k (x10b's address rule, 1,408 steps per load) | fixtures PASS 9 of 9 (97 registers, 0 spills); 15.8 M lane-works/s at 351 to 366 W: 22,152 and 23,225 nJ per lane-work (709 and 743 uJ per digest) | 2.6x to 2.7x the frozen v6's joules per hash on the same card (8,594 in the session's control cell): the P03 10 percent budget failed; the card pays about 42 pJ per instruction on this text (41,536 shuffles per lane-work); ADVERSARY's v3 1.03x assumed the card equal to v6 |
| batch 2 self-tests | cand-11 to cand-20 PASS 10 of 10 (the worker's --check) | cand-17 stays REJECTED on the census (0 of 8) |
| the three handed to COHORT and ADVERSARY at 4 GiB | cand-14, cand-12, cand-13 (candidates/<id>/pack-ds30, SHA256SUMS-ds30) | SCREEN on v2: board 2.42 to 2.43x at the 5090 knee against the frozen 2.66x; the die above 10x |
## 5. Rows pending at this cut
The x10b 64-load rows, the alu-520k fixture check and row, the v6x2 pair, batch 2's self-tests (the rented 4090; the pod is
destroyed on the lane's done line); the 5090 knee pairs and the AMD and Intel tiers (COHORT); the adversary rows per candidate
on set v3 (ADVERSARY). Every row lands beside its candidate under /srv/artefacts/lab/ and in this directory's `rows/`.
## 6. Every artefact by path and sha (build-1, 13:3x UK)
| Artefact | Path | sha256 (16) |
|---|---|---|
| the ranking on set v0 (batch 1) | /srv/artefacts/lab/candidates/ranking-batch1-v0.md | bbab9085bbfa35b7 |
| the ranking on set v2 (batch 1; batch 2) | candidates/ranking-batch1-v2.md; candidates/ranking-batch2-v2.md | 5a6278fe2b65ab4e; fe62b202efcf5afb |
| the merged rankings on v2 and v3 (this directory carries copies) | candidates/ranking-merged-v2.md; candidates/ranking-merged-v3.md | ed075af407a0ef12; 7ad24b0c965a71a2 |
| the handed three at 4 GiB, kernel.cu | candidates/cand-14/pack-ds30; cand-12/pack-ds30; cand-13/pack-ds30 | 7e86d32bbe1ba100; c93ef7220f320b4a; a4f26e4f1b921a9a |
| the ILP-wide redraw, kernel.cu | candidates/cand-ilp4; candidates/cand-ilp2 | 67b65a21ca4c8a8b; 6df1ffb96221373c |
| X10: sector.cu (both kits, -DX10B for x10b); sector520.cu (alu-520k) | cand-x10/kit; cand-x10b/kit; cand-x10/kit-alu520k | 8d137d1fb19010ca; 8d137d1fb19010ca; 34cbc7999d0c28d3 |
| the frozen v6 controls: v6x2-ds30/kernel.cu (two lane-hashes per thread); headroom.sh | controls/frozen-v6/fix-4gib; controls/frozen-v6/headroom | 202b16239ad1b795; 5cfef1ad212beeb4 |
| the row folders (102 files, one SHA256SUMS) | rows/lab-search-4090-pod/SHA256SUMS | cf91736badb50eb0 |
| the ILP pair rows; the headroom cells; the v6x2 pair | rows/lab-search-4090-pod/lab/pair-ilp.log; lab/headroom.log; lab/pair-v6x2.log | 823709eae0c9db28; 538f7f5d91dbbae6; ab61fe5f016b52aa |
| the self-tests, batches 1 and 2 | lab/selftest.log; lab/selftest2.log | 5823f94036ad60fc; 9bb8792edb0d79f3 |
| X10 rows: x10 as written; x10b (118 then 64 loads); alu-520k | x10/run-x10-long.log; x10/run-x10b.log; x10/run-x10b-2.log; x10/run-alu520k.log | 22320101d56f3251; ce99e6d524a5995f; d7ef8f48d0e46b85; 35a7e649db01fa4f |
| the tools and the generator flags | branch lab-search on the box mirror, tip 719d4f223 (tools/lab/search, tools/lab/x10, igneum-pow/src/generator.rs, igneum-pow/tests/labsearch.rs) | by branch |
The rented pod (one-shot, 4090, driver 570.211.01, CUDA 12.8) was destroyed at 12:24 UTC on the lane's done line; the queue file for build-9 was removed when the lane's last batch ended.

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# Batches 1 and 2 re-scored on adversarial set v2 (SEARCH, 12:5x UK 9 Oct 2026): ranked by the BOARD cell (the energy claim's scope), the die and the other designs beside it (coexistence rows); every chip cell v2 (ADVERSARY's 12:0x rows, the per-design scale fitted on the frozen object: board 1.03, hbm3 1.06, near 0.76, die 1.26, hybrid 1.25); the frozen object on the same model: board 2.66x at the 5090 knee, 5.35x at the 4090 stock, die 12.2x. Self-test (F1): cand-01..10 PASS on a rented 4090 (gen-6 worker --check, 11:43 UTC); cand-11..20 queued. Census (F3): 8 of 8 chain-shaped seeds on every candidate except cand-17 (0 of 8, exhausted: REJECTED on practical generation). The 3090 and 5080 card rows remain PROVISIONAL until COHORT measures the frozen object on them.
| cand | class | board 5090 knee (v2) | BOARD worst cell (v2) | worst credible cell, all designs (v2) | node ahead | instrs/hash | reads | status |
|---|---|---|---|---|---|---|---|---|
| cand-11 | w16m8g+sh1024x13+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.46 | 5.19 (3090 stock) | 17.51 (3090 stock vs sram) | 21.47 | 112348 | 256 | SCREENED |
| cand-12 | mx8+sh128x36+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.43 | 5.20 (3090 stock) | 27.95 (3090 stock vs sram) | 32.83 | 40412 | 256 | SCREENED |
| cand-13 | w32m8g+sh64x54+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.43 | 5.20 (3090 stock) | 29.05 (3090 stock vs sram) | 33.98 | 36572 | 256 | SCREENED |
| cand-14 | w32m8g+sh128x18+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.42 | 5.20 (3090 stock) | 30.85 (3090 stock vs sram) | 35.62 | 27356 | 256 | SCREENED |
| cand-15 | mx8+sh256x13+state+fold+labw12121213130000080000+ilp4+flat | 2.43 | 5.23 (3090 stock) | 33.11 (3090 stock vs sram) | 38.01 | 30172 | 256 | SCREENED |
| cand-16 | mx8+sh512x4+state+reg64c+fold+arxr64 | 2.47 | 5.23 (3090 stock) | 17.61 (3090 stock vs sram) | 21.70 | 20354 | 64 | SCREENED |
| cand-17 | w16m8g+sh256x13+state+fold+labw12121213130000080000+ilp4+flat | 2.44 | 5.23 (3090 stock) | 31.06 (3090 stock vs sram) | 35.73 | 32476 | 256 | SCREENED |
| cand-18 | mx8+sh128x36+state+fold+labw12121213130000080000+ilp4+flat | 2.44 | 5.24 (3090 stock) | 30.06 (3090 stock vs sram) | 34.90 | 40412 | 256 | SCREENED |
| cand-19 | w32m8g+sh1024x4+state+fold+labw12121213130000080000+ilp4+flat | 2.44 | 5.24 (3090 stock) | 29.73 (3090 stock vs sram) | 34.55 | 41692 | 256 | SCREENED |
| cand-20 | mx8+sh256x9+state+reg64c+fold+arxr48 | 2.50 | 5.24 (3090 stock) | 14.90 (3090 stock vs sram) | 18.65 | 22040 | 48 | SCREENED |
| cand-05 | mx8+sh256x81+state+reg64c+fold+arxr48+flat | 3.91 | 7.84 (3090 stock) | 13.08 (3090 stock vs near) | 15.48 | 169496 | 48 | SCREENED |
| cand-06 | mx8+sh256x81+state+reg64c+fold+arxr48 | 3.91 | 7.84 (3090 stock) | 13.08 (3090 stock vs near) | 15.48 | 169496 | 48 | SCREENED |
| cand-04 | w32m8g+sh1024x36+state+reg64c+fold+arxr96 | 3.92 | 7.87 (3090 stock) | 13.43 (3090 stock vs near) | 15.72 | 301621 | 96 | SCREENED |
| cand-08 | mx8+sh1024x27+state+reg64c+fold+arxr64 | 3.97 | 7.94 (3090 stock) | 13.31 (3090 stock vs near) | 15.71 | 225154 | 64 | SCREENED |
| cand-09 | mx8+sh256x108+state+reg64c+fold+arxr64 | 3.97 | 7.94 (3090 stock) | 13.31 (3090 stock vs near) | 15.71 | 225154 | 64 | SCREENED |
| cand-07 | w16m8g+sh1024x27+state+reg64c+fold+arxr64 | 3.97 | 7.95 (3090 stock) | 13.31 (3090 stock vs near) | 15.71 | 225730 | 64 | SCREENED |
| cand-01 | mx8+sh256x108+state+reg64c+fold+arxr48+flat | 4.17 | 8.31 (3090 stock) | 13.43 (3090 stock vs near) | 16.08 | 224792 | 48 | SCREENED |
| cand-02 | mx8+sh256x108+state+reg64c+fold+arxr48 | 4.17 | 8.31 (3090 stock) | 13.43 (3090 stock vs near) | 16.08 | 224792 | 48 | SCREENED |
| cand-03 | w32m8g+sh256x108+state+reg64c+fold+arxr48 | 4.17 | 8.32 (3090 stock) | 13.43 (3090 stock vs near) | 16.09 | 225800 | 48 | SCREENED |
| cand-10 | w64m8g+sh512x81+state+reg64c+fold+arxr64 | 4.37 | 8.76 (3090 stock) | 15.17 (3090 stock vs near) | 18.18 | 338626 | 64 | SCREENED |

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# The search candidates re-ranked on ADVERSARY's set v3 (SEARCH, 13:2x UK 9 Oct 2026): the card side from the lane's calibrated screen (5090 knee 4,109 nJ for the frozen object; the 3090 and 5080 rows PROVISIONAL), the chip side from ADVERSARY's per-candidate v3 rows (scratchpad/lab/adv/cand-NN.json: the cheapest DRAM design = the board column, a_same = the lowest credible design, usually the full SRAM die with fused operations). The board cell is the energy claim; the die is a coexistence row. Every candidate self-test PASS; cand-17 REJECTED on the census (0 of 8).
| cand | class | board cell at the 5090 knee, set v3 (band) | board, worst card cell (card) | die at the 5090 knee (v3) | board a node ahead | die a node ahead | board 5090 knee on my v2 model | v3 lowest credible design |
|---|---|---|---|---|---|---|---|---|
| cand-11 | w16m8g+sh1024x13+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.42 (1.92 to 2.83) | 5.10 (3090 stock) | 8.3 | 2.57 | 10.5 | 2.46 | full SRAM die(s) + sized + fused operations |
| cand-13 | w32m8g+sh64x54+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.51 (1.99 to 2.90) | 5.38 (3090 stock) | 16.0 | 2.57 | 18.9 | 2.43 | full SRAM die(s) + sized + fused operations |
| cand-19 | w32m8g+sh1024x4+state+fold+labw12121213130000080000+ilp4+flat | 2.51 (1.99 to 2.90) | 5.38 (3090 stock) | 15.5 | 2.57 | 18.4 | 2.44 | full SRAM die(s) + sized + fused operations |
| cand-12 | mx8+sh128x36+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.51 (1.99 to 2.90) | 5.38 (3090 stock) | 15.5 | 2.57 | 18.3 | 2.43 | full SRAM die(s) + sized + fused operations |
| cand-18 | mx8+sh128x36+state+fold+labw12121213130000080000+ilp4+flat | 2.52 (2.00 to 2.91) | 5.41 (3090 stock) | 16.3 | 2.58 | 19.1 | 2.44 | full SRAM die(s) + sized + fused operations |
| cand-14 | w32m8g+sh128x18+state+fold+labw0f0f140c0d0000190000+ilp4+flat | 2.52 (2.00 to 2.91) | 5.42 (3090 stock) | 17.4 | 2.57 | 20.2 | 2.42 | full SRAM die(s) + sized + fused operations |
| cand-17 | w16m8g+sh256x13+state+fold+labw12121213130000080000+ilp4+flat | 2.53 (2.01 to 2.91) | 5.43 (3090 stock) | 16.9 | 2.57 | 19.6 | 2.44 | full SRAM die(s) + sized + fused operations |
| cand-15 | mx8+sh256x13+state+fold+labw12121213130000080000+ilp4+flat | 2.54 (2.01 to 2.92) | 5.45 (3090 stock) | 19.0 | 2.58 | 21.9 | 2.43 | full SRAM die(s) + sized + fused operations |
| cand-16 | mx8+sh512x4+state+reg64c+fold+arxr64 | 2.64 (2.10 to 3.06) | 5.59 (3090 stock) | 11.0 | 2.74 | 13.5 | 2.47 | full SRAM die(s) + sized + fused operations |
| cand-20 | mx8+sh256x9+state+reg64c+fold+arxr48 | 2.67 (2.12 to 3.11) | 5.60 (3090 stock) | 9.6 | 2.81 | 11.9 | 2.50 | full SRAM die(s) + sized + fused operations |
| cand-04 | w32m8g+sh1024x36+state+reg64c+fold+arxr96 | 3.09 (2.47 to 3.72) | 6.19 (3090 stock) | 4.1 | 3.66 | 5.2 | 3.92 | hybrid, hottest three quarters in SRAM + sized + fused operations |
| cand-07 | w16m8g+sh1024x27+state+reg64c+fold+arxr64 | 3.12 (2.50 to 3.77) | 6.25 (3090 stock) | 4.2 | 3.73 | 5.4 | 3.97 | full SRAM die(s) + sized + fused operations |
| cand-08 | mx8+sh1024x27+state+reg64c+fold+arxr64 | 3.12 (2.50 to 3.77) | 6.26 (3090 stock) | 4.2 | 3.73 | 5.5 | 3.97 | full SRAM die(s) + sized + fused operations |
| cand-09 | mx8+sh256x108+state+reg64c+fold+arxr64 | 3.12 (2.50 to 3.77) | 6.26 (3090 stock) | 4.2 | 3.73 | 5.5 | 3.97 | full SRAM die(s) + sized + fused operations |
| cand-05 | mx8+sh256x81+state+reg64c+fold+arxr48+flat | 3.13 (2.51 to 3.78) | 6.27 (3090 stock) | 4.2 | 3.74 | 5.5 | 3.91 | full SRAM die(s) + sized + fused operations |
| cand-06 | mx8+sh256x81+state+reg64c+fold+arxr48 | 3.13 (2.51 to 3.78) | 6.27 (3090 stock) | 4.2 | 3.74 | 5.5 | 3.91 | full SRAM die(s) + sized + fused operations |
| cand-03 | w32m8g+sh256x108+state+reg64c+fold+arxr48 | 3.19 (2.56 to 3.87) | 6.36 (3090 stock) | 4.1 | 3.87 | 5.3 | 4.17 | full SRAM die(s) + sized + fused operations |
| cand-01 | mx8+sh256x108+state+reg64c+fold+arxr48+flat | 3.19 (2.56 to 3.88) | 6.37 (3090 stock) | 3.8 | 3.88 | 4.9 | 4.17 | near-memory (base dies) + sized + fused operations |
| cand-02 | mx8+sh256x108+state+reg64c+fold+arxr48 | 3.19 (2.56 to 3.88) | 6.37 (3090 stock) | 4.0 | 3.88 | 5.2 | 4.17 | hybrid, hottest three quarters in SRAM + sized + fused operations |
| cand-10 | w64m8g+sh512x81+state+reg64c+fold+arxr64 | 3.32 (2.65 to 4.06) | 6.65 (3090 stock) | 4.2 | 4.00 | 5.3 | 4.37 | hybrid, hottest three quarters in SRAM + sized + fused operations |
the frozen object on v3: board 1541 nJ, die 335 nJ; my 5090 knee card 4,109 nJ: board 2.67x, die 12.3x

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<!-- the landed copy of the lab's candidate table at this landing; the live table is scratchpad/lab/TABLE.md on the LAB lane's Mac -->
# The 1.5x laboratory candidate table (LAB; current as of 12:2x UK 9 October 2026 by `date`; the interface: scratchpad/lab/INTERFACE.md)
Score = the WORST comparison over the cohort (same node and one node ahead), the candidate's GPU energy per accepted work over the
lowest credible specialist energy for the same work (interface section 3). The working scope since 11:5x UK (8a): the same-node
board is the energy claim; the die and node-ahead chips are coexistence rows. The coexistence table (8b, under the rulings of 8c) is
the headline beside the score. Every ratio names its adversary, column, clock state, card and set (8c.1). PASS is never written
here. Every chip figure is a WITNESS (E_D) unless marked BOUND, CLAIMED or SCREEN. Energies in nJ per hash (per lane-work for X10).
The approved claim wording (8c.9), verbatim: "The current model finds that existing GPU electricity costs are below the assessed
DRAM-board specialist's all-in costs at the tested tariffs and stated lifetime assumptions. This supports a conditional
entry-deterrence result. It does not yet establish post-deployment competitiveness, viable GPU replacement or new entry, or
coexistence against the modelled SRAM fleet at sufficient scale. Those outcomes remain separately assessed."
## The controls and candidates
| id | kind | tree, packs, kits | resource line | cohort rows (board power, stock on every rented pod, lock refused everywhere; wall BLOCKED; median of three) | adversary rows (set v2, instruction convention, complete machine) | worst score (band), labelled | coexistence (8b under 8c) | status | next move (owner, clock UK) |
|---|---|---|---|---|---|---|---|---|---|
| ctl-v6 | control (frozen) | 1a938abe4; the signing object 0x2a1d6caab4c24564 at 2^30 words = 4 GiB (pack x1-ctrl-ds30.tgz 7606c13d, twin 7629ed95; CONTROLS 12:2x on main's correction, build-1:/srv/artefacts/lab/controls/frozen-v6/ with sidecars); kits: l8off c20999d1 (CUDA 218ca414 / 9bfcf728 Linux), gen-6 bb66a546 (Linux CUDA 804a6f7f, OpenCL 371dbb27); COHORT's rows on kit bf9b85d6, worker f5f3846c; the 1 GiB pairing only a cross-check row | 4 GiB; 256 loads per hash of ONE 32-bit word each (1,024 bytes consumed of 8,192 moved; the readwidth fact of record, 8a.1); 62,120 instructions (102,612 counted); state class; layer 8 ON; cold verification 8.3 to 8.6 ms per warp of 32 on one core (the record; the fresh F2 row 13:30) | STOCK (COHORT 12:17, fp b1f90e91cadb15b6 PASS on every cell): RTX 3090 pod 55006505 (capped 260 of 350 W) 8,429 at 30.80 MH/s; RTX 3090 pod 55006552 (capped 220 of 420) 7,109 at 30.90; RTX 5090 pod 55006481 (384 of a 500 W cap, uncapped in effect) 5,597 at 68.66, f 0.811; RTX 5090 pod 55006478 (capped 400 of 600) 5,828 at 68.64; RTX 5080 pod 55006521 (189 of 330, clean) 5,410 at 35.03, f 0.806; the 3090 twins read f 1.02 (meaningless on a capped card). KNEE: the house record only (5090 at 1,300: 4,011). In flight: 4090a (repeat triple at 3.98 percent spread), 4090b, 5080b, uncapped 5090c and 3090c. AMD, Intel: NOT RUN "no rented card; the house rigs unreachable by software" | v2 (ADVERSARY 12:0x to 12:1x; commits f9cb259cc routed lanes, 923f76e74 coexistence, 7c6b538f1 price sheet on class-v6-adversary): the cheapest same-node DRAM board a = 1,543 (1,328 to 1,947) = 2.60x (2.06 to 3.02) at the 5090 knee, 2.70x a node ahead; the split chip memory 527 / ALU 167 / tax 849 against the card's 3,642 / 369 / 0; the tax ladder: the record's static 2.60x, half 3.28x, zero (the bound) 4.43x; ProgPoW's premise 1.01x to 1.02x; the N2 die a = 337 = 11.9x (coexistence) | PARTIAL over {3090, 5090, 5080 at stock; the 5090 knee from the record}; the 4090 cells pending; AMD and Intel NOT RUN. The worst cell: the RTX 3090 at stock on the same-node DRAM board, set v2: 5.46x (4.33 to 6.35) same node, 5.68x a node ahead; the die at that cell 25.0x. The other cells on the board: 3090 (capped) 4.61x, 5090 stock 3.63x, 5090 (capped) 3.78x, 5080 stock 3.51x, 5090 knee 2.60x; the record's rented 4090 at stock (8,091) would read 5.24x | ctl-v6 on set v2 (WITNESS; a 100,000-machine fleet, a 24-month straight-line life, design USD 35 M board chip and 300 M die, the card sunk at USD 30.6 per MH/s on v6 at the knee, 15.7 of record beside it): the same-node board, edge 2.60x at the knee, chip capital USD 14.04 per MH/s (die 0.34, memory 5.42, board 3.15, design 5.13); GPU electricity-only 0.056 / 0.111 / 0.167 USD per TH at the three tested tariffs against the chip's all-in 0.244 / 0.265 / 0.287: cost ratio 4.4x / 2.4x / 1.7x (the curves meet about USD 0.33 per kWh, the reviewer's linear read; ADVERSARY's exact figure owed); the stored-half hybrid, edge 3.80x, USD 9.17: 2.9x / 1.6x / 1.1x; the N2 die, edge 11.9x, USD 1.59: 0.5x / 0.3x / 0.2x, the GPU owner's electricity above the chip's all-in once the fleet passes 14,300 dies at ten cents (break-even 14,300 to 25,000 under the growth schedules; no schedule kills the die at 100,000 dies); the node-ahead board, edge 2.70x: 4.4x / 2.4x / 1.7x. NEW BUYER (8c.7): picks the chip on every row and tier (the board 0.24x to 0.43x a new card's all-in at ten cents, the die 0.04x; indifference USD 9.7 per MH/s on the 5090 knee, 10.5 on the 5080, 5.4 on the 5090 stock, 2.6 on the 4090; the hold is the project share below about 13,500 boards). The two-phase rows, the revenue column, the used-card column and the exact meeting tariff: NOT RUN (ADVERSARY, this afternoon) | MEASURED-partial (the 4090 cells pending) | COHORT: the 4090 and uncapped cells; the read-headroom row (8c.8) with CONTROLS; ADVERSARY: the two phases, revenue, used-card, the meeting tariff, the growth-scaled new buyer; LAB: the full score when the 4090 rows land |
| ctl-progpow-094 | control | CONTROLS building the official 0.9.4 reference from source with its test vectors on build-5 (pid build-5-lab-controls-progpow.pid), by 14:00; ADVERSARY's v2 rows use the KAWPOW census as the proxy | the equivalence contract before any number; 16 KB per hash of DRAM traffic (ADVERSARY) | NOT RUN (the record's 4090 stock row 6,920 is ADVERSARY's numerator) | v2 (proxy): the board 4.24x at the 4090 stock numerator (the 32-register lane costs more than the 8-register one), a_same 545 = 12.7x; the board bandwidth-bound at 16 KB per hash (93 MH/s per board), USD 6.89 per MH/s against 29.7; ProgPoW's premise 1.1x to 1.2x (no twin) | proxy, 4090 stock, board, v2: 4.24x; NOT the lab's score (the pinned build, the cohort rows and a twin pending) | v2 at ten cents, proxy: the board holds 1.1x (the GPU's electricity above the chip's all-in at fifteen cents); the die pushed out above 14,200 dies | NOT RUN (proxy) | CONTROLS 14:00; COHORT rows 15:00 with a twin; ADVERSARY re-prices on the pinned object |
| ctl-fishhash | control | CONTROLS building Iron Fish's implementation on build-9 (pid build-9-lab-controls-fishhash.pid), by 14:00; ADVERSARY read cpp/FishHash.cpp | 32 x 3 fetches of 128 B = 96 random reads over a fixed 4.83 GB dataset, about 9,400 lane-instructions of 64-bit multiply-add and FNV | NOT RUN | v2: a_same 162 (three N2 reticles, fused lane), USD 0.35; the board 1,044 (872 to 1,251), 124 MH/s per board bandwidth-bound, USD 4.78; 95 percent of the board's energy is the memory path | waits on COHORT's card row | NOT RUN | NOT RUN | CONTROLS 14:00; COHORT 15:00 |
| ctl-coop-arx | control and candidate | CONTROLS: the cooperative ARX kernel and CPU reference bit-exact at 2^16 for chain lengths 24 / 264 / 1,032 / 4,104 ARX ops per fetch per lane (build-2, pid build-2-lab-controls-arxcoop.pid); the document and rows 13:00 | 64 coalesced 256 B fetches; target f at or under 14.8 percent non-ARX energy; spills, sync, generation and finalisation counted | NOT RUN (the card MODELLED by ADVERSARY: 35 nJ per coalesced read, 8.5 pJ per ARX instruction at the knee) | v2 (card MODELLED, SCREEN) at 1.6 M ARX per hash: the board 2.40x (1.96 to 2.86) same node against the routed 32-register fused lane, 2.98x ahead; a_same 5,024 (near-memory, fused) = 3.15x; USD 13 to 15 per MH/s against 15.7 | SCREEN, 5090 knee modelled, board, v2: 2.40x | v2 at ten cents, card modelled: the board holds 1.1x; the die holds 1.5x | SCREEN | CONTROLS 13:00; COHORT's 4090 and 5090 rows 15:00; ADVERSARY re-prices within the hour |
| cand-x10 (variants alu-130k / 260k / 520k and sector-118 inside it) | candidate (the founder's third review; the scoped same-node board claim; 8a, 8a.1) | SEARCH: the kit at build-1:/srv/artefacts/lab/cand-x10/kit/ (sector.cu 16417ce6, run-x10.sh, 18 fixtures PASS on a rented 4090 at 11:11 UTC, 112 registers, no spills); the accepted-work contract APPROVED (per lane-work = per digest over 32, both printed) | dependent 32 B sector loads, every byte folded; 118 loads as written; the FAULT OF RECORD: 7 of every 8 loads re-read the same sector, about 16 real misses per lane-hash (8a.1); the verifier under 10 ms owed | SEARCH's first rows (a rented 4090 at stock, SCREEN until COHORT's pairs): 118 loads 810 to 845 nJ per lane-work (25.9 to 27.0 uJ per digest) at 264 to 275 W; 64 loads 567 at 294 W; a tenth of v6's 8,091 on the card class, the cache hits of the fault, not a design gain | v2 with the card MODELLED (SCREEN): sector-118 the board 634 (553 to 798) = 3.00x (2.38 to 3.44) at a card modelled at 1,900 nJ, 3.03x ahead; the split chip 243 / 22 / 369 against the card's 1,650 / 70 / 180; the fold gap 1.2x to 3.9x by core; the die 73 (26x); the ALU ladder 130k / 260k / 520k: the board 4.67x / 2.89x / 1.63x (1.27 to 2.06), 5.52x / 3.56x / 2.08x ahead (the card = v6 by the reviewer's construction). Every modelled-card row re-priced within the hour of COHORT's measured row; the 16-real-misses fault means the chip's memory term in these rows is also overstated for the object as written | SCREEN; the verdict line waits on COHORT's measured pairs (v6 and X10, the same card, the same session) | v2 at ten cents, card modelled: the board holds 2.2x; the die pushed out above 5,800 dies | SCREEN (the object as written carries the fault) | COHORT: run cand-x10 and cand-x10b paired with v6 on the 4090 and 5090 pods now (the kits are staged); ADVERSARY: re-price on the measured rows and on the 16-miss trace; LAB: the verdict line within the hour of the pairs |
| cand-x10b | candidate (main's ratified address rule on X10: load n reads the two registers the previous load's fold wrote last; zero repeats in every trace) | SEARCH: hash-x10b.ts, fixtures-x10b.txt (18), sector.cu under -DX10B; the kit lands under build-1:/srv/artefacts/lab/cand-x10b/ with its fixture line; queued on the same 4090 pod behind the x10 rows | as X10 with 118 real dependent sector misses per lane-work; fixtures 18 of 18 PASS under -DX10B; the kit at build-1:/srv/artefacts/lab/cand-x10b/kit with trace.json | SEARCH's first row (a rented 4090 at stock, sampler rule, SCREEN until COHORT's pair): 118 loads 3,653 nJ per lane-work at 66.1 M lane-works per second and 241.5 W, 31 nJ per dependent sector read, the card at its 7.8 G dependent reads per second ceiling; the 64-load and lock rows queued | set v2's same-node board on the 118-miss object: 634 (553 to 798), WITNESS, the split chip memory 243 / fold 22 / tax 369 | the 4090 at stock, the same-node DRAM board, set v2: 5.8x (4.6 to 6.6); v6 on the same card class 5.4x: the fold buys nothing on the ratio (REG-06 confirmed); the term that holds it above 1.5 is the card's memory path (31 nJ per read against the chip's about 2); PARTIAL: the locked 5090 and 5080 and the AMD card NOT RUN | NOT RUN (ADVERSARY re-prices on the measured row) | MEASURED-partial; FAIL CLOSED per the review (no added arithmetic, rotation or set growth) | COHORT: the v6 and x10b pairs on the uncapped 4090 and 5090 after the dataset-size decider; SEARCH: the 64-load and lock rows; ADVERSARY: the coexistence row on the measured card |
| cand-14, cand-12, cand-13 (SEARCH's top three on set v2, the hand-off 13:2x UK) | candidates | packs at 4 GiB on the signing pair with SHA256SUMS and trace.json at build-1:/srv/artefacts/lab/candidates/<id>/pack-ds30 (the ds28 screening pack beside); self-test PASS (the gen-6 worker --check on the rented 4090), census 8 of 8 | cand-14: w32m8g+sh128x18+state+fold+labw0f0f140c0d0000190000+ilp4+flat (a MAD-heavy table: add 15 sub 15 xor 20 rotl 12 rotr 13 mad 25, four register banks, 32 B entries, 256 reads, 27k instructions, no window layer); cand-12: mx8+sh128x36 on the same table and banks, 4 B entries, 40k instructions; cand-13: w32m8g+sh64x54, 37k instructions | NOT RUN (COHORT: paired with v6 at stock and at the knee on the 4090 VM, behind the ledger session and the X10 pairs) | v2 (SEARCH's model; ADVERSARY's v3 pages for cand-11 to cand-20 beside): board 2.42x / 2.43x / 2.43x at the 5090 knee, 5.20x on the provisional 3090 stock row; the die 14.4x / 11.6x / 13.6x; the frozen object on the same model 2.66x and 12.2x | SCREEN: the realisable space sits between 2.4x and 2.7x on the board cell and above 10x on the die; the top three gain 9 percent on the board through mad (the one family priced near the card, 2.9x) and the ILP-4 banks; no candidate screens near 1.5 on any cell; the measurement at the knee decides whether the 9 percent exists (at stock the ALU sits in the reads' shadow) | NOT RUN | SCREEN | COHORT after the ledger; ADVERSARY re-prices on the measured rows |
| cand-01 to cand-09, cand-ilp2, cand-ilp4 (SEARCH batch 1) | candidates (the workload-search system) | staged at build-1:/srv/artefacts/lab/candidates/ (12:17 UK by the box clock) with trace.json; ADVERSARY's trace watcher prices each within the hour; the GPU self-test on a one-shot 4090 pod by 13:30; the top three to COHORT and ADVERSARY by 14:00 at ds30 | the six knobs with explicit limits; the ARX-only region 48 to 64 reads, 170k to 225k instructions per unit; the ilp variants test the card's dependency structure (11.8 pJ per instruction at the lock on the drawn block against 6.2 on an ILP-4 chain) | NOT RUN | NOT RUN (priced on v2 within the hour) | SCREEN on set v3 (ADVERSARY 12:3x, the card figures SEARCH's screened values; the worst cohort cell the 3090 at stock in every one): cand-01 to cand-10 (arxr48/64 shadow classes, 48 to 96 scattered reads, 169k to 339k instructions): the board 3.1x to 3.3x at the 5090 knee and 6.2x to 6.7x at the worst cell, a (the die, the three-quarter hybrid or near-memory, 574 to 1,168 nJ) 3.9x to 4.2x and 7.7x to 8.4x (9.7x to 10.9x a node ahead); cand-11 to cand-19 (labw classes, 256 scattered reads of 4 to 32 bytes, 27k to 112k instructions): the board 2.4x to 2.5x at the knee, 5.1x to 5.5x at the worst cell, a 8.3x to 19.0x and 17.6x to 40.9x (the full SRAM die serves 256 reads at 187 to 495 nJ); cand-16 and cand-20 (sh512x4, sh256x9 at 64 and 48 reads, 20k to 22k instructions, the 5090 at 0.8 to 1.0 uJ): a 11.0x and 9.6x, boards 2.6x and 2.7x. NONE UNDER 1.5x ON ANY CELL: the die binds every candidate with 256 reads; the board's own tax holds the board cells at 2.4x and above | v3 coexistence rows per candidate on the twenty pages (the new-buyer column included) | SCREEN | SEARCH: the self-tests 13:30, the top three on v3 at 14:00; COHORT measures the top three |
## COHORT's denominator run on ctl-v6 (from 11:49 UK)
Rented by id through the handover gate (two hosts per card: 5090 x2, 4090 x2, 3090 x2, 5080 x2; drivers 570 to 595), the gen-6
worker f5f3846c on kit bf9b85d6, the x1-ctrl-ds30 pack (0x2a1d6caab4c24564) with its read-only twin (X7's twin, kernel 93a6a5ce,
the address path kept by construction, twin_addr none accepted), three timed runs per pack per state interleaved, rows at
build-1:/srv/artefacts/lab/ctl-v6/vast-<pod>/ (rows.jsonl, SHA256SUMS, the .tgz) linked under /srv/artefacts/lab/cohort/ctl-v6/<card>/
and the cohort's own table at /srv/artefacts/lab/cohort/TABLE.md. Every pod refuses the lock: stock only. The capped-host finding
(12:17): f near 1 on a capped card is meaningless; the gate now refuses capped hosts for the f cells; the 4090b pod that never
answered was destroyed and re-rented. AMD and Intel: no RX 7600 to 9070 or Arc card on either provider (AMD there is MI300X and
MI350X only), the house rigs unreachable by software; NOT RUN "no rented card; the house rigs unreachable by software" on every
candidate (build-1:/srv/artefacts/lab/NOT-RUN-amd-intel.md); the hourly provider check retries. Spend: USD 750 at 12:03.
## Adversarial sets
| set | date | contents | candidates scored on it |
|---|---|---|---|
| v0 (the record) | 9 Oct, X0 amendment 5b and X5 | the placed 8-lane 18-family core (6.55 pJ per lane-op at N5), the GDDR7 board, the hybrids at 0.25, 0.50, 0.75, the N2 full-SRAM die, recomputation; X7's HBM3 and near-memory paths; X8's systolic int8 array | ctl-v6 (the record: board 2.35x, die 7.8x); SEARCH's cost model (recalibration owed) |
| v1 | 12:0x UK (ADVERSARY, 0344ec150 on class-v6-adversary) | v0 plus a bandwidth ceiling on every DRAM design (1.79 TB/s at 85 percent), a register file sized to the work (the routed 8-register flop lanes), fused dependent operations (the tail CLAIMED), HBM3 at one and eight stacks and near-memory as complete machines, recomputation priced from the Ethash-family generators, the die on as many reticles as the dataset needs; calibration reproduces X0 5b (1,706 vs 1,707 nJ; the die 511 vs 513) | the four controls (ctl-v6 board 2.57x) |
| v2 | 12:0x to 12:1x UK (ADVERSARY, f9cb259cc the routed lanes, 923f76e74 coexistence, 7c6b538f1 the price sheet; tools/chip-model/floor-k-lab with the routed power logs) | v1 with the routed fused-ARX lanes (ASAP7 routed with SPEF, 1,200 ps, timing met: arxf 8-register window 1.87 pJ per fused add-rotate-xor triple, 464 um2, against the single-op lane's 2.16 pJ per op; arxf32 32-register window 5.42 pJ per triple, 1,316 um2): the ARX-fused rows WITNESS; the non-ARX fused groups (mul-xor, 64-bit multiply-add, math and merge) CLAIMED-partial until the two lanes in the flow on build-4 land (the 64-register fused-ARX window that X10 carries as "x1.6 claimed", a fused multiply-xor lane), about 12:3x; every modelled-card row labelled "card": "MODELLED" and SCREEN; the coexistence tables, the new-buyer column, the growth schedules (growth-schedules.json) and the price sheet with the break-even sensitivity (the board breaks even at ten cents only with devices under about USD 8 to 10 each, a fleet above a million machines and a 36-month life together) | every control and candidate (ctl-v6 board 2.60x, die 11.9x; ctl-progpow-094 4.24x proxy; ctl-coop-arx 2.40x screen; cand-x10 3.00x screen) |
| v3 | 12:2x UK (ADVERSARY b2b9ee0b9; v3/ beside v2/ under lab/adv/; the JSONs in scratchpad/lab/adv/ now v3) | v2 plus two more ROUTED lanes (the 64-register fused-ARX window 9.90 pJ per triple, 2,469 um2, replacing the "x1.6 claimed"; the fused multiply-xor pair 4.13 pJ over 32 registers, replacing the claimed tail on the FNV and merge steps) and two corrections (a shadow class's window is the 8 registers its shadow runs on, as v6; a sized lane pays for a window above 8, so the 64-register sized lane is dearer than the placed core's SRAM window) | every control and candidate: ctl-progpow-094 a_same 669 (10.3x), board 3.94x (proxy); cand-x10 Sector 2.92x; cand-x10 at 520k ALU the board 1.03x (0.83 to 1.14) same node, 1.35x ahead, SCREEN with the card assumed = v6 (the measurement ordered: SEARCH builds the point, COHORT pairs it; the card's own 520k instructions at 5.9 to 11.8 pJ are 3 to 6 uJ, so the P03 line decides first); cand-01 to cand-10 a_same 574 to 1,168, the board 769 to 1,472 (about 3.1x to 3.3x against their screened 5090 knee figures, a 3.9x to 5.4x) |
## Rejections and regression hits
| when | source | what |
|---|---|---|
| 12:1x UK | SEARCH, the first screen (4,000 draws, seed 1) | 1,762 int8 mixes by REG-04; 122 scattered-ARX designs at or under 32 reads by REG-05; 343 on the verification or granularity limits (F2); SCREEN rejections, none measured |
| 12:1x UK | SEARCH on cand-x10 | the Sector reference as written re-reads the same sector for 7 of every 8 loads (16 real misses per lane-hash): the object is measured as written (its own row) and the corrected address rule measured beside it as cand-x10b; the author's energy split and the 10 percent budget do not describe the object as written |
## Faults
| when | source | what | state |
|---|---|---|---|
| 11:49 UK | COHORT | no AMD (RX 7600 to 9070) or Intel Arc card rentable on either provider; the house rigs unreachable by software | the two tiers NOT RUN with the reason on every candidate; hourly retry |
| 12:1x UK | SEARCH | a parse fault on +arxr48+flat in batch 1 | fixed in the cut; a 20-minute slip on the 13:30 clock, absorbed |
| 12:1x UK | COHORT | the 4090b pod never answered on the provider's ssh proxy | destroyed and re-rented on another host |
| 12:17 UK | COHORT | the read-only twin reads f near 1 on a power-capped card (the saved ALU power goes to clock) | the lab rule 1.11: f on uncapped cards only; the gate refuses capped hosts for the f cells; capped rows stand named |
| 12:2x UK | LAB | the line to main of 12:1x carried "13:1x UK" (main's clock, not `date`) | the lab's lines carry `date` from here; reported once |
## The shipping row (the claim's phase B is NOT LIVE until a shipped package runs a prover; main 12:4x UK: the most important 2.0 shipping item)
| item | what the claim needs on the record | state | owner |
|---|---|---|---|
| the two-phase result it serves | ADVERSARY 545f3f8a0: with the ratified 80/20 split (D04, token-value/README.md: the 80/20 split emission allocation only) a GPU earns the mining share plus the proving share, a hash chip the mining share only; the proving share at which the chip's operating advantage disappears at ten cents is 9 percent for the board, 13 for the hybrid, 20 for the die, against the ratified 20: with proving live the GPU out-earns the board chip in phase B. The stated assumption on the phase B row: all proving stays on the GPU cohort; a chip maker who fields GPUs to prove is a GPU miner with a sidecar | NOT LIVE | ADVERSARY (the row), the release lane (the package) |
| which shipped packages prove today, at what VRAM, by what switch | the Windows and Mac apps: the VRAM threshold and the switch by file and line; the HiveOS package: none (mines only); the 24 GB threshold (proving turns on at 24 GB) stated against the proving manifest and the app's settings code | BLOCKED: the file-and-line facts from the release lane and the app lane | the release lane aa4391fd50c62e28f |
| whether a 16 GB card can prove a smaller instance | the proving instance sizes against the 16 GB tier (the B3 feasibility rows explored 32, 128 and 512 MiB per instance for Track B; the live prover's own instance size by its manifest) | BLOCKED: the prover's instance table | the release lane with the proving lane |
| the share of the live cohort that can prove | the workers page's card census (the share of cards at 24 GB and above; the share at 16 GB) | NOT RUN: the fleet lane's workers.json read | the fleet lane |
| a HiveOS prover beside the miner | a named 2.0.3.1 item beside snapshot sync, with the memory and VRAM rules from this row; no new research | NOT RUN: scheduled by the release lane | the release lane aa4391fd50c62e28f |
| the 4 GiB proving cap defined precisely (8c.10) | which of the mining state, the proof-generation allocation, the verifier requirement or the advertised hardware profile it limits | NOT RUN | CONTROLS (the definition), ADVERSARY (the economics) |
## The read-headroom row (8c.8), answered 12:4x UK (CONTROLS and SEARCH, WITNESS)
| card | achieved sector reads per second on v6 at 4 GiB (rate x 256) | the activation bound (JEDEC-family timing approximations, named so) | nJ per 32 B sector read (stock) | the fold | the ILP lever (SEARCH, in-session ABBA) | reading |
|---|---|---|---|---|---|---|
| RTX 4090 | 7.86 G | at its tFAW form, 7.9 G | 26.4 to 28.4 | the whole-sector load free (a32x = a4); the full fold +1.0 nJ (+3.7 percent) | cand-ilp4 rate +0.00 percent, joules -0.64 (8,560 against 8,615); cand-ilp2 +0.00 / +0.00 | AT the limit: no card-side headroom; the ALU in the reads' shadow |
| RTX 5090 | 17.6 G | within a third of its tRC form | 18.9 to 19.8 | the full fold +1.2 nJ (+6.2 percent) | not yet paired | AT the limit; flat from 1 to 8 GiB (no TLB cliff for a flat stream) |
| RTX 5080 | 8.97 G | CONTROLS owed | | | | |
| RTX 3090 | 7.91 G (capped pods) | CONTROLS owed | | | | |
The miner-side lever "more loads in flight per core" is CLOSED on v6 by these rows; the phase B lever on the card is its memory
system itself. The "2.4x at 4 GiB" reading is WITHDRAWN (a contention fault of the CONTROLS lane: the 4 GiB bench shared the card
with the sector sweep; clean ABAB on a 5090: the 4 GiB object costs 3 percent of rate against the 1 GiB research pack).
## The shipping row's facts (the release lane, 12:5x UK, release-2.0.3 at 034cdad1, app/igneum-app/src)
The Mac and Windows apps carry the prover (SP1 6.8.1 through igneum-prove-host), ON by default on an NVIDIA card of 23,552 MiB or
more (provedefault.rs:23-24; a 24 GB card reports 24,564), mining or not, on Linux or Windows with WSL2; OFF with the reason on 16 to
24 GB, under 16 GB, Windows under 32 GB RAM, Apple silicon, AMD-only; the prover refuses to start under 12 GB (provedefault.rs:31) and
a card under 12 GB holds the prover or the miner, never both (engine.rs:41, :2717). HiveOS: none (h-run.sh has no prover section);
the HiveOS prover is SCHEDULED as a 2.0.3.1 item beside snapshot sync (cut by 18:00 UK, the rule-33 canary on a 24 GB 4090 by
19:00). A 16 GB card proves no shard today: the floor 13,874 MiB for an empty shard and 15,670 beside the miner (provedefault.rs:8);
the v1 shard (30,000 pgas, 4.7 M cycles) 20,434 alone, 22,210 beside the miner; the devnet's prototype shards until the fee switch
at DAA 210,000 need 32 GB (28,307 alone, 30,039 beside; VRAM_MB_PROTOTYPE_SHARD 31,000, provedefault.rs:27, :135); aggregation
16,751 MiB with the miner (24 GB; prover.rs:1122); no smaller instance exists (provedefault.rs:9 open). The Hive package applies the
app's device.rs:63 mode table (Simultaneous at or above 23,552 MiB, ProveOnly, MiningOnly). Phase B therefore reads LIVE today only
on Windows and Mac where a 32 GB NVIDIA card is present, NOT LIVE on the 24 GB tier until DAA 210,000 and on HiveOS until the cut.
## Results of record, 13:0x UK
- THE DECIDER (COHORT, uncapped 5090 pod 55012544, 575 W default, driver 580.173.02, worker f5f3846c, 250 x 2^24, three runs
each, one session; build-1:/srv/artefacts/lab/ctl-v6-decider/vast-55012544/): the 4 GiB signing object 68.63 MH/s at 410.4 W =
5,979.9 nJ per hash, twin 4,806.2, f 0.804, spread 0.46 percent, fp b1f90e91cadb15b6 PASS; the same program at 2^28 (1 GiB)
70.63 MH/s at 414.7 W = 5,871.2 nJ (fp 01f51b9d4805e5e6); the research pack hl-v6-all as staged under tas/same-work-20261008-01
(program id 0x4de7b836cc40a4ea, not the l8off kit's 0x9d40978601a7df2a) 70.63 at 402.2 W = 5,694.8 nJ. VERDICT: the 4 GiB
object costs this worker 2.9 percent of rate and 1.8 percent of joules per hash against its own 1 GiB export; occupancy
identical (96 registers, 20 blocks per SM, 3,400 resident lanes per SM); reads 17.57 G per second at 4 GiB against 18.08 at 1
GiB. The 3.4 against 7.9 G reading was CONTROLS' instrument; withdrawn. The uncapped 5090 ctl-v6 cell: 5,979.9 nJ at stock =
3.88x (3.07 to 4.50) on set v2's same-node board; the 5090 knee stays the record's 2.60x.
- The TLB rows (CONTROLS, both cards, mode a4 at 118 loads, build-1:/srv/artefacts/lab/controls/frozen-v6/tlb/): the 4090 8.02 /
7.92 / 7.87 / 7.84 G reads per second at 1 / 2 / 4 / 8 GiB (26.07 to 26.81 nJ per read), the 5090 18.11 / 17.76 / 17.60 / 17.52
(19.11 to 19.77 nJ): a flat random stream loses 2 to 3 percent of rate from 1 to 8 GiB on either card, no cliff; the layer-8
windows at 2^30 touch the whole 4 GiB as a flat stream does; the live object's cost is the 2 to 3 percent page-walk margin.
- The 4 GiB cap defined (CONTROLS, 8c.10): the MINING DATASET floor and nothing else: docs/spec/01-lottery-hash.md lines 849 to
850 (4,096 MiB from genesis, one step, no later step; the dataset policy 70a6c703, register row 10; the cache 2^26 words, line
434); the proof-generation allocation carries no 4 GiB figure (proving/igneum-prove/host/src/memory_profile.rs TIERS lines 115 to
121: full 26 GiB free, 24gb 20 GiB, 16gb 14 GiB, small 0; the ELF manifest pins no memory line); the verifier is independent of the
dataset size (spec 01 line 702: at most 4,096 item derivations per unit from the 256 MiB cache; the F2 row 10.63 ms per warp);
the advertised hardware profile (docs/design/app-audit-2026-10-08.md row F8) is constrained only through the miner's resident set
pushing a co-resident prover into the small tier (memory_profile.rs line 117).
- ctl-progpow-094 at the live DAG (CONTROLS): the official CUDA kernel's mix digests at Ethereum epoch 871 (block 26,154,532, DAG
8,380,217,984 bytes) equal the CPU reference's on both nonces: F1 holds at the live size; the live rate on the rented 4090 at
stock 58.75 / 58.76 MH/s (0.96 TB/s of coalesced 256-byte entries) against 62.58 at the 1 GiB DAG: the live DAG costs 6 percent;
the by-construction read-only twin gpu/pp_twin built, rows queued; the KAWPOW live size (epoch 609, 6,182,403,712 bytes) queued.
- ctl-coop-arx on the 5090 (CONTROLS, stock, sm_120): 105.3 M units per second at 72 ops (1.72 TB/s, the DRAM ceiling; the twin
103.8), 14.32 at 1,032 and 3.66 at 4,104 (ALU-bound, equal to the 4090's 14.18 / 3.69); five chain lengths F1-complete (CHAIN 86
fingerprint 84f43aecf5d8a8cd on CPU and GPU).
- THE PROVING CORRECTION (PROVING LIVE and the release lane): the prototype-shard 32 GB clause (provedefault.rs) is Devnet 1's
(params.rs:3082 LIVE_13); Devnet 4 runs fees_v1_activation_daa 0 (params.rs:2307 on 27f54124; the node reports shardBudget
30,000 pgas), so a 24 GB NVIDIA card proves the v1 shard and aggregates beside its miner NOW (13,523 to 14,899 MiB peak beside
the miner on the fleet's 4090s, 117 to 120 s per 8-block segment, 0.99 to 1.88 IGN paid); on chain 4465 at tip 31,719 (11:50Z)
663 paid v1 segment records = 653.93 IGN to 30 prover keys; 0 segments proven in the last 600 blocks (payments paused since the
hub roll at about 11:00Z, the cause under fix). The proving row reads NOT LIVE "paid on Devnet 4 to 30 keys, epoch evidence
pending" until docs/analysis/class-v6/1p5x/lab/proving-live.md lands with one full epoch of paid rows (by 16:00). Phase B
therefore reads live today for the 24 GB tier on Mac and Windows once that record lands, and on HiveOS from the prover package's
entry (cut by 18:00); the 16 GB tier holds no shard.
- X10 pairs: the first 4090 pair carried valid v6 rows (8,692 nJ at 30.69 MH/s, f 0.859) and valid X10 rates (x10b 66.1 M
lane-works per second at 118 loads = the v6 pair's 30.69 x 256/118 within 1 percent: memory-bound exactly as v6; the x10b ladder
64 / 96 / 118 / 128 loads 122.1 / 81.3 / 66.1 / 60.9 M scales as 1/loads) but ZERO watts on every X10 row (the 40-batch default
ran a quarter second, under the sampler's 8 s warm-in); kit r3 (sha 323e3970) sizes the batches per variant (45 to 85 s), adds
cand-x10's fixtures and an x10b by-construction twin (-DX10B -DTWIN: the address rule kept, the fold one xor per loaded word,
the mix and shuffles removed; its address stream a dependent chain of the same count and width, named so in twin_addr), and the
driver refuses any row with watts 0.0 at staging; both pairs re-rented on uncapped 4090 and 5090. ADVERSARY's interim: the
Sector card from its rate at the pod's v6 watts, 4,039 nJ per lane-work MODELLED-from-rate (bounded below at about 3,470 by the
twin's ALU share), the cheapest DRAM board (650 nJ) 6.2x on the 4090 at stock.
- THE LEDGER ORDER (the founder, 12:5x UK; the LEDGER lane a101aa8329d1e82bf): the lab's lanes feed the GPU NETWORK LEDGER first:
every live GPU chain measured the same way on the same rented 4090 and 5090 in one session each (Igneum v6 at 4 GiB, KAWPOW via
ProgPoW 0.9.4 at the live DAG, FishHash, Etchash via the pinned chfast hashimoto at ETC's current DAG, Autolykos2 if the in-house
rule and the clock allow), the set v3 board ratio and the ProgPoW-premise ratio per chain, the two-phase rows with each chain's
actual split (only Igneum pays provers), the E9 Pro calibration line (ADVERSARY models the one real chip against Etchash; the gap
to its public rate and power stated as the model's calibration). COHORT's ledger session is renting (v6, FishHash full and twin,
ProgPoW 1 GiB class now; the live-DAG binary pp_harness_26154532 from CONTROLS pulled in if it lands in time, else a second short
session); CONTROLS' Etchash harness is built and F1-checked against chfast at blocks 0 and 12,750,000 (ETC epoch 425). The ledger
table on the record at docs/analysis/class-v6/1p5x/ledger/README.md 15:30, the kit 16:30, the page 17:30; the registry cell
ledger:cross-chain beside lab:candidate on R15-09, NOT RUN until the kit's rows reproduce. The candidate search continues
fail-closed at lower priority (the 520k-ALU point and the headroom row close their records; no new families).
- The 4090 decider CLOSED (CONTROLS, one quiet session, stock, the 4 GiB signing pack): the kit zip 4 worker f5f3846c 30.661 MH/s
at 20 x 2^22 and 30.693 at 50 x 2^24; the build-1 worker 804a6f7f 30.663 and 30.692 on the same pack and shape; the 1 GiB
research pack 31.313: the two builds are the same instrument to four figures, the batch shape moves nothing, the live 4 GiB
object costs the 4090 2.0 percent of rate (3 percent on the 5090); the 13.16 was the shared-card read, withdrawn
(build-1:/srv/artefacts/lab/controls/frozen-v6/decider-4090.log). ctl-progpow-094's by-construction twin on the 4090: 77.42 MH/s
at the 1 GiB DAG and 60.20 at the live 8.38 GB DAG against the full kernel's 62.58 and 58.75: at the live size the card is at
its memory limit (the ALU hidden under the reads). ctl-fishhash on the 5090: F1 PASS (fingerprint f841605125ce375e equal to
the 4090's), 45.37 MH/s full against 39.71 for the twin (19.73 / 17.75 on the 4090). The F2 row re-run on the same pinned core:
10.440 ms per warp for the signing object at 2^30, 5.134 for the class v4 calibration (frozen-v6/f2-verifier-build5.txt).
- CONTROLS' done line (13:0x to 13:1x UK): the four controls and the ledger rows staged under build-1:/srv/artefacts/lab/controls/
with SHA256SUMS (frozen-v6 with tlb/, coop-arx, progpow-094, fishhash, sector-read, etchash, autolykos; 25 MB). Autolykos2 landed
in-house and bit-exact (hashlib reference against the CUDA harness at N = 65,536 and at Ergo's live N = 227,251,815, 7.27 GB;
216.2 / 201.8 MH/s full / twin on the rented 4090; the live-block end-to-end row owed). coop-arx's OpenCL text F1-complete on two
OpenCL platforms at all five chain lengths (the AMD tier runs the moment a card is reachable; Metal owed). Open on that lane: the
knee rows (every rented pod refuses the lock; COHORT's VM-host lock hunt reports by 14:30), the Metal text, the Ergo live-block row.
- ADVERSARY (12:5x to 13:0x): phase B tier rows on the on-chain read (commit 82330b04c; 47f16b86f with Etchash on the mirror): the
24 GB-and-up NVIDIA tier on Windows and Mac LIVE on Devnet 4 and out-earning the board chip in phase B (the GPU's contribution per
TH after electricity 0.341 against the chip's 0.288 after its recurring cost at ten cents on the flat path); HiveOS NOT LIVE until
the 2.0.3.1 package; the 16 GB tier never (mining share only, 0.046 per TH behind the chip). ctl-etchash as a control (64 x 128 B
reads over about 3.3 GB) with the calibration line: the modelled DRAM board 765 nJ per hash against the shipped Antminer E9 Pro's
598 (3,680 MH/s at 2,200 W, the public figure as the ledger lane quotes it): the model 1.28x pessimistic for the chip, a witness.
Phase A and B for Ravencoin, Ethereum Classic and Iron Fish in their own units (commit d7db3e596, README section 14): no fleet
recovers a board chip's spend on any of the three on any path (each chain's 24-month mining emission under one design cost: RVN
about USD 2.9 M, IRON 1.4 M, ETC 83 M at a 10,000-board fleet); phase B with no prover income: on Ravencoin the chip's operating
advantage stands in full at USD 0.123 per TH; on ETC the mining revenue per TH (0.0087) is below the board's recurring cost (0.031)
and the E9 Pro's electricity alone (0.017), a loss on both sides at ten cents. The reading: on every chain in the set the board
chip's phase B advantage is real and its phase A recovery is not at today's emissions; the proving share is the one term that lets
Igneum's live GPU tier out-earn the chip in phase B.
- The boxes (the build steward, 13:1x): the lab's ended box runs' pid files removed as stale after each pid's command line was read
dead; the steward's defaults on build-4, build-5 and build-6 stand until a lane claims with a live pid file.
- THE 4090 DECIDER (COHORT 13:10, uncapped pod 55012546, 450 W default, driver 570.172.08, worker f5f3846c, 250 x 2^24, three
runs each, one session; build-1:/srv/artefacts/lab/ctl-v6-decider/vast-55012546/): the 4 GiB signing object 31.52 MH/s at
275.1 W = 8,728.3 nJ per hash, twin 7,398.0, f 0.848, spread 1.06 percent, fp PASS; the same id at 2^28 32.14 MH/s = 8,600.1
nJ; the research pack 32.15 = 8,448.2; occupancy identical (88 registers, 20 blocks per SM). CLOSED on both denominator cards:
the 4 GiB set costs 2.0 (4090) and 2.9 (5090) percent of rate and 1.5 to 1.8 percent of joules; reads 8.07 G per second at 4 GiB
against 8.23 at 1 GiB; the batch-shape question closed by CONTROLS' own pair (20 x 2^22 and 50 x 2^24 equal to four figures), so
no fix pair exists to measure. The uncapped 4090 ctl-v6 cells: 8,369 / 8,692 / 8,728 / 8,751 nJ over four pods (host spread 4.5
percent, drivers 570 to 595): the scoreboard's 4090 figure is the median 8,710 with the spread, the worst cell 8,751 = 5.67x.
- Autolykos2 priced on set v3 (ADVERSARY 13:1x, README section 15): the same-node board 198 nJ (172 to 249) = 5.8x on the 4090 at
stock from CONTROLS' 216.2 MH/s at 250 W claimed (MODELLED-from-rate until COHORT's session row); the die on four reticles 46
nJ (25x); premise 1.01x; phase A no recovery on any path (Ergo's 24-month mining emission about USD 0.6 M); phase B mining only,
the chip's advantage USD 0.024 per TH standing in full.
- SEARCH handed build-9 back (batches 1 and 2 done and exported); its measurements continue on the rented 4090 (x10b 64-load,
alu-520k, the v6x2 pair, batch 2's self-tests); row folders at build-1:/srv/artefacts/lab/rows/lab-search-4090-pod/ with SUMS;
the lane record docs/analysis/class-v6/1p5x/lab/search/README.md on branch lab-search.
- The "no emergency intervention" row (8g): Devnet 4 on finality rule v3, paused since lock 1980, the chain on PoW through the
pause, nothing certified reversed, proving unaffected once the finality gate on provers was lifted; the first new lock expected
15:30 to 17:00 UK; the vote key label-derived (no key file).
- THE 520k CELL CLOSED (SEARCH 13:2x, the rented 4090 at stock, fixtures 9 of 9 PASS, 97 registers, no spills, two passes):
cand-x10 variant alu-520k 15.8 M lane-works per second at 351 to 366 W = 22,152 and 23,225 nJ per lane-work (709 to 743 uJ per
digest) against the frozen v6's 8,594 nJ per hash in the same session: 2.6x to 2.7x v6's joules per unit, the P03 10 percent
budget failed by 160 percent (about 42 pJ per instruction on this text; the 41,536 shuffles per lane-work at the card's dearest
family); set v3's 1.03x (the card assumed equal to v6) scales to about 2.7x on this cell. REJECTED (F4). NO MEASURED OR SCREENED
CELL ON ANY CARD SITS UNDER 1.5x ON THE SAME-NODE BOARD after the X10 family, the twenty search candidates and the four controls;
the best cell is the frozen v6 on the 5090 at its knee, 2.60x (2.06 to 3.02), WITNESS, set v2 and v3.
- 8c.8 CLOSED: the v6x2 confirming row (two lane-hashes per thread, fingerprint equal) 30.697 against 30.697 MH/s, 8,574 against
8,594 nJ (-0.2 percent); fifteen headroom cells flat at 7.85 to 7.86 G reads per second against the memprobe ceiling 8.1: the 4090
is at its bound. cand-x10b at 64 loads 122.2 M lane-works per second = 1,993 and 2,020 nJ per lane-work (31.1 nJ per read).
- A LOCKABLE RENTED HOST (COHORT 13:23): Vast VM offers (KVM, GPU passthrough, the driver in the guest) hold -lgc; the 4090 VM
55018643 (driver 575.51.03) locked 0 to 1,500 and restored; the five-chain ledger session runs there at stock and at the knee the
recipe picks from a clock ladder (1,200 to 1,900); the 5090 VM at the record's 1,300 once it boots; the stock sessions mid-run on
the uncapped containers 55017318 (4090) and 55018470 (5090). The scoreboard's claim column gets measured knee rows on rented
cards for every chain today.
## Open rows (NOT RUN)
| row | owner | clock |
|---|---|---|
| the card's random-read headroom per cohort card against its memory-timing bound and the chip's 148 MH/s (8c.8) | COHORT with CONTROLS | this afternoon with the scoreboard |
| the two-phase coexistence rows, the revenue column, the used-card column, the growth-scaled new buyer, the exact meeting tariff per row (8c.2 to 8c.7) | ADVERSARY | this afternoon |
| the 4 GiB proving cap defined precisely (8c.10) | CONTROLS (the definition), ADVERSARY (the economics) | this afternoon |
| the comparative review of what other GPU chains publish on chip resistance (8c.9) | unassigned; NOT RUN until done | none |
| the units rule in every control's contract (revenue per accepted work in the algorithm's own units) | CONTROLS | with each pin |
| the founder's bundle (8d) | LAB | 14:00 |

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# The GPU network ledger (the 1.5x laboratory, LEDGER lane, 9 October 2026)
Every live GPU-mined chain the lab could pin, measured the same way on the same rented cards in the same sessions, with the same
adversary method applied to each, ranked on (a) the same-node chip-to-GPU energy edge under the lab's convention, (b) the same
under ProgPoW's own premise, and (c) the two-phase economics with each chain's ACTUAL reward split (only Igneum pays a share of
every block to provers). Every number is MEASURED or WITNESS with its source on the row; a number that does not exist yet reads
"pending" with the lane that owes it, never blank; a chain the lab could not run in-house reads NOT RUN with the reason.
The data lives in `ledger.json` beside this file; every table here, on the public page (`docs/ledger/gpu-ledger.md`, served at
/gpu-ledger) and in the reproduction kit is rendered from it by `tools/ledger/render.mjs`, so no two copies of a row can drift.
The public page carries the same tables with less of the lane bookkeeping.
<!-- ledger:stamp:start -->
Data: ledger.json, stamp 2026-10-09, adversarial set v3 (build-1:/srv/artefacts/lab/adv/ (README.md, design-notes/adversarial-sets-v1-v2-v3.md, rows/, SHA256SUMS); set v3 commit b2b9ee0b9 on class-v6-adversary).
<!-- ledger:stamp:end -->
## 1. The method (the same for every chain)
1. **The object.** Each chain's proof of work as its own pinned reference code, built in-house from source (the in-house rule: no
downloaded miner binary; the CONTROLS lane's pins with commit ids and sha256s on build-1 under /srv/artefacts/lab/controls/).
Igneum: the frozen class v6 at the live 4 GiB dataset. Ravencoin: the official ProgPoW 0.9.4 reference kernel (KAWPOW is
ProgPoW 0.9.4 with Ravencoin's constants, so the official kernel at Raven's DAG size is a labelled PROXY). Firo: the same row
(FiroPoW differs from KAWPOW in its constants only). Iron Fish: the FishHash reference library and a bit-exact CUDA port. Ethereum
Classic: the ethash hashimoto of the pinned chfast/ethash library at ETC's current epoch. Ergo: NOT RUN (the reason on the row).
2. **The card rows** (the COHORT lane, the lab's measurement recipe, interface section 1): one rented RTX 4090 and one rented RTX
5090, both on uncapped hosts, every chain back to back in ONE session per card at stock; board power from `nvidia-smi` at 1 Hz
(the mean from 8 s in to the end, idle not subtracted); the rate from the harness's own counter; nJ per hash = W / MH/s x 1,000;
three timed runs per cell, the median served with the spread; `clocks_sm_median` and the dataset size on every row; the
read-only twin (the same reads, the arithmetic cut) where the harness has one, giving f = J_twin / J_full, the card's memory
share. Rented containers refuse clock locks, so every row is stock; the Igneum knee rows exist only in the record.
3. **The chip rows** (the ADVERSARY lane, adversarial set v3): for each chain the cheapest credible specialist on the same node, a
complete machine (die, memory, board, PSU and host terms), modelled and labelled WITNESS; the same-node DRAM board is the energy
row, the SRAM die the residual (coexistence) row. Two conventions beside every ratio: **ours** (the cheapest programmable core,
fused where the work allows, register file sized to the work, instruction convention) and **ProgPoW's premise** (the chip must
keep a GPU-class datapath, so its edge is the compute term's 1.1x to 1.2x weighted by the card's measured memory share f).
4. **The real chip.** Ethereum Classic is the one chain on the ledger with a chip on the market, the Antminer E9 Pro; its public
rate and power go on the row as a WITNESS and the modelled DRAM board for Etchash goes beside it as the model's calibration
line: the row says how close the model's ratio sits to the ratio from the public figures.
5. **The two phases** (the lab's rulings 8c.5 and 8c.11): phase A, can a chip maker recover its spend before investment under
growing, flat and falling price paths; phase B, with the spend sunk, who exits first on operating cost, with the chain's actual
reward split: a GPU on Igneum earns the mining share plus the proving share (80 / 20 ratified), a hash chip the mining share
only; on every other chain the GPU's share is mining only (100 / 0), so the second-income term is zero by construction.
6. **The ranking rule.** Rank (a) ascending on the same-node DRAM board ratio under our convention at the WORSE of the two cards
(the lower ratio is the smaller chip edge); (b) ascending on the ProgPoW-premise ratio at the same cell; (c) phase B: whether
the chain's GPUs earn an income a hash chip cannot. A chain with any pending or proxy cell in a column is ranked provisionally
in that column and says so; a NOT RUN chain is unranked. PASS is never written; the ranking is the rows' order, nothing more.
## 2. The card rows (MEASURED; board power; stock)
<!-- ledger:cards:start -->
| chain | algorithm | dataset on the row | reward split (mining / proving) | RTX 4090 stock: nJ per hash (MH/s, W, f) | RTX 5090 stock: nJ per hash (MH/s, W, f) | twin | sources |
|---|---|---|---|---|---|---|---|---|
| Igneum | class v6, the live signing object 0x2a1d6caab4c24564 (2.0 devnet, chain id 4465) | 4.29 GB (4,294,967,296 bytes); 2^30 words, the live policy (70a6c703); 256 random 4-byte reads per hash, 62,120 instructions per hash (instruction convention) | 80 / 20 (the Token Value volume on master (D04, token-value/README.md: the 80/20 emission allocation); PROVING_POOL_SHARE_PERCENT) | 8,369 MEASURED (30.67 MH/s, 256.7 W, f 0.848; spread 0.67%; vast 55009211, driver 580; stock (the pod refused -lgc); clocks_sm_median pending the ledger session) | 5,597 MEASURED (68.66 MH/s, 384.3 W, f 0.811; spread 2.11%; vast 55006481, driver 580; stock (the pod refused -lgc); the host cap 500 W, the card drew 384) | yes (the same address stream, the arithmetic cut) | RTX 4090: build-1:/srv/artefacts/lab/ctl-v6/vast-55009211/ (rows.jsonl, SHA256SUMS); the cohort table build-1:/srv/artefacts/lab/cohort/TABLE.md; RTX 5090: build-1:/srv/artefacts/lab/ctl-v6/vast-55006481/; the cohort table build-1:/srv/artefacts/lab/cohort/TABLE.md |
| Ravencoin | KAWPOW (ProgPoW 0.9.4 with Ravencoin's kiss99 constants, 7,500-block epochs and a 512-parent DAG; live since block 1,219,736, 6 May 2020) | 6.18 GB (6,182,403,712 bytes); KAWPOW's current DAG size at Ravencoin height 4,573,707 (epoch 609, read 13:0x UK): the official ProgPoW 0.9.4 kernel built at Ethash block 18,270,000 (epoch 609, the same byte count), harness progpow-094/gpu/pp_harness_18270000; KAWPOW's own constants NOT applied, so the row is 'ProgPoW 0.9.4 official at KAWPOW's DAG size (proxy)'; 64 coalesced 256-byte reads per hash; F1 GPU = CPU on both nonces (cpu/vectors-094-kawpow-size-18270000.txt) | 100 / 0 (Ravencoin's block reward goes to the miner in full (no second income to GPUs)) | 6,920 MEASURED (prior row: kawpowminer, not the pinned kernel; a PROXY until the ledger session's pinned-kernel row lands) (58.95 MH/s, 409.0 W, f none; spread none; RunPod, the comparative lane a2ed5c31; stock) | pending: pending (COHORT, the ledger session) | yes, by construction (progpow-094/gpu/pp_twin 18270000 26 250: the 64 dependent entry reads per 16-lane hash) | RTX 4090: build-1:/srv/artefacts/lab/adv/rows/rows.md (the ctl-progpow-094 section, card rows) |
| Firo | FiroPoW (ProgPoW 0.9.4 with Firo's constants; live since block 419,264, 26 October 2021) | = Ravencoin's row | 100 / 0 | = Ravencoin's row | = Ravencoin's row | as Ravencoin | as KAWPOW: the pinned ProgPoW 0.9.4 reference; FiroPoW differs from KAWPOW only in its constants and DAG schedule, so the lab serves ONE row for both and says so |
| Iron Fish | FishHash (live since hardfork 1, April 2024) | 4.83 GB (4,831,835,776 bytes); 37,748,717 items of 128 bytes, FIXED (no epochs); 96 random 128-byte reads per hash, 9,856 lane-instructions | 100 / 0 (Iron Fish's block reward is mining only) | pending: pending (COHORT, the ledger session); CONTROLS' rate-only read 19.73 MH/s at stock, no sampler (rate only 19.73 MH/s) | pending: pending (COHORT, the ledger session); CONTROLS' rate-only sm_120 read 45.37 MH/s full, 39.71 twin, F1 PASS (rate only 45.37 MH/s) | yes (a trace replay of the kernel's own item indexes; its energy read as a bound: the twin runs 10 percent slower than the full kernel) | RTX 4090: build-1:/srv/artefacts/lab/controls/fishhash/gpu/bench-4090.log; RTX 5090: build-1:/srv/artefacts/lab/controls/fishhash/ (fishhash.md) |
| Ethereum Classic | Etchash (Ethash with ECIP-1099's 60,000-block epochs; live since block 11,700,000, November 2020) | 4.64 GB (4,638,898,816 bytes); ETC height 25,502,946 (read 12:5x UK) = Etchash epoch 425 (ECIP-1099: height / 60,000), the harness's block argument 12,750,000 (the Ethash epoch with the same size table index); 64 coalesced 128-byte reads per hash (two 64-byte half-mixes); CONTROLS' rate-only read on a 4090 at stock 29.90 MH/s full and 29.90 twin (memory-bound) | 100 / 0 (ETC's block reward is mining only) | pending: pending (COHORT, the ledger session; the harness staged 13:0x UK); CONTROLS' rate-only read 29.90 MH/s (rate only 29.90 MH/s) | pending: pending (COHORT, the ledger session; the sm_120 build from etchash/src) | yes, by construction | RTX 4090: build-1:/srv/artefacts/lab/controls/etchash/ (etchash.md) |
| Ergo | Autolykos2 (k = 32, n = 26, Blake2b-256; the table grows 5 percent every 51,200 blocks) | 7.27 GB (7,272,058,080 bytes); the live table at Ergo height 1,890,820 (api.ergoplatform.com, 13:0x UK): N = 227,251,815 elements of 32 bytes (+5 percent at height 1,894,400; the row names its height); 33 random 32-byte reads per hash; the table builds on the device in 1.5 s; CONTROLS' rate-only read on a 4090 at stock 216.2 MH/s full, 201.8 twin | 100 / 0 (Ergo's block reward is mining only) | pending: pending (COHORT, the ledger session; the harness staged 13:1x UK); CONTROLS' rate-only read 216.2 MH/s full, 201.8 twin (rate only 216.20 MH/s) | pending: pending (COHORT, the ledger session; the sm_120 build from src) | yes (a trace replay) | RTX 4090: build-1:/srv/artefacts/lab/controls/autolykos/ (autolykos.md) |
<!-- ledger:cards:end -->
## 3. The chip-to-GPU edge, both conventions (WITNESS chip rows over MEASURED card rows)
<!-- ledger:edge:start -->
| chain | the cheapest credible same-node DRAM board (set v3, nJ per hash, band) | ratio at the RTX 4090 stock (ours) | ratio at the RTX 5090 stock (ours) | ProgPoW-premise ratio at the RTX 4090 | ProgPoW-premise ratio at the RTX 5090 | the die as the residual (nJ; ratio at the worse card) | real chip on the market | source |
|---|---|---|---|---|---|---|---|---|
| Igneum | 1,542 (1,329 to 1,941); GDDR7 board + register file sized to the work + fused operations, N5; split memory 527 / ALU 166 / tax 849; WITNESS (modelled, complete machine, instruction convention) | 5.43x (4.31 to 6.30) | 3.63x (2.88 to 4.21) | 1.01x to 1.03x (f 0.853 measured) | 1.02x to 1.03x (f 0.811 measured on the stock pod) | 335 (N2 full-SRAM die, the coexistence row); 25.0x | none on the market | docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f); build-1:/srv/artefacts/lab/adv/rows/ctl-v6.json and rows.md (set v3, 2026-10-09T11:33Z); the die 12.0x at the 5090 knee, USD 0.77 per MH/s |
| Ravencoin | 1,757 (1,453 to 2,147); GDDR7 board + register file sized to the work + fused operations, N5; bandwidth-bound at 16 KB per hash (93 MH/s per board); split memory 647 / ALU and tax per rows.md; WITNESS (modelled on the kawpowminer census as the work proxy until CONTROLS' trace replaces it) | 3.94x (3.22 to 4.76) | pending | 1.10x to 1.20x (the premise's own figure; no measured twin on this kernel yet) | 1.10x to 1.20x (the premise's own figure; the twin row makes it measured) | 697 (N2 full-SRAM die, the coexistence row (USD 1.89 per MH/s); the cheapest specialist of any kind is near-memory base dies at 669 nJ); 9.9x | none on the market | docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f); build-1:/srv/artefacts/lab/adv/rows/ctl-progpow-094.json (set v3) |
| Firo (= Ravencoin's row) | 1,757 (1,453 to 2,147); GDDR7 board + register file sized to the work + fused operations, N5; bandwidth-bound at 16 KB per hash (93 MH/s per board); split memory 647 / ALU and tax per rows.md; WITNESS (modelled on the kawpowminer census as the work proxy until CONTROLS' trace replaces it) | 3.94x (3.22 to 4.76) | pending | 1.10x to 1.20x (the premise's own figure; no measured twin on this kernel yet) | 1.10x to 1.20x (the premise's own figure; the twin row makes it measured) | 697 (N2 full-SRAM die, the coexistence row (USD 1.89 per MH/s); the cheapest specialist of any kind is near-memory base dies at 669 nJ); 9.9x | none on the market | = Ravencoin's row |
| Iron Fish | 1,051 (881 to 1,257); GDDR7 board + register file sized to the work + fused operations, N5; bandwidth-bound at 124 MH/s per board; 95 percent of the board's energy is the memory path; split memory 529 / ALU 46 / tax 503; WITNESS (modelled; the card's cell pending, so the ratio is pending) | pending | pending | pending (needs the measured f from the twin) | pending | 170 (full SRAM dies (three N2 reticles) + sized + fused operations); pending | none on the market | build-1:/srv/artefacts/lab/adv/rows/ctl-fishhash.json and rows.md (set v3) |
| Ethereum Classic | 765 (638 to 919); GDDR7 board + register file sized to the work + fused operations, N5; USD 3.25 per MH/s; split per ledger-rows.md; WITNESS (modelled; the card cells pending, so the ratios are pending) | pending | pending | 1.10x to 1.20x (the premise's own figure; the twin row makes it measured) | 1.10x to 1.20x (the premise's own figure) | 177 (N2 full-SRAM die, the coexistence row); pending | Bitmain Antminer E9 Pro: 3,680 MH/s at 2,200 W = 598 nJ per hash, WITNESS (a manufacturer's published figure, not measured by the lab); Bitmain's stated figures as listed on minerstat's hardware page (https://minerstat.com/hardware/antminer-e9-pro): 3.68 GH/s on Ethash at 2,200 W, release 2023-02; 2,200 W / 3,680 MH/s = 0.598 J per MH = 598 nJ per hash | docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f, wording 82330b04c) |
| Ergo | pending: pending (ADVERSARY: the chip rows from CONTROLS' trace; default 15:00 UK, else pending (adversary)) | pending | pending | pending | pending | pending | none on the market | pending |
<!-- ledger:edge:end -->
## 4. The two phases with each chain's actual split
<!-- ledger:phases:start -->
| chain | split | phase A (before investment) | phase B (spend sunk) | an income a hash chip cannot earn | source |
|---|---|---|---|---|---|
| Igneum | 80 / 20 | before investment (24 months, the mining share 80 percent of the year-1 subsidy): the same-node board maker recovers its spend on NO fleet from 100 to 100 M boards on the growing or flat price path (100,000 boards: net USD -55.4 M on 58.8 M revenue growing; -37.6 M on 76.6 M flat); only the falling path pays it; the N2 die recovers on no path | spend sunk, flat path at USD 0.10 per kWh, the chip at 10 percent of the hash: mining revenue USD 0.354 per TH; the GPU's proving income at the ratified 20 percent share USD 0.098 per TH against the board chip's operating advantage USD 0.046 per TH (GPU electricity 0.111 less the chip's electricity, hosting and maintenance 0.066): the GPU out-earns the built board chip; the cancelling proving share 9 percent (board), 13 (hybrid), 20 (die) | yes by rule (the proving share of every block, 20 percent ratified); LIVE ON DEVNET with on-chain paid records (663 paid v1 segment records to 30 prover keys on chain 4465, the PROVING LIVE lane's file bd3f53c1 on build-1), not yet in a shipped package | build-1:/srv/artefacts/lab/adv/rows/rows.md (the two-phase section), ADVERSARY commit 545f3f8a0; ctl-v6-coexistence.json; WITNESS; phase B NOT LIVE until a shipped package runs a prover |
| Ravencoin | 100 / 0 | before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path, because Ravencoin's whole mining emission over 24 months (about USD 2.9 M at the public price) sits below one USD 35 M design cost; 10,000 boards would take 56 percent of the 721 GH/s network and earn USD 1.6 M to 2.4 M against a USD 44 M spend | spend sunk, mining only: mining revenue USD 0.064 per TH of the chain's own hashes; the board chip's recurring cost USD 0.069 per TH at ten cents; the chip's operating advantage over the RTX 4090 at stock (6,920 nJ) USD 0.123 per TH (the GPU's electricity 0.192 less the chip's 0.069) stands in full, no prover income | no (the block reward is mining only) | docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-progpow-094-coexistence.json (rows[].phase_a, rows[].phase_b_split; method lab/adv/README.md section 14), ADVERSARY commit d7db3e596 on class-v6-adversary; WITNESS, the chain's own units, the 100/0 split, the same 24-month life, design cost and fleet rule as v6, the three price paths (flat at the public price, x2 growing, x0.5 falling, the hash held); the public lines on the row |
| Firo | 100 / 0 | as KAWPOW | as KAWPOW | no | as KAWPOW; = KAWPOW's row at a 100/0 split |
| Iron Fish | 100 / 0 | before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path; Iron Fish's whole mining emission over 24 months is about USD 1.4 M at the public price (10,000 boards would take 84 percent of the hash for USD 1.1 M to 1.6 M) | spend sunk, mining only: mining revenue USD 0.086 per TH of the chain's own hashes; the board chip's recurring cost USD 0.043 per TH at ten cents; the GPU side NOT RUN until the card cell lands; no prover income by construction | no | docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-fishhash-coexistence.json, ADVERSARY commit d7db3e596 on class-v6-adversary; WITNESS, the chain's own units, the 100/0 split, the same life, design cost, fleet rule and price paths as v6; the GPU side of phase B NOT RUN until COHORT's card rows |
| Ethereum Classic | 100 / 0 | before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path; ETC's whole mining emission over 24 months is about USD 83 M at the public price, but 10,000 boards are 2 percent of 120.9 TH/s and earn USD 1.0 M to 1.5 M, and 100,000 boards (13 percent) USD 9 M to 13 M against a USD 150 M spend | spend sunk, mining only: mining revenue USD 0.0087 per TH of the chain's own hashes, below even the modelled board's recurring cost (USD 0.031 per TH) and below the E9 Pro's own electricity at ten cents (598 nJ = USD 0.017 per TH): at the public figures nobody mines ETC at a profit at ten cents and phase B is a loss on both sides; the GPU side NOT RUN until the card cell lands | no | docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-etchash-coexistence.json, ADVERSARY commit d7db3e596 on class-v6-adversary; WITNESS, the chain's own units, the 100/0 split, the same life, design cost, fleet rule and price paths as v6; the GPU side of phase B NOT RUN until COHORT's card rows |
| Ergo | 100 / 0 | pending (ADVERSARY) | pending (ADVERSARY); no prover income by construction | no | pending; pending (ADVERSARY at the 100/0 split, the public line on the row) |
<!-- ledger:phases:end -->
## 5. The ranking
<!-- ledger:ranking:start -->
**(a) Ours, the same-node DRAM board at the worse card (the smaller chip edge first):**
No order in this column yet: a cross-chain comparison is made only between cells from the same card, state and session, and the measured cells today come from 2 sessions (lab-cohort-ctl-v6 (COHORT, 11:49 to 12:30 UK, one chain); comparative-lane a2ed5c31 (RunPod, one chain, an earlier session)); the ledger session (both cards, every chain back to back) fills it. Each chain's own number, same card and state, as it stands:
- Igneum: RTX 4090 stock 5.43x (4.31 to 6.30); RTX 5090 stock 3.63x (2.88 to 4.21)
- Ravencoin: RTX 4090 stock 3.94x (3.22 to 4.76); RTX 5090 stock pending (a pending or proxy cell in this row)
- Iron Fish: unranked in this column (no measured card cell yet)
- Ethereum Classic: unranked in this column (no measured card cell yet)
- Ergo: unranked in this column (no measured card cell yet)
**(b) ProgPoW's premise (the chip keeps a GPU-class datapath):**
- Igneum: RTX 4090 1.01x to 1.03x (f 0.853 measured); RTX 5090 1.02x to 1.03x (f 0.811 measured on the stock pod)
- Ravencoin: RTX 4090 1.10x to 1.20x (the premise's own figure; no measured twin on this kernel yet); RTX 5090 1.10x to 1.20x (the premise's own figure; the twin row makes it measured)
- Iron Fish: RTX 4090 pending (needs the measured f from the twin); RTX 5090 pending
- Ethereum Classic: RTX 4090 1.10x to 1.20x (the premise's own figure; the twin row makes it measured); RTX 5090 1.10x to 1.20x (the premise's own figure)
- Ergo: RTX 4090 pending; RTX 5090 pending
**(c) Phase B, an income a hash chip cannot earn:**
- Igneum: yes by rule (the proving share of every block, 20 percent ratified); LIVE ON DEVNET with on-chain paid records (663 paid v1 segment records to 30 prover keys on chain 4465, the PROVING LIVE lane's file bd3f53c1 on build-1), not yet in a shipped package
- Ravencoin: no (the block reward is mining only)
- Firo: no
- Iron Fish: no
- Ethereum Classic: no
- Ergo: no
<!-- ledger:ranking:end -->
## 6. The claim under test, clause by clause
The sentence the ledger was ordered to carry, in exactly these words and nothing stronger, is served as the claim UNDER TEST with
each clause labelled by its state on the current rows; it reads as established only when every clause is SUPPORTED. The fifth
review's ruling stands (interface 8c.9): a comparative sentence needs the comparative row, and this ledger is that row.
<!-- ledger:claim:start -->
**The headline, built from the supported clauses only:** under ProgPoW's own convention, the lowest measured chip-to-GPU edge of the chains on this ledger; and the only chain on this ledger whose GPUs are paid, by rule, an income a hash chip cannot earn (LIVE ON DEVNET, on-chain records (the PROVING LIVE lane, read 11:50:22Z 9 October 2026): on chain id 4465 (the Igneum 2.0 devnet) 663 paid v1 segment records (8 shards plus aggregation each) = 653.93 IGN paid from the proving pool to 30 distinct prover keys across chain blocks 3,000 to 30,687 (tip 31,719 at the read), plus 6,474 paid v0 shard records = 7,196 IGN; read by igneum_getProvingStatus, igneum_getSegmentRecords (3,965 segments) and igneum_getSegment; evidence build-1:/srv/artefacts/proving-live/prov-ledger-4465-tip31719-115022Z.json sha256 bd3f53c18c3ffa20354ea62ade9fd5e7a5794202a71c3c369a5be71484f7143a. NOT YET LIVE IN A SHIPPED PACKAGE: the payees are the fleet's prover stack (the same binaries the 2.0.3.1 HiveOS package wraps, cut 18:00 UK); the apps' prover is on by default on 24 GB cards but no app-proved record is on the record yet; a full-epoch line follows by 16:00 UK).
The sentence as ordered, served as the claim under test: "the lowest measured chip-to-GPU edge of any live GPU network under a published method, on both conventions, and the only one whose GPUs earn income a chip cannot"
Rule: the headline reads only what the like-for-like rows support, clause by clause (main's ruling, 13:2x UK 9 October 2026); under the ledger's own convention the measured edge per chain on the same card and state is stated as numbers, with no ranking word until the rows say so after the ledger session.
| clause | convention | state on the current rows | why |
|---|---|---|---|
| under ProgPoW's own convention, the lowest measured chip-to-GPU edge of the chains on this ledger | ProgPoW's premise (a chip that keeps a GPU-class datapath) | SUPPORTED on the current rows | Igneum v6 1.01x to 1.03x (its measured f 0.81 to 0.85) against ProgPoW's own 1.10x to 1.20x for KAWPOW and FiroPoW; FishHash and Etchash pending their twins |
| under the ledger's convention (the cheapest credible programmable specialist, adversarial set v3), each chain's measured edge on the same card and state, as numbers | ours | NUMBERS ONLY; no ranking until the ledger session (COHORT, both cards, every chain back to back, the pinned 0.9.4 kernel, twins; 14:45 UK) | the current cells come from different sessions (the lab's cohort pods for v6, the comparative lane's pod for KAWPOW) and a cross-chain comparison is made only between cells from the same card, state and session; at the RTX 4090 at stock the cells read v6 5.4x (5.67x on the second pod) and KAWPOW 3.9x (a proxy row from an earlier session); FishHash and Etchash pending |
| and the only chain on this ledger whose GPUs are paid, by rule, an income a hash chip cannot earn | phase B, each chain's actual reward split | LABELLED BY THE PROVING LIVE LANE | the proving share (20 percent ratified) is paid to GPUs for work a hash chip cannot do; every other chain on the ledger pays mining only; the live state of that income is the PROVING LIVE lane's evidence line |
Withdrawn: the earlier line 'KAWPOW and FiroPoW read 5 to 6x on the measured 4090 rows and v6 reads 2.35x' is withdrawn: it compared v6 at the 5090's 1,300 MHz knee with KAWPOW at the 4090 at stock, two cards and two states; the like-for-like cells are the ones on this ledger.
The last clause's label from the PROVING LIVE lane: LIVE ON DEVNET, on-chain records (the PROVING LIVE lane, read 11:50:22Z 9 October 2026): on chain id 4465 (the Igneum 2.0 devnet) 663 paid v1 segment records (8 shards plus aggregation each) = 653.93 IGN paid from the proving pool to 30 distinct prover keys across chain blocks 3,000 to 30,687 (tip 31,719 at the read), plus 6,474 paid v0 shard records = 7,196 IGN; read by igneum_getProvingStatus, igneum_getSegmentRecords (3,965 segments) and igneum_getSegment; evidence build-1:/srv/artefacts/proving-live/prov-ledger-4465-tip31719-115022Z.json sha256 bd3f53c18c3ffa20354ea62ade9fd5e7a5794202a71c3c369a5be71484f7143a. NOT YET LIVE IN A SHIPPED PACKAGE: the payees are the fleet's prover stack (the same binaries the 2.0.3.1 HiveOS package wraps, cut 18:00 UK); the apps' prover is on by default on 24 GB cards but no app-proved record is on the record yet; a full-epoch line follows by 16:00 UK
<!-- ledger:claim:end -->
## 7. The reproduction kit
build-1:/srv/artefacts/ledger/<stamp>/ (the stamp and the sha256 of the kit on the row below when it lands): the pinned controls
(the frozen v6 pack and twin, the ProgPoW 0.9.4 reference harness, the FishHash harness, the Etchash harness when staged), the
gen-6 Igneum worker, the lab's sampler and session script, the chain references by commit and sha, SHA256SUMS, and a README with
one command per card and the expected rows within their bands (ROWS.md, rendered from ledger.json). Anyone with a 4090 can run it.
| item | state |
|---|---|
| the kit on build-1 | pending (16:30 UK clock) |
| the kit's sha256 | pending |
| the public page | pending (17:30 UK clock; /gpu-ledger) |
## 8. Faults and corrections (reported once)
| when (UK) | what | state |
|---|---|---|
| 13:1x | the brief's "Ravencoin's own 1.5x claim" has no source in the pinned ProgPoW text (the README states 1.1x to 1.2x); the row carries the README's figure and the brief's figure as NOT FOUND | on the row |
| 13:1x | the earlier like-for-like line ("KAWPOW 5 to 6x against v6 2.35x") compared v6 at the 5090 knee with KAWPOW at the 4090 stock; at the same cell (4090 stock, set v3) the rows read v6 5.4x against KAWPOW 3.9x (proxy), so clause (a) of the claim is NOT SUPPORTED on today's rows | reported to main 13:1x; the ledger session's pinned-kernel rows decide |
| 13:0x | the lab's cohort cells stand in for the ledger session's cells until COHORT's back-to-back rows land (clock 14:45) | pending |

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# Comparative review: what other live GPU chains publish about their own chip resistance (9 October 2026)
The row the laboratory interface names in section 8c item 9 ("a comparative review of what other chains publish: a row of the table, NOT RUN until done"). Method: the chain's own pages were read on 9 October 2026 (the date-read column); every quotation is verbatim and under 15 words, with its URL; nothing was downloaded or run; a paraphrase is never inside quotation marks. The last column answers one question per chain: does the chain's own record carry a measured or priced attacker row (a chip designed, modelled or measured against the chain's work), and where we looked. This file states what others publish; it serves no ranking sentence. The site's own claim stays the approved wording of the interface, verbatim, and nothing stronger.
## 1. The rows
| Chain, algorithm | Their statement, verbatim | Where it sits (URL), date read | Their convention | A measured or priced attacker row in their record |
|---|---|---|---|---|
| Ravencoin, KAWPOW | "ASIC resistant – Uses the KAWPOW hashing algorithm to discourage the development of ASIC hardware" | https://ravencoin.org/about/ (the project page, no date shown), read 9 October 2026 | ProgPoW's premise, inherited: "The KAWPOW algorithm was derived from ProgPOW and ethhash, with modifications" (same page) | None found. Looked at ravencoin.org/about, the Ravencoin repository README (github.com/RavenProject/Ravencoin, no ASIC text) and EIP-1057. A "1.5x" figure for KAWPOW was not found on any Ravencoin page; the number quoted to the project in review is a reviewer's, not Ravencoin's. |
| Ravencoin, KAWPOW (the second sentence) | "limited potential for ASIC efficiency gains compared to consumer grade hardware" | https://ravencoin.org/about/, read 9 October 2026 | as above | as above |
| ProgPoW (the algorithm KAWPOW and FiroPoW derive from; EIP-1057) | "These would result in minimal, roughly 1.1-1.2x, efficiency gains." | https://eips.ethereum.org/EIPS/eip-1057 (section "ProgPoW Algorithm Walkthrough"), read 9 October 2026 | Its premise, in its own words: "can have a customized ASIC created for it with slightly less functionality" (section "Rationale for PoW on Commodity Hardware"); the goal: "have the algorithm's requirements match what is available on commodity GPUs" | None found on the EIP page or the reference README (github.com/ifdefelse/ProgPOW): the 1.1x to 1.2x is a design-walkthrough estimate of what a chip saves by leaving GPU parts out, not a priced design. Version 0.9.4's stated purpose: "patch the condition modifying the input state of the last keccak pass" (the README). |
| Iron Fish, FishHash (FIP-3, 20 December 2023) | "levels the playing field between different mining hardware (ASICS, FPGAs and GPUs)" | https://fips.ironfish.network/fips/fip-3-memory-hard-mining-algorithm (Abstract), read 9 October 2026 | Memory-bound by design: "difference between specialized and widely available hardware is as small as possible" (Specification); the dataset "equals 4608 MBytes" | None found. FIP-3's analysis is static (memory and compute demand); its one ratio is about Ethash's shipped chips: "much more efficient (2-10x) in terms of power consumption" (Rationale). The Trail of Bits audit (https://ironfish.network/learn/blog/2024-05-14-fish-hash-audit, read 9 October 2026) is cryptanalytic: "no practical exploitations were discovered around the memory-hardness requirement"; it prices no chip. |
| Ethereum Classic, ETChash | "there is no such thing as ASIC resistance" | https://ethereumclassic.org/faqs/miners/ (the question "Is Ethereum Classic's mining algorithm ASIC resistant?"), read 9 October 2026 | A shipped-chip observation, not a model: "mine ETCHash 2x to 6x more energy efficiently than GPUs" (same answer) | The only chain of the six with real chips on its work; the 2x to 6x is stated without a source on the page, and the hardware guide names no model: "A range of ASIC miners Ethereum Classic are available" (https://ethereumclassic.org/mining/hardware/, read 9 October 2026). No designed-attacker row; none claimed. |
| Ergo, Autolykos v2 | "fairly launched efficient ASIC-resistant Proof of Work algorithm" | https://docs.ergoplatform.com/mining/autolykos/, read 9 October 2026 | A stored table: "a single table of ~2 GB (initially)"; "designed to be efficient for miners who store the table" | None found on the Autolykos documentation page: no ratio, no priced or measured design. (The project's own comparative lane found no open GPU miner that passes its verifier on today's table, so Ergo is a non-comparable peer under the open-miner rule; recorded, not scored.) |
| Firo, FiroPoW (release post, 1 October 2021) | "designed to be both FPGA and ASIC resistant to even the playing field" | https://firo.org/2021/10/01/firopow-and-instantsend-release.html, read 9 October 2026 | ProgPoW's premise, inherited: "FiroPoW follows ProgPoW's 0.9.4 spec with a small change" (same post) | None found in the release post: no ratio, no priced or measured design; the post states the DAG start ("slightly over 4GB") and the per-block change. |
## 2. What the rows say together
- Four of the six (Ravencoin, FishHash, Ergo, Firo) publish a qualitative sentence (resistant, levels the playing field) and no number; two publish a number: ProgPoW's 1.1x to 1.2x (a design estimate under its own premise, inherited by Ravencoin and Firo) and Ethereum Classic's 2x to 6x (shipped chips, no source on the page).
- None of the six carries, on the pages read, a priced or measured attacker design against its own work (a chip designed, placed and costed, or a chip measured). "None found" on every row means: not on the pages named in the row; a page we did not read may exist.
- Two conventions are in play across the field: ProgPoW's premise (a chip keeps a GPU-class datapath; its edge is what it leaves out) and the whole-machine premise (the cheapest programmable core the specialist would build, as a complete machine). Ethereum Classic's figure is neither: it is what shipped chips do.
- This project's own rows, for the record beside them (docs/analysis/class-v6/1p5x/lab/table.md on master; the adversary lane's rows on branch class-v6-adversary): under ProgPoW's premise the frozen class v6 object reads 1.01x to 1.02x; under the whole-machine premise the same-node DRAM board reads 2.60x at the 5090 knee (2.06x to 3.02x, set v2, WITNESS) and 5.67x at the worst cohort cell; KAWPOW and FiroPoW under the whole-machine premise read 4.24x on set v2 against a rented 4090 at stock (the KAWPOW census as the op-count proxy, PROXY until the pinned 0.9.4 control is measured). No chip is measured on any side.
## 3. What this review does not license
The fifth review withdrew the sentence that no other GPU chain has such a record written down; this file is the row that was NOT RUN. It establishes only what the named pages say on the date read. It does not establish that no other chain holds a priced attacker row somewhere else, and it does not rank any chain; a ranking sentence needs the laboratory's ruling on this row, not this file.

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{
"title": "The GPU network ledger",
"stamp": "2026-10-09",
"adversarial_set": "v3",
"adversarial_set_source": "build-1:/srv/artefacts/lab/adv/ (README.md, design-notes/adversarial-sets-v1-v2-v3.md, rows/, SHA256SUMS); set v3 commit b2b9ee0b9 on class-v6-adversary",
"cards": [
{"id": "4090", "name": "RTX 4090", "state": "stock", "note": "uncapped host (450 of 450 W)"},
{"id": "5090", "name": "RTX 5090", "state": "stock", "note": "uncapped host (575 or 600 W at default)"}
],
"ranking_rule": "Rank (a) ascending on the same-node DRAM board ratio under the ledger's convention at the WORSE of the two cards (the lower ratio is the smaller chip edge); (b) ascending on the ProgPoW-premise ratio at the same cell; (c) phase B: whether the chain's GPUs earn an income a hash chip cannot. A cross-chain comparison is made only between cells from the SAME card, the SAME state and the SAME session (main's ruling, 13:2x UK 9 October 2026); until the ledger session's cells exist the (a) column shows each chain's own number and no order. A chain with any pending or proxy cell in a column is ranked provisionally in that column and says so; a NOT RUN chain is unranked.",
"mechanism": {
"title": "Why the two honest-convention edges differ: the shape of the memory traffic",
"rows": [
{"chain": "Igneum v6", "traffic": "256 dependent random reads of one 32-byte sector each per hash over 4 GiB (8 KB moved, 1 KB consumed); the card is activation-bound: 7.86 G sector reads per second on the 4090 at its tFAW form, 17.6 G on the 5090", "card_cost": "27 to 31 nJ per random sector read all-in on the 4090 at stock (X7 and the sector-read rows); the ALU runs in the reads' shadow (f 0.85)", "chip_cost": "about 2.1 nJ per read on the chip's own GDDR7 board (1.2 on HBM3, 0.7 beside the bank): s = 12.8", "consequence": "the chip's edge on random reads is the largest of any term in the model; a read-dominated object carries it in full"},
{"chain": "Ravencoin KAWPOW (and FiroPoW)", "traffic": "64 coalesced 256-byte DAG entries per 16-lane hash = 16 KB streamed per hash; the card is bandwidth-bound (1.03 TB/s at 62.6 MH/s on the 4090; 93 MH/s per modelled board)", "card_cost": "a coalesced 256-byte read costs the card far less per byte than a scattered sector (modelled 35 nJ per 256-byte entry against 27 nJ per 32-byte sector)", "chip_cost": "the chip streams the same bytes at the same DRAM bandwidth bound; its gain is on the per-byte energy and the 18 random-math ops per loop (a GPU-class datapath on the premise, fused lanes under ours)", "consequence": "a smaller memory-term gap, so a smaller honest-convention edge at the same card; the price is a DAG that grows (8.38 GB at Ethereum's epoch 871 for the control) and a 16 KB stream per hash"},
{"chain": "Iron Fish FishHash", "traffic": "96 random 128-byte lines per hash over a fixed 4.83 GB (12 KB per hash, every byte consumed): between the two shapes (four sectors per activation)", "card_cost": "pending the measured cell (CONTROLS' rate-only read 242 GB/s of lines at 19.73 MH/s on the 4090)", "chip_cost": "95 percent of the modelled board's energy is its memory path", "consequence": "the ratio is pending its card cell"},
{"chain": "Ethereum Classic Etchash", "traffic": "64 loops of two 64-byte half-mixes = 128-byte coalesced reads per hash over the epoch DAG; bandwidth-bound", "card_cost": "pending", "chip_cost": "the one chip that exists (the E9 Pro) on this shape", "consequence": "the calibration line"}
],
"note": "Stated as the mechanism, not as a mitigation: the lab's X7 verdict is that no read-dominated design reaches a small edge against a chip with its own memory on the same node, and the ledger shows the shape of each chain's traffic beside its ratio so a reader sees where each number comes from."
},
"chains": [
{
"id": "igneum-v6",
"chain": "Igneum",
"algorithm": "class v6, the live signing object 0x2a1d6caab4c24564 (2.0 devnet, chain id 4465)",
"control": "ctl-v6",
"pin": "tree 1a938abe4; pack x1-ctrl-ds30.tgz sha256 7606c13d92546e44feef485fde25716a206643e6466ef5d5251d41354eee9532; read-only twin x1-ctrl-ds30-readonly.tgz 7629ed9598c0297533c03d4a9cbd83338d47a7693a26dc8b86566f3f0982174b; worker igneum-worker-cuda-gen6 804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd (COHORT's rows on worker f5f3846c, kit bf9b85d6); build-1:/srv/artefacts/lab/controls/frozen-v6/",
"dataset_bytes": 4294967296,
"dataset_note": "2^30 words, the live policy (70a6c703); 256 random 4-byte reads per hash, 62,120 instructions per hash (instruction convention)",
"twin": "yes (the same address stream, the arithmetic cut)",
"split": {"mining": 80, "proving": 20, "source": "the Token Value volume on master (D04, token-value/README.md: the 80/20 emission allocation); PROVING_POOL_SHARE_PERCENT"},
"own_claim": "none published as a number; the lab's X0 record: the same-node DRAM board 2.35x at the 5090 knee (set v0), 2.60x (set v3)",
"cells": {
"4090": {"status": "MEASURED", "session": "lab-cohort-ctl-v6 (COHORT, 11:49 to 12:30 UK, one chain)", "nj": 8368.9, "mhs": 30.673, "w": 256.7, "f": 0.848, "twin_nj": 7098.9, "spread_pct": 0.67, "clock": "stock (the pod refused -lgc); clocks_sm_median pending the ledger session", "pod": "vast 55009211, driver 580", "source": "build-1:/srv/artefacts/lab/ctl-v6/vast-55009211/ (rows.jsonl, SHA256SUMS); the cohort table build-1:/srv/artefacts/lab/cohort/TABLE.md", "note": "the lab's cohort cell (median of three); the second uncapped 4090 (vast 55006526) read 8,751; the ledger session's own row replaces this cell when it lands"},
"5090": {"status": "MEASURED", "session": "lab-cohort-ctl-v6 (COHORT, 11:49 to 12:30 UK, one chain)", "nj": 5597.1, "mhs": 68.661, "w": 384.3, "f": 0.811, "twin_nj": 4537.6, "spread_pct": 2.11, "clock": "stock (the pod refused -lgc); the host cap 500 W, the card drew 384", "pod": "vast 55006481, driver 580", "source": "build-1:/srv/artefacts/lab/ctl-v6/vast-55006481/; the cohort table build-1:/srv/artefacts/lab/cohort/TABLE.md", "note": "the lab's cohort cell; the ledger session's uncapped-host row replaces it when it lands"}
},
"adversary": {
"status": "WITNESS (modelled, complete machine, instruction convention)",
"board": {"low": 1329, "nominal": 1542, "high": 1941, "design": "GDDR7 board + register file sized to the work + fused operations, N5", "split_nj": "memory 527 / ALU 166 / tax 849"},
"die": {"nominal": 335, "design": "N2 full-SRAM die, the coexistence row"},
"premise": {"4090": "1.01x to 1.03x (f 0.853 measured)", "5090": "1.02x to 1.03x (f 0.811 measured on the stock pod)"},
"source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f); build-1:/srv/artefacts/lab/adv/rows/ctl-v6.json and rows.md (set v3, 2026-10-09T11:33Z); the die 12.0x at the 5090 knee, USD 0.77 per MH/s"
},
"real_chip": null,
"phases": {
"status": "WITNESS; phase B NOT LIVE until a shipped package runs a prover",
"A": "before investment (24 months, the mining share 80 percent of the year-1 subsidy): the same-node board maker recovers its spend on NO fleet from 100 to 100 M boards on the growing or flat price path (100,000 boards: net USD -55.4 M on 58.8 M revenue growing; -37.6 M on 76.6 M flat); only the falling path pays it; the N2 die recovers on no path",
"B": "spend sunk, flat path at USD 0.10 per kWh, the chip at 10 percent of the hash: mining revenue USD 0.354 per TH; the GPU's proving income at the ratified 20 percent share USD 0.098 per TH against the board chip's operating advantage USD 0.046 per TH (GPU electricity 0.111 less the chip's electricity, hosting and maintenance 0.066): the GPU out-earns the built board chip; the cancelling proving share 9 percent (board), 13 (hybrid), 20 (die)",
"income_a_chip_cannot_earn": "yes by rule (the proving share of every block, 20 percent ratified); LIVE ON DEVNET with on-chain paid records (663 paid v1 segment records to 30 prover keys on chain 4465, the PROVING LIVE lane's file bd3f53c1 on build-1), not yet in a shipped package",
"source": "build-1:/srv/artefacts/lab/adv/rows/rows.md (the two-phase section), ADVERSARY commit 545f3f8a0; ctl-v6-coexistence.json"
}
},
{
"id": "rvn-kawpow",
"chain": "Ravencoin",
"algorithm": "KAWPOW (ProgPoW 0.9.4 with Ravencoin's kiss99 constants, 7,500-block epochs and a 512-parent DAG; live since block 1,219,736, 6 May 2020)",
"control": "ctl-progpow-094",
"pin": "ifdefelse/ProgPOW d035ae56536d2e6fc71aad609ac5085c9785d1b3, the reference's own CUDA kernel text, DAG generator and light cache (256 parents as the code implements); harness progpow-094/gpu/pp_harness_<block>, CPU reference cpu/pp094_ref; build-1:/srv/artefacts/lab/controls/progpow-094/ (SHA256SUMS)",
"dataset_bytes": 6182403712,
"dataset_note": "KAWPOW's current DAG size at Ravencoin height 4,573,707 (epoch 609, read 13:0x UK): the official ProgPoW 0.9.4 kernel built at Ethash block 18,270,000 (epoch 609, the same byte count), harness progpow-094/gpu/pp_harness_18270000; KAWPOW's own constants NOT applied, so the row is 'ProgPoW 0.9.4 official at KAWPOW's DAG size (proxy)'; 64 coalesced 256-byte reads per hash; F1 GPU = CPU on both nonces (cpu/vectors-094-kawpow-size-18270000.txt)",
"twin": "yes, by construction (progpow-094/gpu/pp_twin 18270000 26 250: the 64 dependent entry reads per 16-lane hash)",
"split": {"mining": 100, "proving": 0, "source": "Ravencoin's block reward goes to the miner in full (no second income to GPUs)"},
"public": {"block_reward": "1,250 RVN", "block_time": "60 s", "network_hash": "721.3 GH/s", "price_usd": "0.0022", "source": "minerstat.com/coin/RVN, read 9 October 2026 13:3x UK (public figures, not measured by the lab)"},
"own_claim": "the ProgPoW README (the pinned commit) states a specialised chip gains 1.1x to 1.2x on ProgPoW's premise (the chip keeps a GPU-class datapath). The figure 1.5x quoted in the ledger's brief as Ravencoin's own claim has no source in the pinned text or on the record: NOT FOUND; the row carries the README's 1.1x to 1.2x",
"cells": {
"4090": {"status": "MEASURED (prior row: kawpowminer, not the pinned kernel; a PROXY until the ledger session's pinned-kernel row lands)", "session": "comparative-lane a2ed5c31 (RunPod, one chain, an earlier session)", "nj": 6920, "mhs": 58.95, "w": 409, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "RunPod, the comparative lane a2ed5c31", "source": "build-1:/srv/artefacts/lab/adv/rows/rows.md (the ctl-progpow-094 section, card rows)", "note": "407 to 411 W at 58.95 MH/s; the ledger session re-measures with the pinned official kernel at Raven's DAG size (CONTROLS' rate-only read on a 4090 at stock: 58.95 MH/s full, the twin 60.99), board power sampled, median of three, the twin beside it"},
"5090": {"status": "pending (COHORT, the ledger session)", "session": "pending", "nj": null, "mhs": null, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "pending", "source": "pending", "note": ""}
},
"adversary": {
"status": "WITNESS (modelled on the kawpowminer census as the work proxy until CONTROLS' trace replaces it)",
"board": {"low": 1453, "nominal": 1757, "high": 2147, "design": "GDDR7 board + register file sized to the work + fused operations, N5; bandwidth-bound at 16 KB per hash (93 MH/s per board)", "split_nj": "memory 647 / ALU and tax per rows.md"},
"die": {"nominal": 697, "design": "N2 full-SRAM die, the coexistence row (USD 1.89 per MH/s); the cheapest specialist of any kind is near-memory base dies at 669 nJ"},
"premise": {"4090": "1.10x to 1.20x (the premise's own figure; no measured twin on this kernel yet)", "5090": "1.10x to 1.20x (the premise's own figure; the twin row makes it measured)"},
"source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f); build-1:/srv/artefacts/lab/adv/rows/ctl-progpow-094.json (set v3)"
},
"real_chip": null,
"phases": {
"status": "WITNESS, the chain's own units, the 100/0 split, the same 24-month life, design cost and fleet rule as v6, the three price paths (flat at the public price, x2 growing, x0.5 falling, the hash held); the public lines on the row",
"A": "before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path, because Ravencoin's whole mining emission over 24 months (about USD 2.9 M at the public price) sits below one USD 35 M design cost; 10,000 boards would take 56 percent of the 721 GH/s network and earn USD 1.6 M to 2.4 M against a USD 44 M spend",
"B": "spend sunk, mining only: mining revenue USD 0.064 per TH of the chain's own hashes; the board chip's recurring cost USD 0.069 per TH at ten cents; the chip's operating advantage over the RTX 4090 at stock (6,920 nJ) USD 0.123 per TH (the GPU's electricity 0.192 less the chip's 0.069) stands in full, no prover income",
"income_a_chip_cannot_earn": "no (the block reward is mining only)",
"source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-progpow-094-coexistence.json (rows[].phase_a, rows[].phase_b_split; method lab/adv/README.md section 14), ADVERSARY commit d7db3e596 on class-v6-adversary"
}
},
{
"id": "firo-firopow",
"chain": "Firo",
"algorithm": "FiroPoW (ProgPoW 0.9.4 with Firo's constants; live since block 419,264, 26 October 2021)",
"control": "ctl-progpow-094 (the same row as KAWPOW)",
"pin": "as KAWPOW: the pinned ProgPoW 0.9.4 reference; FiroPoW differs from KAWPOW only in its constants and DAG schedule, so the lab serves ONE row for both and says so",
"dataset_bytes": null,
"dataset_note": "= KAWPOW's row (its own DAG schedule is not measured separately)",
"twin": "as KAWPOW",
"split": {"mining": 100, "proving": 0, "source": "Firo's block reward splits between miners, masternodes and the development fund; the GPU's share is mining only (no proving income)"},
"own_claim": "as ProgPoW's: 1.1x to 1.2x on its premise",
"same_row_as": "rvn-kawpow",
"cells": {},
"adversary": {"status": "= KAWPOW's row", "board": null, "die": null, "premise": {}, "source": "as KAWPOW"},
"real_chip": null,
"phases": {"status": "= KAWPOW's row at a 100/0 split", "A": "as KAWPOW", "B": "as KAWPOW", "income_a_chip_cannot_earn": "no", "source": "as KAWPOW"}
},
{
"id": "ironfish-fishhash",
"chain": "Iron Fish",
"algorithm": "FishHash (live since hardfork 1, April 2024)",
"control": "ctl-fishhash",
"pin": "iron-fish/fish-hash 823531c002e78259759f8b1f36ac9121c32059b1 (cpp/FishHash.cpp; the spec FishHash.pdf sha256 869870b9...); the lab's CUDA implementation bit-exact with the library on 64 items and 256 hashes, fingerprint f841605125ce375e; gpu/fh_cuda, cpu/fh_cli; build-1:/srv/artefacts/lab/controls/fishhash/ (SHA256SUMS)",
"dataset_bytes": 4831835776,
"dataset_note": "37,748,717 items of 128 bytes, FIXED (no epochs); 96 random 128-byte reads per hash, 9,856 lane-instructions",
"twin": "yes (a trace replay of the kernel's own item indexes; its energy read as a bound: the twin runs 10 percent slower than the full kernel)",
"split": {"mining": 100, "proving": 0, "source": "Iron Fish's block reward is mining only"},
"public": {"block_reward": "17.25 IRON", "block_time": "61 s", "network_hash": "229.5 GH/s", "price_usd": "0.07", "source": "minerstat.com/coin/IRON, read 9 October 2026 13:3x UK (public figures, not measured by the lab)"},
"own_claim": "none as a chip-edge number; the Trail of Bits review (Iron Fish blog, 14 May 2024) is the published outside check",
"cells": {
"4090": {"status": "pending (COHORT, the ledger session); CONTROLS' rate-only read 19.73 MH/s at stock, no sampler", "nj": null, "mhs": 19.73, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "CONTROLS' rented 4090 (rate only)", "source": "build-1:/srv/artefacts/lab/controls/fishhash/gpu/bench-4090.log", "note": "242 GB/s of 128-byte lines at that rate"},
"5090": {"status": "pending (COHORT, the ledger session); CONTROLS' rate-only sm_120 read 45.37 MH/s full, 39.71 twin, F1 PASS", "nj": null, "mhs": 45.37, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "CONTROLS' rented 5090 (rate only)", "source": "build-1:/srv/artefacts/lab/controls/fishhash/ (fishhash.md)", "note": ""}
},
"adversary": {
"status": "WITNESS (modelled; the card's cell pending, so the ratio is pending)",
"board": {"low": 881, "nominal": 1051, "high": 1257, "design": "GDDR7 board + register file sized to the work + fused operations, N5; bandwidth-bound at 124 MH/s per board; 95 percent of the board's energy is the memory path", "split_nj": "memory 529 / ALU 46 / tax 503"},
"die": {"nominal": 170, "design": "full SRAM dies (three N2 reticles) + sized + fused operations"},
"premise": {"4090": "pending (needs the measured f from the twin)", "5090": "pending"},
"source": "build-1:/srv/artefacts/lab/adv/rows/ctl-fishhash.json and rows.md (set v3)"
},
"real_chip": null,
"phases": {"status": "WITNESS, the chain's own units, the 100/0 split, the same life, design cost, fleet rule and price paths as v6; the GPU side of phase B NOT RUN until COHORT's card rows", "A": "before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path; Iron Fish's whole mining emission over 24 months is about USD 1.4 M at the public price (10,000 boards would take 84 percent of the hash for USD 1.1 M to 1.6 M)", "B": "spend sunk, mining only: mining revenue USD 0.086 per TH of the chain's own hashes; the board chip's recurring cost USD 0.043 per TH at ten cents; the GPU side NOT RUN until the card cell lands; no prover income by construction", "income_a_chip_cannot_earn": "no", "source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-fishhash-coexistence.json, ADVERSARY commit d7db3e596 on class-v6-adversary"}
},
{
"id": "etc-etchash",
"chain": "Ethereum Classic",
"algorithm": "Etchash (Ethash with ECIP-1099's 60,000-block epochs; live since block 11,700,000, November 2020)",
"control": "ctl-etchash (new for the ledger)",
"pin": "a CUDA hashimoto over the pinned chfast/ethash v0.8.0 library's light cache and the ProgPOW repo's reference DAG generator (libethash objects), checked against ethash::hash on the CPU at block 0 and at the live epoch (F1: GPU = CPU on both nonces); gpu/etchash_cuda (`check <block> <nonces>`, `bench <block> 22 250`, `bench <block> 22 250 twin`), cpu/etc_ref; build-1:/srv/artefacts/lab/controls/etchash/ (SHA256SUMS; etchash.md)",
"dataset_bytes": 4638898816,
"dataset_note": "ETC height 25,502,946 (read 12:5x UK) = Etchash epoch 425 (ECIP-1099: height / 60,000), the harness's block argument 12,750,000 (the Ethash epoch with the same size table index); 64 coalesced 128-byte reads per hash (two 64-byte half-mixes); CONTROLS' rate-only read on a 4090 at stock 29.90 MH/s full and 29.90 twin (memory-bound)",
"twin": "yes, by construction",
"split": {"mining": 100, "proving": 0, "source": "ETC's block reward is mining only"},
"public": {"block_reward": "2.048 ETC", "block_time": "16 s", "network_hash": "120.9 TH/s", "price_usd": "8.24", "source": "minerstat.com/coin/ETC, read 9 October 2026 13:3x UK (public figures, not measured by the lab)"},
"own_claim": "none; the chain accepts chips (the Antminer E9 Pro mines it)",
"cells": {
"4090": {"status": "pending (COHORT, the ledger session; the harness staged 13:0x UK); CONTROLS' rate-only read 29.90 MH/s", "nj": null, "mhs": 29.90, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "CONTROLS' rented 4090 (rate only)", "source": "build-1:/srv/artefacts/lab/controls/etchash/ (etchash.md)", "note": ""},
"5090": {"status": "pending (COHORT, the ledger session; the sm_120 build from etchash/src)", "nj": null, "mhs": null, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "pending", "source": "pending", "note": ""}
},
"adversary": {
"status": "WITNESS (modelled; the card cells pending, so the ratios are pending)",
"board": {"low": 638, "nominal": 765, "high": 919, "design": "GDDR7 board + register file sized to the work + fused operations, N5; USD 3.25 per MH/s", "split_nj": "per ledger-rows.md"},
"die": {"nominal": 177, "design": "N2 full-SRAM die, the coexistence row"},
"premise": {"4090": "1.10x to 1.20x (the premise's own figure; the twin row makes it measured)", "5090": "1.10x to 1.20x (the premise's own figure)"},
"source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ledger-rows.md and ledger-rows.json (class-v6-adversary 47f16b86f, wording 82330b04c)",
"calibration": "the modelled same-node DRAM board 765 nJ per hash against the Antminer E9 Pro's 598 from its public figures: the model reads 1.28x PESSIMISTIC for the chip (it gives the chip more energy than the one real chip spends); a witness, never a ceiling"
},
"real_chip": {
"name": "Bitmain Antminer E9 Pro",
"mhs": 3680,
"w": 2200,
"nj": 597.8,
"status": "WITNESS (a manufacturer's published figure, not measured by the lab)",
"source": "Bitmain's stated figures as listed on minerstat's hardware page (https://minerstat.com/hardware/antminer-e9-pro): 3.68 GH/s on Ethash at 2,200 W, release 2023-02; 2,200 W / 3,680 MH/s = 0.598 J per MH = 598 nJ per hash",
"note": "the ONE live GPU-mined chain with a chip on the market; the modelled board (765 nJ) sits beside it: 1.28x pessimistic for the chip"
},
"phases": {"status": "WITNESS, the chain's own units, the 100/0 split, the same life, design cost, fleet rule and price paths as v6; the GPU side of phase B NOT RUN until COHORT's card rows", "A": "before investment: no fleet from 100 to 100 M machines recovers a board chip's spend on any path; ETC's whole mining emission over 24 months is about USD 83 M at the public price, but 10,000 boards are 2 percent of 120.9 TH/s and earn USD 1.0 M to 1.5 M, and 100,000 boards (13 percent) USD 9 M to 13 M against a USD 150 M spend", "B": "spend sunk, mining only: mining revenue USD 0.0087 per TH of the chain's own hashes, below even the modelled board's recurring cost (USD 0.031 per TH) and below the E9 Pro's own electricity at ten cents (598 nJ = USD 0.017 per TH): at the public figures nobody mines ETC at a profit at ten cents and phase B is a loss on both sides; the GPU side NOT RUN until the card cell lands", "income_a_chip_cannot_earn": "no", "source": "docs/analysis/class-v6/1p5x/lab/adv/v3/ctl-etchash-coexistence.json, ADVERSARY commit d7db3e596 on class-v6-adversary"}
},
{
"id": "ergo-autolykos2",
"chain": "Ergo",
"algorithm": "Autolykos2 (k = 32, n = 26, Blake2b-256; the table grows 5 percent every 51,200 blocks)",
"control": "ctl-autolykos (new for the ledger, landed 13:1x UK)",
"pin": "the published text ergoplatform/ergo master 3a6b00d3, AutolykosPowScheme.scala (sha256 330ae870...; the copy in src/), implemented in-house: CPU reference src/autolykos_ref.py (hashlib's Blake2b, lazy elements), GPU gpu/autolykos_cuda (`check <height> <N> <count> < fixtures`, `bench <height> <N> 20 250`, `bench ... twin`; sm_89, the sm_120 build from src); F1 at N = 65,536 and at the live table: elements 0 and last, 64 hits and the 256-hit fingerprints equal the reference's (f3cf1fd34d1002fa small, b6d07a7b15956179 live); build-1:/srv/artefacts/lab/controls/autolykos/ (SHA256SUMS; autolykos.md). CAVEAT on the row: the fixtures are the lab's own from an independent implementation of the published text (the reference repository has no known-answer v2 hit vector); the end-to-end check against a live Ergo block is owed, not claimed",
"dataset_bytes": 7272058080,
"dataset_note": "the live table at Ergo height 1,890,820 (api.ergoplatform.com, 13:0x UK): N = 227,251,815 elements of 32 bytes (+5 percent at height 1,894,400; the row names its height); 33 random 32-byte reads per hash; the table builds on the device in 1.5 s; CONTROLS' rate-only read on a 4090 at stock 216.2 MH/s full, 201.8 twin",
"twin": "yes (a trace replay)",
"split": {"mining": 100, "proving": 0, "source": "Ergo's block reward is mining only"},
"public": {"block_reward": "3.009 ERG", "block_time": "120 s", "network_hash": "569.1 GH/s", "price_usd": "0.29", "source": "minerstat.com/coin/ERG, read 9 October 2026 13:4x UK (public figures, not measured by the lab)"},
"own_claim": "none on the record as a chip-edge number",
"cells": {
"4090": {"status": "pending (COHORT, the ledger session; the harness staged 13:1x UK); CONTROLS' rate-only read 216.2 MH/s full, 201.8 twin", "session": "pending", "nj": null, "mhs": 216.2, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "CONTROLS' rented 4090 (rate only)", "source": "build-1:/srv/artefacts/lab/controls/autolykos/ (autolykos.md)", "note": ""},
"5090": {"status": "pending (COHORT, the ledger session; the sm_120 build from src)", "session": "pending", "nj": null, "mhs": null, "w": null, "f": null, "twin_nj": null, "spread_pct": null, "clock": "stock", "pod": "pending", "source": "pending", "note": ""}
},
"adversary": {"status": "pending (ADVERSARY: the chip rows from CONTROLS' trace; default 15:00 UK, else pending (adversary))", "board": null, "die": null, "premise": {"4090": "pending", "5090": "pending"}, "source": "pending"},
"real_chip": null,
"phases": {"status": "pending (ADVERSARY at the 100/0 split, the public line on the row)", "A": "pending (ADVERSARY)", "B": "pending (ADVERSARY); no prover income by construction", "income_a_chip_cannot_earn": "no", "source": "pending"}
}
],
"claim": {
"ordered_sentence": "the lowest measured chip-to-GPU edge of any live GPU network under a published method, on both conventions, and the only one whose GPUs earn income a chip cannot",
"headline_rule": "the headline reads only what the like-for-like rows support, clause by clause (main's ruling, 13:2x UK 9 October 2026); under the ledger's own convention the measured edge per chain on the same card and state is stated as numbers, with no ranking word until the rows say so after the ledger session",
"clauses": [
{"text": "under ProgPoW's own convention, the lowest measured chip-to-GPU edge of the chains on this ledger", "convention": "ProgPoW's premise (a chip that keeps a GPU-class datapath)", "state": "SUPPORTED on the current rows", "why": "Igneum v6 1.01x to 1.03x (its measured f 0.81 to 0.85) against ProgPoW's own 1.10x to 1.20x for KAWPOW and FiroPoW; FishHash and Etchash pending their twins"},
{"text": "under the ledger's convention (the cheapest credible programmable specialist, adversarial set v3), each chain's measured edge on the same card and state, as numbers", "convention": "ours", "state": "NUMBERS ONLY; no ranking until the ledger session (COHORT, both cards, every chain back to back, the pinned 0.9.4 kernel, twins; 14:45 UK)", "why": "the current cells come from different sessions (the lab's cohort pods for v6, the comparative lane's pod for KAWPOW) and a cross-chain comparison is made only between cells from the same card, state and session; at the RTX 4090 at stock the cells read v6 5.4x (5.67x on the second pod) and KAWPOW 3.9x (a proxy row from an earlier session); FishHash and Etchash pending"},
{"text": "and the only chain on this ledger whose GPUs are paid, by rule, an income a hash chip cannot earn", "convention": "phase B, each chain's actual reward split", "state": "LABELLED BY THE PROVING LIVE LANE", "why": "the proving share (20 percent ratified) is paid to GPUs for work a hash chip cannot do; every other chain on the ledger pays mining only; the live state of that income is the PROVING LIVE lane's evidence line"}
],
"withdrawn": "the earlier line 'KAWPOW and FiroPoW read 5 to 6x on the measured 4090 rows and v6 reads 2.35x' is withdrawn: it compared v6 at the 5090's 1,300 MHz knee with KAWPOW at the 4090 at stock, two cards and two states; the like-for-like cells are the ones on this ledger",
"proving_live_label": "LIVE ON DEVNET, on-chain records (the PROVING LIVE lane, read 11:50:22Z 9 October 2026): on chain id 4465 (the Igneum 2.0 devnet) 663 paid v1 segment records (8 shards plus aggregation each) = 653.93 IGN paid from the proving pool to 30 distinct prover keys across chain blocks 3,000 to 30,687 (tip 31,719 at the read), plus 6,474 paid v0 shard records = 7,196 IGN; read by igneum_getProvingStatus, igneum_getSegmentRecords (3,965 segments) and igneum_getSegment; evidence build-1:/srv/artefacts/proving-live/prov-ledger-4465-tip31719-115022Z.json sha256 bd3f53c18c3ffa20354ea62ade9fd5e7a5794202a71c3c369a5be71484f7143a. NOT YET LIVE IN A SHIPPED PACKAGE: the payees are the fleet's prover stack (the same binaries the 2.0.3.1 HiveOS package wraps, cut 18:00 UK); the apps' prover is on by default on 24 GB cards but no app-proved record is on the record yet; a full-epoch line follows by 16:00 UK"
}
}

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@ -0,0 +1,236 @@
# X0: the latest model reconciled with the exact frozen software (the 1.5x programme, 9 October 2026, 10:0x UK)
The adversary lane with the hash lane's pins (its line of 09:58 UK, every closing report staged with its sha256 at
build-1:/srv/artefacts/tas/x0-pins/<job id>.report.txt, SHA256SUMS.txt beside them; the recipe every X lane reads,
build-1:/srv/artefacts/1p5x/gpu-row-recipe.md sha cbab453c). The brief: the founder's
igneum-1p5x-experiment-brief.md (sha256 74ee073286d4a6e2…, landing under docs/plans/igneum-2.0-master/1p5x/). This
file reconciles every served and placed chip figure with the software and the measurements it rests on, names the
assumptions that differ between the served 1.9x to 2.1x hybrid line and the placed 2.4x line, and states the r0 the
programme uses with its range. Nothing here is a new measurement; no PASS is claimed.
## 1. The frozen control, as pinned
| Pin | Value | Read back | Label |
|---|---|---|---|
| The generator tree | class-v6 at 1a938abe4 (on branch class-v6, tip 755c2dbcf), generator 6, ProgramClass::V6, class string mx8-erad810f22d+sh256x27+state+reg64c+fold+rw, layer 8 ON, class_v6_family_flags 0xf, CLASS_V6_FLAG_NOWIN (1<<4) defined and off | the fingerprint recipe run on build-1 at 09:34 UK: 5f4d6dc6199294db89042171004e6420c1e5791e716d4b39b73d375818c10b6f, equal to the brief's | read back |
| The dataset policy | 70a6c703 (4 GiB at genesis, no later step) | F0's dataset row | pinned by F0 |
| The signing id | 2a1d6caab4c24564 at (epoch seed af89be5d, era edc4fa84, day 20730, state abb58003) | F0's freeze-candidate row | pinned by F0 |
| The research pairing (never the freeze) | hl-v6-all, id 0x4de7b836cc40a4ea (the genesis seed over node1's state) and the l8off kit's export 0x9d40978601a7df2a (era edc4fa84, day 20730, the node1 state) | the hash lane's line | pinned |
## 2. The GPU side: every figure, its software, its boundary, its state
Every figure is the three-card Windows rig's RTX 5090 (or 5080) alone through the runner's cards-off; power is
nvidia-smi board power.draw sampled at 1 Hz, the row's watts the sampler's mean from 8 s in to the end of the timed
dispatches, idle NOT subtracted (the microbench rows are the one exception, residency-subtracted); no wall meter
anywhere; fingerprints equal at every state. No GPU figure carries layer-8-off or a result compaction.
| Figure (as served) | Job and report sha256 | Software by sha | Pack | State | Where it is used |
|---|---|---|---|---|---|
| The 5090 at its 1,300 MHz lock: 134.764 MH/s at 312.5 W, 2.319 microjoules per hash (served as 2.33) | run-ca3-pc1-v4-eff-5090-20261007-b (7 Oct 18:40 to 19:16Z), report ead72106… | the installed app's igneum-worker-cuda.exe d7a413c7… (0.3.20); kit igneum-ca3-v4-sub3-pc1-kit.zip 1d441f5a… (program.json a746c924…, program.h 18bca6be…, kernel.cu 80e92839…) | v4-devnet-epoch0, the Devnet 3 epoch 0 class v4 program, fingerprint e370fb2080b7dbb1; 491 batches of 2^24 | the knee | the numerator of every served chip ratio (the "served convention") |
| The class v5 control at the lock: v5-genesis 125.932 MH/s at 299.8 W against v4-genesis 125.924 at 294.0 (+2.0 percent watts) | run-ca3-pc1-v5lock-5090-20261008-b, report 0f444306… | the class v5 kit's worker | v5-genesis, v4-genesis | the knee | denominator.md's +2 percent (the 2.37 row) |
| The class v6 control on the frozen tree at the lock: hl-v6-all 70.306 MH/s at 282.0 W (4.011 microjoules); stock 70.526 at 412.0 (5.842) | run-ca3-pc1-l8off-5090-20261008 (9 Oct 02:52 to 03:00Z), report 05f00bd8… | the l8off kit igneum-ca3-l8off-kit-20261008.zip c20999d1…, CUDA worker 218ca414…; fingerprint 59e6708e46f1e87c; 250 batches | hl-v6-all 0x9d40978601a7df2a (the frozen class at the research pairing) | both | NOT yet in any served chip ratio (section 4) |
| The 5080 at its 1,100 lock: 71.201 MH/s at 146.6 W, 2.059 microjoules | run-ca3-pc1-v4-eff-5080-20261007-d (8 Oct 00:45 to 01:54Z), report 6acec71d… | the same worker d7a413c7…, the same pack | v4-devnet-epoch0, e370fb2080b7dbb1 | the knee | the 5080 column |
| The cohort rows (14 rented card classes, stock only) | the fleet lane's rows.jsonl; denominator.md sha a4ec182a… on master | per row | per row | stock | the cohort column (count-weighted about 3.6 microjoules, approximate) |
| Layer 8 off (register row 18, CLOSED 04:49 UK): hl-v6-all against hl-v6-all-nowin 0xec0c3757f8caef4a: stock 70.526 / 412.0 W against 70.209 / 417.2 (rate -0.4, joules +1.7 percent); lock 70.306 / 282.0 against 66.303 / 275.5 (rate -5.7, joules +3.6); the v5 pair the same way, +5.7 percent at the lock | the same job, report 05f00bd8…; the row document docs/analysis/class-v6/rows/pc1-l8off-ds2g-20261009.md sha fb2d5686… (master ac2f143c) | the l8off kit | the four packs | both | the D2 row: performed and closed, the layer stays ON |
| The microbench per-op rows (int_arx 11.3 pJ stock, 6.2 at the lock; the class v4 draw read as 10.3 pJ per op at the lock from the packs job's 10.8 / 6.4) | run-ca4-pc1-microbench-5090-20261008-c (8 Oct 05:15 to 05:56Z), report 62dbb138…; the 10.3 is counter-asic-4-research.md's reading (sha 82af4424…) | igneum-worker-cuda-ca4mb.exe 49aa60c4… | 20 probes x 60 s at full residency | both | the denominator of every per-family k |
A caveat the hash lane names: since 14:2x UK on 8 October the rig's 5090 reads about 13 percent under the morning
(the enclosure swap), so pairs inside a job are the figures and a job's absolutes are not compared with 7 October's.
The served 2.33 microjoules is a 7 October absolute; the frozen-tree control is a 9 October job. Section 4 carries
what that does to r0.
## 3. The chip side: every figure, its software, its boundary, its node
| Figure | Software by sha | What it is | Boundary | Node scaling |
|---|---|---|---|---|
| The placed 8-lane 18-family core: 9.36 pJ per lane-op on the class v4 draw at ASAP7 (8.6 to 11.1), 6.55 at N5, 4.72 at N3 | class-v6-adversary 43c9f7cd8: tools/chip-model/mf (RTL core_mf.v, the flow, results/table.csv), docs/analysis/class-v6/multi-family-adversary.md (landed e3d0208d) | ORFS on ASAP7 (Yosys 0.68, OpenROAD, the orfs docker image), placed and routed with SPEF, OpenSTA power under a gate-level VCD of a random-input simulation; the register window a FakeRAM2.0 64x256 macro per 8 lanes whose dynamic energy is MODELLED (3.5 pJ per access, 2.0 to 7.0) | the core only: no memory controller, no PHY, no host; the machine terms are board.py's (section 5) | ASAP7 to N5 x0.70, to N3 x0.50 (TSMC's claimed per-node reductions at the same speed) |
| The placed 32-lane 18-family core: 9.54 pJ (8.9 to 11.0), 6.68 at N5 | the same; parasitics from the global route, calibrated within 1 percent of SPEF on the 32-lane genesis core; the detailed route did not converge (the fault, multi-family-adversary.md section 14) | | | the same |
| The program the chip rows execute | the testbench's draw with the class v4 WEIGHTS (add 12, xor 10, mul 8, mad 8, shfl 8, rotl 7, sub 6, mulhi 6, rotr 6, or 4), NOT the frozen tree's drawn program: the chip rows are per-op energies by family under the draw's weights; the frozen program's op counts (102,100 shadow ops, 512 base, 128 loads, W = 1) set the per-hash sum | | | |
| The memory system | chip-model-v3.md 5.3 and 5.5 (the GDDR7 board: 2.0 nJ per random read, 1.5 to 2.6; 21.3 G activates per second, the 5090's 82 percent as the sustained fraction; 20 W static, 15 W controller; USD 320 of devices), the N2 SRAM die (floor lane 3, 0.25 nJ per read at W = 1) | modelled on claimed device figures | the devices, controller and PHY | the memory does not scale with the core's node |
| The hybrid's hit rate | adv-cache-2's window-layer distribution on Devnet 3's programs (the hottest half of the items serves 0.7188 of reads: the p98 program), the hash lane's census reconcile (the mean over programs 0.581, coexistence-model.md line 537), census-packs.md's flat-control ratio 1.1 to 1.7x (sha 146b578c…) | measured on programs of the class v5 and v6 crates, the window model as the null | | |
| The complete machine | tools/chip-model/mf/flow/board.py: PSU 92 percent, VRM 90 percent, cooling 3 percent, one full node per 100 machines (85 W, USD 1,500), board and assembly USD 200, the core die sized to the memory's sustained rate | approximate allowances | the wall of the machine, less the host's share | |
## 4. The reconciliation, line by line
### 4.1 The served 1.9x to 2.1x hybrid against the placed 2.4x hybrid
Both are the stored-half hybrid (1 GiB of SRAM beside the 16 GDDR7 devices) against the 5090 at its lock, same
node. They differ in four assumptions, each named:
| Assumption | The served line (10.0r, "about 2.4x") | This lane's placed line (1.9x to 2.1x) | Which the programme uses |
|---|---|---|---|
| The hit rate of the hottest half | 0.72 (adv-cache-2's p98 program) | 0.581 (the hash lane's reconciled mean over programs) for the 1.93x; 0.72 for the 2.09x | the mean, 0.581: the p98 is the tail, carried beside it |
| The core's energy | the synthesised 8-lane core (4.61 pJ at N5) scaled by the first placed genesis core's factor | the placed 8-lane 18-family core itself, 6.55 pJ at N5 | the placed row |
| The machine terms | the board identity (2.33 over 0.466 + the shadow) with the hybrid's memory term, no power train | the complete machine: PSU, VRM, cooling, the host share, the sustained derate | the complete machine (the review's evidence standard) |
| The node | N5 node-for-node | N5 node-for-node | the same |
So the 2.4x is the synthesised core at the tail hit rate on the board identity, and the 1.9x to 2.1x is the placed
core at the mean and the tail on the complete machine; the two agree once the three assumptions are aligned
(section 13 of multi-family-adversary.md: 1.93x at 0.581 placed, 2.09x at 0.72 placed; 2.69x at 0.72 synthesised
on the board identity, the 10.0q figure). The programme's hybrid r0 is the placed, complete-machine, mean-hit
figure.
### 4.2 The window-conditioned 72 percent against the flat control, as the brief states it
The brief reads: the hottest half serves 72 percent because the window model concentrates traffic, and a flat
distribution would give 50 percent. The record's reading (census-packs.md section 3): the 72 percent is the p98
program on the window-conditioned null, the mean over programs is 0.581, and a flat control sits at 1.1 to 1.7x of
the window model's top-0.1-percent share (printed beside the census, not used). The layer-8-off experiment is
PERFORMED and CLOSED (register row 18): with the windows removed the hit of the hottest half is exactly 0.50 at
every program (multi-family-adversary.md section 13 (5)), and the honest side at the knee loses 5.7 percent of rate
and 3.6 to 5.7 percent of joules, so the layer stays ON. The chip-side arithmetic of the brief's conditional cache
calculation holds (misses 0.50 against 0.419 at the mean, +19 percent of DRAM reads; against 0.28 at the tail, +79
percent) and the placed rows say what it buys: the hybrid at hit 0.50 reads 1.85x against 1.93x at the mean and
2.09x at the tail, 4 percent at the mean, 11 at the tail; the honest side pays more than that at the knee. X1 is the
new-consensus-version form of the same question (a class v7 shape without the fixed windows, everything else
frozen) and its traces replace this arithmetic on the hybrid rows when they land.
### 4.3 Layer-8-off and compaction in any figure
Layer 8 off is in NO served or placed figure (every GPU row and every chip row above carries the windows ON; the
hit-0.50 row is a labelled variant). Result compaction (X2) is in NO figure on either side.
### 4.4 The wall-power boundary, both sides
The GPU side's boundary is the card's board power (nvidia-smi, 1 Hz, idle not subtracted), the card alone through
cards-off: it excludes the host, the PSU's loss and the fans' share beyond the card's own. The chip side's boundary
is the complete machine (the core, the memory, the controller and PHY, PSU and VRM losses, cooling, the host's
share). The two are not the same boundary: the GPU's host, PSU loss and case fans are NOT in its 2.33, while the
chip carries about 21 percent of power-train loss, 3 percent of cooling and 0.85 W of host. The reconciliation the
programme should carry: either add the GPU's own machine terms (a mining rig's PSU at 92 percent and its host share,
about +10 percent on the card's figure, approximate) or read the chip at the board identity; the first is the honest
one and moves every served ratio up by about 0.1x. It is NOT applied in this file's r0 (the served convention is
kept so every row stays comparable); it is the first of the three assumptions below.
### 4.5 The node scaling applied
Every chip row is stated at ASAP7 and scaled by claimed factors: N5 (the 5090's class, "same node") x0.70, N3 ("a
node ahead") x0.50, N2 x0.36. The served sentence's "2.0x on the GPU's own node" is the N5 column; "2.2x to 2.4x"
the N3. The memory terms do not scale. The GPU side is measured at its own node and never scaled.
## 5. The r0 the programme uses
| Opponent (complete machine, placed core, same node N5) | r0 | Range | Source rows |
|---|---|---|---|
| The pure DRAM board | 1.5x | 1.3x to 1.7x (the SRAM access band and the memory band) | multi-family-adversary.md section 6 at the placed energy; the 32-lane core the same |
| The stored-half hybrid at the mean hit 0.581 | 1.93x | 1.65x to 2.12x | section 13 (placed) |
| The stored-half hybrid at the tail hit 0.72 (the 10.0q case) | 2.09x | 1.78x to 2.29x | section 13 (placed) |
| The N2 SRAM die | 2.3x | 2.0x to 2.7x | section 6 at the placed energy |
**The reconciled r0 the programme uses is the worst credible opponent's: the pure DRAM board at 1.5x (1.3x to
1.7x) same-node; the hybrid at 1.93x (1.65x to 2.12x) is the X5 sweep's starting row and X1's target.** The
yardstick from 1.5x to 1.5x is nothing; from the hybrid's 1.93x, a 22 percent GPU cut or a 29 percent specialist
rise. A node ahead: the board 1.8x (1.5x to 2.0x), the hybrid 2.4x (2.05x to 2.63x).
The three assumptions most likely to move r0:
1. The boundary mismatch (4.4): putting the GPU's own PSU loss and host share into its figure moves every ratio up
about 0.1x (the board to about 1.6x, the hybrid to about 2.1x), approximate.
2. The frozen-tree control against the class v4 numerator: the served 2.33 is class v4 on a 7 October job; the
frozen class v6 object reads 4.011 microjoules at the lock on the l8off kit's export at the research pairing (a
9 October job on a card reading 13 percent low). The chip's shadow at class v6's op count is the same core on
102,612 ops; if the honest card's class v6 energy per hash is 4.0 against the chip's 1.53, the board ratio reads
2.6x and the hybrid 3.3x, which is the number the programme must reconcile first: either the class v6 object
costs the 5090 1.7x what class v4 did (then the chip's shadow op count for class v6 must be re-read from the
frozen program, not from class v4's 102,100) or the l8off job's absolute is the enclosure-swap artefact. The
hash lane's paired control (class v4 and class v6 in one session on one card, same kit) decides it; until it
lands r0 stays on the class v4 pair.
3. The SRAM macro's access energy (the one modelled chip term; 2.0 to 7.0 pJ per access gives the band's width) and
the hybrid's hit rate (0.50 with the windows off, 0.581 mean, 0.72 tail).
## 5a. The decider in (the hash lane, 09:59 UK): assumption 2 is real, and what it does to r0
One session on a rented RTX 5090 (Vast 54992886, driver 580.105.08, the gen-6 Linux CUDA worker sha 804a6f7f…, 250 batches of
2^24 per pack, board power at 1 Hz, mean from 8 s in, idle not subtracted, stock only; evidence
build-1:/srv/artefacts/tas/x0-pins/x0-run-fk-5090c/, run-x0.log sha 9bc40685…, smi.csv 7ab9f16f…): class v4 v4-devnet-epoch0
(0xa785001687d8688a, fingerprint e370fb2080b7dbb1) 141.963 MH/s at 500.0 W = 3,522 nJ per hash; the frozen class v6 hl-v6-all
(0x9d40978601a7df2a, 59e6708e46f1e87c) 70.900 at 445.1 W = 6,278 nJ; the signing object hl-v6-all-cs (0x2a1d6caab4c24564,
01f51b9d4805e5e6) 70.650 at 457.1 W = 6,470 nJ. Class v6 over class v4: 1.78x and 1.84x in joules per hash, 2.00x in rate; the
house 5090's own pair 1.68x at stock and 1.73x at the 1,300 MHz knee (2,319 against 4,011 nJ). So the served numerator (2.33
microjoules, class v4) understates the frozen object's card cost by about 1.7x, and the only class v6 lock row is 4.01
microjoules per hash on the house 5090.
What it does to r0: the chip must be paired with the card on the same program. X4's read of the exported texts (10:0x UK)
gives the frozen object 256 loads per hash against class v4's 128, so the card's doubled cost per hash is doubled work, and
the chip's memory term doubles with it while its shadow (carried at class v4's 102,612 ALU ops until the hash lane's count lands)
does not. On the consistent class v6 pair (the card 4.011 microjoules at the knee, the chip at 256 loads) every ratio moves UP,
not down: X5's sweep (section 2, pair B) reads the DRAM board 1.85x (1.5x to 2.1x), the stored-half hybrid 2.53x, the N2 die 4.0x
(3.4x to 4.4x) same-node. The earlier worry (a 1.7x structural card cost the chip does not share) is not what the data say: the
cost is loads, which the chip pays too. The programme's r0 is therefore pair B's, with pair A (the served class v4 convention:
the board 1.5x, the hybrid 1.93x, the die 2.44x) kept as the served convention's row until the ALU count lands:
| Opponent, same node | r0, pair A (class v4: the card 2.319, 128 loads) | r0, pair B (the frozen object: the card 4.011, 256 loads, the shadow at class v4's count) | Source |
|---|---|---|---|
| The pure DRAM board | 1.5x (1.3 to 1.7) | 1.85x (1.5 to 2.1) | X5's sweep on the placed core |
| The stored-half hybrid, mean hit | 1.93x (1.65 to 2.12) | 2.53x | the same |
| The N2 SRAM die (the worst credible design) | 2.44x (2.05 to 2.66) | 4.0x (3.4 to 4.4) | the same |
The hash lane's per-family count (10:11 UK): the frozen object executes 62,120 ALU instructions per hash (loads 256, the base
1,024, the per-load address path 5,376, the shadow 55,296 unchanged, the reg64 init and fold 168); class v4 about 56,300; the card
halves its rate on the read count, which the chip pays too. That settles assumption 2 and opens the largest term of all: every
placed chip row charges the chip 102,612 ops per hash (the record's counted-op convention, from which the card's 0.652
microjoules reads 6.4 pJ per counted op), but the chip executes one instruction per lane-op, so at the instruction count its
shadow energy is 0.36 to 0.41 microjoules instead of 0.67 and every ratio rises by 1.3x to 1.6x (X5 section 2: the board 2.05x
and 2.2x, the die 4.3x and 6.3x same-node on the two pairs). Both counts are carried until the hash lane defines the counted op
(asked 10:1x UK, default 10:45); the instruction count is the chip's physics and the default.
## 5b. The amendment (the coordinator's order, 10:1x UK; every row WITNESS E_D): the frozen object's own numerator, the instruction count, the measured hits
Two facts change every chip ratio. (1) The decider (5a): the frozen class v6 object does twice the random dataset reads per hash of
class v4 (256 against 128) with 9 to 10 percent more ALU (62,120 instructions against about 56,300; the hash lane's per-family
read of the signing object, 10:11 UK); the card pays 1.78x to 1.84x the joules per hash at stock on the rented 5090 and 1.68x at
stock / 1.73x at the knee on the house 5090. (2) The units fault (the hash lane, 10:13 UK, from the record's own units table,
attack-pass/f1-shadow.md section 1 and shadow-k.md section 1): the record's "counted op" is unit B, the GPU's micro-op tally (add
5, rotr 2, shfl 2, every other family 1: 1.83 per shadow instruction), so the 102,100 counted ops per class v4 hash are 55,296
instructions; the chip executes one instruction per lane-op and its k was derived per instruction (algorithm.md 5.3), so every
placed row that multiplied 102,612 counted ops by a per-instruction chip energy (chip-model-v3's re-reads, the design document's
10.0r, this lane's sections 4, 6, 13 of multi-family-adversary.md and X5's first tables) overstated the chip's shadow term by
1.85x. The record's own gate unit is the instruction (unit A); the chip datapath count (unit C, rotates as wiring, the constants
hoisted) is lower still, about 50,100 per class v4 hash.
Recomputed on the placed 8-lane 18-family core's per-family energies (ASAP7 placed with SPEF, N5 x0.70, N3 x0.50, claimed)
weighted by the frozen object's own per-family instruction counts: the chip's ALU energy per hash 0.312 microjoules at N5 (0.280
to 0.388; 0.231 at unit C with the rotates as wiring), 0.225 at N3; 5.05 pJ per instruction at N5 (3.64 at N3). The GPU numerator
is the frozen object's own measured joules per hash: the house 5090 at the 1,300 MHz knee 4.011 microjoules (run-ca3-pc1-l8off-5090-
20261008, hl-v6-all, the only class v6 lock row; the card alone, nvidia-smi board power at 1 Hz, idle not subtracted); at stock
6.470 (the signing object on the rented 5090, x0-run-fk-5090c). The board-power boundary excludes the rig's PSU loss and host,
which the chip's machine carries; the wall-meter column adds 10 percent to the card's figure for them (approximate, unmeasured).
The hybrid's hit rate is the measured one for the hottest half: 0.56 on the signing object, 0.61 the mean over programs (the
quarter and three quarters scaled by the same ratio); 0.72 is the p98 tail and is not used. 256 loads per hash on both sides.
Nothing here is a chip measurement; every row is a modelled witness; no pass and no fail is claimed on these lines.
| Opponent (WITNESS E_D, complete machine) | microjoules per hash, same node (band) | USD per MH/s | Knee, same node, hit 0.56 (signing) | Knee, same node, hit 0.61 (mean) | Knee + the wall-meter term (+10 percent on the card) | Stock, same node | Knee, a node ahead | Stock, a node ahead |
|---|---|---|---|---|---|---|---|---|
| The pure DRAM board | 1.707 (1.516 to 2.112) | 8.91 | 2.35x (1.90 to 2.65) | 2.35x (1.90 to 2.65) | 2.58x (2.09 to 2.91) | 3.79x (3.06 to 4.27) | 2.51x (2.02 to 2.83) | 4.05x (3.26 to 4.57) |
| The hybrid, the hottest quarter | 1.362 (1.222 to 1.679) | 7.02 | 2.86x (2.32 to 3.19) | 2.94x (2.39 to 3.28) | 3.24x (2.63 to 3.61) | 4.75x (3.85 to 5.29) | 3.20x (2.59 to 3.58) | 5.16x (4.18 to 5.77) |
| The hybrid, the hottest half | 1.077 (0.973 to 1.322) | 5.11 | 3.49x (2.84 to 3.86) | 3.73x (3.03 to 4.12) | 4.10x (3.34 to 4.54) | 6.01x (4.89 to 6.65) | 4.15x (3.36 to 4.60) | 6.69x (5.43 to 7.42) |
| The hybrid, the hottest three quarters | 0.894 (0.811 to 1.094) | 3.77 | 4.03x (3.29 to 4.45) | 4.49x (3.67 to 4.95) | 4.94x (4.03 to 5.44) | 7.24x (5.91 to 7.98) | 5.11x (4.16 to 5.64) | 8.25x (6.71 to 9.11) |
| The full SRAM die (one N2 reticle) at 1 kW | 0.513 (0.464 to 0.622) | 0.68 | 7.81x (6.45 to 8.65) | 7.81x (6.45 to 8.65) | 8.60x (7.10 to 9.51) | 12.60x (10.41 to 13.95) | 10.01x (8.22 to 11.13) | 16.15x (13.26 to 17.95) |
| Recomputation | 7.000 (6.459 to 8.238) | 7.74 | 0.51x (0.44 to 0.55) | 0.57x (0.49 to 0.62) | 0.63x (0.54 to 0.68) | 0.92x (0.79 to 1.00) | 0.77x (0.66 to 0.84) | 1.25x (1.06 to 1.35) |
The one sentence: at the frozen object's own numerator and the instruction count, the pure DRAM board as a complete machine sits
ABOVE 1.5x by 0.85x (2.35x same-node at the knee, band 1.90x to 2.65x; 2.58x with the wall-meter term; 3.79x at stock; 2.51x a node
ahead), the stored-half hybrid at the measured hit 3.5x to 3.7x, and the N2 SRAM die, the worst credible design and the
programme's a (0.513 microjoules per hash, 0.464 to 0.622), 7.8x; the earlier 1.5x read was two errors in the honest side's
favour (class v4's numerator against a class v6 chip, and the GPU's micro-op tally charged to the chip), not the chip's cost.
What this means for the yardstick: r_new = r0 x g / a from the board's 2.35x needs a 36 percent GPU cut at a = 1 (a 15 plus 20
split reaches 1.66x); from the die's 7.8x no candidate within the brief's arithmetic reaches 1.5x on energy, which puts the
die's hold where the coexistence model put it (its dollars and its project), and the per-joule target at the board. X5's rows
and X6's blind run follow this line; the served energy sentence should not be re-worded from this file (the panel reads it).
## 6. BLOCKED rows
| Row | Why | Owner |
|---|---|---|
| The class v6 paired control at the lock (the rented pod refuses the clock lock; the stock pair is in, section 5a) | stock done 09:59 UK; the knee pair is the house 5090's 1.73x | the hash lane |
| The definition of the record's "counted op" | CLOSED 10:13 UK: unit B, the GPU's micro-op tally (1.83 per instruction); the chip's unit is the instruction (5b) | the hash lane |
| The chip's op count on the frozen program (the shadow's 55,296 writes in r0..r7, the base program's 512, the loads' 128 at W = 1: read from 1a938abe4's generator, not from class v4) | the chip rows use the class v4 draw's weights; the frozen program's per-family counts are owed | this lane, with the hash lane |
| The GPU's own machine terms (PSU, host) | not measured; approximate +10 percent | the hash lane (a wall meter on the rig) |
## 7. Sources
The hash lane's pin line (09:58 UK) and build-1:/srv/artefacts/tas/x0-pins/; the gpu-row-recipe.md (sha cbab453c…);
docs/analysis/class-v6/multi-family-adversary.md (master e3d0208d); docs/analysis/class-v6/coexistence-model.md (line
537); docs/analysis/class-v6/census-packs.md (sha 146b578c…); docs/design/class-v6-rotating-family.md 10.0h, 10.0i,
10.0q, 10.0r (sha 6eaf43bd…); docs/analysis/counter-asic-4-research.md 15.1a and 20.3 (sha 82af4424…);
docs/analysis/class-v6/floor/denominator.md (sha a4ec182a…); the register rows 18 and 105 to 126.

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@ -0,0 +1,182 @@
# X1: fixed-window removal as a versioned candidate (the class v7 shape), 9 October 2026
The 1.5x programme's X1 (the founder's brief, `docs/plans/igneum-2.0-master/1p5x/igneum-1p5x-experiment-brief.md`; the
matrix in `docs/plans/igneum-2.0-master/1p5x/README.md`). This document lands rows, tools and the candidate's identity.
Nothing activates: the frozen object keeps layer 8 on (`class_v6_family_flags` 0xf), the candidate is a research class
behind its own flag, and no row here is a PASS. Every figure below is printed by `tools/1p5x/x1/summarise.py` from the
row files under `rows/` (the command at the end). UTC in the rows, UK time in the prose.
## 1. The candidate and its identity
| Item | Value |
|---|---|
| Frozen control | class-v6 tree `1a938abe4`, generator 6, class `mx8-erad810f22d+sh256x27+state+reg64c+fold+rw`, igneum-pow/src fingerprint `5f4d6dc6199294db89042171004e6420c1e5791e716d4b39b73d375818c10b6f` (read back at the candidate's merge-base by this lane and by the hash lane, 09:49 UK) |
| Candidate | branch `1p5x-x1-v7` on the box mirror, sha `a99de07cded99a9daa0e5bbd1a6192783322347e` (parent `e4b6bb633`, parent `1a938abe4`) |
| Candidate fingerprint | igneum-pow/src `b9b5d0d1448bc9ce4003b119c66c5734c554c4a84e95b008476a02fb69ae2b54` (the recipe `cd igneum-pow && find src -type f \| LC_ALL=C sort \| xargs shasum -a 256 \| shasum -a 256`; pin confirmed by the hash lane) |
| Candidate class string | `mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat` (on the signing pair) |
| The one flag | `LoadClass::flat`, class suffix `+flat` (outermost), program-id literal `v7flat/`; NOT `+nowin` (layer 8 off, register row 18, closed) |
| What it changes | the window layer does not exist: no window draw is made, every load site has `win = 0, off = 0` and addresses the whole live dataset as `stride(e, x) & mask` (the frozen class's own product, fold and rotation); the family set, the fold, rw1, the state leaves, reg64c and the dataset policy `70a6c703` are the frozen class's |
| The diff | `igneum-pow/src/generator.rs` +39 (the field, `with_flat`, the suffix, the id literal, the draw guard), `accept.rs` (the acceptance shape sets the flag aside like `nowin`), `main.rs` +31 (`--flat` on the export path), `tests/v7flat.rs` (3 tests) |
| Pack shape | generator 6, `program_class` v6: the generator-6 readers (engine, CLI, CUDA, OpenCL, Metal gates) take it unchanged |
| Signing pair (epoch seed `af89be5d...`, era `0:edc4fa84...`, day 20730, node1 state `abb58003...`) | control `2a1d6caab4c24564` (attempt 0), candidate `34d0b421b17fe803` (attempt 1) |
| Packs | `build-1:/srv/artefacts/1p5x/x1/packs/x1-{ctrl,flat}-ds{28,30}.tgz` with sha256 files (ctrl-ds28 `69e009cd...`, ctrl-ds30 `7606c13d...`, flat-ds28 `020dbdc7...`, flat-ds30 `f25160bd...`); the kit lane's zip `packs-x1-20261009T085304Z.zip` (`88f5abf4...`) carries the same four byte for byte |
The export recipe (any epoch seed, era seed and day): `igneum-pow export --out <dir> --epoch-hex <epoch seed> --day-hex <day bytes> --program-class v6 --era-hex <era seed> --state <state stream> --dataset-log2 <28|30> --flat` (omit `--flat` for the control). The control export reproduces the hash lane's `hl-v6-all-cs` pack byte for byte (`kernel.cu` blake2b `c3ee55b0...`).
**What this candidate is, said plainly.** At the program level the class v7 shape is the address form of the closed layer-8-off row (`+nowin` zeroes the windows after drawing them; `+flat` never draws them), so the two differ in the draw stream and the id, not in what a load site reads. The GPU side was therefore expected to repeat register row 18; the new evidence X1 owes is the cache side.
## 2. Native correctness and generation availability
| Row | Result | Evidence |
|---|---|---|
| Crate check | `cargo check --all-targets` clean on build-9 (rustc 1.99.0) | `rows/suite-a99de07cd.log` |
| The pow suite | `cargo test --release --no-fail-fast` on build-9, EXIT 0, every binary green, `tests/v7flat.rs` 3 of 3 (the frozen class string and draw untouched; no window on any instruction of 64 accepted programs under 4 eras, every load `stride & mask` at 2^28 and 2^30; the frozen control keeps live windows) | `rows/suite-a99de07cd.log` |
| A fault found on the frozen tree, not the candidate's | `tests/derive.rs` `stats_beside_x8` overflows under `cargo test` WITHOUT `--release` (a debug-profile multiply at line 191) on `1a938abe4` itself; the gate runs release, where it passes | `rows/suite-a99de07cd.log` (the release run); the debug run's log on build-9 `/srv/builds/x1/logs/suite-e4b6bb633.log` |
| Same work, three contexts on the candidate's own pack | (1) the CLI export path (`--program-class v6 --flat`) draws `34d0b421b17fe803` attempt 1; (2) the class-string recipe (`--class ...+flat --era 0:...`, the census harness) draws the same id and attempt; (3) CUDA on the pack: the self-test PASS on all 32 runs (cache head, last line and FNV, dataset samples, 96 of 96 vector lanes against the CPU reference's vectors) and the 2^24 fingerprint equal on four cards of two architectures (`8cd11a827ac3ffe4` at 1 GiB, `18c4c6a80809c4b9` at 4 GiB); the kit lane's CPU emulation check on `x1-flat-ds28` PASS | `rows/cache/cache-flat-sign.txt`, `rows/cache/export-x1-flat-ds30.txt`, `rows/gpu/*/worker.log` |
| Generation availability | 64 accepted draws (chain-shaped seeds, era `edc4fa84`, 2^30): control 136.0 and 138.3 s, candidate 135.9 and 136.2 s (two runs each, build-9, one thread); the attempts over 256 seeds: control mean 0.176 (215 at 0, 37 at 1, 4 at 2), candidate mean 0.160 (218, 35, 3), 0 exhausted both; the day pack (export at 4 GiB) 2.87 s control and 4.90 s candidate, the extra 2.0 s being the CLI drawing the frozen program first and then the candidate's (an export-path artefact, not the class: the draws above are equal) | `rows/cache/draw-timing.txt`, `rows/cache/model-*-256.txt`, `rows/cache/gen-timing.txt` |
## 3. (a) The census on the candidate (build-8, 09:49 to 09:56 UK)
The frozen live-dataset census jobs verbatim (`live-dataset-census-1a938abe4.md` section 3: the object on the genesis pairing over headers 0 to 7, the 16 chain-shaped seeds p18 to p33, the node1 state, 2^28 words) with the class `+flat`, through `addrsite` of the frozen census harness (`class-v6-census-all4` `b819c23a4`) with the candidate's two commits cherry-picked (branch `1p5x-x1-harness`, binary `bin-h-5264b8152` sha256 `9dc22b1d...`). The control seed p18 was re-run in the same session and reproduces the frozen row to the last digit, so the instrument is the frozen one.
| Run | Program | Reads | Top 0.1 percent share | Against flat | Against window model | Min site distinct ratio | Worst bit (sigma) | Top-K 1 GiB / 256 MiB / 64 MiB |
|---|---|---|---|---|---|---|---|---|
| ctrl-seed-p18 | 0b686c80e25cb4d3 | 67,108,864 | 0.003391 | 1.1032x | 1.0006x | 0.99991 | 3.09 | 1.0000 / 0.4404 / 0.1414 |
| flat-object-h0 | caf198d6c4b4767b | 268,435,456 | 0.001942 | 1.0002x | 1.0000x | 1.00010 | 3.06 | 1.0000 / 0.3316 / 0.0951 |
| flat-object-h4 | caf198d6c4b4767b | 268,435,456 | 0.001942 | 1.0003x | 1.0001x | 1.00006 | -3.11 | 1.0000 / 0.3316 / 0.0951 |
| flat-seed-p18 | 0fc8727ab6190454 | 67,108,864 | 0.003075 | 1.0005x | 0.9993x | 0.99993 | 3.55 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p19 | 7c5149150271b038 | 67,108,864 | 0.003075 | 1.0004x | 1.0013x | 0.99990 | -4.10 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p20 | 8ecb2e06575657b8 | 67,108,864 | 0.003069 | 0.9983x | 0.9992x | 0.99996 | -3.09 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p21 | 8b36c28c52ba99c4 | 67,108,864 | 0.003072 | 0.9990x | 1.0008x | 0.99989 | 3.07 | 1.0000 / 0.4150 / 0.1305 |
| flat-seed-p22 | 970fb4d69b2fe33c | 67,108,864 | 0.003080 | 1.0012x | 1.0036x | 0.99995 | 3.36 | 1.0000 / 0.4152 / 0.1306 |
| flat-seed-p23 | a251a84ef66d3834 | 67,108,864 | 0.003073 | 0.9987x | 0.9990x | 0.99996 | -3.24 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p24 | 46acf991dd1407dd | 67,108,864 | 0.003074 | 1.0005x | 0.9999x | 0.99992 | 4.01 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p25 | b9b94de564ab230b | 67,108,864 | 0.003075 | 0.9996x | 1.0010x | 0.99992 | 3.03 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p26 | 134b855d549b2f7e | 67,108,864 | 0.003071 | 0.9995x | 1.0003x | 0.99991 | 3.73 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p27 | 2d87599f68893d21 | 67,108,864 | 0.003072 | 1.0003x | 0.9980x | 0.99995 | -3.68 | 1.0000 / 0.4150 / 0.1305 |
| flat-seed-p28 | 2e3f0c9b69ebfbbe | 67,108,864 | 0.003071 | 1.0005x | 1.0002x | 0.99993 | 3.26 | 1.0000 / 0.4150 / 0.1305 |
| flat-seed-p29 | 4668c5c8a3f7250e | 67,108,864 | 0.003072 | 0.9998x | 0.9982x | 0.99995 | 2.88 | 1.0000 / 0.4151 / 0.1305 |
| flat-seed-p30 | a62cdf47fc0fe7f8 | 67,108,864 | 0.003072 | 0.9991x | 1.0004x | 0.99991 | -3.42 | 1.0000 / 0.4150 / 0.1305 |
| flat-seed-p31 | bf0d33b7f1958a63 | 67,108,864 | 0.003070 | 1.0001x | 0.9998x | 0.99994 | 4.30 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p32 | 80b54bc0701d7269 | 67,108,864 | 0.003076 | 1.0015x | 1.0008x | 0.99990 | 3.59 | 1.0000 / 0.4151 / 0.1306 |
| flat-seed-p33 | b025a053532694f0 | 67,108,864 | 0.003076 | 1.0018x | 1.0007x | 0.99995 | 3.68 | 1.0000 / 0.4150 / 0.1306 |
Reading: the candidate's live-dataset access distribution is flat to the Poisson floor on all 17 programs. The top 0.1 percent of items hold 0.998x to 1.002x the flat control's share (the frozen class: 1.03x to 1.28x flat on these seeds, 1.10x on the object, its windows by design); every site's distinct ratio sits at 0.99989 to 1.00010; no index bit reaches 4.4 sigma (band 6); the object touches every one of its 16,777,216 items. Nothing new concentrates when the windows go.
## 4. (b) The live memory trace and (c) the cache-hit curves (build-9, 08:45 to 09:01 UTC)
`x1cache` (branch `1p5x-x1-harness` `5264b8152`, `tools/1p5x/x1/cache.sh`): the interpreter's tracing probe on the chain's dataset at 4 GiB (2^30 words, 67,108,864 items of 64 bytes) with the node1 state, the header-bound init words as `addrsite` makes them; 2^22 nonces per program (the frozen trace's N), header 0 the TRAIN half and header 1 the HOLDOUT half (2^21 nonces, 536,870,912 reads each, 256 reads per nonce). The policies: the window-model static set (exact: the items of highest probability from the program's own load sites, a set a chip can compute at the era's start), the train-ranked static set (the brief's train and holdout policy), the in-sample oracle (an upper bound inflated by ranking noise at 8 reads per item), and exact LRU over the holdout stream in warp order from a cold start. `x1model` (`fc6bfaf25`): the exact window-model hot-set mass of 256 accepted chain-shaped seeds.
```
# x1cache: program 2a1d6caab4c24564 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw attempt 0 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 65536 nonces/header 2097152 threads 32
# load sites (instr order): 0:0 1:0 2:1 0:0 1:1 1:0 2:3 0:0 1:0 0:0 2:2 0:0 1:1 0:0 1:0 1:0
# trace: 536870912 train reads, 536870912 holdout reads (256 reads per nonce), 59.0 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0625 0.10:0.1250 0.15:0.1875 0.20:0.2500 0.25:0.3125 0.30:0.3625 0.35:0.4125 0.40:0.4625 0.45:0.5125 0.50:0.5625 0.55:0.6062 0.60:0.6500 0.65:0.6938 0.70:0.7375 0.75:0.7812 0.80:0.8250 0.85:0.8687 0.90:0.9125 0.95:0.9563 1.00:1.0000
# (1) window model: 3 distinct probability levels; max/min item probability 1.4286; max item probability x items 1.2500
policy f=0.25 f=0.50 f=0.75
window-model static 0.3125 0.5625 0.7813
train-ranked static (holdout) 0.2717 0.5240 0.7662
oracle static (in-sample) 0.3775 0.6519 0.8640
LRU (holdout stream, cold start) 0.2506 0.4883 0.7064
# (3) holdout counts per item: mean 8.000; quantiles max 29 p0.1% 19 p1% 16 p10% 12 p25% 10 p50% 8 p75% 6 p90% 4 min 0; untouched items 37303; 177.2 s
```
```
# x1cache: program 34d0b421b17fe803 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 1 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 65536 nonces/header 2097152 threads 32
# load sites (instr order): 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0
# trace: 536870912 train reads, 536870912 holdout reads (256 reads per nonce), 49.5 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0500 0.10:0.1000 0.15:0.1500 0.20:0.2000 0.25:0.2500 0.30:0.3000 0.35:0.3500 0.40:0.4000 0.45:0.4500 0.50:0.5000 0.55:0.5500 0.60:0.6000 0.65:0.6500 0.70:0.7000 0.75:0.7500 0.80:0.8000 0.85:0.8500 0.90:0.9000 0.95:0.9500 1.00:1.0000
# (1) window model: 1 distinct probability levels; max/min item probability 1.0000; max item probability x items 1.0000
policy f=0.25 f=0.50 f=0.75
window-model static 0.2500 0.5000 0.7500
train-ranked static (holdout) 0.2500 0.5000 0.7500
oracle static (in-sample) 0.3657 0.6396 0.8563
LRU (holdout stream, cold start) 0.2457 0.4808 0.6996
# (3) holdout counts per item: mean 8.000; quantiles max 29 p0.1% 18 p1% 15 p10% 12 p25% 10 p50% 8 p75% 6 p90% 5 min 0; untouched items 22336; 171.0 s
```
ctrl, 256 accepted chain-shaped seeds: attempts mean 0.176, max 2
f=0.25: programs 256 min 0.2656 mean 0.3409 median 0.3438 p90 0.4062 max 0.5625
f=0.50: programs 256 min 0.5312 mean 0.6110 median 0.5938 p90 0.6875 max 0.7812
f=0.75: programs 256 min 0.7656 mean 0.8301 median 0.8281 p90 0.8750 max 0.9375
flat, 256 accepted chain-shaped seeds: attempts mean 0.160, max 2
f=0.25: programs 256 min 0.2500 mean 0.2500 median 0.2500 p90 0.2500 max 0.2500
f=0.50: programs 256 min 0.5000 mean 0.5000 median 0.5000 p90 0.5000 max 0.5000
f=0.75: programs 256 min 0.7500 mean 0.7500 median 0.7500 p90 0.7500 max 0.7500
### The brief's conditional cache calculation, re-done with measured numbers
At the half store the miss fraction goes from the control's to the candidate's 0.5000:
| Control reading | Control hit at f = 0.5 | Misses | Candidate misses | Relative miss increase |
|---|---|---|---|---|
| the signing program, window-model static (exact) | 0.5625 | 0.4375 | 0.5000 | +14.3 percent |
| the signing program, train-ranked static (measured, holdout) | 0.5240 | 0.4760 | 0.5000 | +5.0 percent |
| the signing program, LRU (measured) | 0.4883 | 0.5117 | 0.5192 (LRU) | +1.5 percent |
| 256 chain-shaped seeds, window model, mean | 0.6110 | 0.3890 | 0.5000 | +28.5 percent |
| 256 seeds, p90 | 0.6875 | 0.3125 | 0.5000 | +60.0 percent |
| 256 seeds, max | 0.7812 | 0.2188 | 0.5000 | +128.5 percent |
| the brief's reported static figure | 0.72 | 0.28 | 0.50 | +78.6 percent |
What it means. Removing the windows does what the hypothesis says: every static and LRU policy sees the uniform stream and a half store serves exactly half. But the window concentration the hybrid row assumed (72 percent at the half store) is not the frozen object's: the signing program's windows put 56.25 percent of reads in the hottest half (3 probability levels, max to min 1.43), the chain-shaped seeds 61.1 percent on average (53 to 78 percent; 72 percent sits near the 95th percentile). On the signing object the candidate takes the hybrid's half-store misses up by 14.3 percent, not 78.6. This is a miss count, not an energy (the brief's own caveat): the energy is X5's.
## 5. The GPU rows (rented cards, stock; the four sessions 08:48 to 09:11 UTC)
The hash lane's recipe (`build-1:/srv/artefacts/1p5x/gpu-row-recipe.md`, `cbab453c...`): the generator-6 CUDA worker `igneum-worker-cuda-gen6` (sha256 `804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd`), `--bench --batches 250 --batch-log2 24 --block-warps 1 --device 0`, `nvidia-smi` at 1 Hz for the whole session, watts the mean `power.draw` from 8 s into the timed window (the worker's 250 x mean dispatch, ending at the run's end) to its end, board power as the card reports it (no wall meter, idle not subtracted); same-session ABBA pairs per dataset on one card (control, candidate, candidate, control at 1 GiB, then at 4 GiB, 10 s apart); the pack's self-test gates each row. `tools/1p5x/x1/gpu-pairs.sh` ran the sessions, `tools/1p5x/x1/gpu-rows.py` read them. The cards: two RTX 5090 (one host capped at 400 W against a 575 W default, so its rows are a power-capped state; the other at a 500 W limit, unthrottled at 2,932 MHz) and two RTX 4090 at their default 450 W; all rented through the fleet lane, every row on an island, not a network.
| Card (pod) | Dataset | Control MH/s | Candidate MH/s | Rate | Control W | Candidate W | Control nJ/hash | Candidate nJ/hash | g |
|---|---|---|---|---|---|---|---|---|---|
| g5090b | 1 GiB | 70.66 | 70.55 | -0.14% | 400.0 | 400.0 | 5662 | 5669 | 1.0014 |
| g5090b | 4 GiB | 68.66 | 68.59 | -0.10% | 400.0 | 400.0 | 5826 | 5832 | 1.0010 |
| g5090e | 1 GiB | 70.64 | 70.54 | -0.15% | 441.5 | 439.5 | 6249 | 6230 | 0.9970 |
| g5090e | 4 GiB | 68.64 | 68.59 | -0.08% | 448.6 | 440.6 | 6534 | 6423 | 0.9830 |
| g4090b | 1 GiB | 31.30 | 31.28 | -0.06% | 262.4 | 259.9 | 8382 | 8308 | 0.9911 |
| g4090b | 4 GiB | 30.70 | 30.69 | -0.01% | 261.6 | 258.1 | 8521 | 8410 | 0.9869 |
| g4090c | 1 GiB | 31.30 | 31.28 | -0.06% | 251.2 | 248.9 | 8025 | 7958 | 0.9916 |
| g4090c | 4 GiB | 30.70 | 30.69 | -0.01% | 250.8 | 248.2 | 8171 | 8088 | 0.9898 |
The knee: NOT RUN. Rented containers refuse a clock lock (`nvidia-smi -lgc 0,1300`: "does not have permission to change clocks", read on all four cards) and the house rigs are BLOCKED today. The only knee figure for this address form is register row 18 (`+nowin` on the frozen class, the first rig's 5090 at the 1,300 MHz lock: rate -5.7 percent, joules +3.6 percent), which a knee row of this candidate is expected to repeat.
Reading: at stock the candidate costs no card anything (rate within -0.15 percent on all four, joules -1.7 to +0.14 percent; g 0.983 to 1.001, median 0.990). ABBA spread under 0.03 percent of rate on every card; the 5090 at 500 W drifted in watts within a session (431 to 452 W on the control at 1 GiB), which the ABBA mean carries.
## 6. The arithmetic (the brief's yardstick, r_new = r0 x g / a)
g, the GPU side, from the rows: 0.99 at stock (0.983 to 1.001); at the knee row 18's 1.036 is the best estimate until a knee row of this candidate exists. a, the specialist side, is X5's. What the cache rows bound: the window layer only ever reached the hybrid through its stored fraction; even if all of a hybrid's energy per hash were its DRAM misses, its energy rises at most by the miss ratio, a <= 0.5 / 0.4375 = 1.143 on the signing object, 1.285 at the 256-seed mean, 1.786 only at the 72 percent premise. With the hybrid placed at about 2.4x (the coordinator's common brief):
| Case | g | a (upper bound) | r_new from 2.4 |
|---|---|---|---|
| the signing object, stock | 0.99 | 1.143 | 2.08 |
| the 256-seed mean, stock | 0.99 | 1.285 | 1.85 |
| the 72 percent premise, stock | 0.99 | 1.786 | 1.33 |
| the signing object, at the knee (row 18's g) | 1.036 | 1.143 | 2.18 |
| the pure DRAM board (no store: the windows buy it nothing), 1.6x | 0.99 | 1.00 | 1.58 |
| the full-SRAM die (stores everything: uniform does not hurt it), 2.4x | 0.99 | 1.00 | 2.38 |
So on the frozen object's own windows, fixed-window removal moves the hybrid at most from about 2.4x toward 2.1x and leaves the DRAM board and the SRAM die where they are; the 1.5x target is not reached by X1 alone on any measured row. These are bounds on the arithmetic, not a verdict: X5 re-optimises the specialist on the candidate and X6 runs blind.
## 7. BLOCKED and NOT RUN rows
| Row | State | Why, and what unblocks it |
|---|---|---|
| GPU at the knee (5090 at the 1,300 MHz lock, 4090 at its knee) | NOT RUN | rented containers cannot lock clocks; the house rigs unreachable (BLOCKED for every lane today); unblocks on a house rig or a bare-metal rented card with clock control |
| GPU wall power | NOT RUN | no wall meter on rented cards; board power only |
| GPU cohort beyond 5090 and 4090 (5080, AMD, Intel, Apple) | NOT RUN | not in X1's order; X6's cohort |
| Same work on OpenCL and Metal for the candidate's pack | NOT RUN | CUDA only today (the kit carries the OpenCL worker; Metal needs the mini) |
| The specialist side a | BLOCKED on X5 | the adversary lane's sweep re-run on these traces (the x1cache command regenerates any program's stream) |
| A live trace at 2^24 nonces per header (the 64 x 2^24 point the frozen census owes too) | NOT RUN | 50 to 100 core-hours per object |
| Registry batch | NOT RUN, filed | `tools/ci/batches/1p5x-x1-20261009-01.json`, every cell NOT RUN, for the steward to record |
## 8. Reproduce
```
# the tables above, from the row files
python3 tools/1p5x/x1/summarise.py docs/analysis/class-v6/1p5x/x1/rows
# (a) on a box: build branch 1p5x-x1-harness (cargo build --release --bin igneum-pow in igneum-pow), then
tools/1p5x/x1/census.sh # paths inside name build-8's layout; run.sh writes the pid files
# (b) and (c)
tools/1p5x/x1/cache.sh <harness binary> <node1 state stream>
# GPU, on a rented card with the worker and the four packs under /root/x1
tools/1p5x/x1/gpu-pairs.sh <label>; python3 tools/1p5x/x1/gpu-rows.py /root/x1/runs/gpu-<label>
```
Sources by sha: the candidate `a99de07cd` (branch `1p5x-x1-v7`), the harness `fc6bfaf25` (branch `1p5x-x1-harness`, over `b819c23a4`), the frozen control `1a938abe4`, the frozen census rows `docs/analysis/class-v6/rows/live-dataset-census-1a938abe4.md` and `chainseed-census-1a938abe4.md`, register row 18 `docs/analysis/class-v6/rows/pc1-l8off-ds2g-20261009.md`.

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# 2026-10-09T08:45:35Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-5264b8152 x1cache --count 2 --warps 65536 --threads 32 --dataset-log2 30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1 --class mx8+sh256x27+state+reg64c+fold+rw
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# x1cache: program 2a1d6caab4c24564 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw attempt 0 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 65536 nonces/header 2097152 threads 32
# load sites (instr order): 0:0 1:0 2:1 0:0 1:1 1:0 2:3 0:0 1:0 0:0 2:2 0:0 1:1 0:0 1:0 1:0
# trace: 536870912 train reads, 536870912 holdout reads (256 reads per nonce), 59.0 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0625 0.10:0.1250 0.15:0.1875 0.20:0.2500 0.25:0.3125 0.30:0.3625 0.35:0.4125 0.40:0.4625 0.45:0.5125 0.50:0.5625 0.55:0.6062 0.60:0.6500 0.65:0.6938 0.70:0.7375 0.75:0.7812 0.80:0.8250 0.85:0.8687 0.90:0.9125 0.95:0.9563 1.00:1.0000
# (1) window model: 3 distinct probability levels; max/min item probability 1.4286; max item probability x items 1.2500
policy f=0.25 f=0.50 f=0.75
window-model static 0.3125 0.5625 0.7813
train-ranked static (holdout) 0.2717 0.5240 0.7662
oracle static (in-sample) 0.3775 0.6519 0.8640
LRU (holdout stream, cold start) 0.2506 0.4883 0.7064
# (3) holdout counts per item: mean 8.000; quantiles max 29 p0.1% 19 p1% 16 p10% 12 p25% 10 p50% 8 p75% 6 p90% 4 min 0; untouched items 37303; 177.2 s
# end 2026-10-09T08:48:35Z rc 0

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# 2026-10-09T08:45:35Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-5264b8152 x1cache --count 2 --warps 65536 --threads 32 --dataset-log2 30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1 --class mx8+sh256x27+state+reg64c+fold+rw+flat
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# x1cache: program 34d0b421b17fe803 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 1 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 65536 nonces/header 2097152 threads 32
# load sites (instr order): 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0
# trace: 536870912 train reads, 536870912 holdout reads (256 reads per nonce), 49.5 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0500 0.10:0.1000 0.15:0.1500 0.20:0.2000 0.25:0.2500 0.30:0.3000 0.35:0.3500 0.40:0.4000 0.45:0.4500 0.50:0.5000 0.55:0.5500 0.60:0.6000 0.65:0.6500 0.70:0.7000 0.75:0.7500 0.80:0.8000 0.85:0.8500 0.90:0.9000 0.95:0.9500 1.00:1.0000
# (1) window model: 1 distinct probability levels; max/min item probability 1.0000; max item probability x items 1.0000
policy f=0.25 f=0.50 f=0.75
window-model static 0.2500 0.5000 0.7500
train-ranked static (holdout) 0.2500 0.5000 0.7500
oracle static (in-sample) 0.3657 0.6396 0.8563
LRU (holdout stream, cold start) 0.2457 0.4808 0.6996
# (3) holdout counts per item: mean 8.000; quantiles max 29 p0.1% 18 p1% 15 p10% 12 p25% 10 p50% 8 p75% 6 p90% 5 min 0; untouched items 22336; 171.0 s
# end 2026-10-09T08:48:29Z rc 0

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# 2026-10-09T08:44:21Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-5264b8152 x1cache --count 2 --warps 32 --threads 32 --dataset-log2 30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1 --class mx8+sh256x27+state+reg64c+fold+rw
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# x1cache: program 2a1d6caab4c24564 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw attempt 0 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 32 nonces/header 1024 threads 32
# load sites (instr order): 0:0 1:0 2:1 0:0 1:1 1:0 2:3 0:0 1:0 0:0 2:2 0:0 1:1 0:0 1:0 1:0
# trace: 262144 train reads, 262144 holdout reads (256 reads per nonce), 0.0 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0625 0.10:0.1250 0.15:0.1875 0.20:0.2500 0.25:0.3125 0.30:0.3625 0.35:0.4125 0.40:0.4625 0.45:0.5125 0.50:0.5625 0.55:0.6062 0.60:0.6500 0.65:0.6938 0.70:0.7375 0.75:0.7812 0.80:0.8250 0.85:0.8687 0.90:0.9125 0.95:0.9563 1.00:1.0000
# (1) window model: 3 distinct probability levels; max/min item probability 1.4286; max item probability x items 1.2500
policy f=0.25 f=0.50 f=0.75
window-model static 0.3125 0.5616 0.7812
train-ranked static (holdout) 0.2504 0.5012 0.7499
oracle static (in-sample) 1.0000 1.0000 1.0000
LRU (holdout stream, cold start) 0.0020 0.0020 0.0020
# (3) holdout counts per item: mean 0.004; quantiles max 2 p0.1% 1 p1% 0 p10% 0 p25% 0 p50% 0 p75% 0 p90% 0 min 0; untouched items 66847246; 49.9 s
# end 2026-10-09T08:45:13Z rc 0

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@ -0,0 +1,14 @@
# 2026-10-09T08:44:21Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-5264b8152 x1cache --count 2 --warps 32 --threads 32 --dataset-log2 30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1 --class mx8+sh256x27+state+reg64c+fold+rw+flat
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# x1cache: program 34d0b421b17fe803 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 1 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^30 words (memory-hard, 67108864 items of 64 B) headers 2 from 0 (train 1, holdout 1) warps/header 32 nonces/header 1024 threads 32
# load sites (instr order): 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0
# trace: 262144 train reads, 262144 holdout reads (256 reads per nonce), 0.0 s
# (1) window model, hot-set mass at stored fraction f (exact): 0.05:0.0500 0.10:0.1000 0.15:0.1500 0.20:0.2000 0.25:0.2500 0.30:0.3000 0.35:0.3500 0.40:0.4000 0.45:0.4500 0.50:0.5000 0.55:0.5500 0.60:0.6000 0.65:0.6500 0.70:0.7000 0.75:0.7500 0.80:0.8000 0.85:0.8500 0.90:0.9000 0.95:0.9500 1.00:1.0000
# (1) window model: 1 distinct probability levels; max/min item probability 1.0000; max item probability x items 1.0000
policy f=0.25 f=0.50 f=0.75
window-model static 0.2483 0.4992 0.7484
train-ranked static (holdout) 0.2483 0.4992 0.7484
oracle static (in-sample) 1.0000 1.0000 1.0000
LRU (holdout stream, cold start) 0.0019 0.0019 0.0019
# (3) holdout counts per item: mean 0.004; quantiles max 3 p0.1% 1 p1% 0 p10% 0 p25% 0 p50% 0 p75% 0 p90% 0 min 0; untouched items 66847219; 50.8 s
# end 2026-10-09T08:45:14Z rc 0

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@ -0,0 +1,4 @@
ctrl run1 64 accepted draws 135.954324113 s
flat run1 64 accepted draws 135.904787836 s
ctrl run2 64 accepted draws 138.311705871 s
flat run2 64 accepted draws 136.222405217 s

View file

@ -0,0 +1,25 @@
# 2026-10-09T08:47:52Z host igneum-build-9 cmd: /srv/builds/x1/bin-a99de07cd export --out packs-out/x1-ctrl-ds28 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state packs/node1-state.igsd1 --dataset-log2 28
state stream packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/x1-ctrl-ds28
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^28 words (memory-hard), generator v6 attempt 0 program id 2a1d6caab4c24564, loads/hash 128; epoch built in 2529.0 ms
op mix: load=16 add=10 shfl=8 rotl=5 rotr=5 xor=5 mad=4 mul=4 sub=4 mulhi=3; class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/x1-ctrl-ds28/program.json (57646 bytes)
wrote packs-out/x1-ctrl-ds28/identity.json (995 bytes)
wrote packs-out/x1-ctrl-ds28/vectors.json (6435 bytes)
wrote packs-out/x1-ctrl-ds28/kernel.cu (86706 bytes)
wrote packs-out/x1-ctrl-ds28/kernel.cl (94771 bytes)
wrote packs-out/x1-ctrl-ds28/program.h (7694 bytes)
wrote packs-out/x1-ctrl-ds28/vectors.h (5918 bytes)
wrote packs-out/x1-ctrl-ds28/program.metal (82654 bytes)
wrote packs-out/x1-ctrl-ds28/program_bound.metal (82806 bytes)
wrote packs-out/x1-ctrl-ds28/kernel_bound.cu (84481 bytes)
wrote packs-out/x1-ctrl-ds28/kernel_bound.cl (177158 bytes)
wrote packs-out/x1-ctrl-ds28/memhard.h (7369 bytes)
wrote packs-out/x1-ctrl-ds28/memhard.metal (7258 bytes)
vector warp base 0: lane0 1622090e6446f887 lane31 a6a77c3e6146a18e
vector warp base 4096: lane0 a419b22606fe741d lane31 5184fe27855a3c9a
vector warp base 1000000: lane0 082d4fda6ab0e7da lane31 76cdecd145ff0270
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T08:47:55Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T08:47:55Z host igneum-build-9 cmd: /srv/builds/x1/bin-a99de07cd export --out packs-out/x1-ctrl-ds30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state packs/node1-state.igsd1 --dataset-log2 30
state stream packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/x1-ctrl-ds30
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 0 program id 2a1d6caab4c24564, loads/hash 128; epoch built in 2537.2 ms
op mix: load=16 add=10 shfl=8 rotl=5 rotr=5 xor=5 mad=4 mul=4 sub=4 mulhi=3; class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0]
seed words 0x9c8caa3d 0x83537296 0xf21169a4 0x12d4d157 0x66e0ce33 0xcc049080 0x8579c352 0x4c6e4ac9
wrote packs-out/x1-ctrl-ds30/program.json (57646 bytes)
wrote packs-out/x1-ctrl-ds30/identity.json (995 bytes)
wrote packs-out/x1-ctrl-ds30/vectors.json (6458 bytes)
wrote packs-out/x1-ctrl-ds30/kernel.cu (86706 bytes)
wrote packs-out/x1-ctrl-ds30/kernel.cl (94771 bytes)
wrote packs-out/x1-ctrl-ds30/program.h (7694 bytes)
wrote packs-out/x1-ctrl-ds30/vectors.h (5942 bytes)
wrote packs-out/x1-ctrl-ds30/program.metal (82654 bytes)
wrote packs-out/x1-ctrl-ds30/program_bound.metal (82806 bytes)
wrote packs-out/x1-ctrl-ds30/kernel_bound.cu (84481 bytes)
wrote packs-out/x1-ctrl-ds30/kernel_bound.cl (177158 bytes)
wrote packs-out/x1-ctrl-ds30/memhard.h (7369 bytes)
wrote packs-out/x1-ctrl-ds30/memhard.metal (7258 bytes)
vector warp base 0: lane0 66e49c7c7e8ff768 lane31 1be50893eafe01d6
vector warp base 4096: lane0 5a1ed1e578bc6379 lane31 54238f6fabc4f5e5
vector warp base 1000000: lane0 572e7cedf5cbd28c lane31 cd5923c994e9a1c7
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T08:47:58Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T08:47:58Z host igneum-build-9 cmd: /srv/builds/x1/bin-a99de07cd export --out packs-out/x1-flat-ds28 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state packs/node1-state.igsd1 --dataset-log2 28 --flat
state stream packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/x1-flat-ds28
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^28 words (memory-hard), generator v6 attempt 1 program id 34d0b421b17fe803, loads/hash 128; epoch built in 4566.2 ms
op mix: load=16 xor=10 sub=8 add=6 mad=6 shfl=6 rotr=5 rotl=4 mul=3; class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0]
seed words 0xe60ed2a2 0x883319ea 0x6b6aa4f7 0xc4c7864e 0x5d7f9712 0x6027eee6 0x37f56d14 0x9555c104
wrote packs-out/x1-flat-ds28/program.json (57656 bytes)
wrote packs-out/x1-flat-ds28/identity.json (1000 bytes)
wrote packs-out/x1-flat-ds28/vectors.json (6435 bytes)
wrote packs-out/x1-flat-ds28/kernel.cu (85799 bytes)
wrote packs-out/x1-flat-ds28/kernel.cl (93802 bytes)
wrote packs-out/x1-flat-ds28/program.h (7688 bytes)
wrote packs-out/x1-flat-ds28/vectors.h (5918 bytes)
wrote packs-out/x1-flat-ds28/program.metal (81794 bytes)
wrote packs-out/x1-flat-ds28/program_bound.metal (81946 bytes)
wrote packs-out/x1-flat-ds28/kernel_bound.cu (83574 bytes)
wrote packs-out/x1-flat-ds28/kernel_bound.cl (175220 bytes)
wrote packs-out/x1-flat-ds28/memhard.h (7369 bytes)
wrote packs-out/x1-flat-ds28/memhard.metal (7258 bytes)
vector warp base 0: lane0 83fb47bf0f22157b lane31 4a4ef60478466c75
vector warp base 4096: lane0 585856e5af7b2752 lane31 be7d4bfef849d1c6
vector warp base 1000000: lane0 853e2ad04bc31a15 lane31 e0330b1c45fcb6a5
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T08:48:03Z rc 0

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@ -0,0 +1,25 @@
# 2026-10-09T08:48:03Z host igneum-build-9 cmd: /srv/builds/x1/bin-a99de07cd export --out packs-out/x1-flat-ds30 --epoch-hex af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 --day-hex 69676e65756d2d6461792ffa50000000000000 --program-class v6 --era-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state packs/node1-state.igsd1 --dataset-log2 30 --flat
state stream packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
igneum-pow export packs-out/x1-flat-ds30
seed "igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000", day "bytes:69676e65756d2d6461792ffa50000000000000", dataset 2^30 words (memory-hard), generator v6 attempt 1 program id 34d0b421b17fe803, loads/hash 128; epoch built in 4585.0 ms
op mix: load=16 xor=10 sub=8 add=6 mad=6 shfl=6 rotr=5 rotl=4 mul=3; class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0]
seed words 0xe60ed2a2 0x883319ea 0x6b6aa4f7 0xc4c7864e 0x5d7f9712 0x6027eee6 0x37f56d14 0x9555c104
wrote packs-out/x1-flat-ds30/program.json (57656 bytes)
wrote packs-out/x1-flat-ds30/identity.json (1000 bytes)
wrote packs-out/x1-flat-ds30/vectors.json (6458 bytes)
wrote packs-out/x1-flat-ds30/kernel.cu (85799 bytes)
wrote packs-out/x1-flat-ds30/kernel.cl (93802 bytes)
wrote packs-out/x1-flat-ds30/program.h (7688 bytes)
wrote packs-out/x1-flat-ds30/vectors.h (5942 bytes)
wrote packs-out/x1-flat-ds30/program.metal (81794 bytes)
wrote packs-out/x1-flat-ds30/program_bound.metal (81946 bytes)
wrote packs-out/x1-flat-ds30/kernel_bound.cu (83574 bytes)
wrote packs-out/x1-flat-ds30/kernel_bound.cl (175220 bytes)
wrote packs-out/x1-flat-ds30/memhard.h (7369 bytes)
wrote packs-out/x1-flat-ds30/memhard.metal (7258 bytes)
vector warp base 0: lane0 befcb8f25203629a lane31 40a2ec6c88d253e1
vector warp base 4096: lane0 61cad00f0dced854 lane31 40fda71998029103
vector warp base 1000000: lane0 f3e24f8a530f2ba5 lane31 74e39329549863df
cache FNV-1a 64 448274a57f508cbc
OVERALL: PASS (pack written)
# end 2026-10-09T08:48:08Z rc 0

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@ -0,0 +1,10 @@
ctrl 1 2.874449269
flat 1 4.907988679
ctrl 2 2.848766497
flat 2 4.884445411
ctrl 3 2.868956005
flat 3 4.885651751
ctrl 4 2.885697000
flat 4 4.923610101
ctrl 5 2.874501765
flat 5 4.923965116

View file

@ -0,0 +1,262 @@
# 2026-10-09T08:51:49Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-fc6bfaf25 x1model --count 256 --header-from 0 --seed igneum-attack-f8/program/ --dataset-log2 30 --class mx8+sh256x27+state+reg64c+fold+rw --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07
seed program attempt windows(k:off) mass_f0.25 mass_f0.50 mass_f0.75
igneum-attack-f8/program/0 568d26d6a417d6f4 0 0:0 1:0 2:3 1:0 1:0 2:0 0:0 0:0 1:0 1:0 1:0 2:3 1:0 2:2 1:1 0:0 0.3438 0.6250 0.8438
igneum-attack-f8/program/1 8955f4a4c322643c 0 0:0 0:0 1:0 0:0 0:0 2:0 1:0 2:1 2:1 2:1 1:0 2:3 0:0 1:1 0:0 1:1 0.3750 0.6250 0.8438
igneum-attack-f8/program/2 e758dfa168b7e6e9 0 2:3 1:0 1:0 2:2 0:0 1:1 1:1 2:0 2:3 1:1 0:0 1:1 1:1 2:0 2:0 0:0 0.3281 0.6250 0.8906
igneum-attack-f8/program/3 f7f5ac4a1906e3ab 0 1:1 1:0 0:0 1:1 1:1 1:1 2:2 1:1 1:0 0:0 2:0 0:0 1:1 2:3 0:0 1:1 0.3438 0.6875 0.8750
igneum-attack-f8/program/4 59d9baaffb4413e3 0 0:0 2:0 1:0 1:0 2:2 1:1 0:0 0:0 0:0 0:0 2:1 1:1 2:1 0:0 1:0 2:1 0.3750 0.6250 0.8438
igneum-attack-f8/program/5 a03ef0f2864672cb 0 0:0 1:0 1:0 0:0 0:0 0:0 1:1 1:0 2:2 2:2 0:0 2:0 0:0 2:0 0:0 0:0 0.3438 0.6250 0.8438
igneum-attack-f8/program/6 892d340b89976eb9 1 2:3 2:3 1:0 0:0 1:1 1:1 2:0 1:1 1:0 0:0 1:0 0:0 0:0 1:0 1:1 1:0 0.3125 0.5938 0.8125
igneum-attack-f8/program/7 32bce70d5a2e5988 0 0:0 0:0 0:0 0:0 2:2 0:0 2:0 0:0 1:1 2:2 2:3 0:0 1:1 0:0 2:2 0:0 0.3906 0.6562 0.8594
igneum-attack-f8/program/8 b72728f8287974d1 0 2:2 0:0 0:0 2:1 2:3 0:0 1:0 1:1 0:0 2:2 2:0 0:0 2:1 0:0 1:1 0:0 0.2969 0.5625 0.7969
igneum-attack-f8/program/9 707fab3add04f4fa 0 0:0 0:0 0:0 0:0 2:0 1:0 2:0 0:0 1:1 0:0 2:3 1:0 0:0 2:1 1:0 1:1 0.3281 0.5938 0.8281
igneum-attack-f8/program/10 df880268c35607aa 0 0:0 1:0 0:0 0:0 0:0 2:3 2:3 2:0 2:1 1:0 1:0 2:1 2:0 1:1 1:1 0:0 0.2969 0.5938 0.8594
igneum-attack-f8/program/11 d4a1ab319f55a81d 0 0:0 0:0 1:0 0:0 1:0 1:0 1:0 2:1 0:0 1:1 2:2 1:0 1:0 1:0 1:1 1:1 0.3438 0.6250 0.8438
igneum-attack-f8/program/12 82b413301a9acea6 0 2:0 2:0 0:0 1:1 2:2 1:0 1:0 1:1 2:1 1:1 1:0 0:0 2:1 2:3 2:3 2:1 0.3125 0.5625 0.8125
igneum-attack-f8/program/13 04f86d41ffe73438 0 2:3 1:0 2:0 2:1 0:0 2:0 2:1 1:1 1:1 2:1 2:3 2:1 0:0 1:1 2:0 2:2 0.3125 0.5625 0.8125
igneum-attack-f8/program/14 d90468c7fd569a0c 0 1:1 2:3 1:1 0:0 2:1 1:0 1:1 0:0 0:0 0:0 1:0 1:1 0:0 0:0 2:2 2:2 0.3438 0.6250 0.8438
igneum-attack-f8/program/15 43a1b86d19c31411 1 2:1 1:0 2:2 0:0 2:0 0:0 2:2 0:0 2:1 1:1 1:0 2:1 2:2 1:1 0:0 1:1 0.3438 0.6562 0.8438
igneum-attack-f8/program/16 5786bc5b573af75f 0 0:0 2:2 0:0 2:1 0:0 2:2 2:0 0:0 2:3 1:0 1:0 0:0 1:0 2:1 1:0 2:1 0.3906 0.6562 0.8594
igneum-attack-f8/program/17 b73b3f83686d73bf 0 0:0 0:0 2:2 1:1 0:0 2:0 1:1 0:0 0:0 2:1 2:2 0:0 2:1 0:0 1:1 1:0 0.3281 0.5938 0.7969
igneum-attack-f8/program/18 0b686c80e25cb4d3 0 1:0 0:0 1:1 2:0 2:1 2:0 1:0 2:3 2:0 2:2 2:3 0:0 2:3 1:0 1:1 0:0 0.3281 0.6250 0.8281
igneum-attack-f8/program/19 bf8510cd00c0c70f 0 2:2 2:1 0:0 1:1 2:3 0:0 0:0 0:0 1:1 1:0 1:1 1:1 2:2 2:0 0:0 0:0 0.3438 0.6250 0.8125
igneum-attack-f8/program/20 24133bd7265e958f 0 1:0 2:2 0:0 2:2 1:1 1:0 0:0 0:0 2:3 2:0 1:0 1:0 1:0 2:2 2:0 0:0 0.3438 0.6250 0.8438
igneum-attack-f8/program/21 ed647abf60a5bd32 0 1:0 1:0 0:0 2:0 0:0 0:0 2:0 0:0 1:0 2:2 2:0 0:0 1:0 2:3 1:0 2:3 0.4219 0.6562 0.8594
igneum-attack-f8/program/22 f8e8969443448ecb 0 2:0 0:0 0:0 2:1 1:1 0:0 0:0 1:0 0:0 0:0 0:0 1:1 1:0 2:1 0:0 2:3 0.3125 0.5625 0.8125
igneum-attack-f8/program/23 160649503341aaab 1 2:3 1:0 0:0 1:1 0:0 2:3 0:0 1:1 0:0 1:0 0:0 0:0 0:0 0:0 2:2 0:0 0.3281 0.5938 0.7969
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igneum-attack-f8/program/216 2d667c7f3cdee51b 0 2:0 2:1 0:0 0:0 0:0 0:0 1:1 1:1 0:0 1:0 2:2 0:0 2:0 1:1 2:2 1:1 0.3438 0.5938 0.8125
igneum-attack-f8/program/217 b9be46ea30beedef 0 2:0 0:0 1:1 0:0 1:0 2:2 1:0 1:0 1:0 0:0 2:0 1:1 0:0 0:0 2:2 1:1 0.3281 0.6250 0.8281
igneum-attack-f8/program/218 e3a0dd8c51c6dd19 0 2:0 2:2 0:0 2:2 2:2 1:0 1:1 2:0 2:0 2:3 2:0 0:0 0:0 2:3 0:0 2:0 0.4062 0.6875 0.9062
igneum-attack-f8/program/219 ea6596ed0336cbbe 0 2:1 1:0 2:2 0:0 1:0 1:1 2:2 2:3 1:1 0:0 1:1 2:3 2:0 0:0 1:1 2:0 0.2969 0.5938 0.8281
igneum-attack-f8/program/220 d1f942e4d4dca7d6 0 2:3 2:1 0:0 1:1 2:1 0:0 1:0 0:0 2:1 0:0 0:0 0:0 0:0 2:2 0:0 0:0 0.3594 0.5938 0.8281
igneum-attack-f8/program/221 45e80018394bdacb 0 0:0 0:0 0:0 1:1 0:0 2:0 0:0 1:1 0:0 0:0 1:0 2:2 0:0 1:1 1:0 0:0 0.2969 0.5625 0.7969
igneum-attack-f8/program/222 86a04e69e6eeb702 1 1:0 2:1 2:1 1:1 0:0 0:0 2:0 1:1 0:0 2:1 1:1 1:1 2:2 2:3 1:0 0:0 0.3125 0.5625 0.8125
igneum-attack-f8/program/223 e8d3fdb75ae0b341 0 0:0 0:0 1:1 0:0 2:0 2:3 1:1 1:0 2:0 2:0 1:1 0:0 1:0 0:0 1:1 1:1 0.3281 0.6250 0.8594
igneum-attack-f8/program/224 7c0a5e56b8d25385 0 0:0 1:0 1:0 1:0 1:1 0:0 0:0 2:0 1:1 0:0 1:0 2:0 1:1 0:0 2:3 0:0 0.3438 0.5938 0.8125
igneum-attack-f8/program/225 62902cf6655c3d90 0 2:3 0:0 0:0 0:0 2:2 0:0 0:0 1:0 0:0 1:1 1:0 2:0 2:2 0:0 2:3 0:0 0.2812 0.5625 0.8125
igneum-attack-f8/program/226 bba4a32171bf71b5 1 0:0 0:0 0:0 1:1 1:1 1:1 1:0 0:0 0:0 1:0 2:2 0:0 1:0 2:2 2:0 2:0 0.3125 0.6250 0.8125
igneum-attack-f8/program/227 ab38477d5543a7dd 0 1:0 0:0 2:2 0:0 0:0 2:0 1:0 0:0 0:0 0:0 2:0 1:1 2:1 0:0 2:0 0:0 0.3750 0.6250 0.8438
igneum-attack-f8/program/228 7d111865d771f734 0 2:2 1:0 2:0 0:0 2:0 2:2 0:0 1:0 0:0 0:0 0:0 1:0 0:0 0:0 1:0 0:0 0.3750 0.6250 0.8750
igneum-attack-f8/program/229 e2f7ccf6dbaaf6da 0 0:0 2:2 1:1 1:0 0:0 2:0 0:0 2:3 1:0 1:0 0:0 2:1 0:0 0:0 0:0 0:0 0.2812 0.5625 0.7812
igneum-attack-f8/program/230 2cce395acf0eeb17 0 1:0 0:0 2:3 1:1 1:0 0:0 1:1 2:1 2:0 2:1 1:0 1:0 1:1 0:0 2:0 2:0 0.3594 0.6562 0.8594
igneum-attack-f8/program/231 736dbc061363a9bb 0 1:0 1:0 0:0 1:0 0:0 2:3 1:1 0:0 1:0 2:2 2:1 0:0 1:1 1:1 0:0 0:0 0.2812 0.5312 0.7812
igneum-attack-f8/program/232 c26a46a8637152e3 0 0:0 2:3 0:0 1:1 1:0 1:1 1:1 2:3 1:0 1:1 2:3 0:0 1:0 2:3 2:0 1:1 0.4531 0.6562 0.8594
igneum-attack-f8/program/233 abe9e909ea5ef50d 0 2:1 1:0 1:0 2:0 1:0 0:0 0:0 0:0 2:1 0:0 2:3 0:0 2:3 0:0 2:1 2:3 0.3750 0.6562 0.9062
igneum-attack-f8/program/234 6b9ac091d5be7517 0 2:1 2:3 0:0 1:1 2:2 0:0 1:1 2:0 2:2 0:0 1:0 1:1 2:2 2:2 0:0 0:0 0.4219 0.6562 0.8281
igneum-attack-f8/program/235 fe73f160ad5c14b2 0 0:0 1:1 2:2 1:1 0:0 2:2 0:0 1:1 1:1 2:1 0:0 0:0 1:1 0:0 1:1 2:1 0.4062 0.6875 0.9062
igneum-attack-f8/program/236 fcdb9bddde4226e9 0 2:1 1:1 0:0 1:0 0:0 1:1 2:1 1:0 0:0 0:0 0:0 0:0 0:0 2:3 1:1 0:0 0.3125 0.5938 0.8125
igneum-attack-f8/program/237 9a57d9596b9c6bdb 0 2:1 2:2 0:0 1:0 1:1 0:0 2:0 0:0 2:2 0:0 1:0 0:0 0:0 2:1 1:0 0:0 0.3281 0.5938 0.8594
igneum-attack-f8/program/238 e3016a33e5ca1550 0 2:1 2:2 1:1 1:0 1:1 2:3 2:1 1:1 2:2 1:1 0:0 1:0 0:0 0:0 2:1 1:1 0.3281 0.6250 0.8906
igneum-attack-f8/program/239 230693673cd059b6 0 0:0 1:0 2:2 1:0 1:0 2:2 0:0 1:0 2:1 0:0 1:0 0:0 0:0 1:0 2:3 1:1 0.3281 0.5938 0.8281
igneum-attack-f8/program/240 6eb7ea3efc816697 0 1:0 0:0 1:1 0:0 2:2 0:0 2:1 2:3 1:0 0:0 1:0 1:1 1:0 2:1 1:1 0:0 0.3281 0.5625 0.7969
igneum-attack-f8/program/241 5d16c6fbda023aeb 1 0:0 2:2 1:0 1:1 1:1 2:0 1:1 0:0 0:0 0:0 2:3 2:0 2:2 1:1 0:0 1:1 0.3594 0.6562 0.8906
igneum-attack-f8/program/242 5f56c2d02b085f16 0 1:1 1:0 1:0 2:1 2:0 1:0 2:3 2:0 0:0 1:1 1:0 1:1 1:0 0:0 0:0 2:2 0.3281 0.5938 0.7969
igneum-attack-f8/program/243 508ea3c6c8b72cc0 0 1:0 1:0 1:1 2:3 1:0 1:0 0:0 0:0 1:1 2:3 2:1 1:0 2:3 2:2 0:0 1:0 0.2969 0.5938 0.8281
igneum-attack-f8/program/244 2a45fb7f52d29259 1 2:1 2:1 2:0 0:0 0:0 0:0 2:3 2:0 2:0 1:1 0:0 0:0 0:0 2:0 1:1 1:0 0.3750 0.6250 0.8438
igneum-attack-f8/program/245 7db54383dbaa9a1f 0 2:3 2:2 1:0 1:0 1:0 2:2 0:0 0:0 1:1 1:1 2:3 0:0 2:3 1:0 2:3 0:0 0.3750 0.6250 0.8125
igneum-attack-f8/program/246 a1b84d0442e44432 0 2:2 0:0 0:0 2:0 0:0 1:1 0:0 1:0 0:0 1:0 0:0 1:0 1:1 1:1 2:2 0:0 0.3281 0.5938 0.7969
igneum-attack-f8/program/247 38d51861e7cde056 0 2:3 1:0 2:2 1:1 2:2 1:1 0:0 2:1 1:1 1:1 2:3 1:1 0:0 1:0 2:2 0:0 0.3906 0.7188 0.8906
igneum-attack-f8/program/248 77ad6a91c6018adf 0 1:1 0:0 1:0 0:0 2:2 2:3 0:0 2:1 0:0 2:2 1:0 2:2 2:1 1:1 0:0 2:1 0.3281 0.6562 0.8594
igneum-attack-f8/program/249 47780ddee28a68bb 0 0:0 2:2 0:0 0:0 0:0 2:3 1:0 1:0 1:0 0:0 1:1 1:1 1:1 2:2 1:0 0:0 0.3125 0.5625 0.7812
igneum-attack-f8/program/250 100df5f48ac80b36 0 2:1 1:0 1:0 1:1 1:1 0:0 1:1 0:0 1:0 1:0 1:1 0:0 1:1 0:0 2:0 2:3 0.2812 0.5312 0.7812
igneum-attack-f8/program/251 1d5e19d2284c1281 0 0:0 1:1 1:1 2:1 1:0 1:1 2:0 0:0 0:0 2:0 1:1 1:1 2:0 2:1 1:1 1:0 0.2969 0.5312 0.7656
igneum-attack-f8/program/252 f90a785233c79b83 1 1:1 2:0 0:0 0:0 2:1 0:0 1:1 1:0 1:0 1:0 1:1 0:0 1:0 0:0 2:0 0:0 0.3438 0.6250 0.8125
igneum-attack-f8/program/253 98129bd9d05fe504 1 0:0 2:3 2:0 0:0 1:1 1:1 2:1 0:0 1:1 0:0 0:0 0:0 1:1 0:0 2:3 2:1 0.3594 0.5938 0.8281
igneum-attack-f8/program/254 c2c15fb96f4207df 0 2:3 2:3 1:1 2:3 0:0 2:3 2:1 0:0 1:0 0:0 0:0 0:0 2:0 1:1 2:2 0:0 0.4062 0.6250 0.8125
igneum-attack-f8/program/255 387974c34af537ad 0 1:0 2:1 1:1 0:0 1:1 0:0 1:1 0:0 1:1 2:2 0:0 1:0 0:0 1:0 2:3 0:0 0.2812 0.5625 0.8125
# f=0.25: programs 256 min 0.2656 mean 0.3409 median 0.3438 p90 0.4062 max 0.5625
# f=0.50: programs 256 min 0.5312 mean 0.6110 median 0.5938 p90 0.6875 max 0.7812
# f=0.75: programs 256 min 0.7656 mean 0.8301 median 0.8281 p90 0.8750 max 0.9375
# end 2026-10-09T09:00:58Z rc 0

View file

@ -0,0 +1,262 @@
# 2026-10-09T08:51:49Z host igneum-build-9 cmd: /srv/builds/x1/bin-h-fc6bfaf25 x1model --count 256 --header-from 0 --seed igneum-attack-f8/program/ --dataset-log2 30 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07
seed program attempt windows(k:off) mass_f0.25 mass_f0.50 mass_f0.75
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igneum-attack-f8/program/1 24a36c1b4307da39 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/2 d9cab84b908a1ba6 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/3 3f23082c96f90e19 1 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/4 f8ab0b40e18c3ca4 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/5 f286122466d5ef3c 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/6 ceadee7e68a386b7 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
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igneum-attack-f8/program/12 b118940d22a2dcdf 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/13 1c76406c07d70aed 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/14 c88c753c29ad8509 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/15 a173ab9704787cfe 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/16 8d34af47c996ae88 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/17 987bf3c147f8f468 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/18 0fc8727ab6190454 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
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igneum-attack-f8/program/20 8ecb2e06575657b8 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
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igneum-attack-f8/program/32 80b54bc0701d7269 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/33 b025a053532694f0 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/34 50bcf00034aa1f93 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
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igneum-attack-f8/program/249 8fdbfa468bec612c 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/250 c0ab808ce92972ef 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/251 1747e8cee744616e 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/252 b00910422510e131 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/253 e589e0fb8fb2c0e9 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/254 f0460f873caacc08 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
igneum-attack-f8/program/255 44df045133126502 0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0:0 0.2500 0.5000 0.7500
# f=0.25: programs 256 min 0.2500 mean 0.2500 median 0.2500 p90 0.2500 max 0.2500
# f=0.50: programs 256 min 0.5000 mean 0.5000 median 0.5000 p90 0.5000 max 0.5000
# f=0.75: programs 256 min 0.7500 mean 0.7500 median 0.7500 p90 0.7500 max 0.7500
# end 2026-10-09T09:00:59Z rc 0

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# 2026-10-09T08:51:38Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/18 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 0b686c80e25cb4d3 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 261876 0x000e4f1d 3 0.000011
0 1 3 262144 261871 0x05807101 2 0.000008
# worst cell: iteration 0 site 0 address 0x000e4f1d in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 1 8388608 2097152 2080929 0x04b26299 4 0.000002 1.0000 1.0000 0.6154 1.0000 0.5000 0.1250 1.00008 -2.60 22
1 3 1 8388608 2097152 2080879 0x0693accf 3 0.000001 1.0000 1.0000 0.6154 1.0000 0.5000 0.1250 1.00005 -2.51 18
2 6 0 16777216 2097152 2089195 0x0e4e082d 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00011 -1.82 22
3 6 0 16777216 2097152 2089046 0x0ea9550b 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 -1.95 9
4 11 1 8388608 2097152 2080698 0x0e68ce36 3 0.000001 1.0000 1.0000 0.6154 1.0000 0.5000 0.1250 0.99997 -1.88 21
5 11 1 8388608 2097152 2080934 0x0f6682d8 3 0.000001 1.0000 1.0000 0.6155 1.0000 0.5000 0.1250 1.00008 -2.87 7
6 18 2 4194304 2097152 2064883 0x00482c0a 4 0.000002 1.0000 1.0000 0.7130 1.0000 1.0000 0.2500 1.00024 1.85 17
7 18 2 4194304 2097152 2064474 0x0107e1f5 4 0.000002 1.0000 1.0000 0.7127 1.0000 1.0000 0.2500 1.00004 2.09 17
8 27 2 4194304 2097152 2064914 0x066b8f5f 4 0.000002 1.0000 1.0000 0.7132 1.0000 1.0000 0.2500 1.00026 -2.61 3
9 27 2 4194304 2097152 2064236 0x04666edb 4 0.000002 1.0000 1.0000 0.7132 1.0000 1.0000 0.2500 0.99993 3.08 19
10 34 2 4194304 2097152 2064642 0x03de3c5a 3 0.000001 1.0000 1.0000 0.7129 1.0000 1.0000 0.2500 1.00012 2.44 14
11 34 2 4194304 2097152 2064513 0x0214c14a 4 0.000002 1.0000 1.0000 0.7133 1.0000 1.0000 0.2500 1.00006 -1.94 17
12 37 1 8388608 2097152 2080803 0x00fa4c0e 3 0.000001 1.0000 1.0000 0.6153 1.0000 0.5000 0.1250 1.00002 -2.47 19
13 37 1 8388608 2097152 2080758 0x014397ae 3 0.000001 1.0000 1.0000 0.6151 1.0000 0.5000 0.1250 1.00000 -2.26 13
14 40 2 4194304 2097152 2064723 0x0e24ab8d 4 0.000002 1.0000 1.0000 0.7132 1.0000 1.0000 0.2500 1.00016 -2.98 6
15 40 2 4194304 2097152 2064774 0x0ec5a875 4 0.000002 1.0000 1.0000 0.7131 1.0000 1.0000 0.2500 1.00019 -1.61 22
16 41 2 4194304 2097152 2064682 0x03ec6eec 4 0.000002 1.0000 1.0000 0.7131 1.0000 1.0000 0.2500 1.00014 -2.38 9
17 41 2 4194304 2097152 2064788 0x002b996b 3 0.000001 1.0000 1.0000 0.7131 1.0000 1.0000 0.2500 1.00020 2.55 20
18 42 2 4194304 2097152 2064547 0x0857257a 4 0.000002 1.0000 1.0000 0.7127 1.0000 1.0000 0.2500 1.00008 1.76 9
19 42 2 4194304 2097152 2064774 0x0b615202 4 0.000002 1.0000 1.0000 0.7129 1.0000 1.0000 0.2500 1.00019 1.98 6
20 48 2 4194304 2097152 2064698 0x0fd0c838 4 0.000002 1.0000 1.0000 0.7129 1.0000 1.0000 0.2500 1.00015 -2.57 10
21 48 2 4194304 2097152 2064685 0x0c9c58e6 4 0.000002 1.0000 1.0000 0.7129 1.0000 1.0000 0.2500 1.00015 2.09 2
22 50 0 16777216 2097152 2088969 0x0ead2bcb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -2.30 23
23 50 0 16777216 2097152 2088913 0x07668717 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 -1.63 21
24 55 2 4194304 2097152 2064704 0x0ec4fb7c 3 0.000001 1.0000 1.0000 0.7135 1.0000 1.0000 0.2500 1.00016 3.09 16
25 55 2 4194304 2097152 2064810 0x0e5b8c25 3 0.000001 1.0000 1.0000 0.7130 1.0000 1.0000 0.2500 1.00021 1.79 23
26 57 1 8388608 2097152 2080683 0x071707d2 4 0.000002 1.0000 1.0000 0.6152 1.0000 0.5000 0.1250 0.99996 2.26 18
27 57 1 8388608 2097152 2080580 0x018d75a0 3 0.000001 1.0000 1.0000 0.6151 1.0000 0.5000 0.1250 0.99991 -2.78 16
28 60 1 8388608 2097152 2081125 0x0cce7425 3 0.000001 1.0000 1.0000 0.6153 1.0000 0.5000 0.1250 1.00017 -2.33 11
29 60 1 8388608 2097152 2080624 0x0a7f548e 3 0.000001 1.0000 1.0000 0.6152 1.0000 0.5000 0.1250 0.99993 -1.99 14
30 62 0 16777216 2097152 2088835 0x0c4be669 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99994 1.61 15
31 62 0 16777216 2097152 2088964 0x0968d944 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 -1.98 12
# F8 form over the live stream: top 0.1 percent of items hold 0.003391 of reads; flat control 0.003074 (ratio 1.1032x), windowed control 0.003389 (ratio 1.0006x; the gate 1.2x); min site distinct ratio 0.99991 (floors 0.98 and 0.995); worst index bit inside its window 3.09 sigma at site 24 bit 16 (the band 6)
# program: reads 67108864, distinct items 16288897, worst site 0 address 0x04b26299 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4404, 64 MiB 0.1414; the per-site ideal caches summed: 1.0000, 1.0000, 0.6538; 33.4 s
# end 2026-10-09T08:52:14Z rc 0

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# 2026-10-09T08:49:13Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --header-from 0 --warps 8192 --threads 30 --epoch-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program caf198d6c4b4767b class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^28 words (memory-hard) headers 4 warps 8192 nonces/header 262144 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 7 1048576 1046582 0x0ef4d4da 3 0.000003
0 1 7 1048576 1046533 0x014a5fd7 3 0.000003
# worst cell: iteration 0 site 0 address 0x0ef4d4da in 3 reads, share 0.000003
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 7 0 16777216 8388608 8258529 0x044a296f 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00012 2.06 5
1 7 0 16777216 8388608 8258908 0x0203e072 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00017 3.06 6
2 8 0 16777216 8388608 8258741 0x049f213a 4 0.000000 1.0000 0.7132 0.2827 1.0000 0.2500 0.0625 1.00015 -1.59 21
3 8 0 16777216 8388608 8259116 0x0fdcf9a9 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00019 2.13 6
4 9 0 16777216 8388608 8258594 0x08b06953 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00013 1.87 21
5 9 0 16777216 8388608 8259012 0x03dec1c2 4 0.000000 1.0000 0.7132 0.2827 1.0000 0.2500 0.0625 1.00018 -2.42 18
6 10 0 16777216 8388608 8259492 0x069ef837 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00024 -2.97 3
7 10 0 16777216 8388608 8259301 0x045bddf8 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00021 2.34 4
8 11 0 16777216 8388608 8259404 0x04a0d01e 4 0.000000 1.0000 0.7130 0.2825 1.0000 0.2500 0.0625 1.00023 -1.94 10
9 11 0 16777216 8388608 8258543 0x0209ba16 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00012 -2.25 27
10 13 0 16777216 8388608 8258705 0x066bd7ea 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00014 2.14 10
11 13 0 16777216 8388608 8258562 0x0dc78a14 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00012 -2.99 0
12 29 0 16777216 8388608 8258355 0x0ce78c99 4 0.000000 1.0000 0.7132 0.2827 1.0000 0.2500 0.0625 1.00010 2.52 8
13 29 0 16777216 8388608 8259081 0x05824fe7 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00019 2.00 22
14 30 0 16777216 8388608 8258910 0x0489190c 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00017 2.38 27
15 30 0 16777216 8388608 8259478 0x08585a70 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00024 -1.44 16
16 31 0 16777216 8388608 8258868 0x0c482484 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00016 -2.25 21
17 31 0 16777216 8388608 8258517 0x0ae7cc8e 4 0.000000 1.0000 0.7133 0.2827 1.0000 0.2500 0.0625 1.00012 2.31 16
18 44 0 16777216 8388608 8258504 0x090caa6b 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00012 2.86 14
19 44 0 16777216 8388608 8258738 0x032b56ba 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00015 2.70 5
20 46 0 16777216 8388608 8259383 0x0036c34d 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00022 -2.38 4
21 46 0 16777216 8388608 8259230 0x0533c0ca 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00021 -1.84 18
22 47 0 16777216 8388608 8258678 0x09107e29 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00014 2.29 13
23 47 0 16777216 8388608 8259371 0x064a3789 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00022 -2.89 22
24 52 0 16777216 8388608 8258583 0x0bdfbb40 4 0.000000 1.0000 0.7133 0.2827 1.0000 0.2500 0.0625 1.00013 -1.84 9
25 52 0 16777216 8388608 8259300 0x040821ec 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00021 1.87 10
26 56 0 16777216 8388608 8258378 0x09854dc2 4 0.000000 1.0000 0.7132 0.2827 1.0000 0.2500 0.0625 1.00010 2.66 12
27 56 0 16777216 8388608 8258943 0x0c0f7cda 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00017 2.43 19
28 58 0 16777216 8388608 8258905 0x0d4278bb 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00017 -1.84 25
29 58 0 16777216 8388608 8258545 0x01220789 4 0.000000 1.0000 0.7132 0.2826 1.0000 0.2500 0.0625 1.00012 1.97 1
30 63 0 16777216 8388608 8259127 0x0a20cbc4 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00019 2.34 11
31 63 0 16777216 8388608 8258769 0x05434735 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00015 -1.80 23
# F8 form over the live stream: top 0.1 percent of items hold 0.001942 of reads; flat control 0.001942 (ratio 1.0002x), windowed control 0.001942 (ratio 1.0000x; the gate 1.2x); min site distinct ratio 1.00010 (floors 0.98 and 0.995); worst index bit inside its window 3.06 sigma at site 1 bit 6 (the band 6)
# program: reads 268435456, distinct items 16777214, worst site 0 address 0x044a296f in 4 reads (share 0.000000); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.3316, 64 MiB 0.0951; the per-site ideal caches summed: 1.0000, 0.7131, 0.2826; 142.5 s
# end 2026-10-09T08:51:38Z rc 0

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@ -0,0 +1,45 @@
# 2026-10-09T08:49:13Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --header-from 4 --warps 8192 --threads 30 --epoch-hex edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program caf198d6c4b4767b class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day bytes:69676e65756d2d6461792ffa50000000000000 dataset 2^28 words (memory-hard) headers 4 warps 8192 nonces/header 262144 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 7 1048576 1046526 0x01b7dfc8 3 0.000003
0 1 7 1048576 1046479 0x0b718cea 3 0.000003
# worst cell: iteration 5 site 17 address 0x078a27ae in 4 reads, share 0.000004
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 7 0 16777216 8388608 8258910 0x0a6d63a4 4 0.000000 1.0000 0.7130 0.2825 1.0000 0.2500 0.0625 1.00017 -1.67 6
1 7 0 16777216 8388608 8258420 0x03df7b6a 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00011 -3.11 11
2 8 0 16777216 8388608 8258781 0x03d6e97b 4 0.000000 1.0000 0.7132 0.2826 1.0000 0.2500 0.0625 1.00015 -1.93 2
3 8 0 16777216 8388608 8259202 0x0b3d7eef 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00020 -2.46 19
4 9 0 16777216 8388608 8258607 0x0cae64db 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00013 -1.92 3
5 9 0 16777216 8388608 8258827 0x02e43e1a 4 0.000000 1.0000 0.7133 0.2827 1.0000 0.2500 0.0625 1.00016 -2.01 23
6 10 0 16777216 8388608 8258875 0x0f576e4c 4 0.000000 1.0000 0.7132 0.2827 1.0000 0.2500 0.0625 1.00016 -1.58 26
7 10 0 16777216 8388608 8259162 0x022305be 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00020 2.58 9
8 11 0 16777216 8388608 8258418 0x0f038556 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00011 2.27 9
9 11 0 16777216 8388608 8259073 0x00011585 4 0.000000 1.0000 0.7131 0.2826 1.0000 0.2500 0.0625 1.00019 1.87 16
10 13 0 16777216 8388608 8258849 0x08112614 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00016 2.16 5
11 13 0 16777216 8388608 8259306 0x0212f95d 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00021 -2.07 24
12 29 0 16777216 8388608 8258539 0x0e52b3a4 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00012 2.88 1
13 29 0 16777216 8388608 8259121 0x00d3dae3 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00019 2.42 22
14 30 0 16777216 8388608 8258978 0x0151420e 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00017 1.72 18
15 30 0 16777216 8388608 8259331 0x0a7ee620 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00022 -2.21 19
16 31 0 16777216 8388608 8259183 0x0bc9c9e3 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00020 -2.31 5
17 31 0 16777216 8388608 8259182 0x0dcbd756 4 0.000000 1.0000 0.7128 0.2825 1.0000 0.2500 0.0625 1.00020 2.04 12
18 44 0 16777216 8388608 8259950 0x0a190478 4 0.000000 1.0000 0.7132 0.2826 1.0000 0.2500 0.0625 1.00029 -2.80 27
19 44 0 16777216 8388608 8258836 0x05312882 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00016 -2.04 16
20 46 0 16777216 8388608 8258353 0x0f004b17 4 0.000000 1.0000 0.7132 0.2828 1.0000 0.2500 0.0625 1.00010 1.89 26
21 46 0 16777216 8388608 8258661 0x06c8340c 5 0.000001 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00014 1.88 9
22 47 0 16777216 8388608 8258821 0x07423911 4 0.000000 1.0000 0.7133 0.2828 1.0000 0.2500 0.0625 1.00016 2.44 25
23 47 0 16777216 8388608 8259359 0x09001fec 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00022 2.34 11
24 52 0 16777216 8388608 8258951 0x03bcf13a 4 0.000000 1.0000 0.7129 0.2826 1.0000 0.2500 0.0625 1.00017 2.17 4
25 52 0 16777216 8388608 8258769 0x07d27d93 4 0.000000 1.0000 0.7131 0.2827 1.0000 0.2500 0.0625 1.00015 2.36 14
26 56 0 16777216 8388608 8259659 0x04fc83d1 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00026 -1.80 10
27 56 0 16777216 8388608 8258551 0x0081a7a1 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00012 2.18 1
28 58 0 16777216 8388608 8258700 0x04073f7c 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00014 -2.80 14
29 58 0 16777216 8388608 8258933 0x0c83a0a7 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00017 2.08 7
30 63 0 16777216 8388608 8258022 0x07901146 4 0.000000 1.0000 0.7130 0.2827 1.0000 0.2500 0.0625 1.00006 1.93 5
31 63 0 16777216 8388608 8258821 0x06003c70 4 0.000000 1.0000 0.7130 0.2826 1.0000 0.2500 0.0625 1.00016 -2.16 22
# F8 form over the live stream: top 0.1 percent of items hold 0.001942 of reads; flat control 0.001942 (ratio 1.0003x), windowed control 0.001942 (ratio 1.0001x; the gate 1.2x); min site distinct ratio 1.00006 (floors 0.98 and 0.995); worst index bit inside its window -3.11 sigma at site 1 bit 11 (the band 6)
# program: reads 268435456, distinct items 16777216, worst site 21 address 0x06c8340c in 5 reads (share 0.000001); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.3316, 64 MiB 0.0951; the per-site ideal caches summed: 1.0000, 0.7130, 0.2826; 143.3 s
# end 2026-10-09T08:51:39Z rc 0

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# 2026-10-09T08:52:14Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/18 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 0fc8727ab6190454 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 262013 0x04d47d21 2 0.000008
0 1 3 262144 262003 0x06e0286e 2 0.000008
# worst cell: iteration 0 site 8 address 0x01fa4053 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 0 16777216 2097152 2088863 0x0d70afdb 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99995 3.55 19
1 3 0 16777216 2097152 2088999 0x00718a60 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00002 -2.33 25
2 6 0 16777216 2097152 2088988 0x06602aeb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 -1.90 18
3 6 0 16777216 2097152 2088874 0x080da5b5 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99996 3.28 10
4 11 0 16777216 2097152 2089050 0x052b3357 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.74 2
5 11 0 16777216 2097152 2088963 0x0fa45751 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 -2.33 2
6 18 0 16777216 2097152 2088997 0x07e55e31 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00002 2.29 18
7 18 0 16777216 2097152 2088903 0x086758ad 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.53 27
8 27 0 16777216 2097152 2089005 0x05dcf7fc 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 -2.02 11
9 27 0 16777216 2097152 2088896 0x0dd64106 4 0.000002 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 -1.90 19
10 34 0 16777216 2097152 2088997 0x0a007f26 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 3.04 12
11 34 0 16777216 2097152 2088924 0x076e780b 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99998 -2.31 8
12 37 0 16777216 2097152 2089079 0x00ab483c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 1.96 10
13 37 0 16777216 2097152 2088968 0x0374c23a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 2.41 17
14 40 0 16777216 2097152 2088995 0x0803d1f2 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00002 2.18 17
15 40 0 16777216 2097152 2088902 0x05669918 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99997 2.27 1
16 41 0 16777216 2097152 2088873 0x063ab3c9 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 2.02 12
17 41 0 16777216 2097152 2089032 0x096a5e68 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00003 2.99 22
18 42 0 16777216 2097152 2088993 0x0328fed3 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.39 8
19 42 0 16777216 2097152 2089079 0x06b9f809 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 -2.06 3
20 48 0 16777216 2097152 2088813 0x0bbaa25b 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99993 -2.29 26
21 48 0 16777216 2097152 2088992 0x073bfdb2 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 -2.04 2
22 50 0 16777216 2097152 2088912 0x0ab741ca 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.37 16
23 50 0 16777216 2097152 2089105 0x0d2d71fd 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 2.30 4
24 55 0 16777216 2097152 2089050 0x01f522ec 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00004 -2.34 8
25 55 0 16777216 2097152 2089035 0x084eb59c 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00004 2.82 5
26 57 0 16777216 2097152 2088963 0x026624ba 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.10 4
27 57 0 16777216 2097152 2088974 0x0bf93c7d 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 2.38 11
28 60 0 16777216 2097152 2089140 0x0eb09f7b 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00009 -1.83 24
29 60 0 16777216 2097152 2088904 0x034ba031 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99997 -2.05 17
30 62 0 16777216 2097152 2088917 0x0ddf294c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 1.82 22
31 62 0 16777216 2097152 2089025 0x06e22d29 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 2.54 15
# F8 form over the live stream: top 0.1 percent of items hold 0.003075 of reads; flat control 0.003073 (ratio 1.0005x), windowed control 0.003077 (ratio 0.9993x; the gate 1.2x); min site distinct ratio 0.99993 (floors 0.98 and 0.995); worst index bit inside its window 3.55 sigma at site 0 bit 19 (the band 6)
# program: reads 67108864, distinct items 16469311, worst site 9 address 0x0dd64106 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 34.4 s
# end 2026-10-09T08:52:51Z rc 0

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# 2026-10-09T08:52:51Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/19 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 7c5149150271b038 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 262015 0x0d6c09cc 2 0.000008
0 1 3 262144 262007 0x0d1ac661 2 0.000008
# worst cell: iteration 1 site 13 address 0x08438673 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 0 16777216 2097152 2088978 0x05752979 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 2.64 16
1 3 0 16777216 2097152 2089037 0x0c5da287 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 -4.10 10
2 5 0 16777216 2097152 2089013 0x01059509 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 -1.83 5
3 5 0 16777216 2097152 2088956 0x0e47f453 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 1.83 21
4 8 0 16777216 2097152 2088951 0x0d02e28d 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.93 7
5 8 0 16777216 2097152 2088914 0x07859ea3 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.02 16
6 15 0 16777216 2097152 2089156 0x0672c11c 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00009 -3.08 0
7 15 0 16777216 2097152 2089041 0x08b3aa90 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00004 2.47 20
8 16 0 16777216 2097152 2088954 0x0b047fe9 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 -2.07 12
9 16 0 16777216 2097152 2088920 0x0d73acc4 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 -1.86 4
10 18 0 16777216 2097152 2088748 0x06b25e0a 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99990 2.13 19
11 18 0 16777216 2097152 2088950 0x02449cf0 3 0.000001 1.0000 1.0000 0.5604 1.0000 0.2500 0.0625 1.00000 -2.27 27
12 20 0 16777216 2097152 2089003 0x08f25a66 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 2.57 14
13 20 0 16777216 2097152 2089068 0x0f481bdb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -2.27 21
14 24 0 16777216 2097152 2088841 0x048709a8 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99994 -2.53 3
15 24 0 16777216 2097152 2088924 0x065f2b8c 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99998 -2.94 9
16 28 0 16777216 2097152 2088952 0x0167f1da 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 2.04 1
17 28 0 16777216 2097152 2088851 0x0f4d063e 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99995 -2.62 5
18 29 0 16777216 2097152 2089047 0x08220630 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.48 0
19 29 0 16777216 2097152 2088929 0x0aa0d55a 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -1.94 24
20 35 0 16777216 2097152 2088959 0x07d6515e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.10 17
21 35 0 16777216 2097152 2089012 0x0d3a4cc5 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00002 2.41 12
22 41 0 16777216 2097152 2089071 0x04ff4e6d 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00005 -2.27 20
23 41 0 16777216 2097152 2088945 0x012afd86 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 -2.83 12
24 52 0 16777216 2097152 2089082 0x00f8eb35 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 2.24 15
25 52 0 16777216 2097152 2088970 0x087476e0 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00000 2.44 6
26 54 0 16777216 2097152 2088929 0x07030316 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 3.71 13
27 54 0 16777216 2097152 2088975 0x01cd619b 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00001 2.50 12
28 55 0 16777216 2097152 2088901 0x00a07527 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 3.12 23
29 55 0 16777216 2097152 2089044 0x024218b9 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 -2.22 7
30 62 0 16777216 2097152 2088947 0x01563e63 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -2.85 11
31 62 0 16777216 2097152 2089115 0x03a7f0e3 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 -2.08 27
# F8 form over the live stream: top 0.1 percent of items hold 0.003075 of reads; flat control 0.003074 (ratio 1.0004x), windowed control 0.003071 (ratio 1.0013x; the gate 1.2x); min site distinct ratio 0.99990 (floors 0.98 and 0.995); worst index bit inside its window -4.10 sigma at site 1 bit 10 (the band 6)
# program: reads 67108864, distinct items 16469896, worst site 0 address 0x05752979 in 3 reads (share 0.000001); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.1 s
# end 2026-10-09T08:53:27Z rc 0

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@ -0,0 +1,45 @@
# 2026-10-09T08:53:27Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/20 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 8ecb2e06575657b8 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 7 262144 262005 0x0cd36e21 2 0.000008
0 1 7 262144 262032 0x01ca5494 2 0.000008
# worst cell: iteration 0 site 9 address 0x0b5eaa84 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 7 0 16777216 2097152 2089005 0x07bfd0a7 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 -2.31 2
1 7 0 16777216 2097152 2088966 0x0d0d719a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 2.65 1
2 12 0 16777216 2097152 2088966 0x056662f7 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -1.96 3
3 12 0 16777216 2097152 2089082 0x0d5db8cc 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 -2.54 16
4 16 0 16777216 2097152 2089094 0x09a006c2 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 -2.77 7
5 16 0 16777216 2097152 2088919 0x0cda70f4 4 0.000002 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99998 2.90 25
6 21 0 16777216 2097152 2089144 0x067f0ab3 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00009 2.51 8
7 21 0 16777216 2097152 2089093 0x06f6f1cb 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00006 -1.64 14
8 23 0 16777216 2097152 2088904 0x0a3af30c 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.39 13
9 23 0 16777216 2097152 2089005 0x0f345596 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 2.37 18
10 26 0 16777216 2097152 2089072 0x038f9617 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00005 1.85 19
11 26 0 16777216 2097152 2089042 0x0fa3fdd4 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 -2.06 12
12 31 0 16777216 2097152 2088986 0x080df601 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00001 2.10 7
13 31 0 16777216 2097152 2089061 0x01bfad4d 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 -2.06 9
14 37 0 16777216 2097152 2089027 0x09eb8e2b 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 1.97 24
15 37 0 16777216 2097152 2089011 0x01d51e3e 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.11 22
16 42 0 16777216 2097152 2088984 0x0999aca2 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00001 -3.09 12
17 42 0 16777216 2097152 2089071 0x006c11c7 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00005 -2.27 22
18 50 0 16777216 2097152 2089052 0x0f6383ec 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.33 3
19 50 0 16777216 2097152 2089060 0x04e0bc13 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 -2.29 27
20 52 0 16777216 2097152 2088931 0x022762ac 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -3.00 18
21 52 0 16777216 2097152 2088965 0x0ab24ccf 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 -2.72 0
22 55 0 16777216 2097152 2088978 0x0d4bf315 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 1.94 17
23 55 0 16777216 2097152 2089060 0x09530aba 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 -2.19 22
24 56 0 16777216 2097152 2089061 0x0ed6136a 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00005 2.43 9
25 56 0 16777216 2097152 2089060 0x04b7f7ce 4 0.000002 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00005 -2.01 27
26 57 0 16777216 2097152 2088973 0x0f57e01c 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00001 -2.10 25
27 57 0 16777216 2097152 2088937 0x0352e67f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 2.44 5
28 59 0 16777216 2097152 2088866 0x05fb6afe 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99996 2.08 6
29 59 0 16777216 2097152 2089021 0x05a57b13 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 1.69 1
30 61 0 16777216 2097152 2089008 0x0bda5df4 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 2.71 3
31 61 0 16777216 2097152 2089085 0x0734400c 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00006 -2.59 2
# F8 form over the live stream: top 0.1 percent of items hold 0.003069 of reads; flat control 0.003074 (ratio 0.9983x), windowed control 0.003071 (ratio 0.9992x; the gate 1.2x); min site distinct ratio 0.99996 (floors 0.98 and 0.995); worst index bit inside its window -3.09 sigma at site 16 bit 12 (the band 6)
# program: reads 67108864, distinct items 16470450, worst site 5 address 0x0cda70f4 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.2 s
# end 2026-10-09T08:54:03Z rc 0

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# 2026-10-09T08:54:03Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/21 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 8b36c28c52ba99c4 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 1 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 1 262144 261998 0x037f27d5 2 0.000008
0 1 1 262144 262027 0x0b1e16ab 2 0.000008
# worst cell: iteration 0 site 13 address 0x05ef6609 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 1 0 16777216 2097152 2088992 0x04afcc67 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00002 3.05 19
1 1 0 16777216 2097152 2088926 0x094ca722 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 1.93 7
2 2 0 16777216 2097152 2089090 0x0320dbf5 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00006 2.18 27
3 2 0 16777216 2097152 2088793 0x0ca1cf30 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99992 2.50 2
4 9 0 16777216 2097152 2088948 0x093d61c0 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 -1.97 2
5 9 0 16777216 2097152 2089005 0x0f6b6f21 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00002 2.35 25
6 10 0 16777216 2097152 2088973 0x08f8b2e5 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00001 2.81 23
7 10 0 16777216 2097152 2089064 0x042e39a3 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 2.64 25
8 15 0 16777216 2097152 2088927 0x0b4b669f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 -1.78 25
9 15 0 16777216 2097152 2088933 0x0b1903b5 3 0.000001 1.0000 1.0000 0.5605 1.0000 0.2500 0.0625 0.99999 -1.79 8
10 18 0 16777216 2097152 2089136 0x0fc60637 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -2.78 1
11 18 0 16777216 2097152 2088883 0x0c0de7fd 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99996 -1.90 4
12 20 0 16777216 2097152 2089033 0x0bf752d3 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 2.63 17
13 20 0 16777216 2097152 2089080 0x097e37e6 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 1.88 20
14 21 0 16777216 2097152 2088735 0x0b339c7f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99989 -1.74 27
15 21 0 16777216 2097152 2089078 0x0e81c420 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 2.65 25
16 26 0 16777216 2097152 2089157 0x09253f02 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00009 -2.58 26
17 26 0 16777216 2097152 2089014 0x010e831c 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 2.30 19
18 27 0 16777216 2097152 2088961 0x05d8106a 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 2.38 10
19 27 0 16777216 2097152 2088938 0x0e2486e0 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 2.33 16
20 28 0 16777216 2097152 2089075 0x0db10a62 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 1.67 26
21 28 0 16777216 2097152 2088801 0x08f11bc5 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99992 -1.55 10
22 33 0 16777216 2097152 2089104 0x09e9ad9a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00007 -2.09 22
23 33 0 16777216 2097152 2088839 0x009754bf 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99994 -1.76 22
24 39 0 16777216 2097152 2089050 0x089b0edb 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 2.67 6
25 39 0 16777216 2097152 2088968 0x08c2826d 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 2.09 22
26 40 0 16777216 2097152 2089065 0x032093b1 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -1.84 3
27 40 0 16777216 2097152 2088997 0x0dbc95a0 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 -2.14 12
28 41 0 16777216 2097152 2088874 0x036d02c5 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 1.77 0
29 41 0 16777216 2097152 2089049 0x0ad1db67 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 1.23 17
30 46 0 16777216 2097152 2088854 0x0b016dcb 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 1.97 26
31 46 0 16777216 2097152 2088957 0x044fa4bf 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 3.07 15
# F8 form over the live stream: top 0.1 percent of items hold 0.003072 of reads; flat control 0.003075 (ratio 0.9990x), windowed control 0.003070 (ratio 1.0008x; the gate 1.2x); min site distinct ratio 0.99989 (floors 0.98 and 0.995); worst index bit inside its window 3.07 sigma at site 31 bit 15 (the band 6)
# program: reads 67108864, distinct items 16469453, worst site 4 address 0x093d61c0 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4150, 64 MiB 0.1305; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.2 s
# end 2026-10-09T08:54:39Z rc 0

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# 2026-10-09T08:54:39Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/22 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 970fb4d69b2fe33c class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 10 262144 262014 0x009d202b 2 0.000008
0 1 10 262144 261997 0x0e65b272 2 0.000008
# worst cell: iteration 0 site 5 address 0x018af466 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 10 0 16777216 2097152 2088881 0x0b1c0114 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 2.87 13
1 10 0 16777216 2097152 2088960 0x0679b31c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 2.76 24
2 16 0 16777216 2097152 2089003 0x02bdf3cc 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -3.20 24
3 16 0 16777216 2097152 2088974 0x09604e9e 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 2.04 13
4 17 0 16777216 2097152 2089123 0x0d4e8f69 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00008 -2.01 1
5 17 0 16777216 2097152 2088901 0x0b53c497 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99997 1.71 22
6 21 0 16777216 2097152 2088931 0x08e9f816 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99999 3.16 25
7 21 0 16777216 2097152 2088967 0x0c9f6532 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.44 3
8 23 0 16777216 2097152 2089178 0x0b9b3bc5 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00010 -2.21 5
9 23 0 16777216 2097152 2088920 0x01561891 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 2.50 20
10 28 0 16777216 2097152 2088910 0x04589bc8 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99998 -1.78 23
11 28 0 16777216 2097152 2088975 0x0e4031eb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 2.91 19
12 29 0 16777216 2097152 2088967 0x0a6195cc 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 -2.16 4
13 29 0 16777216 2097152 2089056 0x084a33ac 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00005 2.32 17
14 33 0 16777216 2097152 2089005 0x0062bf4b 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 1.97 5
15 33 0 16777216 2097152 2088867 0x005ab6ff 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 1.72 19
16 34 0 16777216 2097152 2088975 0x0a1ef07c 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00001 1.85 14
17 34 0 16777216 2097152 2088947 0x049181a5 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 2.29 24
18 35 0 16777216 2097152 2088950 0x0192064d 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 -2.05 10
19 35 0 16777216 2097152 2089084 0x0579336e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 -2.14 15
20 37 0 16777216 2097152 2089127 0x0f41178d 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00008 -2.06 5
21 37 0 16777216 2097152 2088908 0x0ae8a5c4 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99998 2.65 8
22 40 0 16777216 2097152 2089099 0x0e270828 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 -2.71 25
23 40 0 16777216 2097152 2088897 0x058534f6 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.15 17
24 41 0 16777216 2097152 2088912 0x0fd698ff 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 3.11 1
25 41 0 16777216 2097152 2089018 0x08c95a03 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 3.36 11
26 54 0 16777216 2097152 2089093 0x0f0c4c13 4 0.000002 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00006 2.22 16
27 54 0 16777216 2097152 2089091 0x0194bcb9 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00006 2.49 8
28 61 0 16777216 2097152 2088869 0x07c8900b 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99996 -1.69 27
29 61 0 16777216 2097152 2089111 0x088944c7 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00007 1.80 8
30 62 0 16777216 2097152 2088851 0x084df290 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 -2.35 23
31 62 0 16777216 2097152 2089162 0x0310e410 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00010 2.24 14
# F8 form over the live stream: top 0.1 percent of items hold 0.003080 of reads; flat control 0.003076 (ratio 1.0012x), windowed control 0.003069 (ratio 1.0036x; the gate 1.2x); min site distinct ratio 0.99995 (floors 0.98 and 0.995); worst index bit inside its window 3.36 sigma at site 25 bit 11 (the band 6)
# program: reads 67108864, distinct items 16469845, worst site 26 address 0x0f0c4c13 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4152, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 32.7 s
# end 2026-10-09T08:55:14Z rc 0

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# 2026-10-09T08:51:39Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/23 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program a251a84ef66d3834 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 1 262144 262002 0x0949b834 2 0.000008
0 1 1 262144 262021 0x037b41e5 2 0.000008
# worst cell: iteration 0 site 24 address 0x0b515c41 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 1 0 16777216 2097152 2088878 0x0a253b90 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99996 2.07 22
1 1 0 16777216 2097152 2088932 0x04351dcc 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 -2.48 14
2 3 0 16777216 2097152 2088945 0x00370a0f 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 3.10 5
3 3 0 16777216 2097152 2088943 0x0c80dfca 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 1.65 22
4 9 0 16777216 2097152 2088870 0x0124c8ca 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99996 -2.36 1
5 9 0 16777216 2097152 2089182 0x02c33ed8 3 0.000001 1.0000 1.0000 0.5594 1.0000 0.2500 0.0625 1.00011 -2.53 14
6 13 0 16777216 2097152 2089054 0x070010be 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00004 -2.37 2
7 13 0 16777216 2097152 2089053 0x04bbbdc0 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.45 15
8 15 0 16777216 2097152 2088947 0x01b4ede1 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 -2.86 14
9 15 0 16777216 2097152 2088992 0x06af23ca 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.30 23
10 25 0 16777216 2097152 2089023 0x06c11399 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 -3.06 6
11 25 0 16777216 2097152 2088906 0x06af751e 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99997 1.88 2
12 27 0 16777216 2097152 2088961 0x0206dec8 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 -2.07 14
13 27 0 16777216 2097152 2089063 0x08b414b5 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 2.15 27
14 29 0 16777216 2097152 2089094 0x0391cf98 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00006 -2.78 5
15 29 0 16777216 2097152 2089070 0x0a673011 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00005 -2.11 9
16 37 0 16777216 2097152 2089010 0x0f6ac6b5 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 2.43 2
17 37 0 16777216 2097152 2088995 0x05c7586e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 2.29 26
18 40 0 16777216 2097152 2088949 0x0b02fa99 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 1.52 27
19 40 0 16777216 2097152 2088976 0x048f44b1 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00001 -2.34 19
20 41 0 16777216 2097152 2088884 0x003a8ba3 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 -2.68 7
21 41 0 16777216 2097152 2088929 0x0cd15db4 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 2.24 18
22 42 0 16777216 2097152 2089157 0x03376930 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00009 1.45 14
23 42 0 16777216 2097152 2089030 0x0ee0dcd2 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 2.73 18
24 54 0 16777216 2097152 2088918 0x097703f5 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.60 20
25 54 0 16777216 2097152 2089009 0x00633008 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00002 -1.82 17
26 56 0 16777216 2097152 2088953 0x0e08e22b 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 -3.18 13
27 56 0 16777216 2097152 2088933 0x0592a3c9 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99999 -3.24 17
28 61 0 16777216 2097152 2088924 0x0fd34b86 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 -3.09 25
29 61 0 16777216 2097152 2088901 0x0b0f0272 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 -2.63 24
30 62 0 16777216 2097152 2088942 0x0f12e74f 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 1.47 26
31 62 0 16777216 2097152 2088947 0x0f612cfb 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 2.01 3
# F8 form over the live stream: top 0.1 percent of items hold 0.003073 of reads; flat control 0.003077 (ratio 0.9987x), windowed control 0.003076 (ratio 0.9990x; the gate 1.2x); min site distinct ratio 0.99996 (floors 0.98 and 0.995); worst index bit inside its window -3.24 sigma at site 27 bit 17 (the band 6)
# program: reads 67108864, distinct items 16469867, worst site 0 address 0x0a253b90 in 3 reads (share 0.000001); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 34.8 s
# end 2026-10-09T08:52:16Z rc 0

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# 2026-10-09T08:52:16Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/24 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 46acf991dd1407dd class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 2 262144 262018 0x07076d63 2 0.000008
0 1 2 262144 262005 0x03d7e2f4 2 0.000008
# worst cell: iteration 0 site 3 address 0x0a9ac4fc in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 2 0 16777216 2097152 2089172 0x052400e0 4 0.000002 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00010 2.64 27
1 2 0 16777216 2097152 2089132 0x014c7e2a 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00008 1.80 13
2 14 0 16777216 2097152 2089081 0x0a3b7da4 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 3.94 26
3 14 0 16777216 2097152 2088971 0x0323b1e4 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 -3.11 10
4 15 0 16777216 2097152 2089022 0x076a6c68 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00003 -2.17 5
5 15 0 16777216 2097152 2089047 0x05c5face 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 -2.09 13
6 16 0 16777216 2097152 2088877 0x031fc60c 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99996 1.67 17
7 16 0 16777216 2097152 2088969 0x0aa51a49 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 1.99 24
8 21 0 16777216 2097152 2088872 0x0508aa09 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 -2.18 14
9 21 0 16777216 2097152 2089030 0x075eb22d 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00003 2.06 26
10 26 0 16777216 2097152 2088866 0x0484cb63 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 -2.13 2
11 26 0 16777216 2097152 2089136 0x0bd33ac6 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 2.19 23
12 30 0 16777216 2097152 2088949 0x0802968b 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 2.29 22
13 30 0 16777216 2097152 2088805 0x0cde039b 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99993 1.16 9
14 32 0 16777216 2097152 2089091 0x09153180 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 1.87 25
15 32 0 16777216 2097152 2088946 0x09a3a4b4 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 -3.30 10
16 36 0 16777216 2097152 2088986 0x058ffca9 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 -1.82 14
17 36 0 16777216 2097152 2088908 0x05bc8a10 4 0.000002 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 0.99998 2.19 11
18 39 0 16777216 2097152 2088958 0x0bc30e49 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -3.26 6
19 39 0 16777216 2097152 2088873 0x09a5cb40 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99996 1.96 6
20 44 0 16777216 2097152 2089070 0x0329a31a 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00005 -2.49 2
21 44 0 16777216 2097152 2089057 0x0374a838 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 1.85 10
22 45 0 16777216 2097152 2088979 0x077c37eb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 2.67 18
23 45 0 16777216 2097152 2089052 0x078d3ece 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00004 -3.04 27
24 50 0 16777216 2097152 2089071 0x0b57437c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 2.21 18
25 50 0 16777216 2097152 2088954 0x01731aa5 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 2.01 1
26 60 0 16777216 2097152 2088788 0x0ca5373c 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99992 4.01 2
27 60 0 16777216 2097152 2088919 0x030be571 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 2.31 23
28 61 0 16777216 2097152 2088869 0x0e79fd9d 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 2.02 7
29 61 0 16777216 2097152 2089016 0x0a05bf6c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 -2.11 2
30 63 0 16777216 2097152 2088999 0x018f3b6d 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00002 -1.83 22
31 63 0 16777216 2097152 2088895 0x02e9829f 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99997 2.08 12
# F8 form over the live stream: top 0.1 percent of items hold 0.003074 of reads; flat control 0.003072 (ratio 1.0005x), windowed control 0.003074 (ratio 0.9999x; the gate 1.2x); min site distinct ratio 0.99992 (floors 0.98 and 0.995); worst index bit inside its window 4.01 sigma at site 26 bit 2 (the band 6)
# program: reads 67108864, distinct items 16470237, worst site 0 address 0x052400e0 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 34.3 s
# end 2026-10-09T08:52:53Z rc 0

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# 2026-10-09T08:52:53Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/25 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program b9b94de564ab230b class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 262014 0x05b188b3 2 0.000008
0 1 3 262144 262014 0x05e44411 2 0.000008
# worst cell: iteration 0 site 5 address 0x07d98814 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 0 16777216 2097152 2089017 0x029df03d 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 1.80 9
1 3 0 16777216 2097152 2089015 0x0a697726 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00003 3.00 8
2 5 0 16777216 2097152 2088932 0x0703087e 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 -2.23 0
3 5 0 16777216 2097152 2088906 0x0a151cca 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 1.91 24
4 13 0 16777216 2097152 2088970 0x098edc8f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.27 5
5 13 0 16777216 2097152 2088974 0x092e735c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 -2.45 5
6 15 0 16777216 2097152 2088957 0x027a9dd9 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 2.64 23
7 15 0 16777216 2097152 2088946 0x0f66b34d 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 3.03 9
8 16 0 16777216 2097152 2088853 0x05898a18 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99995 -1.73 12
9 16 0 16777216 2097152 2088957 0x0a3e9225 4 0.000002 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 -1.79 3
10 24 0 16777216 2097152 2089066 0x0882f41d 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 2.66 4
11 24 0 16777216 2097152 2089069 0x01787882 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00005 2.90 26
12 33 0 16777216 2097152 2088907 0x0d693d21 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 -2.97 22
13 33 0 16777216 2097152 2089049 0x02966539 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 2.09 5
14 37 0 16777216 2097152 2088931 0x0619ad5f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -2.19 10
15 37 0 16777216 2097152 2088985 0x02c4a78f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 -2.22 0
16 44 0 16777216 2097152 2089091 0x04c5dbd6 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 -2.42 1
17 44 0 16777216 2097152 2089042 0x0be6ff34 4 0.000002 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00004 -1.95 17
18 45 0 16777216 2097152 2088905 0x0e897766 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 -1.87 15
19 45 0 16777216 2097152 2089063 0x01e1b73c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 1.79 1
20 51 0 16777216 2097152 2088820 0x0a2ca046 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99993 2.97 20
21 51 0 16777216 2097152 2089004 0x0bec6160 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 -2.26 11
22 53 0 16777216 2097152 2088863 0x0ee1b441 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 -1.39 12
23 53 0 16777216 2097152 2089024 0x091559cc 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 1.89 9
24 57 0 16777216 2097152 2089079 0x02de535c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 -2.54 2
25 57 0 16777216 2097152 2088887 0x0f0fd5d6 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 2.72 17
26 59 0 16777216 2097152 2089038 0x00c8f4a0 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 2.26 7
27 59 0 16777216 2097152 2088907 0x0b14dc8e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 2.29 22
28 61 0 16777216 2097152 2089005 0x09de3fda 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 2.16 6
29 61 0 16777216 2097152 2088798 0x027b2270 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99992 -1.95 15
30 62 0 16777216 2097152 2088923 0x06eadea4 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 -2.72 25
31 62 0 16777216 2097152 2088997 0x04459088 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 1.84 7
# F8 form over the live stream: top 0.1 percent of items hold 0.003075 of reads; flat control 0.003076 (ratio 0.9996x), windowed control 0.003072 (ratio 1.0010x; the gate 1.2x); min site distinct ratio 0.99992 (floors 0.98 and 0.995); worst index bit inside its window 3.03 sigma at site 7 bit 9 (the band 6)
# program: reads 67108864, distinct items 16469170, worst site 9 address 0x0a3e9225 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.2 s
# end 2026-10-09T08:53:29Z rc 0

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# 2026-10-09T08:53:29Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/26 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 134b855d549b2f7e class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 262035 0x08e41324 2 0.000008
0 1 3 262144 262019 0x02c436c4 2 0.000008
# worst cell: iteration 2 site 28 address 0x03ac7d1f in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 0 16777216 2097152 2088944 0x0eb7cd17 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 -2.00 14
1 3 0 16777216 2097152 2089128 0x090e751c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00008 2.21 27
2 7 0 16777216 2097152 2089046 0x099ba35a 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00004 3.03 12
3 7 0 16777216 2097152 2089018 0x02ac0bf2 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00003 -2.16 18
4 10 0 16777216 2097152 2088961 0x02aea3c8 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 3.73 3
5 10 0 16777216 2097152 2088903 0x070f00d4 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.48 9
6 17 0 16777216 2097152 2089180 0x05fdb19a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00011 2.57 18
7 17 0 16777216 2097152 2089009 0x0bb44580 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.46 8
8 18 0 16777216 2097152 2088974 0x00966a9c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 -2.75 21
9 18 0 16777216 2097152 2088944 0x09118c95 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 1.92 23
10 19 0 16777216 2097152 2088946 0x039aa4c3 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 2.49 25
11 19 0 16777216 2097152 2088986 0x0bdfd7f8 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 -2.06 22
12 20 0 16777216 2097152 2088866 0x0f57ba9c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99996 -1.84 15
13 20 0 16777216 2097152 2088937 0x0a17a4d6 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 2.25 18
14 23 0 16777216 2097152 2089064 0x0270208f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -1.81 27
15 23 0 16777216 2097152 2089108 0x0f18e3c3 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 2.33 12
16 26 0 16777216 2097152 2089037 0x09515fad 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00004 1.88 15
17 26 0 16777216 2097152 2089042 0x00071bdf 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 -2.34 21
18 27 0 16777216 2097152 2088968 0x041a39ff 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 -2.57 18
19 27 0 16777216 2097152 2089035 0x02cef79f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 -2.39 24
20 28 0 16777216 2097152 2088989 0x08f40a22 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 1.94 18
21 28 0 16777216 2097152 2089025 0x09f8ab60 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00003 2.52 4
22 36 0 16777216 2097152 2088972 0x056ff0ff 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 -2.26 11
23 36 0 16777216 2097152 2088770 0x048cae75 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99991 1.91 22
24 39 0 16777216 2097152 2089108 0x0b779c65 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00007 2.12 8
25 39 0 16777216 2097152 2089068 0x09f7a8c4 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -2.24 17
26 40 0 16777216 2097152 2088966 0x085b9063 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -2.80 9
27 40 0 16777216 2097152 2089040 0x03fbab45 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 2.03 11
28 52 0 16777216 2097152 2088993 0x0ab3446d 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 1.68 21
29 52 0 16777216 2097152 2089000 0x00977b0a 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00002 -2.78 8
30 56 0 16777216 2097152 2088888 0x08b4d646 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 2.12 1
31 56 0 16777216 2097152 2089001 0x0a6be8fd 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 -2.26 24
# F8 form over the live stream: top 0.1 percent of items hold 0.003071 of reads; flat control 0.003073 (ratio 0.9995x), windowed control 0.003071 (ratio 1.0003x; the gate 1.2x); min site distinct ratio 0.99991 (floors 0.98 and 0.995); worst index bit inside its window 3.73 sigma at site 4 bit 3 (the band 6)
# program: reads 67108864, distinct items 16468907, worst site 17 address 0x00071bdf in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5599; 33.3 s
# end 2026-10-09T08:54:05Z rc 0

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# 2026-10-09T08:54:05Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/27 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 2d87599f68893d21 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 3 262144 262020 0x08af8093 2 0.000008
0 1 3 262144 262006 0x0655704c 2 0.000008
# worst cell: iteration 0 site 18 address 0x06ec367b in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 3 0 16777216 2097152 2089107 0x08acd1bb 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 1.71 13
1 3 0 16777216 2097152 2088861 0x0d2f0cc9 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99995 -2.53 17
2 5 0 16777216 2097152 2089204 0x0ee6b0b9 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00012 2.40 17
3 5 0 16777216 2097152 2089104 0x06e44f9f 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 -2.06 25
4 6 0 16777216 2097152 2089105 0x0776cac7 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 -2.91 20
5 6 0 16777216 2097152 2089090 0x0a1d788f 4 0.000002 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00006 1.92 25
6 8 0 16777216 2097152 2089020 0x00c1f410 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 -1.57 0
7 8 0 16777216 2097152 2088949 0x08054bff 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 -2.50 0
8 18 0 16777216 2097152 2089060 0x0b2da370 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00005 -2.39 27
9 18 0 16777216 2097152 2088998 0x0103ba1c 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.43 13
10 20 0 16777216 2097152 2089037 0x0b22af8f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 -2.41 1
11 20 0 16777216 2097152 2088873 0x0fead7ca 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99996 -1.87 20
12 39 0 16777216 2097152 2088893 0x0329de12 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99997 1.90 11
13 39 0 16777216 2097152 2089135 0x08784cf8 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -2.92 16
14 45 0 16777216 2097152 2088984 0x0dbabad4 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 -3.68 19
15 45 0 16777216 2097152 2089033 0x071bbb23 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00003 2.22 20
16 47 0 16777216 2097152 2088957 0x02092d53 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 2.27 20
17 47 0 16777216 2097152 2088965 0x05c68479 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 1.97 12
18 48 0 16777216 2097152 2089108 0x0ed37844 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 1.52 3
19 48 0 16777216 2097152 2088967 0x09d17a85 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 2.21 24
20 50 0 16777216 2097152 2088999 0x064076ce 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 -2.27 5
21 50 0 16777216 2097152 2088970 0x04551e1c 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 -2.12 18
22 51 0 16777216 2097152 2089100 0x0f480dcb 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00007 -2.19 19
23 51 0 16777216 2097152 2089067 0x05429b43 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00005 -1.62 10
24 53 0 16777216 2097152 2089044 0x08fd79b7 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 -2.44 15
25 53 0 16777216 2097152 2088968 0x013261e0 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 2.48 5
26 54 0 16777216 2097152 2088960 0x0cd95df3 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 1.80 17
27 54 0 16777216 2097152 2088993 0x0124bf23 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -2.35 21
28 59 0 16777216 2097152 2089061 0x0ce64ec8 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 2.02 26
29 59 0 16777216 2097152 2088995 0x0d5cc606 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -1.65 18
30 63 0 16777216 2097152 2088939 0x01e7be77 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 -2.25 13
31 63 0 16777216 2097152 2089005 0x0a08741d 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00002 1.83 4
# F8 form over the live stream: top 0.1 percent of items hold 0.003072 of reads; flat control 0.003071 (ratio 1.0003x), windowed control 0.003078 (ratio 0.9980x; the gate 1.2x); min site distinct ratio 0.99995 (floors 0.98 and 0.995); worst index bit inside its window -3.68 sigma at site 14 bit 19 (the band 6)
# program: reads 67108864, distinct items 16469673, worst site 5 address 0x0a1d788f in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4150, 64 MiB 0.1305; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.2 s
# end 2026-10-09T08:54:41Z rc 0

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# 2026-10-09T08:49:13Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/28 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 2e3f0c9b69ebfbbe class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 4 262144 262010 0x02fbb5e2 2 0.000008
0 1 4 262144 261998 0x0bab2cce 2 0.000008
# worst cell: iteration 0 site 16 address 0x083d14d5 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 4 0 16777216 2097152 2088913 0x06693f84 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99998 2.18 5
1 4 0 16777216 2097152 2089015 0x086d837c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00003 -3.17 21
2 8 0 16777216 2097152 2088917 0x0c6c52bf 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.11 0
3 8 0 16777216 2097152 2088990 0x0761482e 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00001 3.26 22
4 9 0 16777216 2097152 2088923 0x05393b54 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 2.95 27
5 9 0 16777216 2097152 2089107 0x09d35f17 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00007 2.10 5
6 11 0 16777216 2097152 2088928 0x03bc82ba 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99998 -2.06 27
7 11 0 16777216 2097152 2088827 0x0bf3c672 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99994 2.60 7
8 12 0 16777216 2097152 2089070 0x0ffc0bd8 4 0.000002 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00005 2.14 0
9 12 0 16777216 2097152 2088977 0x096e39dc 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 2.06 8
10 23 0 16777216 2097152 2089043 0x0852e1cc 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00004 -2.93 25
11 23 0 16777216 2097152 2089014 0x0b5d78f7 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00003 -1.88 21
12 24 0 16777216 2097152 2089013 0x0e259a1c 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00003 -2.99 7
13 24 0 16777216 2097152 2089129 0x0dc781d6 3 0.000001 1.0000 1.0000 0.5604 1.0000 0.2500 0.0625 1.00008 2.32 26
14 26 0 16777216 2097152 2089042 0x0ab207c9 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00004 2.03 22
15 26 0 16777216 2097152 2088960 0x0a01c2c6 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -2.32 8
16 27 0 16777216 2097152 2088807 0x084e9b81 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99993 -2.23 0
17 27 0 16777216 2097152 2088961 0x009a9d9b 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 -2.26 24
18 30 0 16777216 2097152 2088877 0x0c6a402c 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99996 -2.13 13
19 30 0 16777216 2097152 2089234 0x0a57c403 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00013 -1.98 2
20 37 0 16777216 2097152 2088897 0x0892a21c 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 -2.61 5
21 37 0 16777216 2097152 2088959 0x014fa2cf 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 -1.92 15
22 39 0 16777216 2097152 2088853 0x0999d000 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 1.52 0
23 39 0 16777216 2097152 2089077 0x05728f20 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 -2.55 5
24 44 0 16777216 2097152 2088963 0x05ce0723 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 2.78 19
25 44 0 16777216 2097152 2089038 0x07045d16 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 2.54 9
26 52 0 16777216 2097152 2088933 0x003d7b99 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 -2.79 22
27 52 0 16777216 2097152 2089033 0x0c23235b 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 2.04 13
28 53 0 16777216 2097152 2088913 0x01931def 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99998 2.36 27
29 53 0 16777216 2097152 2088968 0x03a3bc56 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 1.86 15
30 63 0 16777216 2097152 2088909 0x0f48e38e 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.07 9
31 63 0 16777216 2097152 2088944 0x0cab2b06 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 2.55 23
# F8 form over the live stream: top 0.1 percent of items hold 0.003071 of reads; flat control 0.003070 (ratio 1.0005x), windowed control 0.003071 (ratio 1.0002x; the gate 1.2x); min site distinct ratio 0.99993 (floors 0.98 and 0.995); worst index bit inside its window 3.26 sigma at site 3 bit 22 (the band 6)
# program: reads 67108864, distinct items 16470460, worst site 8 address 0x0ffc0bd8 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4150, 64 MiB 0.1305; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 36.3 s
# end 2026-10-09T08:49:52Z rc 0

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# 2026-10-09T08:49:52Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/29 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 4668c5c8a3f7250e class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 6 262144 262001 0x09765e7e 2 0.000008
0 1 6 262144 262015 0x0f1624db 2 0.000008
# worst cell: iteration 1 site 25 address 0x0c81e96f in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 6 0 16777216 2097152 2088936 0x00cbfb21 3 0.000001 1.0000 1.0000 0.5604 1.0000 0.2500 0.0625 0.99999 -2.12 15
1 6 0 16777216 2097152 2089137 0x04e07805 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -2.64 10
2 7 0 16777216 2097152 2089045 0x0a37c7ab 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 2.25 11
3 7 0 16777216 2097152 2088917 0x0058ec96 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99998 2.05 18
4 9 0 16777216 2097152 2089040 0x0507eb6e 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 2.88 11
5 9 0 16777216 2097152 2088861 0x0fa1a9b4 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 2.22 13
6 12 0 16777216 2097152 2088955 0x0f2d7f1f 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00000 2.32 10
7 12 0 16777216 2097152 2088847 0x066e5182 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 1.89 7
8 16 0 16777216 2097152 2088872 0x04142011 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 2.52 16
9 16 0 16777216 2097152 2088940 0x07a61573 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -1.93 21
10 21 0 16777216 2097152 2089069 0x099b78c2 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -2.15 0
11 21 0 16777216 2097152 2088962 0x032e67c0 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 -2.33 19
12 32 0 16777216 2097152 2089065 0x0d002a27 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00005 2.26 5
13 32 0 16777216 2097152 2089194 0x09cd132f 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00011 2.31 10
14 33 0 16777216 2097152 2089132 0x0edd0f8f 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00008 -2.20 22
15 33 0 16777216 2097152 2089013 0x0218ea07 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 2.15 24
16 37 0 16777216 2097152 2089049 0x08100de7 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 -1.84 22
17 37 0 16777216 2097152 2088930 0x04caf774 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 2.85 0
18 41 0 16777216 2097152 2088952 0x03aa6f3f 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 2.14 23
19 41 0 16777216 2097152 2089038 0x0759a5df 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 1.82 13
20 42 0 16777216 2097152 2088919 0x07762e2a 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99998 2.16 17
21 42 0 16777216 2097152 2089114 0x0a0ba02a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00007 -1.75 10
22 45 0 16777216 2097152 2088983 0x06097c08 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00001 2.06 8
23 45 0 16777216 2097152 2089058 0x0ee02c87 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 -2.72 4
24 53 0 16777216 2097152 2089049 0x0e2ac3fd 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00004 -1.87 16
25 53 0 16777216 2097152 2088885 0x06034567 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99996 2.10 17
26 54 0 16777216 2097152 2089158 0x0a535262 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00009 -2.53 12
27 54 0 16777216 2097152 2089052 0x07d889ce 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.13 27
28 58 0 16777216 2097152 2089026 0x0aa50cca 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 1.90 6
29 58 0 16777216 2097152 2088997 0x0810edc5 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 -2.33 17
30 61 0 16777216 2097152 2089147 0x002f6829 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00009 1.82 18
31 61 0 16777216 2097152 2088895 0x089b71ac 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 2.79 20
# F8 form over the live stream: top 0.1 percent of items hold 0.003072 of reads; flat control 0.003073 (ratio 0.9998x), windowed control 0.003078 (ratio 0.9982x; the gate 1.2x); min site distinct ratio 0.99995 (floors 0.98 and 0.995); worst index bit inside its window 2.88 sigma at site 4 bit 11 (the band 6)
# program: reads 67108864, distinct items 16470390, worst site 29 address 0x0810edc5 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1305; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 32.6 s
# end 2026-10-09T08:50:27Z rc 0

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@ -0,0 +1,45 @@
# 2026-10-09T08:50:27Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/30 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program a62cdf47fc0fe7f8 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 2 262144 262031 0x019c3fa6 2 0.000008
0 1 2 262144 262017 0x0e364710 2 0.000008
# worst cell: iteration 1 site 11 address 0x02d12a57 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 2 0 16777216 2097152 2089029 0x0a0c30fd 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 -2.40 1
1 2 0 16777216 2097152 2088867 0x0b7eb762 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 2.16 7
2 3 0 16777216 2097152 2089029 0x06af8b41 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 -3.22 8
3 3 0 16777216 2097152 2089091 0x0e024169 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00006 -2.14 16
4 5 0 16777216 2097152 2088889 0x0171f94e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 2.14 21
5 5 0 16777216 2097152 2088902 0x0ba34121 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 -3.14 25
6 7 0 16777216 2097152 2089099 0x0afbfe98 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00007 -2.72 25
7 7 0 16777216 2097152 2089077 0x066a6d55 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00006 -2.27 6
8 10 0 16777216 2097152 2088773 0x0acca259 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99991 1.66 8
9 10 0 16777216 2097152 2089118 0x0a54d085 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -1.98 2
10 12 0 16777216 2097152 2089079 0x02762d74 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00006 2.07 4
11 12 0 16777216 2097152 2088888 0x03d0387a 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99997 3.02 13
12 14 0 16777216 2097152 2088972 0x0d1e9a2f 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00001 -2.20 2
13 14 0 16777216 2097152 2088885 0x02b7f912 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99996 1.58 19
14 35 0 16777216 2097152 2089097 0x092d51dc 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00007 -1.90 24
15 35 0 16777216 2097152 2089149 0x0f5d12c2 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00009 -2.19 19
16 41 0 16777216 2097152 2088981 0x0f1c5b94 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00001 1.51 17
17 41 0 16777216 2097152 2088946 0x009a0348 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 -2.60 9
18 42 0 16777216 2097152 2088822 0x0de8c542 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 0.99993 -2.44 17
19 42 0 16777216 2097152 2088944 0x0803996b 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99999 1.79 27
20 49 0 16777216 2097152 2088993 0x09c5a5a8 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 2.34 18
21 49 0 16777216 2097152 2088843 0x0e381623 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99994 2.55 10
22 50 0 16777216 2097152 2088935 0x0203066a 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 -1.42 26
23 50 0 16777216 2097152 2089029 0x0b6496b2 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 2.12 10
24 54 0 16777216 2097152 2088863 0x0241bf62 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99995 2.18 4
25 54 0 16777216 2097152 2088938 0x0c1c0a7a 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 2.43 6
26 56 0 16777216 2097152 2089130 0x0c51daf6 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -1.96 8
27 56 0 16777216 2097152 2088926 0x0352be37 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 2.41 6
28 58 0 16777216 2097152 2088989 0x09f7b355 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 -3.18 10
29 58 0 16777216 2097152 2088955 0x00fbe891 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 1.98 16
30 62 0 16777216 2097152 2089181 0x0a0b8265 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00011 -3.42 0
31 62 0 16777216 2097152 2089046 0x06a4ac0f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00004 1.88 4
# F8 form over the live stream: top 0.1 percent of items hold 0.003072 of reads; flat control 0.003075 (ratio 0.9991x), windowed control 0.003071 (ratio 1.0004x; the gate 1.2x); min site distinct ratio 0.99991 (floors 0.98 and 0.995); worst index bit inside its window -3.42 sigma at site 30 bit 0 (the band 6)
# program: reads 67108864, distinct items 16470432, worst site 0 address 0x0a0c30fd in 3 reads (share 0.000001); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4150, 64 MiB 0.1305; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 32.7 s
# end 2026-10-09T08:51:02Z rc 0

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# 2026-10-09T08:51:02Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/31 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program bf0d33b7f1958a63 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 1 262144 262010 0x0f118fe5 2 0.000008
0 1 1 262144 262009 0x0a5a99f1 2 0.000008
# worst cell: iteration 1 site 1 address 0x0bdd45f2 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 1 0 16777216 2097152 2088837 0x023a11c7 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99994 2.49 15
1 1 0 16777216 2097152 2089126 0x0f40d924 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 -2.64 20
2 3 0 16777216 2097152 2089062 0x042ccc09 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00005 -1.83 9
3 3 0 16777216 2097152 2088984 0x0f9a90b4 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 2.62 10
4 4 0 16777216 2097152 2088856 0x043aec90 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99995 -1.87 13
5 4 0 16777216 2097152 2089148 0x07494127 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00009 1.85 14
6 7 0 16777216 2097152 2089097 0x0491d46d 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 2.30 1
7 7 0 16777216 2097152 2089013 0x029cbb8a 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00003 2.19 12
8 11 0 16777216 2097152 2088858 0x0d9f51c6 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99995 -1.75 0
9 11 0 16777216 2097152 2088998 0x0a447274 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00002 -2.14 18
10 12 0 16777216 2097152 2089143 0x0bdcdf05 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00009 -2.38 26
11 12 0 16777216 2097152 2089023 0x0f3d7de6 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 1.92 16
12 13 0 16777216 2097152 2089111 0x0b298508 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00007 2.62 15
13 13 0 16777216 2097152 2088850 0x0df7f4c6 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99995 3.30 7
14 21 0 16777216 2097152 2088852 0x0eb7cde7 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99995 -2.54 11
15 21 0 16777216 2097152 2088931 0x0cc2811e 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99999 2.04 3
16 28 0 16777216 2097152 2089116 0x0386e882 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00007 -1.94 22
17 28 0 16777216 2097152 2088862 0x01655610 3 0.000001 1.0000 1.0000 0.5604 1.0000 0.2500 0.0625 0.99995 -3.02 26
18 41 0 16777216 2097152 2089010 0x05d82948 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 -3.10 24
19 41 0 16777216 2097152 2088915 0x05536353 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 4.30 25
20 43 0 16777216 2097152 2089055 0x08a895a9 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 2.65 20
21 43 0 16777216 2097152 2088898 0x0d97029e 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 1.48 8
22 47 0 16777216 2097152 2088966 0x0a1f1673 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00000 3.01 4
23 47 0 16777216 2097152 2088940 0x09a7e2d6 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 2.36 4
24 54 0 16777216 2097152 2088891 0x09419685 4 0.000002 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99997 -1.96 25
25 54 0 16777216 2097152 2089140 0x062a5f90 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00009 -2.46 24
26 56 0 16777216 2097152 2088884 0x0a5ec47b 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99996 -1.26 8
27 56 0 16777216 2097152 2088970 0x0754dc76 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00000 -2.20 22
28 61 0 16777216 2097152 2088851 0x007ab40d 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 1.93 25
29 61 0 16777216 2097152 2088943 0x0a4ff44e 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 -2.48 15
30 62 0 16777216 2097152 2088981 0x08bd7d41 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00001 -2.45 19
31 62 0 16777216 2097152 2089028 0x07622fc6 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00003 2.17 13
# F8 form over the live stream: top 0.1 percent of items hold 0.003070 of reads; flat control 0.003070 (ratio 1.0001x), windowed control 0.003071 (ratio 0.9998x; the gate 1.2x); min site distinct ratio 0.99994 (floors 0.98 and 0.995); worst index bit inside its window 4.30 sigma at site 19 bit 25 (the band 6)
# program: reads 67108864, distinct items 16469093, worst site 2 address 0x042ccc09 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 33.1 s
# end 2026-10-09T08:51:38Z rc 0

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# 2026-10-09T08:51:38Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/32 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program 80b54bc0701d7269 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 7 262144 262006 0x0dbafe13 2 0.000008
0 1 7 262144 262010 0x020705d3 2 0.000008
# worst cell: iteration 0 site 7 address 0x0a82286a in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 7 0 16777216 2097152 2088884 0x0afc3d21 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99996 1.63 15
1 7 0 16777216 2097152 2089071 0x018b5e78 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 2.07 14
2 21 0 16777216 2097152 2088903 0x04f30bf0 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99997 -2.68 1
3 21 0 16777216 2097152 2089175 0x0ac3dcb9 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00010 2.26 6
4 25 0 16777216 2097152 2088905 0x01f28f38 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 1.95 25
5 25 0 16777216 2097152 2088964 0x0ba3850b 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -2.01 16
6 26 0 16777216 2097152 2088758 0x0216a576 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99990 -2.16 23
7 26 0 16777216 2097152 2089106 0x0e01588f 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 2.63 16
8 27 0 16777216 2097152 2088831 0x040db470 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99994 -1.75 27
9 27 0 16777216 2097152 2089030 0x0aec1f01 4 0.000002 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00003 2.69 23
10 28 0 16777216 2097152 2088753 0x01315c66 4 0.000002 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99990 -2.67 17
11 28 0 16777216 2097152 2089058 0x010e9eac 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 -2.58 15
12 31 0 16777216 2097152 2088874 0x0bcc3e55 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99996 3.59 2
13 31 0 16777216 2097152 2088932 0x00f7ab52 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 -2.08 2
14 35 0 16777216 2097152 2088764 0x097aec30 3 0.000001 1.0000 1.0000 0.5604 1.0000 0.2500 0.0625 0.99991 2.49 26
15 35 0 16777216 2097152 2088948 0x09fb1420 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99999 2.80 10
16 39 0 16777216 2097152 2088966 0x0d9d1ecf 4 0.000002 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 -2.98 19
17 39 0 16777216 2097152 2089042 0x0032b1c4 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.62 24
18 40 0 16777216 2097152 2089176 0x00ff9739 3 0.000001 1.0000 1.0000 0.5596 1.0000 0.2500 0.0625 1.00010 2.14 27
19 40 0 16777216 2097152 2089031 0x0c988635 3 0.000001 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00003 1.86 23
20 41 0 16777216 2097152 2088829 0x02a36d70 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 0.99994 -2.29 17
21 41 0 16777216 2097152 2088899 0x0a0aeb92 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99997 1.87 11
22 44 0 16777216 2097152 2089044 0x0081a45b 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00004 2.95 2
23 44 0 16777216 2097152 2088899 0x0bf45ca5 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.36 25
24 48 0 16777216 2097152 2089043 0x068ae437 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00004 -1.73 20
25 48 0 16777216 2097152 2089036 0x05f4c203 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00004 2.09 22
26 55 0 16777216 2097152 2088983 0x03a357c8 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 1.56 0
27 55 0 16777216 2097152 2088966 0x02db64ad 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00000 -1.85 1
28 57 0 16777216 2097152 2089098 0x06f760ff 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00007 2.10 22
29 57 0 16777216 2097152 2089172 0x08021fdb 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00010 -2.67 5
30 62 0 16777216 2097152 2088965 0x098d9aab 4 0.000002 1.0000 1.0000 0.5597 1.0000 0.2500 0.0625 1.00000 -1.95 1
31 62 0 16777216 2097152 2088853 0x0867333a 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99995 -1.83 7
# F8 form over the live stream: top 0.1 percent of items hold 0.003076 of reads; flat control 0.003071 (ratio 1.0015x), windowed control 0.003073 (ratio 1.0008x; the gate 1.2x); min site distinct ratio 0.99990 (floors 0.98 and 0.995); worst index bit inside its window 3.59 sigma at site 12 bit 2 (the band 6)
# program: reads 67108864, distinct items 16470032, worst site 1 address 0x018b5e78 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4151, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 34.8 s
# end 2026-10-09T08:52:16Z rc 0

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# 2026-10-09T08:52:16Z host igneum-build-8 cmd: /srv/builds/x1/bin-h-5264b8152 addrsite --count 4 --warps 2048 --threads 30 --seed igneum-attack-f8/program/33 --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw+flat --era 0:edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07 --state /srv/builds/x1/packs/node1-state.igsd1
state stream /srv/builds/x1/packs/node1-state.igsd1: chain block 159357 af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3, root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, 93 records, 93 leaves
# addrsite: program b025a053532694f0 class mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat attempt 0 generator v6 day 2026-10-03 dataset 2^28 words (memory-hard) headers 4 warps 2048 nonces/header 65536 threads 30
# per (iteration, site) cell: the most read address and its share (A03's form); cells over 0.1 percent listed
it site instr reads distinct top_addr top_count top_share
0 0 4 262144 262031 0x076869ce 2 0.000008
0 1 4 262144 262025 0x04927765 2 0.000008
# worst cell: iteration 1 site 13 address 0x0d6e9359 in 3 reads, share 0.000011
# per site, pooled over the 8 iterations (hit rates: an ideal cache of the site's top K items, K = bytes / 64; exp = min(1, K / window items))
site instr win window_items reads distinct top_addr top_count top_share hit_1GiB hit_256MiB hit_64MiB exp_1GiB exp_256MiB exp_64MiB distinct_ratio bit_z_max bit
0 4 0 16777216 2097152 2089059 0x08845449 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00005 2.78 1
1 4 0 16777216 2097152 2089057 0x0bfeb4f8 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 1.00005 -2.11 6
2 6 0 16777216 2097152 2088997 0x0404ef5a 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00002 2.11 21
3 6 0 16777216 2097152 2089020 0x07136329 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00003 3.68 21
4 7 0 16777216 2097152 2088942 0x0c1392d3 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 2.00 9
5 7 0 16777216 2097152 2088947 0x0cc64fcd 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99999 -2.35 0
6 8 0 16777216 2097152 2088850 0x05032255 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 2.51 0
7 8 0 16777216 2097152 2088907 0x07043c78 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99997 -2.05 1
8 10 0 16777216 2097152 2088922 0x098aff4a 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 1.88 24
9 10 0 16777216 2097152 2088852 0x0f7efb2a 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 0.99995 2.47 7
10 13 0 16777216 2097152 2089103 0x0d596c3e 3 0.000001 1.0000 1.0000 0.5603 1.0000 0.2500 0.0625 1.00007 2.18 21
11 13 0 16777216 2097152 2088974 0x04e16a32 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00001 -2.23 2
12 14 0 16777216 2097152 2088944 0x0bde9be4 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99999 1.67 22
13 14 0 16777216 2097152 2088919 0x0ebc9577 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 2.42 19
14 21 0 16777216 2097152 2088996 0x0baae90c 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00002 2.91 20
15 21 0 16777216 2097152 2088848 0x0173ddcb 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 -1.37 25
16 26 0 16777216 2097152 2088964 0x08124606 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00000 -2.71 19
17 26 0 16777216 2097152 2088966 0x0401aaec 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00000 2.22 21
18 30 0 16777216 2097152 2088909 0x042db705 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99998 -2.42 11
19 30 0 16777216 2097152 2089128 0x06a84ef0 3 0.000001 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00008 2.67 25
20 41 0 16777216 2097152 2088923 0x06977434 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 2.27 19
21 41 0 16777216 2097152 2088983 0x0ed610c1 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00001 2.22 5
22 42 0 16777216 2097152 2089069 0x033cea67 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 1.00005 -3.00 0
23 42 0 16777216 2097152 2089008 0x0336cb88 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 1.00002 -2.56 18
24 43 0 16777216 2097152 2089079 0x0e8ce5ec 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00006 2.14 19
25 43 0 16777216 2097152 2088853 0x06b311df 4 0.000002 1.0000 1.0000 0.5601 1.0000 0.2500 0.0625 0.99995 2.43 3
26 48 0 16777216 2097152 2088919 0x0316cffb 3 0.000001 1.0000 1.0000 0.5602 1.0000 0.2500 0.0625 0.99998 -2.46 0
27 48 0 16777216 2097152 2089151 0x02bf293b 3 0.000001 1.0000 1.0000 0.5598 1.0000 0.2500 0.0625 1.00009 3.44 5
28 49 0 16777216 2097152 2088908 0x00b5d7b7 3 0.000001 1.0000 1.0000 0.5599 1.0000 0.2500 0.0625 0.99998 1.91 13
29 49 0 16777216 2097152 2089130 0x05f205ac 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00008 2.36 23
30 62 0 16777216 2097152 2088890 0x06db693c 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 0.99997 1.85 14
31 62 0 16777216 2097152 2089110 0x02cc4e1e 3 0.000001 1.0000 1.0000 0.5600 1.0000 0.2500 0.0625 1.00007 -2.06 8
# F8 form over the live stream: top 0.1 percent of items hold 0.003076 of reads; flat control 0.003071 (ratio 1.0018x), windowed control 0.003074 (ratio 1.0007x; the gate 1.2x); min site distinct ratio 0.99995 (floors 0.98 and 0.995); worst index bit inside its window 3.68 sigma at site 3 bit 21 (the band 6)
# program: reads 67108864, distinct items 16470798, worst site 22 address 0x033cea67 in 4 reads (share 0.000002); one cache over the program's reads: 1 GiB 1.0000, 256 MiB 0.4150, 64 MiB 0.1306; the per-site ideal caches summed: 1.0000, 1.0000, 0.5600; 34.4 s
# end 2026-10-09T08:52:53Z rc 0

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run pack check fingerprint MH/s W W_inst W_avg sm_MHz mem_MHz util nJ/hash samples
1 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 31.31 262.24 262.19 262.24 2775.00 10251.00 100.00 8376.38 126
2 x1-flat-ds28 PASS 8cd11a827ac3ffe4 31.28 260.46 260.51 260.46 2775.00 10251.00 99.98 8326.31 126
3 x1-flat-ds28 PASS 8cd11a827ac3ffe4 31.28 259.33 259.29 259.33 2775.00 10251.00 100.00 8289.69 126
4 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 31.30 262.53 262.45 262.53 2775.00 10251.00 99.94 8388.29 126
5 x1-ctrl-ds30 PASS b1f90e91cadb15b6 30.70 261.42 261.38 261.42 2775.00 10251.00 100.00 8515.31 129
6 x1-flat-ds30 PASS 18c4c6a80809c4b9 30.69 258.84 258.76 258.84 2775.00 10251.00 99.99 8433.05 128
7 x1-flat-ds30 PASS 18c4c6a80809c4b9 30.69 257.41 257.20 257.41 2775.00 10251.00 99.99 8386.99 129
8 x1-ctrl-ds30 PASS b1f90e91cadb15b6 30.69 261.75 261.74 261.75 2775.00 10251.00 100.00 8527.66 129
PAIR ds28: control 31.30 MH/s 262.4 W 8382 nJ; candidate 31.28 MH/s 259.9 W 8308 nJ; rate -0.06 percent, joules per hash -0.89 percent (g = 0.9911); fingerprints control ['01f51b9d4805e5e6'] candidate ['8cd11a827ac3ffe4']; ABBA spread control 0.03 percent candidate 0.01 percent
PAIR ds30: control 30.70 MH/s 261.6 W 8521 nJ; candidate 30.69 MH/s 258.1 W 8410 nJ; rate -0.01 percent, joules per hash -1.31 percent (g = 0.9869); fingerprints control ['b1f90e91cadb15b6'] candidate ['18c4c6a80809c4b9']; ABBA spread control 0.02 percent candidate 0.01 percent

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@ -0,0 +1,8 @@
# 2026-10-09T08:50:40Z 99b986ba17b1 worker sha256 804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd
GPU 0: NVIDIA GeForce RTX 4090 (UUID: GPU-2209c592-1cbc-72f2-ab2e-dc48f7de281a)
name, driver_version, power.limit [W], power.default_limit [W], clocks.max.sm [MHz], clocks.max.memory [MHz]
NVIDIA GeForce RTX 4090, 595.104.02, 450.00 W, 450.00 W, 3120 MHz, 10501 MHz
The current user does not have permission to change clocks for GPU 00000000:21:00.0.
Terminating early due to previous errors.
The current user does not have permission to change clocks for GPU 00000000:21:00.0.
# end 2026-10-09T09:10:43Z

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### run 1 x1-ctrl-ds28 start 1791535845.374982809
1791535845.631817796 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791535982.397553494 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1559 cache 2 dataset 31 hot 0 check 376 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791535982.398776308 warm-up dispatch (base 0): 535.96 ms; 250 timed dispatches of 16777216 nonces: mean 535.89 ms
1791535982.400036833 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=31.307 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 1 x1-ctrl-ds28 end 1791535982.416381035
### run 2 x1-flat-ds28 start 1791535992.419009779
1791535992.778618104 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536129.490671628 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1415 cache 2 dataset 32 hot 0 check 375 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536129.491888255 warm-up dispatch (base 0): 536.22 ms; 250 timed dispatches of 16777216 nonces: mean 536.33 ms
1791536129.493045782 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=31.281 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 2 x1-flat-ds28 end 1791536129.513038712
### run 3 x1-flat-ds28 start 1791536139.515509138
1791536139.706097926 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536281.254473251 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 6265 cache 2 dataset 31 hot 0 check 371 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536281.255795117 warm-up dispatch (base 0): 536.21 ms; 250 timed dispatches of 16777216 nonces: mean 536.30 ms
1791536281.257227268 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=31.283 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 3 x1-flat-ds28 end 1791536281.275043826
### run 4 x1-ctrl-ds28 start 1791536291.295339137
1791536292.452488003 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536430.323673191 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 2646 cache 2 dataset 31 hot 0 check 378 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536430.324882199 warm-up dispatch (base 0): 535.91 ms; 250 timed dispatches of 16777216 nonces: mean 536.06 ms
1791536430.326102417 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=31.297 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 4 x1-ctrl-ds28 end 1791536430.343614376
### run 5 x1-ctrl-ds30 start 1791536440.346813978
1791536440.543869608 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536580.078431499 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1489 cache 2 dataset 124 hot 0 check 454 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536580.079708014 warm-up dispatch (base 0): 546.53 ms; 250 timed dispatches of 16777216 nonces: mean 546.50 ms
1791536580.081068576 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=30.700 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 5 x1-ctrl-ds30 end 1791536580.097753152
### run 6 x1-flat-ds30 start 1791536590.100963743
1791536590.296823626 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536730.096187735 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1415 cache 2 dataset 124 hot 0 check 375 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536730.123861973 warm-up dispatch (base 0): 546.51 ms; 250 timed dispatches of 16777216 nonces: mean 546.60 ms
1791536730.147271876 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=30.694 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 6 x1-flat-ds30 end 1791536730.318562711
### run 7 x1-flat-ds30 start 1791536740.354763421
1791536740.742270280 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536883.998136496 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 5264 cache 2 dataset 124 hot 0 check 367 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536883.999336600 warm-up dispatch (base 0): 546.54 ms; 250 timed dispatches of 16777216 nonces: mean 546.65 ms
1791536884.000540592 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=30.691 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 7 x1-flat-ds30 end 1791536884.017709481
### run 8 x1-ctrl-ds30 start 1791536894.020141604
1791536894.219191898 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791537033.691509177 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1475 cache 2 dataset 124 hot 0 check 374 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791537033.692753154 warm-up dispatch (base 0): 546.49 ms; 250 timed dispatches of 16777216 nonces: mean 546.59 ms
1791537033.693784263 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=30.694 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 8 x1-ctrl-ds30 end 1791537033.721088923

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@ -0,0 +1,11 @@
run pack check fingerprint MH/s W W_inst W_avg sm_MHz mem_MHz util nJ/hash samples
1 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 31.30 249.58 249.61 249.58 2745.60 10251.00 100.00 7973.65 126
2 x1-flat-ds28 PASS 8cd11a827ac3ffe4 31.28 248.68 248.68 248.68 2745.00 10251.00 100.00 7949.60 126
3 x1-flat-ds28 PASS 8cd11a827ac3ffe4 31.28 249.18 249.20 249.18 2745.00 10251.00 100.00 7965.71 126
4 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 31.30 252.79 252.83 252.79 2741.07 10251.00 100.00 8076.63 126
5 x1-ctrl-ds30 PASS b1f90e91cadb15b6 30.70 251.15 251.17 251.15 2743.49 10251.00 99.99 8182.19 129
6 x1-flat-ds30 PASS 18c4c6a80809c4b9 30.69 248.26 248.28 248.26 2745.00 10251.00 100.00 8088.73 128
7 x1-flat-ds30 PASS 18c4c6a80809c4b9 30.69 248.21 248.25 248.21 2745.00 10251.00 100.00 8087.44 128
8 x1-ctrl-ds30 PASS b1f90e91cadb15b6 30.70 250.48 250.47 250.48 2742.56 10251.00 100.00 8160.22 129
PAIR ds28: control 31.30 MH/s 251.2 W 8025 nJ; candidate 31.28 MH/s 248.9 W 7958 nJ; rate -0.06 percent, joules per hash -0.84 percent (g = 0.9916); fingerprints control ['01f51b9d4805e5e6'] candidate ['8cd11a827ac3ffe4']; ABBA spread control 0.01 percent candidate 0.00 percent
PAIR ds30: control 30.70 MH/s 250.8 W 8171 nJ; candidate 30.69 MH/s 248.2 W 8088 nJ; rate -0.01 percent, joules per hash -1.02 percent (g = 0.9898); fingerprints control ['b1f90e91cadb15b6'] candidate ['18c4c6a80809c4b9']; ABBA spread control 0.00 percent candidate 0.00 percent

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@ -0,0 +1,8 @@
# 2026-10-09T08:50:47Z 43fb5342ca73 worker sha256 804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd
GPU 0: NVIDIA GeForce RTX 4090 (UUID: GPU-40966419-60c8-d741-dd9d-016ad5600b96)
name, driver_version, power.limit [W], power.default_limit [W], clocks.max.sm [MHz], clocks.max.memory [MHz]
NVIDIA GeForce RTX 4090, 595.91.07, 450.00 W, 450.00 W, 3105 MHz, 10501 MHz
The current user does not have permission to change clocks for GPU 00000000:01:00.0.
Terminating early due to previous errors.
The current user does not have permission to change clocks for GPU 00000000:01:00.0.
# end 2026-10-09T09:10:44Z

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### run 1 x1-ctrl-ds28 start 1791535852.987677286
1791535853.246771428 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791535990.444710324 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1794 cache 3 dataset 32 hot 0 check 484 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791535990.446618742 warm-up dispatch (base 0): 536.06 ms; 250 timed dispatches of 16777216 nonces: mean 535.99 ms
1791535990.448513841 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=31.301 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 1 x1-ctrl-ds28 end 1791535990.466239712
### run 2 x1-flat-ds28 start 1791536000.470056887
1791536000.676893961 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536137.866103375 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1743 cache 2 dataset 32 hot 0 check 479 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536137.868129084 warm-up dispatch (base 0): 536.27 ms; 250 timed dispatches of 16777216 nonces: mean 536.32 ms
1791536137.871480659 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=31.282 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 2 x1-flat-ds28 end 1791536137.890172125
### run 3 x1-flat-ds28 start 1791536147.894446312
1791536148.100122291 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536285.611106544 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1662 cache 3 dataset 32 hot 0 check 584 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536285.613308364 warm-up dispatch (base 0): 536.30 ms; 250 timed dispatches of 16777216 nonces: mean 536.32 ms
1791536285.615261253 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=31.282 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 3 x1-flat-ds28 end 1791536285.633921128
### run 4 x1-ctrl-ds28 start 1791536295.637863584
1791536296.166418465 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536433.512117831 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_4090: nvrtc 1905 cache 2 dataset 122 hot 0 check 453 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536433.514280420 warm-up dispatch (base 0): 535.95 ms; 250 timed dispatches of 16777216 nonces: mean 536.03 ms
1791536433.516297750 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=31.299 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 4 x1-ctrl-ds28 end 1791536433.533900148
### run 5 x1-ctrl-ds30 start 1791536443.538871181
1791536443.756588201 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536583.738558907 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1792 cache 2 dataset 125 hot 0 check 495 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536583.742084323 warm-up dispatch (base 0): 546.60 ms; 250 timed dispatches of 16777216 nonces: mean 546.57 ms
1791536583.744974476 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=30.695 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 5 x1-ctrl-ds30 end 1791536583.761670770
### run 6 x1-flat-ds30 start 1791536593.765585539
1791536593.972056229 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536733.906352202 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1707 cache 2 dataset 125 hot 0 check 532 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536733.908279500 warm-up dispatch (base 0): 546.62 ms; 250 timed dispatches of 16777216 nonces: mean 546.64 ms
1791536733.910233899 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=30.692 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 6 x1-flat-ds30 end 1791536733.934702868
### run 7 x1-flat-ds30 start 1791536743.941532070
1791536744.150640701 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791536884.080755105 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1689 cache 3 dataset 125 hot 0 check 520 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536884.084309971 warm-up dispatch (base 0): 546.63 ms; 250 timed dispatches of 16777216 nonces: mean 546.65 ms
1791536884.087476405 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=90 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=30.691 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 7 x1-flat-ds30 end 1791536884.105516816
### run 8 x1-ctrl-ds30 start 1791536894.111470213
1791536894.335966554 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
1791537034.314148871 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_4090: nvrtc 1802 cache 3 dataset 124 hot 0 check 495 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791537034.316518601 warm-up dispatch (base 0): 546.59 ms; 250 timed dispatches of 16777216 nonces: mean 546.58 ms
1791537034.318721471 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=30.695 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 8 x1-ctrl-ds30 end 1791537034.335791327

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@ -0,0 +1,11 @@
run pack check fingerprint MH/s W W_inst W_avg sm_MHz mem_MHz util nJ/hash samples
1 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 70.66 400.08 400.09 400.08 2833.51 13801.00 100.00 5662.14 51
2 x1-flat-ds28 PASS 8cd11a827ac3ffe4 70.56 400.01 400.01 400.01 2813.85 13801.00 100.00 5669.42 52
3 x1-flat-ds28 PASS 8cd11a827ac3ffe4 70.55 399.99 399.98 399.99 2813.85 13801.00 100.00 5669.29 52
4 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 70.65 399.99 399.99 399.99 2796.37 13801.00 100.00 5661.26 51
5 x1-ctrl-ds30 PASS b1f90e91cadb15b6 68.66 399.99 400.05 399.99 2802.06 13801.00 100.00 5826.05 54
6 x1-flat-ds30 PASS 18c4c6a80809c4b9 68.59 399.96 399.74 399.96 2811.77 13801.00 99.85 5831.32 53
7 x1-flat-ds30 PASS 18c4c6a80809c4b9 68.59 400.02 400.01 400.02 2814.72 13801.00 99.98 5832.36 53
8 x1-ctrl-ds30 PASS b1f90e91cadb15b6 68.66 399.99 400.03 399.99 2800.25 13801.00 100.00 5825.54 53
PAIR ds28: control 70.66 MH/s 400.0 W 5662 nJ; candidate 70.55 MH/s 400.0 W 5669 nJ; rate -0.14 percent, joules per hash +0.14 percent (g = 1.0014); fingerprints control ['01f51b9d4805e5e6'] candidate ['8cd11a827ac3ffe4']; ABBA spread control 0.01 percent candidate 0.00 percent
PAIR ds30: control 68.66 MH/s 400.0 W 5826 nJ; candidate 68.59 MH/s 400.0 W 5832 nJ; rate -0.10 percent, joules per hash +0.10 percent (g = 1.0010); fingerprints control ['b1f90e91cadb15b6'] candidate ['18c4c6a80809c4b9']; ABBA spread control 0.01 percent candidate 0.00 percent

View file

@ -0,0 +1,8 @@
# 2026-10-09T08:48:50Z a251332ae314 worker sha256 804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd
GPU 0: NVIDIA GeForce RTX 5090 (UUID: GPU-848b3087-94b0-d664-e099-e542fc28a3a9)
name, driver_version, power.limit [W], power.default_limit [W], clocks.max.sm [MHz], clocks.max.memory [MHz]
NVIDIA GeForce RTX 5090, 580.159.03, 400.00 W, 575.00 W, 3090 MHz, 14001 MHz
The current user does not have permission to change clocks for GPU 00000000:A1:00.0.
Terminating early due to previous errors.
The current user does not have permission to change clocks for GPU 00000000:A1:00.0.
# end 2026-10-09T08:58:51Z

View file

@ -0,0 +1,602 @@
2026/10/09 08:48:50.541, 17.51 W, 180 MHz, 405 MHz, 35, 0 %, 17.59 W, 17.51 W
2026/10/09 08:48:51.548, 17.83 W, 180 MHz, 405 MHz, 35, 0 %, 18.06 W, 17.83 W
2026/10/09 08:48:52.548, 17.90 W, 180 MHz, 405 MHz, 35, 0 %, 17.75 W, 17.90 W
2026/10/09 08:48:53.548, 17.71 W, 180 MHz, 405 MHz, 35, 0 %, 17.71 W, 17.71 W
2026/10/09 08:48:54.549, 17.67 W, 180 MHz, 405 MHz, 35, 0 %, 17.67 W, 17.67 W
2026/10/09 08:48:55.549, 17.68 W, 180 MHz, 405 MHz, 35, 0 %, 17.68 W, 17.68 W
2026/10/09 08:48:56.549, 29.55 W, 2362 MHz, 13801 MHz, 36, 0 %, 58.08 W, 29.55 W
2026/10/09 08:48:57.549, 57.87 W, 2400 MHz, 13801 MHz, 37, 0 %, 57.82 W, 57.87 W
2026/10/09 08:48:58.549, 63.47 W, 2400 MHz, 13801 MHz, 37, 1 %, 93.81 W, 63.47 W
2026/10/09 08:48:59.549, 58.13 W, 2400 MHz, 13801 MHz, 37, 0 %, 57.38 W, 58.13 W
2026/10/09 08:49:00.550, 272.17 W, 2872 MHz, 13801 MHz, 46, 100 %, 387.82 W, 272.17 W
2026/10/09 08:49:01.550, 388.38 W, 2865 MHz, 13801 MHz, 48, 99 %, 387.52 W, 388.38 W
2026/10/09 08:49:02.550, 390.03 W, 2865 MHz, 13801 MHz, 49, 100 %, 390.59 W, 390.03 W
2026/10/09 08:49:03.550, 391.65 W, 2865 MHz, 13801 MHz, 50, 100 %, 392.68 W, 391.65 W
2026/10/09 08:49:04.550, 392.39 W, 2865 MHz, 13801 MHz, 50, 100 %, 393.63 W, 392.39 W
2026/10/09 08:49:05.550, 393.78 W, 2865 MHz, 13801 MHz, 51, 100 %, 393.42 W, 393.78 W
2026/10/09 08:49:06.551, 394.60 W, 2865 MHz, 13801 MHz, 51, 100 %, 394.48 W, 394.60 W
2026/10/09 08:49:07.551, 394.86 W, 2865 MHz, 13801 MHz, 52, 100 %, 395.50 W, 394.86 W
2026/10/09 08:49:08.551, 396.28 W, 2865 MHz, 13801 MHz, 53, 100 %, 397.07 W, 396.28 W
2026/10/09 08:49:09.551, 396.82 W, 2865 MHz, 13801 MHz, 53, 100 %, 397.84 W, 396.82 W
2026/10/09 08:49:10.551, 397.73 W, 2857 MHz, 13801 MHz, 54, 100 %, 396.95 W, 397.73 W
2026/10/09 08:49:11.552, 398.35 W, 2857 MHz, 13801 MHz, 54, 100 %, 398.07 W, 398.35 W
2026/10/09 08:49:12.552, 399.13 W, 2857 MHz, 13801 MHz, 55, 100 %, 400.07 W, 399.13 W
2026/10/09 08:49:13.552, 400.14 W, 2857 MHz, 13801 MHz, 55, 100 %, 400.52 W, 400.14 W
2026/10/09 08:49:14.552, 401.03 W, 2857 MHz, 13801 MHz, 56, 100 %, 402.02 W, 401.03 W
2026/10/09 08:49:15.553, 401.86 W, 2857 MHz, 13801 MHz, 56, 100 %, 402.06 W, 401.86 W
2026/10/09 08:49:16.553, 403.29 W, 2857 MHz, 13801 MHz, 56, 100 %, 402.77 W, 403.29 W
2026/10/09 08:49:17.553, 403.19 W, 2857 MHz, 13801 MHz, 56, 100 %, 402.12 W, 403.19 W
2026/10/09 08:49:18.553, 401.89 W, 2857 MHz, 13801 MHz, 56, 100 %, 401.91 W, 401.89 W
2026/10/09 08:49:19.553, 402.59 W, 2857 MHz, 13801 MHz, 56, 100 %, 404.10 W, 402.59 W
2026/10/09 08:49:20.553, 402.26 W, 2857 MHz, 13801 MHz, 56, 100 %, 399.49 W, 402.26 W
2026/10/09 08:49:21.554, 400.01 W, 2850 MHz, 13801 MHz, 57, 100 %, 400.05 W, 400.01 W
2026/10/09 08:49:22.554, 400.00 W, 2850 MHz, 13801 MHz, 57, 100 %, 400.64 W, 400.00 W
2026/10/09 08:49:23.554, 400.04 W, 2850 MHz, 13801 MHz, 57, 100 %, 399.76 W, 400.04 W
2026/10/09 08:49:24.554, 399.89 W, 2842 MHz, 13801 MHz, 57, 100 %, 398.90 W, 399.89 W
2026/10/09 08:49:25.554, 400.05 W, 2842 MHz, 13801 MHz, 58, 100 %, 399.61 W, 400.05 W
2026/10/09 08:49:26.554, 400.05 W, 2842 MHz, 13801 MHz, 58, 100 %, 401.06 W, 400.05 W
2026/10/09 08:49:27.555, 399.98 W, 2842 MHz, 13801 MHz, 58, 100 %, 400.43 W, 399.98 W
2026/10/09 08:49:28.555, 400.02 W, 2842 MHz, 13801 MHz, 58, 100 %, 399.79 W, 400.02 W
2026/10/09 08:49:29.555, 399.92 W, 2835 MHz, 13801 MHz, 59, 100 %, 399.23 W, 399.92 W
2026/10/09 08:49:30.555, 399.98 W, 2835 MHz, 13801 MHz, 59, 100 %, 400.03 W, 399.98 W
2026/10/09 08:49:31.555, 400.01 W, 2835 MHz, 13801 MHz, 59, 100 %, 400.85 W, 400.01 W
2026/10/09 08:49:32.555, 400.05 W, 2835 MHz, 13801 MHz, 59, 100 %, 399.98 W, 400.05 W
2026/10/09 08:49:33.556, 399.99 W, 2835 MHz, 13801 MHz, 60, 100 %, 399.85 W, 399.99 W
2026/10/09 08:49:34.556, 399.94 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.65 W, 399.94 W
2026/10/09 08:49:35.556, 400.02 W, 2827 MHz, 13801 MHz, 60, 100 %, 400.01 W, 400.02 W
2026/10/09 08:49:36.556, 400.01 W, 2827 MHz, 13801 MHz, 60, 100 %, 400.57 W, 400.01 W
2026/10/09 08:49:37.556, 399.97 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.94 W, 399.97 W
2026/10/09 08:49:38.556, 399.93 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.32 W, 399.93 W
2026/10/09 08:49:39.557, 399.95 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.61 W, 399.95 W
2026/10/09 08:49:40.557, 400.01 W, 2820 MHz, 13801 MHz, 61, 100 %, 400.79 W, 400.01 W
2026/10/09 08:49:41.557, 399.97 W, 2820 MHz, 13801 MHz, 61, 100 %, 400.47 W, 399.97 W
2026/10/09 08:49:42.557, 400.03 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.91 W, 400.03 W
2026/10/09 08:49:43.557, 399.92 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.38 W, 399.92 W
2026/10/09 08:49:44.558, 399.98 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.83 W, 399.98 W
2026/10/09 08:49:45.558, 400.03 W, 2820 MHz, 13801 MHz, 62, 100 %, 401.27 W, 400.03 W
2026/10/09 08:49:46.558, 399.98 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.24 W, 399.98 W
2026/10/09 08:49:47.558, 400.02 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.78 W, 400.02 W
2026/10/09 08:49:48.558, 399.90 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.21 W, 399.90 W
2026/10/09 08:49:49.559, 400.07 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.01 W, 400.07 W
2026/10/09 08:49:50.559, 400.00 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.89 W, 400.00 W
2026/10/09 08:49:51.559, 400.05 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.98 W, 400.05 W
2026/10/09 08:49:52.559, 399.99 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.83 W, 399.99 W
2026/10/09 08:49:53.559, 399.94 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.57 W, 399.94 W
2026/10/09 08:49:54.560, 400.00 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.18 W, 400.00 W
2026/10/09 08:49:55.560, 399.98 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.46 W, 399.98 W
2026/10/09 08:49:56.560, 400.02 W, 2812 MHz, 13801 MHz, 63, 100 %, 399.81 W, 400.02 W
2026/10/09 08:49:57.560, 399.92 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.07 W, 399.92 W
2026/10/09 08:49:58.561, 399.97 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.82 W, 399.97 W
2026/10/09 08:49:59.561, 369.35 W, 2805 MHz, 14001 MHz, 59, 2 %, 113.52 W, 369.35 W
2026/10/09 08:50:00.561, 105.97 W, 2865 MHz, 14001 MHz, 57, 0 %, 103.57 W, 105.97 W
2026/10/09 08:50:01.562, 104.20 W, 2865 MHz, 14001 MHz, 56, 0 %, 103.73 W, 104.20 W
2026/10/09 08:50:02.562, 87.47 W, 555 MHz, 14001 MHz, 55, 0 %, 87.47 W, 87.47 W
2026/10/09 08:50:03.562, 66.20 W, 352 MHz, 7001 MHz, 53, 0 %, 44.92 W, 66.20 W
2026/10/09 08:50:04.562, 43.06 W, 225 MHz, 810 MHz, 53, 0 %, 43.06 W, 43.06 W
2026/10/09 08:50:05.563, 37.91 W, 180 MHz, 810 MHz, 52, 0 %, 32.76 W, 37.91 W
2026/10/09 08:50:06.563, 31.34 W, 180 MHz, 405 MHz, 51, 0 %, 31.34 W, 31.34 W
2026/10/09 08:50:07.563, 29.93 W, 180 MHz, 405 MHz, 51, 0 %, 29.93 W, 29.93 W
2026/10/09 08:50:08.563, 29.64 W, 180 MHz, 405 MHz, 50, 0 %, 29.36 W, 29.64 W
2026/10/09 08:50:09.564, 29.28 W, 180 MHz, 405 MHz, 50, 0 %, 29.28 W, 29.28 W
2026/10/09 08:50:10.564, 45.92 W, 2400 MHz, 13801 MHz, 50, 0 %, 72.77 W, 45.92 W
2026/10/09 08:50:11.564, 72.64 W, 2400 MHz, 13801 MHz, 50, 0 %, 72.62 W, 72.64 W
2026/10/09 08:50:12.565, 77.49 W, 2400 MHz, 13801 MHz, 50, 0 %, 72.69 W, 77.49 W
2026/10/09 08:50:13.565, 144.93 W, 2640 MHz, 13801 MHz, 55, 57 %, 245.30 W, 144.93 W
2026/10/09 08:50:14.565, 364.18 W, 2857 MHz, 13801 MHz, 58, 100 %, 406.30 W, 364.18 W
2026/10/09 08:50:15.565, 406.06 W, 2857 MHz, 13801 MHz, 58, 100 %, 406.71 W, 406.06 W
2026/10/09 08:50:16.566, 405.95 W, 2857 MHz, 13801 MHz, 59, 100 %, 400.41 W, 405.95 W
2026/10/09 08:50:17.566, 400.14 W, 2842 MHz, 13801 MHz, 59, 100 %, 399.81 W, 400.14 W
2026/10/09 08:50:18.566, 400.03 W, 2842 MHz, 13801 MHz, 59, 100 %, 400.90 W, 400.03 W
2026/10/09 08:50:19.566, 400.06 W, 2842 MHz, 13801 MHz, 60, 100 %, 400.18 W, 400.06 W
2026/10/09 08:50:20.567, 400.00 W, 2842 MHz, 13801 MHz, 60, 100 %, 399.85 W, 400.00 W
2026/10/09 08:50:21.567, 399.92 W, 2842 MHz, 13801 MHz, 60, 100 %, 399.31 W, 399.92 W
2026/10/09 08:50:22.567, 399.97 W, 2842 MHz, 13801 MHz, 60, 100 %, 399.79 W, 399.97 W
2026/10/09 08:50:23.567, 400.04 W, 2842 MHz, 13801 MHz, 60, 100 %, 400.90 W, 400.04 W
2026/10/09 08:50:24.568, 400.05 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.32 W, 400.05 W
2026/10/09 08:50:25.568, 400.02 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.83 W, 400.02 W
2026/10/09 08:50:26.568, 399.93 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.34 W, 399.93 W
2026/10/09 08:50:27.569, 400.06 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.01 W, 400.06 W
2026/10/09 08:50:28.569, 400.00 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.80 W, 400.00 W
2026/10/09 08:50:29.569, 400.01 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.20 W, 400.01 W
2026/10/09 08:50:30.569, 400.01 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.79 W, 400.01 W
2026/10/09 08:50:31.570, 399.93 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.46 W, 399.93 W
2026/10/09 08:50:32.570, 400.03 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.89 W, 400.03 W
2026/10/09 08:50:33.570, 399.98 W, 2827 MHz, 13801 MHz, 62, 100 %, 400.51 W, 399.98 W
2026/10/09 08:50:34.570, 400.02 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.94 W, 400.02 W
2026/10/09 08:50:35.571, 400.00 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.93 W, 400.00 W
2026/10/09 08:50:36.571, 399.94 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.67 W, 399.94 W
2026/10/09 08:50:37.571, 400.00 W, 2827 MHz, 13801 MHz, 62, 100 %, 400.04 W, 400.00 W
2026/10/09 08:50:38.571, 400.00 W, 2827 MHz, 13801 MHz, 63, 100 %, 400.57 W, 400.00 W
2026/10/09 08:50:39.572, 400.03 W, 2827 MHz, 13801 MHz, 63, 100 %, 399.92 W, 400.03 W
2026/10/09 08:50:40.572, 400.00 W, 2827 MHz, 13801 MHz, 63, 100 %, 400.04 W, 400.00 W
2026/10/09 08:50:41.572, 399.95 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.57 W, 399.95 W
2026/10/09 08:50:42.572, 400.06 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.11 W, 400.06 W
2026/10/09 08:50:43.573, 399.98 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.56 W, 399.98 W
2026/10/09 08:50:44.573, 400.03 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.79 W, 400.03 W
2026/10/09 08:50:45.573, 399.82 W, 2805 MHz, 13801 MHz, 63, 100 %, 398.23 W, 399.82 W
2026/10/09 08:50:46.574, 400.12 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.65 W, 400.12 W
2026/10/09 08:50:47.574, 400.01 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.71 W, 400.01 W
2026/10/09 08:50:48.574, 400.05 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.43 W, 400.05 W
2026/10/09 08:50:49.574, 400.02 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.82 W, 400.02 W
2026/10/09 08:50:50.575, 399.93 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.23 W, 399.93 W
2026/10/09 08:50:51.575, 400.03 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.80 W, 400.03 W
2026/10/09 08:50:52.575, 400.01 W, 2805 MHz, 13801 MHz, 64, 100 %, 401.14 W, 400.01 W
2026/10/09 08:50:53.575, 400.08 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.23 W, 400.08 W
2026/10/09 08:50:54.576, 399.97 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.72 W, 399.97 W
2026/10/09 08:50:55.576, 399.94 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.35 W, 399.94 W
2026/10/09 08:50:56.576, 400.04 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.85 W, 400.04 W
2026/10/09 08:50:57.576, 400.02 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.90 W, 400.02 W
2026/10/09 08:50:58.577, 400.07 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.17 W, 400.07 W
2026/10/09 08:50:59.577, 400.01 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.77 W, 400.01 W
2026/10/09 08:51:00.577, 399.94 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.37 W, 399.94 W
2026/10/09 08:51:01.577, 400.04 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.86 W, 400.04 W
2026/10/09 08:51:02.578, 400.03 W, 2797 MHz, 13801 MHz, 64, 100 %, 403.09 W, 400.03 W
2026/10/09 08:51:03.578, 400.23 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.21 W, 400.23 W
2026/10/09 08:51:04.578, 400.01 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.74 W, 400.01 W
2026/10/09 08:51:05.579, 399.93 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.36 W, 399.93 W
2026/10/09 08:51:06.579, 400.05 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.95 W, 400.05 W
2026/10/09 08:51:07.579, 400.01 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.78 W, 400.01 W
2026/10/09 08:51:08.579, 400.05 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.01 W, 400.05 W
2026/10/09 08:51:09.580, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.86 W, 400.00 W
2026/10/09 08:51:10.580, 399.95 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.59 W, 399.95 W
2026/10/09 08:51:11.580, 399.98 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.90 W, 399.98 W
2026/10/09 08:51:12.580, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.54 W, 400.00 W
2026/10/09 08:51:13.581, 290.91 W, 2865 MHz, 14001 MHz, 59, 0 %, 108.62 W, 290.91 W
2026/10/09 08:51:14.581, 109.49 W, 2865 MHz, 14001 MHz, 58, 0 %, 107.01 W, 109.49 W
2026/10/09 08:51:15.581, 90.91 W, 1222 MHz, 14001 MHz, 56, 0 %, 90.91 W, 90.91 W
2026/10/09 08:51:16.582, 43.06 W, 367 MHz, 810 MHz, 55, 0 %, 43.06 W, 43.06 W
2026/10/09 08:51:17.582, 39.51 W, 217 MHz, 810 MHz, 54, 0 %, 35.96 W, 39.51 W
2026/10/09 08:51:18.582, 32.85 W, 180 MHz, 405 MHz, 53, 0 %, 32.85 W, 32.85 W
2026/10/09 08:51:19.582, 32.77 W, 180 MHz, 405 MHz, 53, 0 %, 32.69 W, 32.77 W
2026/10/09 08:51:20.583, 32.58 W, 180 MHz, 405 MHz, 52, 0 %, 32.48 W, 32.58 W
2026/10/09 08:51:21.583, 32.28 W, 172 MHz, 405 MHz, 52, 0 %, 32.07 W, 32.28 W
2026/10/09 08:51:22.583, 31.56 W, 180 MHz, 405 MHz, 51, 0 %, 31.56 W, 31.56 W
2026/10/09 08:51:23.583, 33.42 W, 180 MHz, 14001 MHz, 51, 0 %, 64.89 W, 33.42 W
2026/10/09 08:51:24.584, 75.20 W, 2400 MHz, 13801 MHz, 51, 0 %, 74.97 W, 75.20 W
2026/10/09 08:51:25.584, 74.92 W, 2400 MHz, 13801 MHz, 51, 0 %, 74.85 W, 74.92 W
2026/10/09 08:51:26.584, 79.39 W, 2400 MHz, 13801 MHz, 51, 0 %, 74.32 W, 79.39 W
2026/10/09 08:51:27.585, 196.64 W, 2865 MHz, 13801 MHz, 57, 100 %, 406.22 W, 196.64 W
2026/10/09 08:51:28.585, 408.47 W, 2857 MHz, 13801 MHz, 59, 100 %, 409.47 W, 408.47 W
2026/10/09 08:51:29.585, 407.46 W, 2857 MHz, 13801 MHz, 59, 100 %, 400.71 W, 407.46 W
2026/10/09 08:51:30.585, 399.94 W, 2842 MHz, 13801 MHz, 59, 100 %, 399.26 W, 399.94 W
2026/10/09 08:51:31.586, 399.99 W, 2842 MHz, 13801 MHz, 60, 100 %, 400.00 W, 399.99 W
2026/10/09 08:51:32.586, 400.01 W, 2835 MHz, 13801 MHz, 60, 100 %, 400.83 W, 400.01 W
2026/10/09 08:51:33.588, 400.05 W, 2835 MHz, 13801 MHz, 60, 100 %, 400.28 W, 400.05 W
2026/10/09 08:51:34.588, 400.00 W, 2835 MHz, 13801 MHz, 60, 100 %, 399.90 W, 400.00 W
2026/10/09 08:51:35.589, 399.92 W, 2835 MHz, 13801 MHz, 60, 100 %, 399.33 W, 399.92 W
2026/10/09 08:51:36.589, 399.98 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.85 W, 399.98 W
2026/10/09 08:51:37.589, 400.02 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.85 W, 400.02 W
2026/10/09 08:51:38.589, 400.05 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.89 W, 400.05 W
2026/10/09 08:51:39.590, 399.98 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.84 W, 399.98 W
2026/10/09 08:51:40.590, 399.94 W, 2835 MHz, 13801 MHz, 61, 100 %, 399.64 W, 399.94 W
2026/10/09 08:51:41.590, 399.99 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.86 W, 399.99 W
2026/10/09 08:51:42.590, 400.00 W, 2835 MHz, 13801 MHz, 62, 100 %, 400.59 W, 400.00 W
2026/10/09 08:51:43.591, 400.04 W, 2827 MHz, 13801 MHz, 62, 100 %, 400.05 W, 400.04 W
2026/10/09 08:51:44.591, 400.00 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.85 W, 400.00 W
2026/10/09 08:51:45.591, 399.93 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.53 W, 399.93 W
2026/10/09 08:51:46.592, 399.98 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.94 W, 399.98 W
2026/10/09 08:51:47.592, 400.02 W, 2827 MHz, 13801 MHz, 62, 100 %, 400.56 W, 400.02 W
2026/10/09 08:51:48.592, 400.03 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.94 W, 400.03 W
2026/10/09 08:51:49.592, 399.94 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.42 W, 399.94 W
2026/10/09 08:51:50.593, 399.94 W, 2827 MHz, 13801 MHz, 63, 100 %, 399.61 W, 399.94 W
2026/10/09 08:51:51.593, 400.00 W, 2827 MHz, 13801 MHz, 63, 100 %, 400.04 W, 400.00 W
2026/10/09 08:51:52.593, 399.95 W, 2827 MHz, 13801 MHz, 63, 100 %, 400.46 W, 399.95 W
2026/10/09 08:51:53.594, 399.98 W, 2827 MHz, 13801 MHz, 63, 100 %, 399.74 W, 399.98 W
2026/10/09 08:51:54.594, 399.90 W, 2827 MHz, 13801 MHz, 63, 100 %, 399.13 W, 399.90 W
2026/10/09 08:51:55.594, 399.96 W, 2827 MHz, 13801 MHz, 63, 100 %, 399.81 W, 399.96 W
2026/10/09 08:51:56.594, 400.06 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.92 W, 400.06 W
2026/10/09 08:51:57.595, 400.04 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.21 W, 400.04 W
2026/10/09 08:51:58.595, 400.00 W, 2812 MHz, 13801 MHz, 63, 100 %, 399.72 W, 400.00 W
2026/10/09 08:51:59.595, 399.92 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.20 W, 399.92 W
2026/10/09 08:52:00.595, 400.04 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.80 W, 400.04 W
2026/10/09 08:52:01.596, 400.02 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.94 W, 400.02 W
2026/10/09 08:52:02.596, 400.06 W, 2805 MHz, 13801 MHz, 63, 100 %, 400.09 W, 400.06 W
2026/10/09 08:52:03.596, 400.00 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.85 W, 400.00 W
2026/10/09 08:52:04.596, 399.90 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.30 W, 399.90 W
2026/10/09 08:52:05.597, 399.98 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.81 W, 399.98 W
2026/10/09 08:52:06.597, 400.02 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.80 W, 400.02 W
2026/10/09 08:52:07.597, 400.06 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.19 W, 400.06 W
2026/10/09 08:52:08.598, 399.98 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.79 W, 399.98 W
2026/10/09 08:52:09.598, 399.92 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.38 W, 399.92 W
2026/10/09 08:52:10.598, 400.04 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.99 W, 400.04 W
2026/10/09 08:52:11.599, 400.00 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.83 W, 400.00 W
2026/10/09 08:52:12.599, 400.05 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.04 W, 400.05 W
2026/10/09 08:52:13.599, 399.99 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.82 W, 399.99 W
2026/10/09 08:52:14.599, 399.94 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.49 W, 399.94 W
2026/10/09 08:52:15.600, 400.04 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.12 W, 400.04 W
2026/10/09 08:52:16.600, 400.00 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.80 W, 400.00 W
2026/10/09 08:52:17.600, 399.98 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.94 W, 399.98 W
2026/10/09 08:52:18.601, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.86 W, 400.00 W
2026/10/09 08:52:19.601, 399.93 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.58 W, 399.93 W
2026/10/09 08:52:20.601, 400.04 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.95 W, 400.04 W
2026/10/09 08:52:21.601, 400.01 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.56 W, 400.01 W
2026/10/09 08:52:22.602, 400.03 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.97 W, 400.03 W
2026/10/09 08:52:23.602, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.99 W, 400.00 W
2026/10/09 08:52:24.602, 399.94 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.64 W, 399.94 W
2026/10/09 08:52:25.602, 400.01 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.05 W, 400.01 W
2026/10/09 08:52:26.603, 399.99 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.45 W, 399.99 W
2026/10/09 08:52:27.603, 224.91 W, 2865 MHz, 14001 MHz, 58, 0 %, 107.57 W, 224.91 W
2026/10/09 08:52:28.603, 108.82 W, 2865 MHz, 14001 MHz, 58, 0 %, 107.04 W, 108.82 W
2026/10/09 08:52:29.603, 90.86 W, 1672 MHz, 14001 MHz, 56, 0 %, 90.86 W, 90.86 W
2026/10/09 08:52:30.604, 43.38 W, 375 MHz, 810 MHz, 55, 0 %, 43.38 W, 43.38 W
2026/10/09 08:52:31.604, 39.31 W, 217 MHz, 810 MHz, 54, 0 %, 35.24 W, 39.31 W
2026/10/09 08:52:32.604, 34.21 W, 180 MHz, 405 MHz, 53, 0 %, 33.17 W, 34.21 W
2026/10/09 08:52:33.604, 32.65 W, 180 MHz, 405 MHz, 53, 0 %, 32.65 W, 32.65 W
2026/10/09 08:52:34.605, 32.32 W, 180 MHz, 405 MHz, 52, 0 %, 32.32 W, 32.32 W
2026/10/09 08:52:35.605, 32.09 W, 180 MHz, 405 MHz, 52, 0 %, 31.86 W, 32.09 W
2026/10/09 08:52:36.605, 31.65 W, 180 MHz, 405 MHz, 51, 0 %, 31.65 W, 31.65 W
2026/10/09 08:52:37.605, 39.59 W, 1050 MHz, 13801 MHz, 51, 0 %, 75.16 W, 39.59 W
2026/10/09 08:52:38.606, 74.97 W, 2400 MHz, 13801 MHz, 51, 0 %, 74.84 W, 74.97 W
2026/10/09 08:52:39.606, 74.63 W, 2400 MHz, 13801 MHz, 52, 4 %, 74.56 W, 74.63 W
2026/10/09 08:52:40.606, 79.67 W, 2400 MHz, 13801 MHz, 51, 0 %, 74.18 W, 79.67 W
2026/10/09 08:52:41.607, 280.63 W, 2865 MHz, 13801 MHz, 59, 100 %, 416.66 W, 280.63 W
2026/10/09 08:52:42.607, 411.55 W, 2842 MHz, 13801 MHz, 59, 100 %, 400.48 W, 411.55 W
2026/10/09 08:52:43.607, 400.05 W, 2827 MHz, 13801 MHz, 59, 100 %, 399.86 W, 400.05 W
2026/10/09 08:52:44.607, 399.92 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.41 W, 399.92 W
2026/10/09 08:52:45.608, 399.98 W, 2820 MHz, 13801 MHz, 60, 100 %, 399.96 W, 399.98 W
2026/10/09 08:52:46.608, 400.01 W, 2820 MHz, 13801 MHz, 60, 100 %, 400.83 W, 400.01 W
2026/10/09 08:52:47.608, 400.05 W, 2820 MHz, 13801 MHz, 60, 100 %, 399.99 W, 400.05 W
2026/10/09 08:52:48.608, 399.99 W, 2820 MHz, 13801 MHz, 60, 100 %, 399.88 W, 399.99 W
2026/10/09 08:52:49.609, 399.94 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.55 W, 399.94 W
2026/10/09 08:52:50.609, 400.05 W, 2820 MHz, 13801 MHz, 61, 100 %, 400.16 W, 400.05 W
2026/10/09 08:52:51.609, 400.01 W, 2812 MHz, 13801 MHz, 61, 100 %, 400.50 W, 400.01 W
2026/10/09 08:52:52.609, 399.97 W, 2812 MHz, 13801 MHz, 61, 100 %, 399.78 W, 399.97 W
2026/10/09 08:52:53.610, 399.92 W, 2812 MHz, 13801 MHz, 61, 100 %, 399.10 W, 399.92 W
2026/10/09 08:52:54.610, 399.97 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.99 W, 399.97 W
2026/10/09 08:52:55.610, 400.02 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.91 W, 400.02 W
2026/10/09 08:52:56.610, 400.06 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.20 W, 400.06 W
2026/10/09 08:52:57.611, 399.98 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.81 W, 399.98 W
2026/10/09 08:52:58.611, 399.92 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.35 W, 399.92 W
2026/10/09 08:52:59.611, 400.06 W, 2812 MHz, 13801 MHz, 62, 100 %, 399.90 W, 400.06 W
2026/10/09 08:53:00.611, 400.00 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.84 W, 400.00 W
2026/10/09 08:53:01.612, 400.04 W, 2812 MHz, 13801 MHz, 62, 100 %, 400.01 W, 400.04 W
2026/10/09 08:53:02.612, 400.00 W, 2812 MHz, 13801 MHz, 63, 100 %, 399.86 W, 400.00 W
2026/10/09 08:53:03.612, 399.95 W, 2812 MHz, 13801 MHz, 63, 100 %, 399.63 W, 399.95 W
2026/10/09 08:53:04.612, 399.99 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.94 W, 399.99 W
2026/10/09 08:53:05.613, 399.99 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.45 W, 399.99 W
2026/10/09 08:53:06.613, 399.98 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.91 W, 399.98 W
2026/10/09 08:53:07.613, 400.00 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.96 W, 400.00 W
2026/10/09 08:53:08.613, 399.94 W, 2790 MHz, 13801 MHz, 63, 100 %, 399.51 W, 399.94 W
2026/10/09 08:53:09.614, 400.01 W, 2790 MHz, 13801 MHz, 63, 100 %, 400.07 W, 400.01 W
2026/10/09 08:53:10.614, 399.98 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.53 W, 399.98 W
2026/10/09 08:53:11.614, 400.03 W, 2790 MHz, 13801 MHz, 63, 100 %, 399.86 W, 400.03 W
2026/10/09 08:53:12.615, 399.91 W, 2790 MHz, 13801 MHz, 63, 100 %, 399.11 W, 399.91 W
2026/10/09 08:53:13.615, 400.05 W, 2790 MHz, 13801 MHz, 63, 100 %, 399.89 W, 400.05 W
2026/10/09 08:53:14.615, 400.05 W, 2790 MHz, 13801 MHz, 63, 100 %, 401.52 W, 400.05 W
2026/10/09 08:53:15.615, 400.11 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.19 W, 400.11 W
2026/10/09 08:53:16.616, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.78 W, 399.98 W
2026/10/09 08:53:17.616, 399.93 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.31 W, 399.93 W
2026/10/09 08:53:18.616, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.01 W, 399.98 W
2026/10/09 08:53:19.617, 400.02 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.84 W, 400.02 W
2026/10/09 08:53:20.617, 399.96 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.92 W, 399.96 W
2026/10/09 08:53:21.617, 399.99 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.91 W, 399.99 W
2026/10/09 08:53:22.617, 399.95 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.58 W, 399.95 W
2026/10/09 08:53:23.618, 400.03 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.98 W, 400.03 W
2026/10/09 08:53:24.618, 400.00 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.40 W, 400.00 W
2026/10/09 08:53:25.618, 400.02 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.90 W, 400.02 W
2026/10/09 08:53:26.618, 399.93 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.24 W, 399.93 W
2026/10/09 08:53:27.619, 400.01 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.62 W, 400.01 W
2026/10/09 08:53:28.619, 400.04 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.83 W, 400.04 W
2026/10/09 08:53:29.620, 400.06 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.39 W, 400.06 W
2026/10/09 08:53:30.620, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.82 W, 399.98 W
2026/10/09 08:53:31.620, 399.92 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.18 W, 399.92 W
2026/10/09 08:53:32.620, 399.93 W, 2782 MHz, 13801 MHz, 64, 100 %, 399.38 W, 399.93 W
2026/10/09 08:53:33.621, 400.01 W, 2782 MHz, 13801 MHz, 64, 100 %, 401.03 W, 400.01 W
2026/10/09 08:53:34.621, 399.97 W, 2782 MHz, 13801 MHz, 64, 100 %, 400.28 W, 399.97 W
2026/10/09 08:53:35.621, 400.02 W, 2782 MHz, 13801 MHz, 64, 100 %, 399.84 W, 400.02 W
2026/10/09 08:53:36.621, 399.90 W, 2782 MHz, 13801 MHz, 64, 100 %, 399.15 W, 399.90 W
2026/10/09 08:53:37.622, 399.99 W, 2782 MHz, 13801 MHz, 64, 100 %, 399.93 W, 399.99 W
2026/10/09 08:53:38.622, 400.00 W, 2782 MHz, 13801 MHz, 64, 100 %, 400.80 W, 400.00 W
2026/10/09 08:53:39.622, 399.97 W, 2782 MHz, 13801 MHz, 64, 100 %, 399.98 W, 399.97 W
2026/10/09 08:53:40.623, 400.00 W, 2782 MHz, 14001 MHz, 61, 100 %, 399.83 W, 400.00 W
2026/10/09 08:53:41.623, 112.43 W, 2865 MHz, 14001 MHz, 58, 0 %, 106.84 W, 112.43 W
2026/10/09 08:53:42.623, 108.42 W, 2865 MHz, 14001 MHz, 58, 0 %, 106.38 W, 108.42 W
2026/10/09 08:53:43.624, 90.36 W, 577 MHz, 7001 MHz, 56, 0 %, 90.36 W, 90.36 W
2026/10/09 08:53:44.624, 48.02 W, 360 MHz, 7001 MHz, 55, 0 %, 48.02 W, 48.02 W
2026/10/09 08:53:45.624, 46.67 W, 232 MHz, 7001 MHz, 54, 0 %, 46.67 W, 46.67 W
2026/10/09 08:53:46.624, 46.34 W, 180 MHz, 7001 MHz, 54, 0 %, 46.01 W, 46.34 W
2026/10/09 08:53:47.625, 45.69 W, 180 MHz, 7001 MHz, 53, 0 %, 45.38 W, 45.69 W
2026/10/09 08:53:48.625, 36.56 W, 180 MHz, 810 MHz, 52, 0 %, 36.56 W, 36.56 W
2026/10/09 08:53:49.625, 35.26 W, 180 MHz, 405 MHz, 52, 0 %, 33.96 W, 35.26 W
2026/10/09 08:53:50.626, 32.47 W, 180 MHz, 405 MHz, 51, 0 %, 32.47 W, 32.47 W
2026/10/09 08:53:51.626, 46.52 W, 2400 MHz, 13801 MHz, 52, 0 %, 73.77 W, 46.52 W
2026/10/09 08:53:52.626, 73.65 W, 2400 MHz, 13801 MHz, 52, 0 %, 73.65 W, 73.65 W
2026/10/09 08:53:53.626, 92.43 W, 2482 MHz, 13801 MHz, 52, 0 %, 73.62 W, 92.43 W
2026/10/09 08:53:54.627, 122.80 W, 2407 MHz, 13801 MHz, 58, 100 %, 407.76 W, 122.80 W
2026/10/09 08:53:55.627, 354.35 W, 2857 MHz, 13801 MHz, 59, 100 %, 412.33 W, 354.35 W
2026/10/09 08:53:56.627, 408.27 W, 2850 MHz, 13801 MHz, 59, 100 %, 399.02 W, 408.27 W
2026/10/09 08:53:57.628, 399.88 W, 2835 MHz, 13801 MHz, 60, 99 %, 398.39 W, 399.88 W
2026/10/09 08:53:58.628, 400.10 W, 2835 MHz, 13801 MHz, 60, 100 %, 399.71 W, 400.10 W
2026/10/09 08:53:59.628, 400.01 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.96 W, 400.01 W
2026/10/09 08:54:00.628, 400.01 W, 2827 MHz, 13801 MHz, 60, 100 %, 400.04 W, 400.01 W
2026/10/09 08:54:01.629, 399.99 W, 2827 MHz, 13801 MHz, 61, 100 %, 400.79 W, 399.99 W
2026/10/09 08:54:02.629, 400.06 W, 2827 MHz, 13801 MHz, 61, 100 %, 400.58 W, 400.06 W
2026/10/09 08:54:03.629, 399.98 W, 2827 MHz, 13801 MHz, 61, 100 %, 400.21 W, 399.98 W
2026/10/09 08:54:04.629, 400.00 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.95 W, 400.00 W
2026/10/09 08:54:05.630, 399.99 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.81 W, 399.99 W
2026/10/09 08:54:06.630, 399.97 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.88 W, 399.97 W
2026/10/09 08:54:07.630, 399.91 W, 2827 MHz, 13801 MHz, 62, 100 %, 399.19 W, 399.91 W
2026/10/09 08:54:08.631, 399.95 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.60 W, 399.95 W
2026/10/09 08:54:09.631, 399.99 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.57 W, 399.99 W
2026/10/09 08:54:10.631, 400.03 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.94 W, 400.03 W
2026/10/09 08:54:11.631, 400.01 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.34 W, 400.01 W
2026/10/09 08:54:12.632, 400.01 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.70 W, 400.01 W
2026/10/09 08:54:13.632, 400.00 W, 2820 MHz, 13801 MHz, 63, 100 %, 400.55 W, 400.00 W
2026/10/09 08:54:14.632, 400.02 W, 2820 MHz, 13801 MHz, 63, 100 %, 400.19 W, 400.02 W
2026/10/09 08:54:15.632, 399.99 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.96 W, 399.99 W
2026/10/09 08:54:16.633, 400.00 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.82 W, 400.00 W
2026/10/09 08:54:17.633, 399.98 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.97 W, 399.98 W
2026/10/09 08:54:18.633, 399.93 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.30 W, 399.93 W
2026/10/09 08:54:19.634, 399.95 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.61 W, 399.95 W
2026/10/09 08:54:20.634, 399.98 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.80 W, 399.98 W
2026/10/09 08:54:21.634, 400.01 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.99 W, 400.01 W
2026/10/09 08:54:22.634, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 401.08 W, 400.00 W
2026/10/09 08:54:23.635, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.96 W, 400.00 W
2026/10/09 08:54:24.635, 400.08 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.61 W, 400.08 W
2026/10/09 08:54:25.635, 399.97 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.82 W, 399.97 W
2026/10/09 08:54:26.635, 400.07 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.80 W, 400.07 W
2026/10/09 08:54:27.636, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.73 W, 400.00 W
2026/10/09 08:54:28.636, 399.98 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.93 W, 399.98 W
2026/10/09 08:54:29.636, 399.93 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.40 W, 399.93 W
2026/10/09 08:54:30.637, 399.96 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.62 W, 399.96 W
2026/10/09 08:54:31.637, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.75 W, 400.00 W
2026/10/09 08:54:32.637, 399.99 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.96 W, 399.99 W
2026/10/09 08:54:33.637, 400.02 W, 2790 MHz, 13801 MHz, 64, 100 %, 401.04 W, 400.02 W
2026/10/09 08:54:34.638, 400.08 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.73 W, 400.08 W
2026/10/09 08:54:35.638, 400.06 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.51 W, 400.06 W
2026/10/09 08:54:36.638, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 400.03 W, 399.98 W
2026/10/09 08:54:37.639, 399.99 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.79 W, 399.99 W
2026/10/09 08:54:38.639, 399.99 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.79 W, 399.99 W
2026/10/09 08:54:39.639, 399.97 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.93 W, 399.97 W
2026/10/09 08:54:40.639, 399.92 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.27 W, 399.92 W
2026/10/09 08:54:41.640, 400.06 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.46 W, 400.06 W
2026/10/09 08:54:42.640, 399.98 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.18 W, 399.98 W
2026/10/09 08:54:43.640, 400.01 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.99 W, 400.01 W
2026/10/09 08:54:44.641, 399.99 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.82 W, 399.99 W
2026/10/09 08:54:45.641, 400.01 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.95 W, 400.01 W
2026/10/09 08:54:46.641, 399.91 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.27 W, 399.91 W
2026/10/09 08:54:47.641, 399.96 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.65 W, 399.96 W
2026/10/09 08:54:48.642, 399.99 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.80 W, 399.99 W
2026/10/09 08:54:49.642, 400.00 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.01 W, 400.00 W
2026/10/09 08:54:50.642, 400.01 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.77 W, 400.01 W
2026/10/09 08:54:51.642, 400.00 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.62 W, 400.00 W
2026/10/09 08:54:52.642, 399.98 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.50 W, 399.98 W
2026/10/09 08:54:53.643, 400.03 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.12 W, 400.03 W
2026/10/09 08:54:54.643, 399.99 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.88 W, 399.99 W
2026/10/09 08:54:55.643, 399.98 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.77 W, 399.98 W
2026/10/09 08:54:56.643, 209.80 W, 2865 MHz, 14001 MHz, 59, 0 %, 108.06 W, 209.80 W
2026/10/09 08:54:57.644, 110.51 W, 2865 MHz, 14001 MHz, 59, 0 %, 107.43 W, 110.51 W
2026/10/09 08:54:58.644, 92.15 W, 1695 MHz, 14001 MHz, 57, 0 %, 92.15 W, 92.15 W
2026/10/09 08:54:59.644, 70.78 W, 397 MHz, 7001 MHz, 56, 0 %, 49.40 W, 70.78 W
2026/10/09 08:55:00.644, 46.64 W, 247 MHz, 7001 MHz, 55, 0 %, 46.64 W, 46.64 W
2026/10/09 08:55:01.644, 46.37 W, 172 MHz, 7001 MHz, 54, 0 %, 46.11 W, 46.37 W
2026/10/09 08:55:02.644, 37.26 W, 180 MHz, 810 MHz, 53, 0 %, 37.26 W, 37.26 W
2026/10/09 08:55:03.645, 35.77 W, 180 MHz, 405 MHz, 53, 0 %, 34.28 W, 35.77 W
2026/10/09 08:55:04.645, 33.59 W, 180 MHz, 405 MHz, 52, 0 %, 33.59 W, 33.59 W
2026/10/09 08:55:05.645, 33.42 W, 180 MHz, 405 MHz, 52, 0 %, 33.25 W, 33.42 W
2026/10/09 08:55:06.645, 43.17 W, 2430 MHz, 13801 MHz, 52, 0 %, 75.30 W, 43.17 W
2026/10/09 08:55:07.646, 74.99 W, 2400 MHz, 13801 MHz, 52, 0 %, 74.78 W, 74.99 W
2026/10/09 08:55:08.646, 94.98 W, 2482 MHz, 13801 MHz, 54, 38 %, 149.76 W, 94.98 W
2026/10/09 08:55:09.646, 74.33 W, 2400 MHz, 13801 MHz, 52, 0 %, 73.71 W, 74.33 W
2026/10/09 08:55:10.646, 287.45 W, 2857 MHz, 13801 MHz, 60, 100 %, 407.06 W, 287.45 W
2026/10/09 08:55:11.646, 406.21 W, 2857 MHz, 13801 MHz, 60, 100 %, 406.74 W, 406.21 W
2026/10/09 08:55:12.647, 406.77 W, 2857 MHz, 13801 MHz, 60, 100 %, 405.18 W, 406.77 W
2026/10/09 08:55:13.647, 401.04 W, 2842 MHz, 13801 MHz, 60, 100 %, 399.33 W, 401.04 W
2026/10/09 08:55:14.647, 400.01 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.55 W, 400.01 W
2026/10/09 08:55:15.647, 399.98 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.75 W, 399.98 W
2026/10/09 08:55:16.647, 400.01 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.92 W, 400.01 W
2026/10/09 08:55:17.648, 400.00 W, 2835 MHz, 13801 MHz, 61, 100 %, 400.90 W, 400.00 W
2026/10/09 08:55:18.648, 399.98 W, 2835 MHz, 13801 MHz, 62, 100 %, 400.49 W, 399.98 W
2026/10/09 08:55:19.648, 400.03 W, 2835 MHz, 13801 MHz, 62, 100 %, 400.31 W, 400.03 W
2026/10/09 08:55:20.649, 400.02 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.97 W, 400.02 W
2026/10/09 08:55:21.649, 399.98 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.74 W, 399.98 W
2026/10/09 08:55:22.649, 399.99 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.75 W, 399.99 W
2026/10/09 08:55:23.649, 399.98 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.95 W, 399.98 W
2026/10/09 08:55:24.649, 399.87 W, 2835 MHz, 13801 MHz, 63, 100 %, 398.90 W, 399.87 W
2026/10/09 08:55:25.649, 399.94 W, 2835 MHz, 13801 MHz, 63, 100 %, 399.41 W, 399.94 W
2026/10/09 08:55:26.650, 399.96 W, 2835 MHz, 13801 MHz, 63, 100 %, 399.66 W, 399.96 W
2026/10/09 08:55:27.650, 400.03 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.95 W, 400.03 W
2026/10/09 08:55:28.650, 400.02 W, 2820 MHz, 13801 MHz, 63, 100 %, 401.67 W, 400.02 W
2026/10/09 08:55:29.650, 400.15 W, 2820 MHz, 13801 MHz, 63, 100 %, 401.16 W, 400.15 W
2026/10/09 08:55:30.651, 399.99 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.79 W, 399.99 W
2026/10/09 08:55:31.651, 400.05 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.28 W, 400.05 W
2026/10/09 08:55:32.652, 400.02 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.06 W, 400.02 W
2026/10/09 08:55:33.652, 399.98 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.83 W, 399.98 W
2026/10/09 08:55:34.652, 399.99 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.92 W, 399.99 W
2026/10/09 08:55:35.652, 399.93 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.44 W, 399.93 W
2026/10/09 08:55:36.653, 399.95 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.47 W, 399.95 W
2026/10/09 08:55:37.653, 398.44 W, 2820 MHz, 13801 MHz, 63, 92 %, 383.20 W, 398.44 W
2026/10/09 08:55:38.653, 399.99 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.86 W, 399.99 W
2026/10/09 08:55:39.653, 400.00 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.90 W, 400.00 W
2026/10/09 08:55:40.654, 400.01 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.94 W, 400.01 W
2026/10/09 08:55:41.654, 400.08 W, 2812 MHz, 13801 MHz, 64, 100 %, 401.22 W, 400.08 W
2026/10/09 08:55:42.654, 399.98 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.27 W, 399.98 W
2026/10/09 08:55:43.655, 400.01 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.05 W, 400.01 W
2026/10/09 08:55:44.655, 399.99 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.76 W, 399.99 W
2026/10/09 08:55:45.655, 400.00 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.87 W, 400.00 W
2026/10/09 08:55:46.655, 400.01 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.08 W, 400.01 W
2026/10/09 08:55:47.656, 399.89 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.21 W, 399.89 W
2026/10/09 08:55:48.656, 399.95 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.65 W, 399.95 W
2026/10/09 08:55:49.656, 400.01 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.85 W, 400.01 W
2026/10/09 08:55:50.656, 399.99 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.94 W, 399.99 W
2026/10/09 08:55:51.657, 400.00 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.89 W, 400.00 W
2026/10/09 08:55:52.657, 399.99 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.77 W, 399.99 W
2026/10/09 08:55:53.657, 400.05 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.47 W, 400.05 W
2026/10/09 08:55:54.657, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.33 W, 399.98 W
2026/10/09 08:55:55.658, 400.02 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.74 W, 400.02 W
2026/10/09 08:55:56.658, 399.97 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.88 W, 399.97 W
2026/10/09 08:55:57.658, 400.00 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.96 W, 400.00 W
2026/10/09 08:55:58.658, 399.93 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.36 W, 399.93 W
2026/10/09 08:55:59.659, 399.95 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.69 W, 399.95 W
2026/10/09 08:56:00.659, 399.99 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.87 W, 399.99 W
2026/10/09 08:56:01.659, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.92 W, 399.98 W
2026/10/09 08:56:02.659, 400.02 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.90 W, 400.02 W
2026/10/09 08:56:03.660, 399.99 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.67 W, 399.99 W
2026/10/09 08:56:04.660, 399.99 W, 2805 MHz, 13801 MHz, 65, 100 %, 401.25 W, 399.99 W
2026/10/09 08:56:05.660, 399.99 W, 2797 MHz, 13801 MHz, 65, 100 %, 400.14 W, 399.99 W
2026/10/09 08:56:06.660, 399.98 W, 2797 MHz, 13801 MHz, 65, 100 %, 400.00 W, 399.98 W
2026/10/09 08:56:07.661, 399.99 W, 2797 MHz, 13801 MHz, 65, 100 %, 399.78 W, 399.99 W
2026/10/09 08:56:08.661, 400.00 W, 2797 MHz, 13801 MHz, 65, 100 %, 399.79 W, 400.00 W
2026/10/09 08:56:09.661, 399.89 W, 2797 MHz, 13801 MHz, 65, 100 %, 399.13 W, 399.89 W
2026/10/09 08:56:10.661, 399.89 W, 2797 MHz, 13801 MHz, 65, 100 %, 399.05 W, 399.89 W
2026/10/09 08:56:11.662, 316.78 W, 2865 MHz, 14001 MHz, 60, 0 %, 113.38 W, 316.78 W
2026/10/09 08:56:12.662, 110.98 W, 2865 MHz, 14001 MHz, 59, 0 %, 109.26 W, 110.98 W
2026/10/09 08:56:13.662, 87.82 W, 780 MHz, 14001 MHz, 57, 0 %, 87.82 W, 87.82 W
2026/10/09 08:56:14.662, 48.15 W, 375 MHz, 810 MHz, 56, 0 %, 48.15 W, 48.15 W
2026/10/09 08:56:15.663, 43.06 W, 217 MHz, 810 MHz, 55, 0 %, 37.98 W, 43.06 W
2026/10/09 08:56:16.663, 36.42 W, 180 MHz, 405 MHz, 54, 0 %, 34.86 W, 36.42 W
2026/10/09 08:56:17.663, 34.40 W, 180 MHz, 405 MHz, 53, 0 %, 33.94 W, 34.40 W
2026/10/09 08:56:18.663, 33.50 W, 180 MHz, 405 MHz, 53, 0 %, 33.50 W, 33.50 W
2026/10/09 08:56:19.664, 33.48 W, 180 MHz, 405 MHz, 52, 0 %, 33.47 W, 33.48 W
2026/10/09 08:56:20.664, 33.20 W, 180 MHz, 405 MHz, 52, 0 %, 32.94 W, 33.20 W
2026/10/09 08:56:21.664, 32.78 W, 180 MHz, 405 MHz, 51, 0 %, 32.78 W, 32.78 W
2026/10/09 08:56:22.664, 69.15 W, 2400 MHz, 13801 MHz, 52, 0 %, 76.14 W, 69.15 W
2026/10/09 08:56:23.664, 76.12 W, 2400 MHz, 13801 MHz, 52, 0 %, 75.99 W, 76.12 W
2026/10/09 08:56:24.664, 96.16 W, 2400 MHz, 13801 MHz, 52, 0 %, 75.54 W, 96.16 W
2026/10/09 08:56:25.665, 168.46 W, 2865 MHz, 13801 MHz, 56, 57 %, 254.65 W, 168.46 W
2026/10/09 08:56:26.665, 392.88 W, 2857 MHz, 13801 MHz, 59, 100 %, 405.53 W, 392.88 W
2026/10/09 08:56:27.665, 407.07 W, 2857 MHz, 13801 MHz, 60, 100 %, 406.68 W, 407.07 W
2026/10/09 08:56:28.665, 402.69 W, 2842 MHz, 13801 MHz, 60, 100 %, 400.92 W, 402.69 W
2026/10/09 08:56:29.665, 400.06 W, 2842 MHz, 13801 MHz, 60, 100 %, 400.52 W, 400.06 W
2026/10/09 08:56:30.665, 399.98 W, 2842 MHz, 13801 MHz, 61, 100 %, 400.26 W, 399.98 W
2026/10/09 08:56:31.666, 400.02 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.98 W, 400.02 W
2026/10/09 08:56:32.666, 400.00 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.81 W, 400.00 W
2026/10/09 08:56:33.666, 400.01 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.87 W, 400.01 W
2026/10/09 08:56:34.666, 399.89 W, 2842 MHz, 13801 MHz, 61, 100 %, 399.01 W, 399.89 W
2026/10/09 08:56:35.666, 399.99 W, 2842 MHz, 13801 MHz, 62, 100 %, 399.20 W, 399.99 W
2026/10/09 08:56:36.667, 399.96 W, 2835 MHz, 13801 MHz, 62, 99 %, 398.88 W, 399.96 W
2026/10/09 08:56:37.667, 399.97 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.73 W, 399.97 W
2026/10/09 08:56:38.667, 400.02 W, 2835 MHz, 13801 MHz, 62, 100 %, 399.87 W, 400.02 W
2026/10/09 08:56:39.667, 400.01 W, 2835 MHz, 13801 MHz, 62, 100 %, 400.96 W, 400.01 W
2026/10/09 08:56:40.668, 400.08 W, 2835 MHz, 13801 MHz, 62, 100 %, 401.07 W, 400.08 W
2026/10/09 08:56:41.668, 399.97 W, 2827 MHz, 13801 MHz, 62, 100 %, 400.21 W, 399.97 W
2026/10/09 08:56:42.668, 400.01 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.02 W, 400.01 W
2026/10/09 08:56:43.668, 399.99 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.85 W, 399.99 W
2026/10/09 08:56:44.668, 399.99 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.92 W, 399.99 W
2026/10/09 08:56:45.668, 400.00 W, 2820 MHz, 13801 MHz, 63, 100 %, 400.10 W, 400.00 W
2026/10/09 08:56:46.668, 399.90 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.25 W, 399.90 W
2026/10/09 08:56:47.669, 399.95 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.56 W, 399.95 W
2026/10/09 08:56:48.669, 399.97 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.80 W, 399.97 W
2026/10/09 08:56:49.669, 400.02 W, 2820 MHz, 13801 MHz, 63, 100 %, 400.00 W, 400.02 W
2026/10/09 08:56:50.669, 400.01 W, 2812 MHz, 13801 MHz, 63, 100 %, 401.05 W, 400.01 W
2026/10/09 08:56:51.669, 400.09 W, 2812 MHz, 13801 MHz, 63, 100 %, 400.88 W, 400.09 W
2026/10/09 08:56:52.669, 399.97 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.56 W, 399.97 W
2026/10/09 08:56:53.670, 399.99 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.32 W, 399.99 W
2026/10/09 08:56:54.670, 400.01 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.09 W, 400.01 W
2026/10/09 08:56:55.670, 399.99 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.79 W, 399.99 W
2026/10/09 08:56:56.670, 400.01 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.98 W, 400.01 W
2026/10/09 08:56:57.670, 399.92 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.34 W, 399.92 W
2026/10/09 08:56:58.671, 399.95 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.57 W, 399.95 W
2026/10/09 08:56:59.671, 399.98 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.78 W, 399.98 W
2026/10/09 08:57:00.671, 400.01 W, 2812 MHz, 13801 MHz, 64, 100 %, 399.99 W, 400.01 W
2026/10/09 08:57:01.671, 400.02 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.07 W, 400.02 W
2026/10/09 08:57:02.671, 399.97 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.85 W, 399.97 W
2026/10/09 08:57:03.671, 400.06 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.47 W, 400.06 W
2026/10/09 08:57:04.671, 400.02 W, 2812 MHz, 13801 MHz, 64, 100 %, 400.22 W, 400.02 W
2026/10/09 08:57:05.672, 400.01 W, 2805 MHz, 13801 MHz, 64, 100 %, 400.08 W, 400.01 W
2026/10/09 08:57:06.672, 400.00 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.86 W, 400.00 W
2026/10/09 08:57:07.672, 400.00 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.81 W, 400.00 W
2026/10/09 08:57:08.672, 399.90 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.06 W, 399.90 W
2026/10/09 08:57:09.672, 399.93 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.32 W, 399.93 W
2026/10/09 08:57:10.673, 400.02 W, 2805 MHz, 13801 MHz, 64, 100 %, 399.64 W, 400.02 W
2026/10/09 08:57:11.673, 400.03 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.99 W, 400.03 W
2026/10/09 08:57:12.673, 400.00 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.07 W, 400.00 W
2026/10/09 08:57:13.673, 400.00 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.76 W, 400.00 W
2026/10/09 08:57:14.673, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.48 W, 399.98 W
2026/10/09 08:57:15.673, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.18 W, 399.98 W
2026/10/09 08:57:16.674, 400.01 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.02 W, 400.01 W
2026/10/09 08:57:17.674, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.79 W, 399.98 W
2026/10/09 08:57:18.674, 399.98 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.90 W, 399.98 W
2026/10/09 08:57:19.674, 399.92 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.18 W, 399.92 W
2026/10/09 08:57:20.675, 399.93 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.36 W, 399.93 W
2026/10/09 08:57:21.675, 399.96 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.70 W, 399.96 W
2026/10/09 08:57:22.675, 400.02 W, 2812 MHz, 13801 MHz, 65, 100 %, 402.14 W, 400.02 W
2026/10/09 08:57:23.675, 400.18 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.94 W, 400.18 W
2026/10/09 08:57:24.675, 401.41 W, 2805 MHz, 13801 MHz, 65, 100 %, 399.93 W, 401.41 W
2026/10/09 08:57:25.676, 400.00 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.84 W, 400.00 W
2026/10/09 08:57:26.676, 400.06 W, 2805 MHz, 13801 MHz, 65, 100 %, 400.58 W, 400.06 W
2026/10/09 08:57:27.676, 141.76 W, 2865 MHz, 14001 MHz, 59, 0 %, 108.36 W, 141.76 W
2026/10/09 08:57:28.676, 112.13 W, 2865 MHz, 14001 MHz, 59, 0 %, 107.61 W, 112.13 W
2026/10/09 08:57:29.677, 95.60 W, 1335 MHz, 7001 MHz, 56, 0 %, 95.60 W, 95.60 W
2026/10/09 08:57:30.677, 48.05 W, 382 MHz, 7001 MHz, 55, 0 %, 48.05 W, 48.05 W
2026/10/09 08:57:31.677, 47.40 W, 240 MHz, 7001 MHz, 55, 0 %, 46.76 W, 47.40 W
2026/10/09 08:57:32.677, 45.82 W, 180 MHz, 7001 MHz, 54, 0 %, 45.82 W, 45.82 W
2026/10/09 08:57:33.677, 45.31 W, 180 MHz, 7001 MHz, 53, 0 %, 44.81 W, 45.31 W
2026/10/09 08:57:34.678, 36.31 W, 180 MHz, 810 MHz, 53, 0 %, 36.31 W, 36.31 W
2026/10/09 08:57:35.678, 34.99 W, 180 MHz, 405 MHz, 52, 0 %, 33.66 W, 34.99 W
2026/10/09 08:57:36.678, 33.01 W, 180 MHz, 405 MHz, 52, 0 %, 32.36 W, 33.01 W
2026/10/09 08:57:37.678, 45.89 W, 2400 MHz, 13801 MHz, 52, 0 %, 76.00 W, 45.89 W
2026/10/09 08:57:38.679, 75.78 W, 2400 MHz, 13801 MHz, 52, 0 %, 75.43 W, 75.78 W
2026/10/09 08:57:39.679, 95.69 W, 2467 MHz, 13801 MHz, 52, 27 %, 75.46 W, 95.69 W
2026/10/09 08:57:40.679, 83.62 W, 2437 MHz, 13801 MHz, 51, 35 %, 168.80 W, 83.62 W
2026/10/09 08:57:41.679, 338.15 W, 2857 MHz, 13801 MHz, 59, 100 %, 413.75 W, 338.15 W
2026/10/09 08:57:42.679, 409.82 W, 2835 MHz, 13801 MHz, 60, 100 %, 400.73 W, 409.82 W
2026/10/09 08:57:43.680, 400.06 W, 2827 MHz, 13801 MHz, 60, 100 %, 400.27 W, 400.06 W
2026/10/09 08:57:44.680, 399.99 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.84 W, 399.99 W
2026/10/09 08:57:45.680, 399.98 W, 2827 MHz, 13801 MHz, 60, 100 %, 399.78 W, 399.98 W
2026/10/09 08:57:46.680, 400.01 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.81 W, 400.01 W
2026/10/09 08:57:47.681, 399.89 W, 2827 MHz, 13801 MHz, 61, 100 %, 399.08 W, 399.89 W
2026/10/09 08:57:48.681, 400.01 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.26 W, 400.01 W
2026/10/09 08:57:49.681, 400.01 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.54 W, 400.01 W
2026/10/09 08:57:50.681, 400.02 W, 2820 MHz, 13801 MHz, 61, 100 %, 399.81 W, 400.02 W
2026/10/09 08:57:51.681, 400.03 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.13 W, 400.03 W
2026/10/09 08:57:52.682, 400.00 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.74 W, 400.00 W
2026/10/09 08:57:53.682, 400.07 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.54 W, 400.07 W
2026/10/09 08:57:54.682, 399.97 W, 2820 MHz, 13801 MHz, 62, 100 %, 400.25 W, 399.97 W
2026/10/09 08:57:55.682, 400.01 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.99 W, 400.01 W
2026/10/09 08:57:56.682, 400.00 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.81 W, 400.00 W
2026/10/09 08:57:57.683, 399.99 W, 2820 MHz, 13801 MHz, 62, 100 %, 399.89 W, 399.99 W
2026/10/09 08:57:58.683, 399.91 W, 2820 MHz, 13801 MHz, 63, 100 %, 399.17 W, 399.91 W
2026/10/09 08:57:59.683, 400.01 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.44 W, 400.01 W
2026/10/09 08:58:00.683, 399.98 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.78 W, 399.98 W
2026/10/09 08:58:01.684, 399.98 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.98 W, 399.98 W
2026/10/09 08:58:02.684, 400.01 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.05 W, 400.01 W
2026/10/09 08:58:03.684, 400.00 W, 2805 MHz, 13801 MHz, 63, 100 %, 401.53 W, 400.00 W
2026/10/09 08:58:04.684, 399.97 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.49 W, 399.97 W
2026/10/09 08:58:05.684, 400.03 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.13 W, 400.03 W
2026/10/09 08:58:06.685, 399.99 W, 2797 MHz, 13801 MHz, 63, 100 %, 400.01 W, 399.99 W
2026/10/09 08:58:07.685, 399.98 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.87 W, 399.98 W
2026/10/09 08:58:08.685, 400.00 W, 2805 MHz, 13801 MHz, 63, 100 %, 399.94 W, 400.00 W
2026/10/09 08:58:09.685, 399.92 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.19 W, 399.92 W
2026/10/09 08:58:10.686, 399.96 W, 2797 MHz, 13801 MHz, 63, 100 %, 399.74 W, 399.96 W
2026/10/09 08:58:11.686, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.84 W, 400.00 W
2026/10/09 08:58:12.686, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.96 W, 400.00 W
2026/10/09 08:58:13.686, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.82 W, 400.00 W
2026/10/09 08:58:14.686, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.77 W, 400.00 W
2026/10/09 08:58:15.687, 400.06 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.47 W, 400.06 W
2026/10/09 08:58:16.687, 399.98 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.27 W, 399.98 W
2026/10/09 08:58:17.687, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.76 W, 400.00 W
2026/10/09 08:58:18.687, 399.98 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.90 W, 399.98 W
2026/10/09 08:58:19.687, 399.99 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.98 W, 399.99 W
2026/10/09 08:58:20.688, 399.92 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.46 W, 399.92 W
2026/10/09 08:58:21.688, 399.97 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.65 W, 399.97 W
2026/10/09 08:58:22.688, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.85 W, 400.00 W
2026/10/09 08:58:23.688, 400.01 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.98 W, 400.01 W
2026/10/09 08:58:24.688, 400.00 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.88 W, 400.00 W
2026/10/09 08:58:25.688, 399.99 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.67 W, 399.99 W
2026/10/09 08:58:26.689, 400.05 W, 2797 MHz, 13801 MHz, 64, 100 %, 400.64 W, 400.05 W
2026/10/09 08:58:27.689, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.97 W, 399.98 W
2026/10/09 08:58:28.689, 399.98 W, 2797 MHz, 13801 MHz, 64, 100 %, 399.86 W, 399.98 W
2026/10/09 08:58:29.689, 399.99 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.84 W, 399.99 W
2026/10/09 08:58:30.689, 399.98 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.98 W, 399.98 W
2026/10/09 08:58:31.690, 399.94 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.39 W, 399.94 W
2026/10/09 08:58:32.690, 400.01 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.65 W, 400.01 W
2026/10/09 08:58:33.690, 400.00 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.85 W, 400.00 W
2026/10/09 08:58:34.690, 400.00 W, 2790 MHz, 13801 MHz, 64, 100 %, 399.95 W, 400.00 W
2026/10/09 08:58:35.691, 400.00 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.79 W, 400.00 W
2026/10/09 08:58:36.691, 400.06 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.49 W, 400.06 W
2026/10/09 08:58:37.691, 400.03 W, 2790 MHz, 13801 MHz, 65, 100 %, 400.20 W, 400.03 W
2026/10/09 08:58:38.691, 399.99 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.94 W, 399.99 W
2026/10/09 08:58:39.691, 399.98 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.77 W, 399.98 W
2026/10/09 08:58:40.692, 399.98 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.85 W, 399.98 W
2026/10/09 08:58:41.692, 399.92 W, 2790 MHz, 13801 MHz, 65, 100 %, 399.31 W, 399.92 W
2026/10/09 08:58:42.692, 266.37 W, 2865 MHz, 14001 MHz, 59, 0 %, 108.97 W, 266.37 W
2026/10/09 08:58:43.692, 108.93 W, 2865 MHz, 14001 MHz, 58, 0 %, 108.00 W, 108.93 W
2026/10/09 08:58:44.693, 86.74 W, 547 MHz, 7001 MHz, 56, 0 %, 86.74 W, 86.74 W
2026/10/09 08:58:45.693, 67.17 W, 337 MHz, 7001 MHz, 55, 0 %, 47.60 W, 67.17 W
2026/10/09 08:58:46.693, 46.92 W, 217 MHz, 7001 MHz, 54, 0 %, 46.25 W, 46.92 W
2026/10/09 08:58:47.693, 45.38 W, 180 MHz, 810 MHz, 54, 0 %, 45.38 W, 45.38 W
2026/10/09 08:58:48.693, 35.34 W, 180 MHz, 810 MHz, 53, 0 %, 35.34 W, 35.34 W
2026/10/09 08:58:49.694, 34.27 W, 180 MHz, 405 MHz, 52, 0 %, 33.20 W, 34.27 W
2026/10/09 08:58:50.694, 32.65 W, 180 MHz, 405 MHz, 52, 0 %, 32.65 W, 32.65 W
2026/10/09 08:58:51.694, 32.03 W, 180 MHz, 405 MHz, 51, 0 %, 32.03 W, 32.03 W
1 2026/10/09 08:48:50.541 17.51 W 180 MHz 405 MHz 35 0 % 17.59 W 17.51 W
2 2026/10/09 08:48:51.548 17.83 W 180 MHz 405 MHz 35 0 % 18.06 W 17.83 W
3 2026/10/09 08:48:52.548 17.90 W 180 MHz 405 MHz 35 0 % 17.75 W 17.90 W
4 2026/10/09 08:48:53.548 17.71 W 180 MHz 405 MHz 35 0 % 17.71 W 17.71 W
5 2026/10/09 08:48:54.549 17.67 W 180 MHz 405 MHz 35 0 % 17.67 W 17.67 W
6 2026/10/09 08:48:55.549 17.68 W 180 MHz 405 MHz 35 0 % 17.68 W 17.68 W
7 2026/10/09 08:48:56.549 29.55 W 2362 MHz 13801 MHz 36 0 % 58.08 W 29.55 W
8 2026/10/09 08:48:57.549 57.87 W 2400 MHz 13801 MHz 37 0 % 57.82 W 57.87 W
9 2026/10/09 08:48:58.549 63.47 W 2400 MHz 13801 MHz 37 1 % 93.81 W 63.47 W
10 2026/10/09 08:48:59.549 58.13 W 2400 MHz 13801 MHz 37 0 % 57.38 W 58.13 W
11 2026/10/09 08:49:00.550 272.17 W 2872 MHz 13801 MHz 46 100 % 387.82 W 272.17 W
12 2026/10/09 08:49:01.550 388.38 W 2865 MHz 13801 MHz 48 99 % 387.52 W 388.38 W
13 2026/10/09 08:49:02.550 390.03 W 2865 MHz 13801 MHz 49 100 % 390.59 W 390.03 W
14 2026/10/09 08:49:03.550 391.65 W 2865 MHz 13801 MHz 50 100 % 392.68 W 391.65 W
15 2026/10/09 08:49:04.550 392.39 W 2865 MHz 13801 MHz 50 100 % 393.63 W 392.39 W
16 2026/10/09 08:49:05.550 393.78 W 2865 MHz 13801 MHz 51 100 % 393.42 W 393.78 W
17 2026/10/09 08:49:06.551 394.60 W 2865 MHz 13801 MHz 51 100 % 394.48 W 394.60 W
18 2026/10/09 08:49:07.551 394.86 W 2865 MHz 13801 MHz 52 100 % 395.50 W 394.86 W
19 2026/10/09 08:49:08.551 396.28 W 2865 MHz 13801 MHz 53 100 % 397.07 W 396.28 W
20 2026/10/09 08:49:09.551 396.82 W 2865 MHz 13801 MHz 53 100 % 397.84 W 396.82 W
21 2026/10/09 08:49:10.551 397.73 W 2857 MHz 13801 MHz 54 100 % 396.95 W 397.73 W
22 2026/10/09 08:49:11.552 398.35 W 2857 MHz 13801 MHz 54 100 % 398.07 W 398.35 W
23 2026/10/09 08:49:12.552 399.13 W 2857 MHz 13801 MHz 55 100 % 400.07 W 399.13 W
24 2026/10/09 08:49:13.552 400.14 W 2857 MHz 13801 MHz 55 100 % 400.52 W 400.14 W
25 2026/10/09 08:49:14.552 401.03 W 2857 MHz 13801 MHz 56 100 % 402.02 W 401.03 W
26 2026/10/09 08:49:15.553 401.86 W 2857 MHz 13801 MHz 56 100 % 402.06 W 401.86 W
27 2026/10/09 08:49:16.553 403.29 W 2857 MHz 13801 MHz 56 100 % 402.77 W 403.29 W
28 2026/10/09 08:49:17.553 403.19 W 2857 MHz 13801 MHz 56 100 % 402.12 W 403.19 W
29 2026/10/09 08:49:18.553 401.89 W 2857 MHz 13801 MHz 56 100 % 401.91 W 401.89 W
30 2026/10/09 08:49:19.553 402.59 W 2857 MHz 13801 MHz 56 100 % 404.10 W 402.59 W
31 2026/10/09 08:49:20.553 402.26 W 2857 MHz 13801 MHz 56 100 % 399.49 W 402.26 W
32 2026/10/09 08:49:21.554 400.01 W 2850 MHz 13801 MHz 57 100 % 400.05 W 400.01 W
33 2026/10/09 08:49:22.554 400.00 W 2850 MHz 13801 MHz 57 100 % 400.64 W 400.00 W
34 2026/10/09 08:49:23.554 400.04 W 2850 MHz 13801 MHz 57 100 % 399.76 W 400.04 W
35 2026/10/09 08:49:24.554 399.89 W 2842 MHz 13801 MHz 57 100 % 398.90 W 399.89 W
36 2026/10/09 08:49:25.554 400.05 W 2842 MHz 13801 MHz 58 100 % 399.61 W 400.05 W
37 2026/10/09 08:49:26.554 400.05 W 2842 MHz 13801 MHz 58 100 % 401.06 W 400.05 W
38 2026/10/09 08:49:27.555 399.98 W 2842 MHz 13801 MHz 58 100 % 400.43 W 399.98 W
39 2026/10/09 08:49:28.555 400.02 W 2842 MHz 13801 MHz 58 100 % 399.79 W 400.02 W
40 2026/10/09 08:49:29.555 399.92 W 2835 MHz 13801 MHz 59 100 % 399.23 W 399.92 W
41 2026/10/09 08:49:30.555 399.98 W 2835 MHz 13801 MHz 59 100 % 400.03 W 399.98 W
42 2026/10/09 08:49:31.555 400.01 W 2835 MHz 13801 MHz 59 100 % 400.85 W 400.01 W
43 2026/10/09 08:49:32.555 400.05 W 2835 MHz 13801 MHz 59 100 % 399.98 W 400.05 W
44 2026/10/09 08:49:33.556 399.99 W 2835 MHz 13801 MHz 60 100 % 399.85 W 399.99 W
45 2026/10/09 08:49:34.556 399.94 W 2827 MHz 13801 MHz 60 100 % 399.65 W 399.94 W
46 2026/10/09 08:49:35.556 400.02 W 2827 MHz 13801 MHz 60 100 % 400.01 W 400.02 W
47 2026/10/09 08:49:36.556 400.01 W 2827 MHz 13801 MHz 60 100 % 400.57 W 400.01 W
48 2026/10/09 08:49:37.556 399.97 W 2827 MHz 13801 MHz 60 100 % 399.94 W 399.97 W
49 2026/10/09 08:49:38.556 399.93 W 2827 MHz 13801 MHz 61 100 % 399.32 W 399.93 W
50 2026/10/09 08:49:39.557 399.95 W 2820 MHz 13801 MHz 61 100 % 399.61 W 399.95 W
51 2026/10/09 08:49:40.557 400.01 W 2820 MHz 13801 MHz 61 100 % 400.79 W 400.01 W
52 2026/10/09 08:49:41.557 399.97 W 2820 MHz 13801 MHz 61 100 % 400.47 W 399.97 W
53 2026/10/09 08:49:42.557 400.03 W 2820 MHz 13801 MHz 61 100 % 399.91 W 400.03 W
54 2026/10/09 08:49:43.557 399.92 W 2820 MHz 13801 MHz 61 100 % 399.38 W 399.92 W
55 2026/10/09 08:49:44.558 399.98 W 2820 MHz 13801 MHz 61 100 % 399.83 W 399.98 W
56 2026/10/09 08:49:45.558 400.03 W 2820 MHz 13801 MHz 62 100 % 401.27 W 400.03 W
57 2026/10/09 08:49:46.558 399.98 W 2812 MHz 13801 MHz 62 100 % 400.24 W 399.98 W
58 2026/10/09 08:49:47.558 400.02 W 2812 MHz 13801 MHz 62 100 % 399.78 W 400.02 W
59 2026/10/09 08:49:48.558 399.90 W 2812 MHz 13801 MHz 62 100 % 399.21 W 399.90 W
60 2026/10/09 08:49:49.559 400.07 W 2812 MHz 13801 MHz 62 100 % 400.01 W 400.07 W
61 2026/10/09 08:49:50.559 400.00 W 2812 MHz 13801 MHz 62 100 % 400.89 W 400.00 W
62 2026/10/09 08:49:51.559 400.05 W 2812 MHz 13801 MHz 62 100 % 399.98 W 400.05 W
63 2026/10/09 08:49:52.559 399.99 W 2812 MHz 13801 MHz 62 100 % 399.83 W 399.99 W
64 2026/10/09 08:49:53.559 399.94 W 2812 MHz 13801 MHz 62 100 % 399.57 W 399.94 W
65 2026/10/09 08:49:54.560 400.00 W 2812 MHz 13801 MHz 63 100 % 400.18 W 400.00 W
66 2026/10/09 08:49:55.560 399.98 W 2812 MHz 13801 MHz 63 100 % 400.46 W 399.98 W
67 2026/10/09 08:49:56.560 400.02 W 2812 MHz 13801 MHz 63 100 % 399.81 W 400.02 W
68 2026/10/09 08:49:57.560 399.92 W 2805 MHz 13801 MHz 63 100 % 399.07 W 399.92 W
69 2026/10/09 08:49:58.561 399.97 W 2805 MHz 13801 MHz 63 100 % 399.82 W 399.97 W
70 2026/10/09 08:49:59.561 369.35 W 2805 MHz 14001 MHz 59 2 % 113.52 W 369.35 W
71 2026/10/09 08:50:00.561 105.97 W 2865 MHz 14001 MHz 57 0 % 103.57 W 105.97 W
72 2026/10/09 08:50:01.562 104.20 W 2865 MHz 14001 MHz 56 0 % 103.73 W 104.20 W
73 2026/10/09 08:50:02.562 87.47 W 555 MHz 14001 MHz 55 0 % 87.47 W 87.47 W
74 2026/10/09 08:50:03.562 66.20 W 352 MHz 7001 MHz 53 0 % 44.92 W 66.20 W
75 2026/10/09 08:50:04.562 43.06 W 225 MHz 810 MHz 53 0 % 43.06 W 43.06 W
76 2026/10/09 08:50:05.563 37.91 W 180 MHz 810 MHz 52 0 % 32.76 W 37.91 W
77 2026/10/09 08:50:06.563 31.34 W 180 MHz 405 MHz 51 0 % 31.34 W 31.34 W
78 2026/10/09 08:50:07.563 29.93 W 180 MHz 405 MHz 51 0 % 29.93 W 29.93 W
79 2026/10/09 08:50:08.563 29.64 W 180 MHz 405 MHz 50 0 % 29.36 W 29.64 W
80 2026/10/09 08:50:09.564 29.28 W 180 MHz 405 MHz 50 0 % 29.28 W 29.28 W
81 2026/10/09 08:50:10.564 45.92 W 2400 MHz 13801 MHz 50 0 % 72.77 W 45.92 W
82 2026/10/09 08:50:11.564 72.64 W 2400 MHz 13801 MHz 50 0 % 72.62 W 72.64 W
83 2026/10/09 08:50:12.565 77.49 W 2400 MHz 13801 MHz 50 0 % 72.69 W 77.49 W
84 2026/10/09 08:50:13.565 144.93 W 2640 MHz 13801 MHz 55 57 % 245.30 W 144.93 W
85 2026/10/09 08:50:14.565 364.18 W 2857 MHz 13801 MHz 58 100 % 406.30 W 364.18 W
86 2026/10/09 08:50:15.565 406.06 W 2857 MHz 13801 MHz 58 100 % 406.71 W 406.06 W
87 2026/10/09 08:50:16.566 405.95 W 2857 MHz 13801 MHz 59 100 % 400.41 W 405.95 W
88 2026/10/09 08:50:17.566 400.14 W 2842 MHz 13801 MHz 59 100 % 399.81 W 400.14 W
89 2026/10/09 08:50:18.566 400.03 W 2842 MHz 13801 MHz 59 100 % 400.90 W 400.03 W
90 2026/10/09 08:50:19.566 400.06 W 2842 MHz 13801 MHz 60 100 % 400.18 W 400.06 W
91 2026/10/09 08:50:20.567 400.00 W 2842 MHz 13801 MHz 60 100 % 399.85 W 400.00 W
92 2026/10/09 08:50:21.567 399.92 W 2842 MHz 13801 MHz 60 100 % 399.31 W 399.92 W
93 2026/10/09 08:50:22.567 399.97 W 2842 MHz 13801 MHz 60 100 % 399.79 W 399.97 W
94 2026/10/09 08:50:23.567 400.04 W 2842 MHz 13801 MHz 60 100 % 400.90 W 400.04 W
95 2026/10/09 08:50:24.568 400.05 W 2835 MHz 13801 MHz 61 100 % 400.32 W 400.05 W
96 2026/10/09 08:50:25.568 400.02 W 2835 MHz 13801 MHz 61 100 % 399.83 W 400.02 W
97 2026/10/09 08:50:26.568 399.93 W 2835 MHz 13801 MHz 61 100 % 399.34 W 399.93 W
98 2026/10/09 08:50:27.569 400.06 W 2835 MHz 13801 MHz 61 100 % 400.01 W 400.06 W
99 2026/10/09 08:50:28.569 400.00 W 2835 MHz 13801 MHz 61 100 % 400.80 W 400.00 W
100 2026/10/09 08:50:29.569 400.01 W 2835 MHz 13801 MHz 61 100 % 400.20 W 400.01 W
101 2026/10/09 08:50:30.569 400.01 W 2835 MHz 13801 MHz 62 100 % 399.79 W 400.01 W
102 2026/10/09 08:50:31.570 399.93 W 2835 MHz 13801 MHz 62 100 % 399.46 W 399.93 W
103 2026/10/09 08:50:32.570 400.03 W 2827 MHz 13801 MHz 62 100 % 399.89 W 400.03 W
104 2026/10/09 08:50:33.570 399.98 W 2827 MHz 13801 MHz 62 100 % 400.51 W 399.98 W
105 2026/10/09 08:50:34.570 400.02 W 2827 MHz 13801 MHz 62 100 % 399.94 W 400.02 W
106 2026/10/09 08:50:35.571 400.00 W 2827 MHz 13801 MHz 62 100 % 399.93 W 400.00 W
107 2026/10/09 08:50:36.571 399.94 W 2827 MHz 13801 MHz 62 100 % 399.67 W 399.94 W
108 2026/10/09 08:50:37.571 400.00 W 2827 MHz 13801 MHz 62 100 % 400.04 W 400.00 W
109 2026/10/09 08:50:38.571 400.00 W 2827 MHz 13801 MHz 63 100 % 400.57 W 400.00 W
110 2026/10/09 08:50:39.572 400.03 W 2827 MHz 13801 MHz 63 100 % 399.92 W 400.03 W
111 2026/10/09 08:50:40.572 400.00 W 2827 MHz 13801 MHz 63 100 % 400.04 W 400.00 W
112 2026/10/09 08:50:41.572 399.95 W 2820 MHz 13801 MHz 63 100 % 399.57 W 399.95 W
113 2026/10/09 08:50:42.572 400.06 W 2805 MHz 13801 MHz 63 100 % 400.11 W 400.06 W
114 2026/10/09 08:50:43.573 399.98 W 2805 MHz 13801 MHz 63 100 % 400.56 W 399.98 W
115 2026/10/09 08:50:44.573 400.03 W 2805 MHz 13801 MHz 63 100 % 399.79 W 400.03 W
116 2026/10/09 08:50:45.573 399.82 W 2805 MHz 13801 MHz 63 100 % 398.23 W 399.82 W
117 2026/10/09 08:50:46.574 400.12 W 2805 MHz 13801 MHz 63 100 % 399.65 W 400.12 W
118 2026/10/09 08:50:47.574 400.01 W 2805 MHz 13801 MHz 63 100 % 400.71 W 400.01 W
119 2026/10/09 08:50:48.574 400.05 W 2805 MHz 13801 MHz 63 100 % 400.43 W 400.05 W
120 2026/10/09 08:50:49.574 400.02 W 2805 MHz 13801 MHz 63 100 % 399.82 W 400.02 W
121 2026/10/09 08:50:50.575 399.93 W 2805 MHz 13801 MHz 63 100 % 399.23 W 399.93 W
122 2026/10/09 08:50:51.575 400.03 W 2805 MHz 13801 MHz 64 100 % 399.80 W 400.03 W
123 2026/10/09 08:50:52.575 400.01 W 2805 MHz 13801 MHz 64 100 % 401.14 W 400.01 W
124 2026/10/09 08:50:53.575 400.08 W 2805 MHz 13801 MHz 64 100 % 400.23 W 400.08 W
125 2026/10/09 08:50:54.576 399.97 W 2805 MHz 13801 MHz 64 100 % 399.72 W 399.97 W
126 2026/10/09 08:50:55.576 399.94 W 2805 MHz 13801 MHz 64 100 % 399.35 W 399.94 W
127 2026/10/09 08:50:56.576 400.04 W 2805 MHz 13801 MHz 64 100 % 399.85 W 400.04 W
128 2026/10/09 08:50:57.576 400.02 W 2805 MHz 13801 MHz 64 100 % 399.90 W 400.02 W
129 2026/10/09 08:50:58.577 400.07 W 2805 MHz 13801 MHz 64 100 % 400.17 W 400.07 W
130 2026/10/09 08:50:59.577 400.01 W 2805 MHz 13801 MHz 64 100 % 399.77 W 400.01 W
131 2026/10/09 08:51:00.577 399.94 W 2797 MHz 13801 MHz 64 100 % 399.37 W 399.94 W
132 2026/10/09 08:51:01.577 400.04 W 2797 MHz 13801 MHz 64 100 % 399.86 W 400.04 W
133 2026/10/09 08:51:02.578 400.03 W 2797 MHz 13801 MHz 64 100 % 403.09 W 400.03 W
134 2026/10/09 08:51:03.578 400.23 W 2797 MHz 13801 MHz 64 100 % 400.21 W 400.23 W
135 2026/10/09 08:51:04.578 400.01 W 2797 MHz 13801 MHz 64 100 % 399.74 W 400.01 W
136 2026/10/09 08:51:05.579 399.93 W 2797 MHz 13801 MHz 64 100 % 399.36 W 399.93 W
137 2026/10/09 08:51:06.579 400.05 W 2797 MHz 13801 MHz 64 100 % 399.95 W 400.05 W
138 2026/10/09 08:51:07.579 400.01 W 2797 MHz 13801 MHz 64 100 % 400.78 W 400.01 W
139 2026/10/09 08:51:08.579 400.05 W 2797 MHz 13801 MHz 64 100 % 400.01 W 400.05 W
140 2026/10/09 08:51:09.580 400.00 W 2797 MHz 13801 MHz 64 100 % 399.86 W 400.00 W
141 2026/10/09 08:51:10.580 399.95 W 2797 MHz 13801 MHz 64 100 % 399.59 W 399.95 W
142 2026/10/09 08:51:11.580 399.98 W 2797 MHz 13801 MHz 64 100 % 399.90 W 399.98 W
143 2026/10/09 08:51:12.580 400.00 W 2797 MHz 13801 MHz 64 100 % 400.54 W 400.00 W
144 2026/10/09 08:51:13.581 290.91 W 2865 MHz 14001 MHz 59 0 % 108.62 W 290.91 W
145 2026/10/09 08:51:14.581 109.49 W 2865 MHz 14001 MHz 58 0 % 107.01 W 109.49 W
146 2026/10/09 08:51:15.581 90.91 W 1222 MHz 14001 MHz 56 0 % 90.91 W 90.91 W
147 2026/10/09 08:51:16.582 43.06 W 367 MHz 810 MHz 55 0 % 43.06 W 43.06 W
148 2026/10/09 08:51:17.582 39.51 W 217 MHz 810 MHz 54 0 % 35.96 W 39.51 W
149 2026/10/09 08:51:18.582 32.85 W 180 MHz 405 MHz 53 0 % 32.85 W 32.85 W
150 2026/10/09 08:51:19.582 32.77 W 180 MHz 405 MHz 53 0 % 32.69 W 32.77 W
151 2026/10/09 08:51:20.583 32.58 W 180 MHz 405 MHz 52 0 % 32.48 W 32.58 W
152 2026/10/09 08:51:21.583 32.28 W 172 MHz 405 MHz 52 0 % 32.07 W 32.28 W
153 2026/10/09 08:51:22.583 31.56 W 180 MHz 405 MHz 51 0 % 31.56 W 31.56 W
154 2026/10/09 08:51:23.583 33.42 W 180 MHz 14001 MHz 51 0 % 64.89 W 33.42 W
155 2026/10/09 08:51:24.584 75.20 W 2400 MHz 13801 MHz 51 0 % 74.97 W 75.20 W
156 2026/10/09 08:51:25.584 74.92 W 2400 MHz 13801 MHz 51 0 % 74.85 W 74.92 W
157 2026/10/09 08:51:26.584 79.39 W 2400 MHz 13801 MHz 51 0 % 74.32 W 79.39 W
158 2026/10/09 08:51:27.585 196.64 W 2865 MHz 13801 MHz 57 100 % 406.22 W 196.64 W
159 2026/10/09 08:51:28.585 408.47 W 2857 MHz 13801 MHz 59 100 % 409.47 W 408.47 W
160 2026/10/09 08:51:29.585 407.46 W 2857 MHz 13801 MHz 59 100 % 400.71 W 407.46 W
161 2026/10/09 08:51:30.585 399.94 W 2842 MHz 13801 MHz 59 100 % 399.26 W 399.94 W
162 2026/10/09 08:51:31.586 399.99 W 2842 MHz 13801 MHz 60 100 % 400.00 W 399.99 W
163 2026/10/09 08:51:32.586 400.01 W 2835 MHz 13801 MHz 60 100 % 400.83 W 400.01 W
164 2026/10/09 08:51:33.588 400.05 W 2835 MHz 13801 MHz 60 100 % 400.28 W 400.05 W
165 2026/10/09 08:51:34.588 400.00 W 2835 MHz 13801 MHz 60 100 % 399.90 W 400.00 W
166 2026/10/09 08:51:35.589 399.92 W 2835 MHz 13801 MHz 60 100 % 399.33 W 399.92 W
167 2026/10/09 08:51:36.589 399.98 W 2835 MHz 13801 MHz 61 100 % 399.85 W 399.98 W
168 2026/10/09 08:51:37.589 400.02 W 2835 MHz 13801 MHz 61 100 % 400.85 W 400.02 W
169 2026/10/09 08:51:38.589 400.05 W 2835 MHz 13801 MHz 61 100 % 399.89 W 400.05 W
170 2026/10/09 08:51:39.590 399.98 W 2835 MHz 13801 MHz 61 100 % 399.84 W 399.98 W
171 2026/10/09 08:51:40.590 399.94 W 2835 MHz 13801 MHz 61 100 % 399.64 W 399.94 W
172 2026/10/09 08:51:41.590 399.99 W 2827 MHz 13801 MHz 61 100 % 399.86 W 399.99 W
173 2026/10/09 08:51:42.590 400.00 W 2835 MHz 13801 MHz 62 100 % 400.59 W 400.00 W
174 2026/10/09 08:51:43.591 400.04 W 2827 MHz 13801 MHz 62 100 % 400.05 W 400.04 W
175 2026/10/09 08:51:44.591 400.00 W 2827 MHz 13801 MHz 62 100 % 399.85 W 400.00 W
176 2026/10/09 08:51:45.591 399.93 W 2827 MHz 13801 MHz 62 100 % 399.53 W 399.93 W
177 2026/10/09 08:51:46.592 399.98 W 2827 MHz 13801 MHz 62 100 % 399.94 W 399.98 W
178 2026/10/09 08:51:47.592 400.02 W 2827 MHz 13801 MHz 62 100 % 400.56 W 400.02 W
179 2026/10/09 08:51:48.592 400.03 W 2827 MHz 13801 MHz 62 100 % 399.94 W 400.03 W
180 2026/10/09 08:51:49.592 399.94 W 2827 MHz 13801 MHz 62 100 % 399.42 W 399.94 W
181 2026/10/09 08:51:50.593 399.94 W 2827 MHz 13801 MHz 63 100 % 399.61 W 399.94 W
182 2026/10/09 08:51:51.593 400.00 W 2827 MHz 13801 MHz 63 100 % 400.04 W 400.00 W
183 2026/10/09 08:51:52.593 399.95 W 2827 MHz 13801 MHz 63 100 % 400.46 W 399.95 W
184 2026/10/09 08:51:53.594 399.98 W 2827 MHz 13801 MHz 63 100 % 399.74 W 399.98 W
185 2026/10/09 08:51:54.594 399.90 W 2827 MHz 13801 MHz 63 100 % 399.13 W 399.90 W
186 2026/10/09 08:51:55.594 399.96 W 2827 MHz 13801 MHz 63 100 % 399.81 W 399.96 W
187 2026/10/09 08:51:56.594 400.06 W 2812 MHz 13801 MHz 63 100 % 400.92 W 400.06 W
188 2026/10/09 08:51:57.595 400.04 W 2805 MHz 13801 MHz 63 100 % 400.21 W 400.04 W
189 2026/10/09 08:51:58.595 400.00 W 2812 MHz 13801 MHz 63 100 % 399.72 W 400.00 W
190 2026/10/09 08:51:59.595 399.92 W 2805 MHz 13801 MHz 63 100 % 399.20 W 399.92 W
191 2026/10/09 08:52:00.595 400.04 W 2805 MHz 13801 MHz 63 100 % 399.80 W 400.04 W
192 2026/10/09 08:52:01.596 400.02 W 2805 MHz 13801 MHz 63 100 % 400.94 W 400.02 W
193 2026/10/09 08:52:02.596 400.06 W 2805 MHz 13801 MHz 63 100 % 400.09 W 400.06 W
194 2026/10/09 08:52:03.596 400.00 W 2805 MHz 13801 MHz 63 100 % 399.85 W 400.00 W
195 2026/10/09 08:52:04.596 399.90 W 2805 MHz 13801 MHz 64 100 % 399.30 W 399.90 W
196 2026/10/09 08:52:05.597 399.98 W 2805 MHz 13801 MHz 64 100 % 399.81 W 399.98 W
197 2026/10/09 08:52:06.597 400.02 W 2805 MHz 13801 MHz 64 100 % 400.80 W 400.02 W
198 2026/10/09 08:52:07.597 400.06 W 2805 MHz 13801 MHz 64 100 % 400.19 W 400.06 W
199 2026/10/09 08:52:08.598 399.98 W 2805 MHz 13801 MHz 64 100 % 399.79 W 399.98 W
200 2026/10/09 08:52:09.598 399.92 W 2805 MHz 13801 MHz 64 100 % 399.38 W 399.92 W
201 2026/10/09 08:52:10.598 400.04 W 2805 MHz 13801 MHz 64 100 % 399.99 W 400.04 W
202 2026/10/09 08:52:11.599 400.00 W 2805 MHz 13801 MHz 64 100 % 400.83 W 400.00 W
203 2026/10/09 08:52:12.599 400.05 W 2805 MHz 13801 MHz 64 100 % 400.04 W 400.05 W
204 2026/10/09 08:52:13.599 399.99 W 2805 MHz 13801 MHz 64 100 % 399.82 W 399.99 W
205 2026/10/09 08:52:14.599 399.94 W 2805 MHz 13801 MHz 64 100 % 399.49 W 399.94 W
206 2026/10/09 08:52:15.600 400.04 W 2805 MHz 13801 MHz 64 100 % 400.12 W 400.04 W
207 2026/10/09 08:52:16.600 400.00 W 2805 MHz 13801 MHz 64 100 % 400.80 W 400.00 W
208 2026/10/09 08:52:17.600 399.98 W 2805 MHz 13801 MHz 64 100 % 399.94 W 399.98 W
209 2026/10/09 08:52:18.601 400.00 W 2797 MHz 13801 MHz 64 100 % 399.86 W 400.00 W
210 2026/10/09 08:52:19.601 399.93 W 2797 MHz 13801 MHz 64 100 % 399.58 W 399.93 W
211 2026/10/09 08:52:20.601 400.04 W 2797 MHz 13801 MHz 64 100 % 399.95 W 400.04 W
212 2026/10/09 08:52:21.601 400.01 W 2797 MHz 13801 MHz 64 100 % 400.56 W 400.01 W
213 2026/10/09 08:52:22.602 400.03 W 2797 MHz 13801 MHz 64 100 % 399.97 W 400.03 W
214 2026/10/09 08:52:23.602 400.00 W 2797 MHz 13801 MHz 64 100 % 399.99 W 400.00 W
215 2026/10/09 08:52:24.602 399.94 W 2797 MHz 13801 MHz 64 100 % 399.64 W 399.94 W
216 2026/10/09 08:52:25.602 400.01 W 2797 MHz 13801 MHz 64 100 % 400.05 W 400.01 W
217 2026/10/09 08:52:26.603 399.99 W 2797 MHz 13801 MHz 64 100 % 400.45 W 399.99 W
218 2026/10/09 08:52:27.603 224.91 W 2865 MHz 14001 MHz 58 0 % 107.57 W 224.91 W
219 2026/10/09 08:52:28.603 108.82 W 2865 MHz 14001 MHz 58 0 % 107.04 W 108.82 W
220 2026/10/09 08:52:29.603 90.86 W 1672 MHz 14001 MHz 56 0 % 90.86 W 90.86 W
221 2026/10/09 08:52:30.604 43.38 W 375 MHz 810 MHz 55 0 % 43.38 W 43.38 W
222 2026/10/09 08:52:31.604 39.31 W 217 MHz 810 MHz 54 0 % 35.24 W 39.31 W
223 2026/10/09 08:52:32.604 34.21 W 180 MHz 405 MHz 53 0 % 33.17 W 34.21 W
224 2026/10/09 08:52:33.604 32.65 W 180 MHz 405 MHz 53 0 % 32.65 W 32.65 W
225 2026/10/09 08:52:34.605 32.32 W 180 MHz 405 MHz 52 0 % 32.32 W 32.32 W
226 2026/10/09 08:52:35.605 32.09 W 180 MHz 405 MHz 52 0 % 31.86 W 32.09 W
227 2026/10/09 08:52:36.605 31.65 W 180 MHz 405 MHz 51 0 % 31.65 W 31.65 W
228 2026/10/09 08:52:37.605 39.59 W 1050 MHz 13801 MHz 51 0 % 75.16 W 39.59 W
229 2026/10/09 08:52:38.606 74.97 W 2400 MHz 13801 MHz 51 0 % 74.84 W 74.97 W
230 2026/10/09 08:52:39.606 74.63 W 2400 MHz 13801 MHz 52 4 % 74.56 W 74.63 W
231 2026/10/09 08:52:40.606 79.67 W 2400 MHz 13801 MHz 51 0 % 74.18 W 79.67 W
232 2026/10/09 08:52:41.607 280.63 W 2865 MHz 13801 MHz 59 100 % 416.66 W 280.63 W
233 2026/10/09 08:52:42.607 411.55 W 2842 MHz 13801 MHz 59 100 % 400.48 W 411.55 W
234 2026/10/09 08:52:43.607 400.05 W 2827 MHz 13801 MHz 59 100 % 399.86 W 400.05 W
235 2026/10/09 08:52:44.607 399.92 W 2827 MHz 13801 MHz 60 100 % 399.41 W 399.92 W
236 2026/10/09 08:52:45.608 399.98 W 2820 MHz 13801 MHz 60 100 % 399.96 W 399.98 W
237 2026/10/09 08:52:46.608 400.01 W 2820 MHz 13801 MHz 60 100 % 400.83 W 400.01 W
238 2026/10/09 08:52:47.608 400.05 W 2820 MHz 13801 MHz 60 100 % 399.99 W 400.05 W
239 2026/10/09 08:52:48.608 399.99 W 2820 MHz 13801 MHz 60 100 % 399.88 W 399.99 W
240 2026/10/09 08:52:49.609 399.94 W 2820 MHz 13801 MHz 61 100 % 399.55 W 399.94 W
241 2026/10/09 08:52:50.609 400.05 W 2820 MHz 13801 MHz 61 100 % 400.16 W 400.05 W
242 2026/10/09 08:52:51.609 400.01 W 2812 MHz 13801 MHz 61 100 % 400.50 W 400.01 W
243 2026/10/09 08:52:52.609 399.97 W 2812 MHz 13801 MHz 61 100 % 399.78 W 399.97 W
244 2026/10/09 08:52:53.610 399.92 W 2812 MHz 13801 MHz 61 100 % 399.10 W 399.92 W
245 2026/10/09 08:52:54.610 399.97 W 2812 MHz 13801 MHz 62 100 % 399.99 W 399.97 W
246 2026/10/09 08:52:55.610 400.02 W 2812 MHz 13801 MHz 62 100 % 400.91 W 400.02 W
247 2026/10/09 08:52:56.610 400.06 W 2812 MHz 13801 MHz 62 100 % 400.20 W 400.06 W
248 2026/10/09 08:52:57.611 399.98 W 2812 MHz 13801 MHz 62 100 % 399.81 W 399.98 W
249 2026/10/09 08:52:58.611 399.92 W 2812 MHz 13801 MHz 62 100 % 399.35 W 399.92 W
250 2026/10/09 08:52:59.611 400.06 W 2812 MHz 13801 MHz 62 100 % 399.90 W 400.06 W
251 2026/10/09 08:53:00.611 400.00 W 2812 MHz 13801 MHz 62 100 % 400.84 W 400.00 W
252 2026/10/09 08:53:01.612 400.04 W 2812 MHz 13801 MHz 62 100 % 400.01 W 400.04 W
253 2026/10/09 08:53:02.612 400.00 W 2812 MHz 13801 MHz 63 100 % 399.86 W 400.00 W
254 2026/10/09 08:53:03.612 399.95 W 2812 MHz 13801 MHz 63 100 % 399.63 W 399.95 W
255 2026/10/09 08:53:04.612 399.99 W 2805 MHz 13801 MHz 63 100 % 399.94 W 399.99 W
256 2026/10/09 08:53:05.613 399.99 W 2797 MHz 13801 MHz 63 100 % 400.45 W 399.99 W
257 2026/10/09 08:53:06.613 399.98 W 2797 MHz 13801 MHz 63 100 % 399.91 W 399.98 W
258 2026/10/09 08:53:07.613 400.00 W 2797 MHz 13801 MHz 63 100 % 399.96 W 400.00 W
259 2026/10/09 08:53:08.613 399.94 W 2790 MHz 13801 MHz 63 100 % 399.51 W 399.94 W
260 2026/10/09 08:53:09.614 400.01 W 2790 MHz 13801 MHz 63 100 % 400.07 W 400.01 W
261 2026/10/09 08:53:10.614 399.98 W 2797 MHz 13801 MHz 63 100 % 400.53 W 399.98 W
262 2026/10/09 08:53:11.614 400.03 W 2790 MHz 13801 MHz 63 100 % 399.86 W 400.03 W
263 2026/10/09 08:53:12.615 399.91 W 2790 MHz 13801 MHz 63 100 % 399.11 W 399.91 W
264 2026/10/09 08:53:13.615 400.05 W 2790 MHz 13801 MHz 63 100 % 399.89 W 400.05 W
265 2026/10/09 08:53:14.615 400.05 W 2790 MHz 13801 MHz 63 100 % 401.52 W 400.05 W
266 2026/10/09 08:53:15.615 400.11 W 2790 MHz 13801 MHz 64 100 % 400.19 W 400.11 W
267 2026/10/09 08:53:16.616 399.98 W 2790 MHz 13801 MHz 64 100 % 399.78 W 399.98 W
268 2026/10/09 08:53:17.616 399.93 W 2790 MHz 13801 MHz 64 100 % 399.31 W 399.93 W
269 2026/10/09 08:53:18.616 399.98 W 2790 MHz 13801 MHz 64 100 % 400.01 W 399.98 W
270 2026/10/09 08:53:19.617 400.02 W 2790 MHz 13801 MHz 64 100 % 400.84 W 400.02 W
271 2026/10/09 08:53:20.617 399.96 W 2790 MHz 13801 MHz 64 100 % 399.92 W 399.96 W
272 2026/10/09 08:53:21.617 399.99 W 2790 MHz 13801 MHz 64 100 % 399.91 W 399.99 W
273 2026/10/09 08:53:22.617 399.95 W 2790 MHz 13801 MHz 64 100 % 399.58 W 399.95 W
274 2026/10/09 08:53:23.618 400.03 W 2790 MHz 13801 MHz 64 100 % 399.98 W 400.03 W
275 2026/10/09 08:53:24.618 400.00 W 2790 MHz 13801 MHz 64 100 % 400.40 W 400.00 W
276 2026/10/09 08:53:25.618 400.02 W 2790 MHz 13801 MHz 64 100 % 399.90 W 400.02 W
277 2026/10/09 08:53:26.618 399.93 W 2790 MHz 13801 MHz 64 100 % 399.24 W 399.93 W
278 2026/10/09 08:53:27.619 400.01 W 2790 MHz 13801 MHz 64 100 % 399.62 W 400.01 W
279 2026/10/09 08:53:28.619 400.04 W 2790 MHz 13801 MHz 64 100 % 400.83 W 400.04 W
280 2026/10/09 08:53:29.620 400.06 W 2790 MHz 13801 MHz 64 100 % 400.39 W 400.06 W
281 2026/10/09 08:53:30.620 399.98 W 2790 MHz 13801 MHz 64 100 % 399.82 W 399.98 W
282 2026/10/09 08:53:31.620 399.92 W 2790 MHz 13801 MHz 64 100 % 399.18 W 399.92 W
283 2026/10/09 08:53:32.620 399.93 W 2782 MHz 13801 MHz 64 100 % 399.38 W 399.93 W
284 2026/10/09 08:53:33.621 400.01 W 2782 MHz 13801 MHz 64 100 % 401.03 W 400.01 W
285 2026/10/09 08:53:34.621 399.97 W 2782 MHz 13801 MHz 64 100 % 400.28 W 399.97 W
286 2026/10/09 08:53:35.621 400.02 W 2782 MHz 13801 MHz 64 100 % 399.84 W 400.02 W
287 2026/10/09 08:53:36.621 399.90 W 2782 MHz 13801 MHz 64 100 % 399.15 W 399.90 W
288 2026/10/09 08:53:37.622 399.99 W 2782 MHz 13801 MHz 64 100 % 399.93 W 399.99 W
289 2026/10/09 08:53:38.622 400.00 W 2782 MHz 13801 MHz 64 100 % 400.80 W 400.00 W
290 2026/10/09 08:53:39.622 399.97 W 2782 MHz 13801 MHz 64 100 % 399.98 W 399.97 W
291 2026/10/09 08:53:40.623 400.00 W 2782 MHz 14001 MHz 61 100 % 399.83 W 400.00 W
292 2026/10/09 08:53:41.623 112.43 W 2865 MHz 14001 MHz 58 0 % 106.84 W 112.43 W
293 2026/10/09 08:53:42.623 108.42 W 2865 MHz 14001 MHz 58 0 % 106.38 W 108.42 W
294 2026/10/09 08:53:43.624 90.36 W 577 MHz 7001 MHz 56 0 % 90.36 W 90.36 W
295 2026/10/09 08:53:44.624 48.02 W 360 MHz 7001 MHz 55 0 % 48.02 W 48.02 W
296 2026/10/09 08:53:45.624 46.67 W 232 MHz 7001 MHz 54 0 % 46.67 W 46.67 W
297 2026/10/09 08:53:46.624 46.34 W 180 MHz 7001 MHz 54 0 % 46.01 W 46.34 W
298 2026/10/09 08:53:47.625 45.69 W 180 MHz 7001 MHz 53 0 % 45.38 W 45.69 W
299 2026/10/09 08:53:48.625 36.56 W 180 MHz 810 MHz 52 0 % 36.56 W 36.56 W
300 2026/10/09 08:53:49.625 35.26 W 180 MHz 405 MHz 52 0 % 33.96 W 35.26 W
301 2026/10/09 08:53:50.626 32.47 W 180 MHz 405 MHz 51 0 % 32.47 W 32.47 W
302 2026/10/09 08:53:51.626 46.52 W 2400 MHz 13801 MHz 52 0 % 73.77 W 46.52 W
303 2026/10/09 08:53:52.626 73.65 W 2400 MHz 13801 MHz 52 0 % 73.65 W 73.65 W
304 2026/10/09 08:53:53.626 92.43 W 2482 MHz 13801 MHz 52 0 % 73.62 W 92.43 W
305 2026/10/09 08:53:54.627 122.80 W 2407 MHz 13801 MHz 58 100 % 407.76 W 122.80 W
306 2026/10/09 08:53:55.627 354.35 W 2857 MHz 13801 MHz 59 100 % 412.33 W 354.35 W
307 2026/10/09 08:53:56.627 408.27 W 2850 MHz 13801 MHz 59 100 % 399.02 W 408.27 W
308 2026/10/09 08:53:57.628 399.88 W 2835 MHz 13801 MHz 60 99 % 398.39 W 399.88 W
309 2026/10/09 08:53:58.628 400.10 W 2835 MHz 13801 MHz 60 100 % 399.71 W 400.10 W
310 2026/10/09 08:53:59.628 400.01 W 2827 MHz 13801 MHz 60 100 % 399.96 W 400.01 W
311 2026/10/09 08:54:00.628 400.01 W 2827 MHz 13801 MHz 60 100 % 400.04 W 400.01 W
312 2026/10/09 08:54:01.629 399.99 W 2827 MHz 13801 MHz 61 100 % 400.79 W 399.99 W
313 2026/10/09 08:54:02.629 400.06 W 2827 MHz 13801 MHz 61 100 % 400.58 W 400.06 W
314 2026/10/09 08:54:03.629 399.98 W 2827 MHz 13801 MHz 61 100 % 400.21 W 399.98 W
315 2026/10/09 08:54:04.629 400.00 W 2827 MHz 13801 MHz 61 100 % 399.95 W 400.00 W
316 2026/10/09 08:54:05.630 399.99 W 2827 MHz 13801 MHz 61 100 % 399.81 W 399.99 W
317 2026/10/09 08:54:06.630 399.97 W 2827 MHz 13801 MHz 62 100 % 399.88 W 399.97 W
318 2026/10/09 08:54:07.630 399.91 W 2827 MHz 13801 MHz 62 100 % 399.19 W 399.91 W
319 2026/10/09 08:54:08.631 399.95 W 2820 MHz 13801 MHz 62 100 % 399.60 W 399.95 W
320 2026/10/09 08:54:09.631 399.99 W 2820 MHz 13801 MHz 62 100 % 399.57 W 399.99 W
321 2026/10/09 08:54:10.631 400.03 W 2820 MHz 13801 MHz 62 100 % 399.94 W 400.03 W
322 2026/10/09 08:54:11.631 400.01 W 2820 MHz 13801 MHz 62 100 % 400.34 W 400.01 W
323 2026/10/09 08:54:12.632 400.01 W 2820 MHz 13801 MHz 62 100 % 400.70 W 400.01 W
324 2026/10/09 08:54:13.632 400.00 W 2820 MHz 13801 MHz 63 100 % 400.55 W 400.00 W
325 2026/10/09 08:54:14.632 400.02 W 2820 MHz 13801 MHz 63 100 % 400.19 W 400.02 W
326 2026/10/09 08:54:15.632 399.99 W 2820 MHz 13801 MHz 63 100 % 399.96 W 399.99 W
327 2026/10/09 08:54:16.633 400.00 W 2820 MHz 13801 MHz 63 100 % 399.82 W 400.00 W
328 2026/10/09 08:54:17.633 399.98 W 2820 MHz 13801 MHz 63 100 % 399.97 W 399.98 W
329 2026/10/09 08:54:18.633 399.93 W 2805 MHz 13801 MHz 63 100 % 399.30 W 399.93 W
330 2026/10/09 08:54:19.634 399.95 W 2805 MHz 13801 MHz 63 100 % 399.61 W 399.95 W
331 2026/10/09 08:54:20.634 399.98 W 2797 MHz 13801 MHz 63 100 % 399.80 W 399.98 W
332 2026/10/09 08:54:21.634 400.01 W 2805 MHz 13801 MHz 63 100 % 399.99 W 400.01 W
333 2026/10/09 08:54:22.634 400.00 W 2797 MHz 13801 MHz 64 100 % 401.08 W 400.00 W
334 2026/10/09 08:54:23.635 400.00 W 2797 MHz 13801 MHz 64 100 % 400.96 W 400.00 W
335 2026/10/09 08:54:24.635 400.08 W 2797 MHz 13801 MHz 64 100 % 400.61 W 400.08 W
336 2026/10/09 08:54:25.635 399.97 W 2797 MHz 13801 MHz 64 100 % 400.82 W 399.97 W
337 2026/10/09 08:54:26.635 400.07 W 2797 MHz 13801 MHz 64 100 % 399.80 W 400.07 W
338 2026/10/09 08:54:27.636 400.00 W 2797 MHz 13801 MHz 64 100 % 399.73 W 400.00 W
339 2026/10/09 08:54:28.636 399.98 W 2797 MHz 13801 MHz 64 100 % 399.93 W 399.98 W
340 2026/10/09 08:54:29.636 399.93 W 2797 MHz 13801 MHz 64 100 % 399.40 W 399.93 W
341 2026/10/09 08:54:30.637 399.96 W 2797 MHz 13801 MHz 64 100 % 399.62 W 399.96 W
342 2026/10/09 08:54:31.637 400.00 W 2797 MHz 13801 MHz 64 100 % 399.75 W 400.00 W
343 2026/10/09 08:54:32.637 399.99 W 2797 MHz 13801 MHz 64 100 % 399.96 W 399.99 W
344 2026/10/09 08:54:33.637 400.02 W 2790 MHz 13801 MHz 64 100 % 401.04 W 400.02 W
345 2026/10/09 08:54:34.638 400.08 W 2790 MHz 13801 MHz 64 100 % 400.73 W 400.08 W
346 2026/10/09 08:54:35.638 400.06 W 2790 MHz 13801 MHz 64 100 % 400.51 W 400.06 W
347 2026/10/09 08:54:36.638 399.98 W 2790 MHz 13801 MHz 64 100 % 400.03 W 399.98 W
348 2026/10/09 08:54:37.639 399.99 W 2790 MHz 13801 MHz 64 100 % 399.79 W 399.99 W
349 2026/10/09 08:54:38.639 399.99 W 2790 MHz 13801 MHz 64 100 % 399.79 W 399.99 W
350 2026/10/09 08:54:39.639 399.97 W 2790 MHz 13801 MHz 64 100 % 399.93 W 399.97 W
351 2026/10/09 08:54:40.639 399.92 W 2790 MHz 13801 MHz 64 100 % 399.27 W 399.92 W
352 2026/10/09 08:54:41.640 400.06 W 2790 MHz 13801 MHz 65 100 % 400.46 W 400.06 W
353 2026/10/09 08:54:42.640 399.98 W 2790 MHz 13801 MHz 65 100 % 400.18 W 399.98 W
354 2026/10/09 08:54:43.640 400.01 W 2790 MHz 13801 MHz 65 100 % 399.99 W 400.01 W
355 2026/10/09 08:54:44.641 399.99 W 2790 MHz 13801 MHz 65 100 % 399.82 W 399.99 W
356 2026/10/09 08:54:45.641 400.01 W 2790 MHz 13801 MHz 65 100 % 399.95 W 400.01 W
357 2026/10/09 08:54:46.641 399.91 W 2790 MHz 13801 MHz 65 100 % 399.27 W 399.91 W
358 2026/10/09 08:54:47.641 399.96 W 2790 MHz 13801 MHz 65 100 % 399.65 W 399.96 W
359 2026/10/09 08:54:48.642 399.99 W 2790 MHz 13801 MHz 65 100 % 399.80 W 399.99 W
360 2026/10/09 08:54:49.642 400.00 W 2790 MHz 13801 MHz 65 100 % 400.01 W 400.00 W
361 2026/10/09 08:54:50.642 400.01 W 2790 MHz 13801 MHz 65 100 % 400.77 W 400.01 W
362 2026/10/09 08:54:51.642 400.00 W 2790 MHz 13801 MHz 65 100 % 400.62 W 400.00 W
363 2026/10/09 08:54:52.642 399.98 W 2790 MHz 13801 MHz 65 100 % 400.50 W 399.98 W
364 2026/10/09 08:54:53.643 400.03 W 2790 MHz 13801 MHz 65 100 % 400.12 W 400.03 W
365 2026/10/09 08:54:54.643 399.99 W 2790 MHz 13801 MHz 65 100 % 399.88 W 399.99 W
366 2026/10/09 08:54:55.643 399.98 W 2790 MHz 13801 MHz 65 100 % 399.77 W 399.98 W
367 2026/10/09 08:54:56.643 209.80 W 2865 MHz 14001 MHz 59 0 % 108.06 W 209.80 W
368 2026/10/09 08:54:57.644 110.51 W 2865 MHz 14001 MHz 59 0 % 107.43 W 110.51 W
369 2026/10/09 08:54:58.644 92.15 W 1695 MHz 14001 MHz 57 0 % 92.15 W 92.15 W
370 2026/10/09 08:54:59.644 70.78 W 397 MHz 7001 MHz 56 0 % 49.40 W 70.78 W
371 2026/10/09 08:55:00.644 46.64 W 247 MHz 7001 MHz 55 0 % 46.64 W 46.64 W
372 2026/10/09 08:55:01.644 46.37 W 172 MHz 7001 MHz 54 0 % 46.11 W 46.37 W
373 2026/10/09 08:55:02.644 37.26 W 180 MHz 810 MHz 53 0 % 37.26 W 37.26 W
374 2026/10/09 08:55:03.645 35.77 W 180 MHz 405 MHz 53 0 % 34.28 W 35.77 W
375 2026/10/09 08:55:04.645 33.59 W 180 MHz 405 MHz 52 0 % 33.59 W 33.59 W
376 2026/10/09 08:55:05.645 33.42 W 180 MHz 405 MHz 52 0 % 33.25 W 33.42 W
377 2026/10/09 08:55:06.645 43.17 W 2430 MHz 13801 MHz 52 0 % 75.30 W 43.17 W
378 2026/10/09 08:55:07.646 74.99 W 2400 MHz 13801 MHz 52 0 % 74.78 W 74.99 W
379 2026/10/09 08:55:08.646 94.98 W 2482 MHz 13801 MHz 54 38 % 149.76 W 94.98 W
380 2026/10/09 08:55:09.646 74.33 W 2400 MHz 13801 MHz 52 0 % 73.71 W 74.33 W
381 2026/10/09 08:55:10.646 287.45 W 2857 MHz 13801 MHz 60 100 % 407.06 W 287.45 W
382 2026/10/09 08:55:11.646 406.21 W 2857 MHz 13801 MHz 60 100 % 406.74 W 406.21 W
383 2026/10/09 08:55:12.647 406.77 W 2857 MHz 13801 MHz 60 100 % 405.18 W 406.77 W
384 2026/10/09 08:55:13.647 401.04 W 2842 MHz 13801 MHz 60 100 % 399.33 W 401.04 W
385 2026/10/09 08:55:14.647 400.01 W 2842 MHz 13801 MHz 61 100 % 399.55 W 400.01 W
386 2026/10/09 08:55:15.647 399.98 W 2842 MHz 13801 MHz 61 100 % 399.75 W 399.98 W
387 2026/10/09 08:55:16.647 400.01 W 2842 MHz 13801 MHz 61 100 % 399.92 W 400.01 W
388 2026/10/09 08:55:17.648 400.00 W 2835 MHz 13801 MHz 61 100 % 400.90 W 400.00 W
389 2026/10/09 08:55:18.648 399.98 W 2835 MHz 13801 MHz 62 100 % 400.49 W 399.98 W
390 2026/10/09 08:55:19.648 400.03 W 2835 MHz 13801 MHz 62 100 % 400.31 W 400.03 W
391 2026/10/09 08:55:20.649 400.02 W 2835 MHz 13801 MHz 62 100 % 399.97 W 400.02 W
392 2026/10/09 08:55:21.649 399.98 W 2835 MHz 13801 MHz 62 100 % 399.74 W 399.98 W
393 2026/10/09 08:55:22.649 399.99 W 2835 MHz 13801 MHz 62 100 % 399.75 W 399.99 W
394 2026/10/09 08:55:23.649 399.98 W 2835 MHz 13801 MHz 62 100 % 399.95 W 399.98 W
395 2026/10/09 08:55:24.649 399.87 W 2835 MHz 13801 MHz 63 100 % 398.90 W 399.87 W
396 2026/10/09 08:55:25.649 399.94 W 2835 MHz 13801 MHz 63 100 % 399.41 W 399.94 W
397 2026/10/09 08:55:26.650 399.96 W 2835 MHz 13801 MHz 63 100 % 399.66 W 399.96 W
398 2026/10/09 08:55:27.650 400.03 W 2820 MHz 13801 MHz 63 100 % 399.95 W 400.03 W
399 2026/10/09 08:55:28.650 400.02 W 2820 MHz 13801 MHz 63 100 % 401.67 W 400.02 W
400 2026/10/09 08:55:29.650 400.15 W 2820 MHz 13801 MHz 63 100 % 401.16 W 400.15 W
401 2026/10/09 08:55:30.651 399.99 W 2812 MHz 13801 MHz 63 100 % 400.79 W 399.99 W
402 2026/10/09 08:55:31.651 400.05 W 2812 MHz 13801 MHz 63 100 % 400.28 W 400.05 W
403 2026/10/09 08:55:32.652 400.02 W 2812 MHz 13801 MHz 63 100 % 400.06 W 400.02 W
404 2026/10/09 08:55:33.652 399.98 W 2812 MHz 13801 MHz 64 100 % 399.83 W 399.98 W
405 2026/10/09 08:55:34.652 399.99 W 2812 MHz 13801 MHz 64 100 % 399.92 W 399.99 W
406 2026/10/09 08:55:35.652 399.93 W 2812 MHz 13801 MHz 64 100 % 399.44 W 399.93 W
407 2026/10/09 08:55:36.653 399.95 W 2812 MHz 13801 MHz 64 100 % 399.47 W 399.95 W
408 2026/10/09 08:55:37.653 398.44 W 2820 MHz 13801 MHz 63 92 % 383.20 W 398.44 W
409 2026/10/09 08:55:38.653 399.99 W 2812 MHz 13801 MHz 64 100 % 399.86 W 399.99 W
410 2026/10/09 08:55:39.653 400.00 W 2812 MHz 13801 MHz 64 100 % 399.90 W 400.00 W
411 2026/10/09 08:55:40.654 400.01 W 2812 MHz 13801 MHz 64 100 % 400.94 W 400.01 W
412 2026/10/09 08:55:41.654 400.08 W 2812 MHz 13801 MHz 64 100 % 401.22 W 400.08 W
413 2026/10/09 08:55:42.654 399.98 W 2805 MHz 13801 MHz 64 100 % 400.27 W 399.98 W
414 2026/10/09 08:55:43.655 400.01 W 2805 MHz 13801 MHz 64 100 % 400.05 W 400.01 W
415 2026/10/09 08:55:44.655 399.99 W 2805 MHz 13801 MHz 64 100 % 399.76 W 399.99 W
416 2026/10/09 08:55:45.655 400.00 W 2805 MHz 13801 MHz 64 100 % 399.87 W 400.00 W
417 2026/10/09 08:55:46.655 400.01 W 2805 MHz 13801 MHz 64 100 % 400.08 W 400.01 W
418 2026/10/09 08:55:47.656 399.89 W 2805 MHz 13801 MHz 65 100 % 399.21 W 399.89 W
419 2026/10/09 08:55:48.656 399.95 W 2805 MHz 13801 MHz 65 100 % 399.65 W 399.95 W
420 2026/10/09 08:55:49.656 400.01 W 2805 MHz 13801 MHz 65 100 % 399.85 W 400.01 W
421 2026/10/09 08:55:50.656 399.99 W 2805 MHz 13801 MHz 65 100 % 399.94 W 399.99 W
422 2026/10/09 08:55:51.657 400.00 W 2805 MHz 13801 MHz 65 100 % 400.89 W 400.00 W
423 2026/10/09 08:55:52.657 399.99 W 2805 MHz 13801 MHz 65 100 % 400.77 W 399.99 W
424 2026/10/09 08:55:53.657 400.05 W 2805 MHz 13801 MHz 65 100 % 400.47 W 400.05 W
425 2026/10/09 08:55:54.657 399.98 W 2805 MHz 13801 MHz 65 100 % 400.33 W 399.98 W
426 2026/10/09 08:55:55.658 400.02 W 2805 MHz 13801 MHz 65 100 % 399.74 W 400.02 W
427 2026/10/09 08:55:56.658 399.97 W 2805 MHz 13801 MHz 65 100 % 399.88 W 399.97 W
428 2026/10/09 08:55:57.658 400.00 W 2805 MHz 13801 MHz 65 100 % 399.96 W 400.00 W
429 2026/10/09 08:55:58.658 399.93 W 2805 MHz 13801 MHz 65 100 % 399.36 W 399.93 W
430 2026/10/09 08:55:59.659 399.95 W 2805 MHz 13801 MHz 65 100 % 399.69 W 399.95 W
431 2026/10/09 08:56:00.659 399.99 W 2805 MHz 13801 MHz 65 100 % 399.87 W 399.99 W
432 2026/10/09 08:56:01.659 399.98 W 2805 MHz 13801 MHz 65 100 % 399.92 W 399.98 W
433 2026/10/09 08:56:02.659 400.02 W 2805 MHz 13801 MHz 65 100 % 400.90 W 400.02 W
434 2026/10/09 08:56:03.660 399.99 W 2805 MHz 13801 MHz 65 100 % 400.67 W 399.99 W
435 2026/10/09 08:56:04.660 399.99 W 2805 MHz 13801 MHz 65 100 % 401.25 W 399.99 W
436 2026/10/09 08:56:05.660 399.99 W 2797 MHz 13801 MHz 65 100 % 400.14 W 399.99 W
437 2026/10/09 08:56:06.660 399.98 W 2797 MHz 13801 MHz 65 100 % 400.00 W 399.98 W
438 2026/10/09 08:56:07.661 399.99 W 2797 MHz 13801 MHz 65 100 % 399.78 W 399.99 W
439 2026/10/09 08:56:08.661 400.00 W 2797 MHz 13801 MHz 65 100 % 399.79 W 400.00 W
440 2026/10/09 08:56:09.661 399.89 W 2797 MHz 13801 MHz 65 100 % 399.13 W 399.89 W
441 2026/10/09 08:56:10.661 399.89 W 2797 MHz 13801 MHz 65 100 % 399.05 W 399.89 W
442 2026/10/09 08:56:11.662 316.78 W 2865 MHz 14001 MHz 60 0 % 113.38 W 316.78 W
443 2026/10/09 08:56:12.662 110.98 W 2865 MHz 14001 MHz 59 0 % 109.26 W 110.98 W
444 2026/10/09 08:56:13.662 87.82 W 780 MHz 14001 MHz 57 0 % 87.82 W 87.82 W
445 2026/10/09 08:56:14.662 48.15 W 375 MHz 810 MHz 56 0 % 48.15 W 48.15 W
446 2026/10/09 08:56:15.663 43.06 W 217 MHz 810 MHz 55 0 % 37.98 W 43.06 W
447 2026/10/09 08:56:16.663 36.42 W 180 MHz 405 MHz 54 0 % 34.86 W 36.42 W
448 2026/10/09 08:56:17.663 34.40 W 180 MHz 405 MHz 53 0 % 33.94 W 34.40 W
449 2026/10/09 08:56:18.663 33.50 W 180 MHz 405 MHz 53 0 % 33.50 W 33.50 W
450 2026/10/09 08:56:19.664 33.48 W 180 MHz 405 MHz 52 0 % 33.47 W 33.48 W
451 2026/10/09 08:56:20.664 33.20 W 180 MHz 405 MHz 52 0 % 32.94 W 33.20 W
452 2026/10/09 08:56:21.664 32.78 W 180 MHz 405 MHz 51 0 % 32.78 W 32.78 W
453 2026/10/09 08:56:22.664 69.15 W 2400 MHz 13801 MHz 52 0 % 76.14 W 69.15 W
454 2026/10/09 08:56:23.664 76.12 W 2400 MHz 13801 MHz 52 0 % 75.99 W 76.12 W
455 2026/10/09 08:56:24.664 96.16 W 2400 MHz 13801 MHz 52 0 % 75.54 W 96.16 W
456 2026/10/09 08:56:25.665 168.46 W 2865 MHz 13801 MHz 56 57 % 254.65 W 168.46 W
457 2026/10/09 08:56:26.665 392.88 W 2857 MHz 13801 MHz 59 100 % 405.53 W 392.88 W
458 2026/10/09 08:56:27.665 407.07 W 2857 MHz 13801 MHz 60 100 % 406.68 W 407.07 W
459 2026/10/09 08:56:28.665 402.69 W 2842 MHz 13801 MHz 60 100 % 400.92 W 402.69 W
460 2026/10/09 08:56:29.665 400.06 W 2842 MHz 13801 MHz 60 100 % 400.52 W 400.06 W
461 2026/10/09 08:56:30.665 399.98 W 2842 MHz 13801 MHz 61 100 % 400.26 W 399.98 W
462 2026/10/09 08:56:31.666 400.02 W 2842 MHz 13801 MHz 61 100 % 399.98 W 400.02 W
463 2026/10/09 08:56:32.666 400.00 W 2842 MHz 13801 MHz 61 100 % 399.81 W 400.00 W
464 2026/10/09 08:56:33.666 400.01 W 2842 MHz 13801 MHz 61 100 % 399.87 W 400.01 W
465 2026/10/09 08:56:34.666 399.89 W 2842 MHz 13801 MHz 61 100 % 399.01 W 399.89 W
466 2026/10/09 08:56:35.666 399.99 W 2842 MHz 13801 MHz 62 100 % 399.20 W 399.99 W
467 2026/10/09 08:56:36.667 399.96 W 2835 MHz 13801 MHz 62 99 % 398.88 W 399.96 W
468 2026/10/09 08:56:37.667 399.97 W 2835 MHz 13801 MHz 62 100 % 399.73 W 399.97 W
469 2026/10/09 08:56:38.667 400.02 W 2835 MHz 13801 MHz 62 100 % 399.87 W 400.02 W
470 2026/10/09 08:56:39.667 400.01 W 2835 MHz 13801 MHz 62 100 % 400.96 W 400.01 W
471 2026/10/09 08:56:40.668 400.08 W 2835 MHz 13801 MHz 62 100 % 401.07 W 400.08 W
472 2026/10/09 08:56:41.668 399.97 W 2827 MHz 13801 MHz 62 100 % 400.21 W 399.97 W
473 2026/10/09 08:56:42.668 400.01 W 2820 MHz 13801 MHz 62 100 % 400.02 W 400.01 W
474 2026/10/09 08:56:43.668 399.99 W 2820 MHz 13801 MHz 63 100 % 399.85 W 399.99 W
475 2026/10/09 08:56:44.668 399.99 W 2820 MHz 13801 MHz 63 100 % 399.92 W 399.99 W
476 2026/10/09 08:56:45.668 400.00 W 2820 MHz 13801 MHz 63 100 % 400.10 W 400.00 W
477 2026/10/09 08:56:46.668 399.90 W 2820 MHz 13801 MHz 63 100 % 399.25 W 399.90 W
478 2026/10/09 08:56:47.669 399.95 W 2820 MHz 13801 MHz 63 100 % 399.56 W 399.95 W
479 2026/10/09 08:56:48.669 399.97 W 2820 MHz 13801 MHz 63 100 % 399.80 W 399.97 W
480 2026/10/09 08:56:49.669 400.02 W 2820 MHz 13801 MHz 63 100 % 400.00 W 400.02 W
481 2026/10/09 08:56:50.669 400.01 W 2812 MHz 13801 MHz 63 100 % 401.05 W 400.01 W
482 2026/10/09 08:56:51.669 400.09 W 2812 MHz 13801 MHz 63 100 % 400.88 W 400.09 W
483 2026/10/09 08:56:52.669 399.97 W 2812 MHz 13801 MHz 64 100 % 400.56 W 399.97 W
484 2026/10/09 08:56:53.670 399.99 W 2812 MHz 13801 MHz 64 100 % 400.32 W 399.99 W
485 2026/10/09 08:56:54.670 400.01 W 2812 MHz 13801 MHz 64 100 % 400.09 W 400.01 W
486 2026/10/09 08:56:55.670 399.99 W 2812 MHz 13801 MHz 64 100 % 399.79 W 399.99 W
487 2026/10/09 08:56:56.670 400.01 W 2812 MHz 13801 MHz 64 100 % 399.98 W 400.01 W
488 2026/10/09 08:56:57.670 399.92 W 2812 MHz 13801 MHz 64 100 % 399.34 W 399.92 W
489 2026/10/09 08:56:58.671 399.95 W 2812 MHz 13801 MHz 64 100 % 399.57 W 399.95 W
490 2026/10/09 08:56:59.671 399.98 W 2812 MHz 13801 MHz 64 100 % 399.78 W 399.98 W
491 2026/10/09 08:57:00.671 400.01 W 2812 MHz 13801 MHz 64 100 % 399.99 W 400.01 W
492 2026/10/09 08:57:01.671 400.02 W 2812 MHz 13801 MHz 64 100 % 400.07 W 400.02 W
493 2026/10/09 08:57:02.671 399.97 W 2812 MHz 13801 MHz 64 100 % 400.85 W 399.97 W
494 2026/10/09 08:57:03.671 400.06 W 2812 MHz 13801 MHz 64 100 % 400.47 W 400.06 W
495 2026/10/09 08:57:04.671 400.02 W 2812 MHz 13801 MHz 64 100 % 400.22 W 400.02 W
496 2026/10/09 08:57:05.672 400.01 W 2805 MHz 13801 MHz 64 100 % 400.08 W 400.01 W
497 2026/10/09 08:57:06.672 400.00 W 2805 MHz 13801 MHz 64 100 % 399.86 W 400.00 W
498 2026/10/09 08:57:07.672 400.00 W 2805 MHz 13801 MHz 64 100 % 399.81 W 400.00 W
499 2026/10/09 08:57:08.672 399.90 W 2805 MHz 13801 MHz 64 100 % 399.06 W 399.90 W
500 2026/10/09 08:57:09.672 399.93 W 2805 MHz 13801 MHz 64 100 % 399.32 W 399.93 W
501 2026/10/09 08:57:10.673 400.02 W 2805 MHz 13801 MHz 64 100 % 399.64 W 400.02 W
502 2026/10/09 08:57:11.673 400.03 W 2805 MHz 13801 MHz 65 100 % 399.99 W 400.03 W
503 2026/10/09 08:57:12.673 400.00 W 2805 MHz 13801 MHz 65 100 % 400.07 W 400.00 W
504 2026/10/09 08:57:13.673 400.00 W 2805 MHz 13801 MHz 65 100 % 400.76 W 400.00 W
505 2026/10/09 08:57:14.673 399.98 W 2805 MHz 13801 MHz 65 100 % 400.48 W 399.98 W
506 2026/10/09 08:57:15.673 399.98 W 2805 MHz 13801 MHz 65 100 % 400.18 W 399.98 W
507 2026/10/09 08:57:16.674 400.01 W 2805 MHz 13801 MHz 65 100 % 400.02 W 400.01 W
508 2026/10/09 08:57:17.674 399.98 W 2805 MHz 13801 MHz 65 100 % 399.79 W 399.98 W
509 2026/10/09 08:57:18.674 399.98 W 2805 MHz 13801 MHz 65 100 % 399.90 W 399.98 W
510 2026/10/09 08:57:19.674 399.92 W 2805 MHz 13801 MHz 65 100 % 399.18 W 399.92 W
511 2026/10/09 08:57:20.675 399.93 W 2805 MHz 13801 MHz 65 100 % 399.36 W 399.93 W
512 2026/10/09 08:57:21.675 399.96 W 2805 MHz 13801 MHz 65 100 % 399.70 W 399.96 W
513 2026/10/09 08:57:22.675 400.02 W 2812 MHz 13801 MHz 65 100 % 402.14 W 400.02 W
514 2026/10/09 08:57:23.675 400.18 W 2805 MHz 13801 MHz 65 100 % 399.94 W 400.18 W
515 2026/10/09 08:57:24.675 401.41 W 2805 MHz 13801 MHz 65 100 % 399.93 W 401.41 W
516 2026/10/09 08:57:25.676 400.00 W 2805 MHz 13801 MHz 65 100 % 400.84 W 400.00 W
517 2026/10/09 08:57:26.676 400.06 W 2805 MHz 13801 MHz 65 100 % 400.58 W 400.06 W
518 2026/10/09 08:57:27.676 141.76 W 2865 MHz 14001 MHz 59 0 % 108.36 W 141.76 W
519 2026/10/09 08:57:28.676 112.13 W 2865 MHz 14001 MHz 59 0 % 107.61 W 112.13 W
520 2026/10/09 08:57:29.677 95.60 W 1335 MHz 7001 MHz 56 0 % 95.60 W 95.60 W
521 2026/10/09 08:57:30.677 48.05 W 382 MHz 7001 MHz 55 0 % 48.05 W 48.05 W
522 2026/10/09 08:57:31.677 47.40 W 240 MHz 7001 MHz 55 0 % 46.76 W 47.40 W
523 2026/10/09 08:57:32.677 45.82 W 180 MHz 7001 MHz 54 0 % 45.82 W 45.82 W
524 2026/10/09 08:57:33.677 45.31 W 180 MHz 7001 MHz 53 0 % 44.81 W 45.31 W
525 2026/10/09 08:57:34.678 36.31 W 180 MHz 810 MHz 53 0 % 36.31 W 36.31 W
526 2026/10/09 08:57:35.678 34.99 W 180 MHz 405 MHz 52 0 % 33.66 W 34.99 W
527 2026/10/09 08:57:36.678 33.01 W 180 MHz 405 MHz 52 0 % 32.36 W 33.01 W
528 2026/10/09 08:57:37.678 45.89 W 2400 MHz 13801 MHz 52 0 % 76.00 W 45.89 W
529 2026/10/09 08:57:38.679 75.78 W 2400 MHz 13801 MHz 52 0 % 75.43 W 75.78 W
530 2026/10/09 08:57:39.679 95.69 W 2467 MHz 13801 MHz 52 27 % 75.46 W 95.69 W
531 2026/10/09 08:57:40.679 83.62 W 2437 MHz 13801 MHz 51 35 % 168.80 W 83.62 W
532 2026/10/09 08:57:41.679 338.15 W 2857 MHz 13801 MHz 59 100 % 413.75 W 338.15 W
533 2026/10/09 08:57:42.679 409.82 W 2835 MHz 13801 MHz 60 100 % 400.73 W 409.82 W
534 2026/10/09 08:57:43.680 400.06 W 2827 MHz 13801 MHz 60 100 % 400.27 W 400.06 W
535 2026/10/09 08:57:44.680 399.99 W 2827 MHz 13801 MHz 60 100 % 399.84 W 399.99 W
536 2026/10/09 08:57:45.680 399.98 W 2827 MHz 13801 MHz 60 100 % 399.78 W 399.98 W
537 2026/10/09 08:57:46.680 400.01 W 2827 MHz 13801 MHz 61 100 % 399.81 W 400.01 W
538 2026/10/09 08:57:47.681 399.89 W 2827 MHz 13801 MHz 61 100 % 399.08 W 399.89 W
539 2026/10/09 08:57:48.681 400.01 W 2820 MHz 13801 MHz 61 100 % 399.26 W 400.01 W
540 2026/10/09 08:57:49.681 400.01 W 2820 MHz 13801 MHz 61 100 % 399.54 W 400.01 W
541 2026/10/09 08:57:50.681 400.02 W 2820 MHz 13801 MHz 61 100 % 399.81 W 400.02 W
542 2026/10/09 08:57:51.681 400.03 W 2820 MHz 13801 MHz 62 100 % 400.13 W 400.03 W
543 2026/10/09 08:57:52.682 400.00 W 2820 MHz 13801 MHz 62 100 % 400.74 W 400.00 W
544 2026/10/09 08:57:53.682 400.07 W 2820 MHz 13801 MHz 62 100 % 400.54 W 400.07 W
545 2026/10/09 08:57:54.682 399.97 W 2820 MHz 13801 MHz 62 100 % 400.25 W 399.97 W
546 2026/10/09 08:57:55.682 400.01 W 2820 MHz 13801 MHz 62 100 % 399.99 W 400.01 W
547 2026/10/09 08:57:56.682 400.00 W 2820 MHz 13801 MHz 62 100 % 399.81 W 400.00 W
548 2026/10/09 08:57:57.683 399.99 W 2820 MHz 13801 MHz 62 100 % 399.89 W 399.99 W
549 2026/10/09 08:57:58.683 399.91 W 2820 MHz 13801 MHz 63 100 % 399.17 W 399.91 W
550 2026/10/09 08:57:59.683 400.01 W 2805 MHz 13801 MHz 63 100 % 399.44 W 400.01 W
551 2026/10/09 08:58:00.683 399.98 W 2805 MHz 13801 MHz 63 100 % 399.78 W 399.98 W
552 2026/10/09 08:58:01.684 399.98 W 2805 MHz 13801 MHz 63 100 % 399.98 W 399.98 W
553 2026/10/09 08:58:02.684 400.01 W 2797 MHz 13801 MHz 63 100 % 400.05 W 400.01 W
554 2026/10/09 08:58:03.684 400.00 W 2805 MHz 13801 MHz 63 100 % 401.53 W 400.00 W
555 2026/10/09 08:58:04.684 399.97 W 2797 MHz 13801 MHz 63 100 % 400.49 W 399.97 W
556 2026/10/09 08:58:05.684 400.03 W 2797 MHz 13801 MHz 63 100 % 400.13 W 400.03 W
557 2026/10/09 08:58:06.685 399.99 W 2797 MHz 13801 MHz 63 100 % 400.01 W 399.99 W
558 2026/10/09 08:58:07.685 399.98 W 2797 MHz 13801 MHz 63 100 % 399.87 W 399.98 W
559 2026/10/09 08:58:08.685 400.00 W 2805 MHz 13801 MHz 63 100 % 399.94 W 400.00 W
560 2026/10/09 08:58:09.685 399.92 W 2797 MHz 13801 MHz 63 100 % 399.19 W 399.92 W
561 2026/10/09 08:58:10.686 399.96 W 2797 MHz 13801 MHz 63 100 % 399.74 W 399.96 W
562 2026/10/09 08:58:11.686 400.00 W 2797 MHz 13801 MHz 64 100 % 399.84 W 400.00 W
563 2026/10/09 08:58:12.686 400.00 W 2797 MHz 13801 MHz 64 100 % 399.96 W 400.00 W
564 2026/10/09 08:58:13.686 400.00 W 2797 MHz 13801 MHz 64 100 % 400.82 W 400.00 W
565 2026/10/09 08:58:14.686 400.00 W 2797 MHz 13801 MHz 64 100 % 400.77 W 400.00 W
566 2026/10/09 08:58:15.687 400.06 W 2797 MHz 13801 MHz 64 100 % 400.47 W 400.06 W
567 2026/10/09 08:58:16.687 399.98 W 2797 MHz 13801 MHz 64 100 % 400.27 W 399.98 W
568 2026/10/09 08:58:17.687 400.00 W 2797 MHz 13801 MHz 64 100 % 399.76 W 400.00 W
569 2026/10/09 08:58:18.687 399.98 W 2797 MHz 13801 MHz 64 100 % 399.90 W 399.98 W
570 2026/10/09 08:58:19.687 399.99 W 2797 MHz 13801 MHz 64 100 % 399.98 W 399.99 W
571 2026/10/09 08:58:20.688 399.92 W 2797 MHz 13801 MHz 64 100 % 399.46 W 399.92 W
572 2026/10/09 08:58:21.688 399.97 W 2797 MHz 13801 MHz 64 100 % 399.65 W 399.97 W
573 2026/10/09 08:58:22.688 400.00 W 2797 MHz 13801 MHz 64 100 % 399.85 W 400.00 W
574 2026/10/09 08:58:23.688 400.01 W 2797 MHz 13801 MHz 64 100 % 399.98 W 400.01 W
575 2026/10/09 08:58:24.688 400.00 W 2797 MHz 13801 MHz 64 100 % 400.88 W 400.00 W
576 2026/10/09 08:58:25.688 399.99 W 2797 MHz 13801 MHz 64 100 % 400.67 W 399.99 W
577 2026/10/09 08:58:26.689 400.05 W 2797 MHz 13801 MHz 64 100 % 400.64 W 400.05 W
578 2026/10/09 08:58:27.689 399.98 W 2790 MHz 13801 MHz 64 100 % 399.97 W 399.98 W
579 2026/10/09 08:58:28.689 399.98 W 2797 MHz 13801 MHz 64 100 % 399.86 W 399.98 W
580 2026/10/09 08:58:29.689 399.99 W 2790 MHz 13801 MHz 64 100 % 399.84 W 399.99 W
581 2026/10/09 08:58:30.689 399.98 W 2790 MHz 13801 MHz 64 100 % 399.98 W 399.98 W
582 2026/10/09 08:58:31.690 399.94 W 2790 MHz 13801 MHz 64 100 % 399.39 W 399.94 W
583 2026/10/09 08:58:32.690 400.01 W 2790 MHz 13801 MHz 64 100 % 399.65 W 400.01 W
584 2026/10/09 08:58:33.690 400.00 W 2790 MHz 13801 MHz 65 100 % 399.85 W 400.00 W
585 2026/10/09 08:58:34.690 400.00 W 2790 MHz 13801 MHz 64 100 % 399.95 W 400.00 W
586 2026/10/09 08:58:35.691 400.00 W 2790 MHz 13801 MHz 65 100 % 400.79 W 400.00 W
587 2026/10/09 08:58:36.691 400.06 W 2790 MHz 13801 MHz 65 100 % 400.49 W 400.06 W
588 2026/10/09 08:58:37.691 400.03 W 2790 MHz 13801 MHz 65 100 % 400.20 W 400.03 W
589 2026/10/09 08:58:38.691 399.99 W 2790 MHz 13801 MHz 65 100 % 399.94 W 399.99 W
590 2026/10/09 08:58:39.691 399.98 W 2790 MHz 13801 MHz 65 100 % 399.77 W 399.98 W
591 2026/10/09 08:58:40.692 399.98 W 2790 MHz 13801 MHz 65 100 % 399.85 W 399.98 W
592 2026/10/09 08:58:41.692 399.92 W 2790 MHz 13801 MHz 65 100 % 399.31 W 399.92 W
593 2026/10/09 08:58:42.692 266.37 W 2865 MHz 14001 MHz 59 0 % 108.97 W 266.37 W
594 2026/10/09 08:58:43.692 108.93 W 2865 MHz 14001 MHz 58 0 % 108.00 W 108.93 W
595 2026/10/09 08:58:44.693 86.74 W 547 MHz 7001 MHz 56 0 % 86.74 W 86.74 W
596 2026/10/09 08:58:45.693 67.17 W 337 MHz 7001 MHz 55 0 % 47.60 W 67.17 W
597 2026/10/09 08:58:46.693 46.92 W 217 MHz 7001 MHz 54 0 % 46.25 W 46.92 W
598 2026/10/09 08:58:47.693 45.38 W 180 MHz 810 MHz 54 0 % 45.38 W 45.38 W
599 2026/10/09 08:58:48.693 35.34 W 180 MHz 810 MHz 53 0 % 35.34 W 35.34 W
600 2026/10/09 08:58:49.694 34.27 W 180 MHz 405 MHz 52 0 % 33.20 W 34.27 W
601 2026/10/09 08:58:50.694 32.65 W 180 MHz 405 MHz 52 0 % 32.65 W 32.65 W
602 2026/10/09 08:58:51.694 32.03 W 180 MHz 405 MHz 51 0 % 32.03 W 32.03 W

View file

@ -0,0 +1,48 @@
### run 1 x1-ctrl-ds28 start 1791535735.501035851
1791535735.832800660 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791535799.157631482 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 2147 cache 2 dataset 13 hot 0 check 1128 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791535799.162425736 warm-up dispatch (base 0): 237.50 ms; 250 timed dispatches of 16777216 nonces: mean 237.44 ms
1791535799.167302349 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=70.659 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 1 x1-ctrl-ds28 end 1791535799.193449703
### run 2 x1-flat-ds28 start 1791535809.200553202
1791535809.540847040 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791535872.818259784 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 2039 cache 1 dataset 13 hot 0 check 1126 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791535872.821893741 warm-up dispatch (base 0): 237.84 ms; 250 timed dispatches of 16777216 nonces: mean 237.79 ms
1791535872.825954240 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=70.555 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 2 x1-flat-ds28 end 1791535872.854143584
### run 3 x1-flat-ds28 start 1791535882.860393440
1791535883.245161874 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791535946.595866529 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 2046 cache 1 dataset 13 hot 0 check 1151 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791535946.600138113 warm-up dispatch (base 0): 237.86 ms; 250 timed dispatches of 16777216 nonces: mean 237.79 ms
1791535946.603995386 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=70.554 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 3 x1-flat-ds28 end 1791535946.632587012
### run 4 x1-ctrl-ds28 start 1791535956.639961245
1791535956.984800341 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536020.244857665 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 2102 cache 1 dataset 13 hot 0 check 1135 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536020.248651729 warm-up dispatch (base 0): 237.48 ms; 250 timed dispatches of 16777216 nonces: mean 237.45 ms
1791536020.252921503 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=70.654 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 4 x1-ctrl-ds28 end 1791536020.278699235
### run 5 x1-ctrl-ds30 start 1791536030.285132188
1791536030.616235300 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536095.609755848 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 2080 cache 1 dataset 49 hot 0 check 1120 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536095.613507983 warm-up dispatch (base 0): 244.42 ms; 250 timed dispatches of 16777216 nonces: mean 244.37 ms
1791536095.617662250 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=68.656 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 5 x1-ctrl-ds30 end 1791536095.644742516
### run 6 x1-flat-ds30 start 1791536105.652062350
1791536105.981221932 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536171.066118836 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 2068 cache 1 dataset 50 hot 0 check 1128 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536171.070043677 warm-up dispatch (base 0): 244.59 ms; 250 timed dispatches of 16777216 nonces: mean 244.61 ms
1791536171.074346821 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=68.588 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 6 x1-flat-ds30 end 1791536171.101820709
### run 7 x1-flat-ds30 start 1791536181.109060575
1791536181.448357503 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536246.440536419 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 2052 cache 1 dataset 49 hot 0 check 1093 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536246.444983410 warm-up dispatch (base 0): 244.59 ms; 250 timed dispatches of 16777216 nonces: mean 244.61 ms
1791536246.449527088 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=68.586 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 7 x1-flat-ds30 end 1791536246.473279752
### run 8 x1-ctrl-ds30 start 1791536256.480687255
1791536256.816492912 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536321.898149330 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 2090 cache 2 dataset 50 hot 0 check 1122 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536321.902085561 warm-up dispatch (base 0): 244.72 ms; 250 timed dispatches of 16777216 nonces: mean 244.34 ms
1791536321.906356676 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=68.662 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 8 x1-ctrl-ds30 end 1791536321.937001800

View file

@ -0,0 +1,11 @@
run pack check fingerprint MH/s W W_inst W_avg sm_MHz mem_MHz util nJ/hash samples
1 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 70.64 430.76 430.86 430.76 2947.10 13801.00 99.92 6097.97 51
2 x1-flat-ds28 PASS 8cd11a827ac3ffe4 70.54 436.87 437.06 436.87 2936.04 13801.00 99.98 6193.45 52
3 x1-flat-ds28 PASS 8cd11a827ac3ffe4 70.53 442.05 442.09 442.05 2932.00 13801.00 100.00 6267.03 51
4 x1-ctrl-ds28 PASS 01f51b9d4805e5e6 70.65 452.15 452.16 452.15 2932.00 13801.00 99.98 6400.10 52
5 x1-ctrl-ds30 PASS b1f90e91cadb15b6 68.64 448.08 448.17 448.08 2932.00 13801.00 99.98 6527.72 53
6 x1-flat-ds30 PASS 18c4c6a80809c4b9 68.59 440.65 440.79 440.65 2932.00 13801.00 99.98 6424.75 53
7 x1-flat-ds30 PASS 18c4c6a80809c4b9 68.59 440.46 440.62 440.46 2932.00 13801.00 100.00 6421.79 53
8 x1-ctrl-ds30 PASS b1f90e91cadb15b6 68.65 449.03 449.00 449.03 2932.00 13801.00 100.00 6541.12 53
PAIR ds28: control 70.64 MH/s 441.5 W 6249 nJ; candidate 70.54 MH/s 439.5 W 6230 nJ; rate -0.15 percent, joules per hash -0.30 percent (g = 0.9970); fingerprints control ['01f51b9d4805e5e6'] candidate ['8cd11a827ac3ffe4']; ABBA spread control 0.01 percent candidate 0.00 percent
PAIR ds30: control 68.64 MH/s 448.6 W 6534 nJ; candidate 68.59 MH/s 440.6 W 6423 nJ; rate -0.08 percent, joules per hash -1.70 percent (g = 0.9830); fingerprints control ['b1f90e91cadb15b6'] candidate ['18c4c6a80809c4b9']; ABBA spread control 0.01 percent candidate 0.00 percent

View file

@ -0,0 +1,8 @@
# 2026-10-09T09:01:27Z 77b957759874 worker sha256 804a6f7fea10a62e07cf6cd01e99331de5149e683112b5870fc25d1e11e199bd
GPU 0: NVIDIA GeForce RTX 5090 (UUID: GPU-5a3e1a31-63f4-0c61-3d13-993e120566a2)
name, driver_version, power.limit [W], power.default_limit [W], clocks.max.sm [MHz], clocks.max.memory [MHz]
NVIDIA GeForce RTX 5090, 580.82.07, 500.00 W, 600.00 W, 3105 MHz, 14001 MHz
The current user does not have permission to change clocks for GPU 00000000:01:00.0.
Terminating early due to previous errors.
The current user does not have permission to change clocks for GPU 00000000:01:00.0.
# end 2026-10-09T09:11:11Z

View file

@ -0,0 +1,585 @@
2026/10/09 09:01:27.675, 12.10 W, 195 MHz, 405 MHz, 36, 0 %, 12.10 W, 12.10 W
2026/10/09 09:01:28.680, 12.55 W, 195 MHz, 405 MHz, 36, 0 %, 12.55 W, 12.55 W
2026/10/09 09:01:29.680, 12.19 W, 195 MHz, 405 MHz, 36, 0 %, 11.82 W, 12.19 W
2026/10/09 09:01:30.681, 11.81 W, 195 MHz, 405 MHz, 36, 0 %, 11.81 W, 11.81 W
2026/10/09 09:01:31.681, 11.60 W, 195 MHz, 405 MHz, 36, 0 %, 11.60 W, 11.60 W
2026/10/09 09:01:32.681, 11.69 W, 195 MHz, 405 MHz, 36, 0 %, 11.78 W, 11.69 W
2026/10/09 09:01:33.682, 25.02 W, 2565 MHz, 13801 MHz, 37, 0 %, 67.64 W, 25.02 W
2026/10/09 09:01:34.682, 73.28 W, 2565 MHz, 13801 MHz, 38, 0 %, 68.23 W, 73.28 W
2026/10/09 09:01:35.682, 293.48 W, 2955 MHz, 13801 MHz, 47, 15 %, 416.93 W, 293.48 W
2026/10/09 09:01:36.683, 416.87 W, 2955 MHz, 13801 MHz, 48, 100 %, 415.79 W, 416.87 W
2026/10/09 09:01:37.683, 417.16 W, 2955 MHz, 13801 MHz, 48, 100 %, 416.94 W, 417.16 W
2026/10/09 09:01:38.683, 418.13 W, 2955 MHz, 13801 MHz, 49, 100 %, 420.63 W, 418.13 W
2026/10/09 09:01:39.683, 421.68 W, 2955 MHz, 13801 MHz, 49, 100 %, 422.18 W, 421.68 W
2026/10/09 09:01:40.684, 421.70 W, 2955 MHz, 13801 MHz, 49, 100 %, 421.38 W, 421.70 W
2026/10/09 09:01:41.684, 421.38 W, 2955 MHz, 13801 MHz, 50, 100 %, 420.82 W, 421.38 W
2026/10/09 09:01:42.684, 421.28 W, 2955 MHz, 13801 MHz, 50, 100 %, 421.44 W, 421.28 W
2026/10/09 09:01:43.684, 421.84 W, 2955 MHz, 13801 MHz, 50, 100 %, 422.86 W, 421.84 W
2026/10/09 09:01:44.684, 422.80 W, 2955 MHz, 13801 MHz, 51, 100 %, 423.64 W, 422.80 W
2026/10/09 09:01:45.685, 423.13 W, 2955 MHz, 13801 MHz, 51, 100 %, 421.76 W, 423.13 W
2026/10/09 09:01:46.685, 423.09 W, 2955 MHz, 13801 MHz, 51, 100 %, 422.60 W, 423.09 W
2026/10/09 09:01:47.685, 422.94 W, 2955 MHz, 13801 MHz, 51, 100 %, 422.92 W, 422.94 W
2026/10/09 09:01:48.686, 422.97 W, 2955 MHz, 13801 MHz, 52, 100 %, 423.77 W, 422.97 W
2026/10/09 09:01:49.686, 423.69 W, 2955 MHz, 13801 MHz, 52, 100 %, 424.30 W, 423.69 W
2026/10/09 09:01:50.686, 423.93 W, 2955 MHz, 13801 MHz, 52, 99 %, 424.16 W, 423.93 W
2026/10/09 09:01:51.686, 425.05 W, 2955 MHz, 13801 MHz, 52, 100 %, 424.66 W, 425.05 W
2026/10/09 09:01:52.687, 426.29 W, 2955 MHz, 13801 MHz, 53, 100 %, 426.79 W, 426.29 W
2026/10/09 09:01:53.687, 427.06 W, 2955 MHz, 13801 MHz, 53, 100 %, 427.24 W, 427.06 W
2026/10/09 09:01:54.687, 426.36 W, 2955 MHz, 13801 MHz, 53, 100 %, 426.01 W, 426.36 W
2026/10/09 09:01:55.687, 425.69 W, 2940 MHz, 13801 MHz, 53, 100 %, 425.49 W, 425.69 W
2026/10/09 09:01:56.687, 424.97 W, 2940 MHz, 13801 MHz, 54, 99 %, 423.61 W, 424.97 W
2026/10/09 09:01:57.688, 425.32 W, 2940 MHz, 13801 MHz, 54, 100 %, 425.75 W, 425.32 W
2026/10/09 09:01:58.688, 426.20 W, 2940 MHz, 13801 MHz, 54, 100 %, 426.84 W, 426.20 W
2026/10/09 09:01:59.688, 426.86 W, 2940 MHz, 13801 MHz, 54, 100 %, 427.17 W, 426.86 W
2026/10/09 09:02:00.688, 427.46 W, 2940 MHz, 13801 MHz, 55, 100 %, 426.36 W, 427.46 W
2026/10/09 09:02:01.688, 427.72 W, 2940 MHz, 13801 MHz, 55, 100 %, 428.60 W, 427.72 W
2026/10/09 09:02:02.688, 428.31 W, 2940 MHz, 13801 MHz, 55, 100 %, 428.07 W, 428.31 W
2026/10/09 09:02:03.689, 427.99 W, 2940 MHz, 13801 MHz, 55, 100 %, 428.18 W, 427.99 W
2026/10/09 09:02:04.689, 427.85 W, 2940 MHz, 13801 MHz, 56, 100 %, 427.46 W, 427.85 W
2026/10/09 09:02:05.689, 428.48 W, 2940 MHz, 13801 MHz, 56, 100 %, 428.07 W, 428.48 W
2026/10/09 09:02:06.689, 429.82 W, 2940 MHz, 13801 MHz, 56, 100 %, 430.12 W, 429.82 W
2026/10/09 09:02:07.689, 430.11 W, 2940 MHz, 13801 MHz, 56, 100 %, 430.68 W, 430.11 W
2026/10/09 09:02:08.689, 430.53 W, 2947 MHz, 13801 MHz, 56, 100 %, 430.64 W, 430.53 W
2026/10/09 09:02:09.690, 430.23 W, 2947 MHz, 13801 MHz, 57, 99 %, 429.70 W, 430.23 W
2026/10/09 09:02:10.690, 429.68 W, 2947 MHz, 13801 MHz, 57, 100 %, 428.78 W, 429.68 W
2026/10/09 09:02:11.690, 430.77 W, 2947 MHz, 13801 MHz, 57, 100 %, 431.27 W, 430.77 W
2026/10/09 09:02:12.691, 431.19 W, 2947 MHz, 13801 MHz, 57, 100 %, 432.40 W, 431.19 W
2026/10/09 09:02:13.691, 432.40 W, 2947 MHz, 13801 MHz, 57, 100 %, 433.11 W, 432.40 W
2026/10/09 09:02:14.691, 433.90 W, 2947 MHz, 13801 MHz, 58, 100 %, 434.61 W, 433.90 W
2026/10/09 09:02:15.692, 434.74 W, 2947 MHz, 13801 MHz, 58, 99 %, 434.73 W, 434.74 W
2026/10/09 09:02:16.692, 435.48 W, 2947 MHz, 13801 MHz, 58, 100 %, 436.87 W, 435.48 W
2026/10/09 09:02:17.692, 435.06 W, 2947 MHz, 13801 MHz, 58, 100 %, 433.81 W, 435.06 W
2026/10/09 09:02:18.693, 434.31 W, 2947 MHz, 13801 MHz, 59, 100 %, 433.72 W, 434.31 W
2026/10/09 09:02:19.693, 434.44 W, 2947 MHz, 13801 MHz, 59, 100 %, 434.47 W, 434.44 W
2026/10/09 09:02:20.693, 435.24 W, 2947 MHz, 13801 MHz, 59, 100 %, 435.70 W, 435.24 W
2026/10/09 09:02:21.694, 435.42 W, 2947 MHz, 13801 MHz, 59, 100 %, 436.35 W, 435.42 W
2026/10/09 09:02:22.694, 436.33 W, 2947 MHz, 13801 MHz, 59, 100 %, 437.24 W, 436.33 W
2026/10/09 09:02:23.694, 436.99 W, 2947 MHz, 13801 MHz, 60, 100 %, 435.87 W, 436.99 W
2026/10/09 09:02:24.695, 437.68 W, 2947 MHz, 13801 MHz, 60, 100 %, 437.16 W, 437.68 W
2026/10/09 09:02:25.695, 437.65 W, 2947 MHz, 13801 MHz, 60, 100 %, 438.46 W, 437.65 W
2026/10/09 09:02:26.695, 437.80 W, 2947 MHz, 13801 MHz, 60, 100 %, 437.66 W, 437.80 W
2026/10/09 09:02:27.695, 437.55 W, 2947 MHz, 13801 MHz, 60, 100 %, 437.80 W, 437.55 W
2026/10/09 09:02:28.696, 438.22 W, 2947 MHz, 13801 MHz, 60, 100 %, 437.90 W, 438.22 W
2026/10/09 09:02:29.696, 438.59 W, 2947 MHz, 13801 MHz, 61, 100 %, 438.59 W, 438.59 W
2026/10/09 09:02:30.696, 439.52 W, 2947 MHz, 13801 MHz, 61, 100 %, 440.12 W, 439.52 W
2026/10/09 09:02:31.696, 440.03 W, 2947 MHz, 13801 MHz, 61, 100 %, 440.13 W, 440.03 W
2026/10/09 09:02:32.697, 439.63 W, 2947 MHz, 13801 MHz, 61, 100 %, 439.97 W, 439.63 W
2026/10/09 09:02:33.697, 439.48 W, 2947 MHz, 13801 MHz, 61, 100 %, 439.56 W, 439.48 W
2026/10/09 09:02:34.697, 411.56 W, 2947 MHz, 14001 MHz, 55, 100 %, 152.91 W, 411.56 W
2026/10/09 09:02:35.697, 108.99 W, 2947 MHz, 14001 MHz, 53, 0 %, 103.29 W, 108.99 W
2026/10/09 09:02:36.697, 88.44 W, 1755 MHz, 14001 MHz, 51, 0 %, 88.44 W, 88.44 W
2026/10/09 09:02:37.697, 37.47 W, 390 MHz, 810 MHz, 50, 0 %, 37.47 W, 37.47 W
2026/10/09 09:02:38.698, 29.80 W, 232 MHz, 810 MHz, 49, 0 %, 22.12 W, 29.80 W
2026/10/09 09:02:39.698, 19.93 W, 195 MHz, 405 MHz, 49, 0 %, 19.93 W, 19.93 W
2026/10/09 09:02:40.698, 19.13 W, 195 MHz, 405 MHz, 49, 0 %, 18.33 W, 19.13 W
2026/10/09 09:02:41.698, 16.82 W, 195 MHz, 405 MHz, 48, 0 %, 16.82 W, 16.82 W
2026/10/09 09:02:42.699, 16.63 W, 195 MHz, 405 MHz, 48, 0 %, 16.44 W, 16.63 W
2026/10/09 09:02:43.699, 16.76 W, 195 MHz, 405 MHz, 48, 0 %, 17.08 W, 16.76 W
2026/10/09 09:02:44.699, 17.15 W, 187 MHz, 405 MHz, 48, 0 %, 17.15 W, 17.15 W
2026/10/09 09:02:45.699, 71.34 W, 2542 MHz, 13801 MHz, 49, 0 %, 78.03 W, 71.34 W
2026/10/09 09:02:46.699, 197.86 W, 2910 MHz, 13801 MHz, 56, 1 %, 424.42 W, 197.86 W
2026/10/09 09:02:47.699, 425.92 W, 2947 MHz, 13801 MHz, 58, 100 %, 427.10 W, 425.92 W
2026/10/09 09:02:48.700, 426.55 W, 2947 MHz, 13801 MHz, 59, 100 %, 426.89 W, 426.55 W
2026/10/09 09:02:49.700, 426.30 W, 2947 MHz, 13801 MHz, 59, 100 %, 426.08 W, 426.30 W
2026/10/09 09:02:50.700, 426.45 W, 2947 MHz, 13801 MHz, 59, 100 %, 426.80 W, 426.45 W
2026/10/09 09:02:51.700, 427.80 W, 2947 MHz, 13801 MHz, 60, 100 %, 428.65 W, 427.80 W
2026/10/09 09:02:52.700, 427.90 W, 2947 MHz, 13801 MHz, 60, 100 %, 428.29 W, 427.90 W
2026/10/09 09:02:53.700, 428.63 W, 2947 MHz, 13801 MHz, 60, 100 %, 429.03 W, 428.63 W
2026/10/09 09:02:54.701, 427.99 W, 2947 MHz, 13801 MHz, 60, 100 %, 426.97 W, 427.99 W
2026/10/09 09:02:55.701, 428.06 W, 2947 MHz, 13801 MHz, 60, 100 %, 428.84 W, 428.06 W
2026/10/09 09:02:56.701, 428.64 W, 2947 MHz, 13801 MHz, 60, 100 %, 428.87 W, 428.64 W
2026/10/09 09:02:57.701, 428.15 W, 2947 MHz, 13801 MHz, 61, 100 %, 428.61 W, 428.15 W
2026/10/09 09:02:58.701, 429.37 W, 2947 MHz, 13801 MHz, 61, 100 %, 429.43 W, 429.37 W
2026/10/09 09:02:59.701, 429.90 W, 2947 MHz, 13801 MHz, 61, 100 %, 430.02 W, 429.90 W
2026/10/09 09:03:00.701, 431.14 W, 2947 MHz, 13801 MHz, 61, 100 %, 431.48 W, 431.14 W
2026/10/09 09:03:01.702, 432.60 W, 2947 MHz, 13801 MHz, 61, 100 %, 433.12 W, 432.60 W
2026/10/09 09:03:02.702, 432.68 W, 2947 MHz, 13801 MHz, 62, 100 %, 432.11 W, 432.68 W
2026/10/09 09:03:03.702, 432.10 W, 2947 MHz, 13801 MHz, 62, 100 %, 432.70 W, 432.10 W
2026/10/09 09:03:04.702, 431.35 W, 2947 MHz, 13801 MHz, 62, 100 %, 431.08 W, 431.35 W
2026/10/09 09:03:05.702, 431.67 W, 2947 MHz, 13801 MHz, 62, 100 %, 431.40 W, 431.67 W
2026/10/09 09:03:06.703, 433.02 W, 2947 MHz, 13801 MHz, 62, 100 %, 434.06 W, 433.02 W
2026/10/09 09:03:07.703, 434.10 W, 2947 MHz, 13801 MHz, 62, 100 %, 435.50 W, 434.10 W
2026/10/09 09:03:08.703, 433.84 W, 2932 MHz, 13801 MHz, 62, 100 %, 434.48 W, 433.84 W
2026/10/09 09:03:09.704, 434.64 W, 2932 MHz, 13801 MHz, 62, 100 %, 434.27 W, 434.64 W
2026/10/09 09:03:10.704, 434.77 W, 2932 MHz, 13801 MHz, 63, 100 %, 434.36 W, 434.77 W
2026/10/09 09:03:11.704, 435.01 W, 2932 MHz, 13801 MHz, 63, 100 %, 434.92 W, 435.01 W
2026/10/09 09:03:12.704, 434.61 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.66 W, 434.61 W
2026/10/09 09:03:13.704, 435.04 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.07 W, 435.04 W
2026/10/09 09:03:14.704, 435.81 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.60 W, 435.81 W
2026/10/09 09:03:15.704, 436.39 W, 2932 MHz, 13801 MHz, 63, 100 %, 436.69 W, 436.39 W
2026/10/09 09:03:16.705, 436.45 W, 2932 MHz, 13801 MHz, 63, 100 %, 436.79 W, 436.45 W
2026/10/09 09:03:17.705, 436.69 W, 2932 MHz, 13801 MHz, 63, 100 %, 436.46 W, 436.69 W
2026/10/09 09:03:18.706, 436.60 W, 2932 MHz, 13801 MHz, 64, 100 %, 436.61 W, 436.60 W
2026/10/09 09:03:19.706, 437.54 W, 2932 MHz, 13801 MHz, 64, 100 %, 437.27 W, 437.54 W
2026/10/09 09:03:20.706, 437.53 W, 2932 MHz, 13801 MHz, 64, 100 %, 438.38 W, 437.53 W
2026/10/09 09:03:21.706, 437.81 W, 2932 MHz, 13801 MHz, 64, 100 %, 438.61 W, 437.81 W
2026/10/09 09:03:22.707, 438.83 W, 2932 MHz, 13801 MHz, 64, 100 %, 440.00 W, 438.83 W
2026/10/09 09:03:23.707, 440.23 W, 2932 MHz, 13801 MHz, 64, 100 %, 440.68 W, 440.23 W
2026/10/09 09:03:24.707, 441.27 W, 2932 MHz, 13801 MHz, 64, 100 %, 440.99 W, 441.27 W
2026/10/09 09:03:25.707, 440.13 W, 2932 MHz, 13801 MHz, 64, 100 %, 440.25 W, 440.13 W
2026/10/09 09:03:26.708, 439.44 W, 2932 MHz, 13801 MHz, 64, 100 %, 440.04 W, 439.44 W
2026/10/09 09:03:27.708, 439.30 W, 2932 MHz, 13801 MHz, 64, 100 %, 439.04 W, 439.30 W
2026/10/09 09:03:28.708, 439.04 W, 2932 MHz, 13801 MHz, 65, 100 %, 438.36 W, 439.04 W
2026/10/09 09:03:29.708, 439.20 W, 2932 MHz, 13801 MHz, 65, 100 %, 438.75 W, 439.20 W
2026/10/09 09:03:30.709, 440.70 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.14 W, 440.70 W
2026/10/09 09:03:31.709, 440.74 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.57 W, 440.74 W
2026/10/09 09:03:32.709, 440.73 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.76 W, 440.73 W
2026/10/09 09:03:33.709, 440.42 W, 2932 MHz, 13801 MHz, 65, 100 %, 439.93 W, 440.42 W
2026/10/09 09:03:34.710, 440.55 W, 2932 MHz, 13801 MHz, 65, 100 %, 439.20 W, 440.55 W
2026/10/09 09:03:35.710, 440.73 W, 2932 MHz, 13801 MHz, 65, 100 %, 442.12 W, 440.73 W
2026/10/09 09:03:36.710, 441.36 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.66 W, 441.36 W
2026/10/09 09:03:37.710, 441.62 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.86 W, 441.62 W
2026/10/09 09:03:38.711, 441.79 W, 2932 MHz, 13801 MHz, 65, 100 %, 442.35 W, 441.79 W
2026/10/09 09:03:39.711, 442.76 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.48 W, 442.76 W
2026/10/09 09:03:40.711, 442.08 W, 2932 MHz, 13801 MHz, 65, 100 %, 442.65 W, 442.08 W
2026/10/09 09:03:41.711, 442.16 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.95 W, 442.16 W
2026/10/09 09:03:42.711, 442.17 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.58 W, 442.17 W
2026/10/09 09:03:43.711, 442.06 W, 2932 MHz, 13801 MHz, 66, 99 %, 442.33 W, 442.06 W
2026/10/09 09:03:44.712, 442.89 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.69 W, 442.89 W
2026/10/09 09:03:45.712, 443.41 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.45 W, 443.41 W
2026/10/09 09:03:46.712, 248.86 W, 2947 MHz, 14001 MHz, 57, 1 %, 112.39 W, 248.86 W
2026/10/09 09:03:47.712, 128.04 W, 2947 MHz, 14001 MHz, 57, 0 %, 112.13 W, 128.04 W
2026/10/09 09:03:48.713, 100.50 W, 2692 MHz, 14001 MHz, 55, 0 %, 100.50 W, 100.50 W
2026/10/09 09:03:49.713, 74.28 W, 405 MHz, 7001 MHz, 54, 0 %, 48.06 W, 74.28 W
2026/10/09 09:03:50.713, 42.98 W, 255 MHz, 7001 MHz, 53, 0 %, 42.98 W, 42.98 W
2026/10/09 09:03:51.713, 36.47 W, 195 MHz, 810 MHz, 53, 0 %, 36.47 W, 36.47 W
2026/10/09 09:03:52.714, 29.16 W, 195 MHz, 810 MHz, 52, 0 %, 21.85 W, 29.16 W
2026/10/09 09:03:53.714, 20.81 W, 195 MHz, 405 MHz, 52, 0 %, 19.78 W, 20.81 W
2026/10/09 09:03:54.714, 19.20 W, 195 MHz, 405 MHz, 52, 0 %, 19.20 W, 19.20 W
2026/10/09 09:03:55.714, 19.17 W, 195 MHz, 405 MHz, 51, 0 %, 19.15 W, 19.17 W
2026/10/09 09:03:56.714, 36.28 W, 2542 MHz, 13801 MHz, 52, 0 %, 79.08 W, 36.28 W
2026/10/09 09:03:57.714, 85.00 W, 2542 MHz, 13801 MHz, 52, 0 %, 78.65 W, 85.00 W
2026/10/09 09:03:58.715, 346.57 W, 2947 MHz, 13801 MHz, 61, 99 %, 431.39 W, 346.57 W
2026/10/09 09:03:59.715, 432.90 W, 2947 MHz, 13801 MHz, 62, 100 %, 434.26 W, 432.90 W
2026/10/09 09:04:00.715, 434.59 W, 2947 MHz, 13801 MHz, 62, 100 %, 435.41 W, 434.59 W
2026/10/09 09:04:01.715, 435.23 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.64 W, 435.23 W
2026/10/09 09:04:02.716, 435.07 W, 2932 MHz, 13801 MHz, 63, 100 %, 434.76 W, 435.07 W
2026/10/09 09:04:03.716, 435.19 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.58 W, 435.19 W
2026/10/09 09:04:04.716, 435.73 W, 2932 MHz, 13801 MHz, 63, 100 %, 436.82 W, 435.73 W
2026/10/09 09:04:05.717, 436.15 W, 2932 MHz, 13801 MHz, 63, 100 %, 436.97 W, 436.15 W
2026/10/09 09:04:06.717, 436.35 W, 2932 MHz, 13801 MHz, 63, 100 %, 435.83 W, 436.35 W
2026/10/09 09:04:07.717, 437.29 W, 2932 MHz, 13801 MHz, 63, 100 %, 437.58 W, 437.29 W
2026/10/09 09:04:08.718, 438.64 W, 2932 MHz, 13801 MHz, 64, 100 %, 439.95 W, 438.64 W
2026/10/09 09:04:09.718, 439.21 W, 2932 MHz, 13801 MHz, 64, 100 %, 438.79 W, 439.21 W
2026/10/09 09:04:10.718, 439.24 W, 2932 MHz, 13801 MHz, 64, 100 %, 439.49 W, 439.24 W
2026/10/09 09:04:11.719, 438.11 W, 2932 MHz, 13801 MHz, 64, 100 %, 436.44 W, 438.11 W
2026/10/09 09:04:12.719, 437.51 W, 2932 MHz, 13801 MHz, 64, 100 %, 435.73 W, 437.51 W
2026/10/09 09:04:13.719, 437.90 W, 2932 MHz, 13801 MHz, 64, 100 %, 438.29 W, 437.90 W
2026/10/09 09:04:14.720, 438.62 W, 2932 MHz, 13801 MHz, 64, 100 %, 438.96 W, 438.62 W
2026/10/09 09:04:15.720, 438.81 W, 2932 MHz, 13801 MHz, 64, 100 %, 439.66 W, 438.81 W
2026/10/09 09:04:16.721, 439.65 W, 2932 MHz, 13801 MHz, 64, 100 %, 439.38 W, 439.65 W
2026/10/09 09:04:17.721, 439.88 W, 2932 MHz, 13801 MHz, 65, 100 %, 439.17 W, 439.88 W
2026/10/09 09:04:18.721, 440.35 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.16 W, 440.35 W
2026/10/09 09:04:19.722, 440.00 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.44 W, 440.00 W
2026/10/09 09:04:20.722, 440.22 W, 2932 MHz, 13801 MHz, 65, 100 %, 441.16 W, 440.22 W
2026/10/09 09:04:21.722, 439.82 W, 2932 MHz, 13801 MHz, 65, 100 %, 439.25 W, 439.82 W
2026/10/09 09:04:22.722, 439.92 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.55 W, 439.92 W
2026/10/09 09:04:23.723, 441.10 W, 2932 MHz, 13801 MHz, 65, 100 %, 442.03 W, 441.10 W
2026/10/09 09:04:24.723, 441.54 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.96 W, 441.54 W
2026/10/09 09:04:25.723, 440.24 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.31 W, 440.24 W
2026/10/09 09:04:26.723, 440.48 W, 2932 MHz, 13801 MHz, 65, 100 %, 439.70 W, 440.48 W
2026/10/09 09:04:27.724, 440.18 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.46 W, 440.18 W
2026/10/09 09:04:28.724, 441.03 W, 2932 MHz, 13801 MHz, 66, 100 %, 441.43 W, 441.03 W
2026/10/09 09:04:29.724, 441.70 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.57 W, 441.70 W
2026/10/09 09:04:30.724, 442.33 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.67 W, 442.33 W
2026/10/09 09:04:31.724, 444.16 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.76 W, 444.16 W
2026/10/09 09:04:32.725, 444.77 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.96 W, 444.77 W
2026/10/09 09:04:33.725, 444.47 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.12 W, 444.47 W
2026/10/09 09:04:34.725, 443.55 W, 2932 MHz, 13801 MHz, 66, 100 %, 443.62 W, 443.55 W
2026/10/09 09:04:35.725, 442.52 W, 2932 MHz, 13801 MHz, 66, 100 %, 441.96 W, 442.52 W
2026/10/09 09:04:36.725, 443.06 W, 2932 MHz, 13801 MHz, 66, 100 %, 443.63 W, 443.06 W
2026/10/09 09:04:37.726, 443.66 W, 2932 MHz, 13801 MHz, 66, 100 %, 443.47 W, 443.66 W
2026/10/09 09:04:38.726, 443.55 W, 2932 MHz, 13801 MHz, 66, 100 %, 443.82 W, 443.55 W
2026/10/09 09:04:39.726, 444.03 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.59 W, 444.03 W
2026/10/09 09:04:40.726, 444.41 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.14 W, 444.41 W
2026/10/09 09:04:41.726, 445.37 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.23 W, 445.37 W
2026/10/09 09:04:42.727, 444.19 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.48 W, 444.19 W
2026/10/09 09:04:43.727, 444.21 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.03 W, 444.21 W
2026/10/09 09:04:44.727, 443.67 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.24 W, 443.67 W
2026/10/09 09:04:45.727, 444.33 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.31 W, 444.33 W
2026/10/09 09:04:46.728, 444.77 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.70 W, 444.77 W
2026/10/09 09:04:47.728, 445.26 W, 2932 MHz, 13801 MHz, 67, 100 %, 445.76 W, 445.26 W
2026/10/09 09:04:48.728, 444.68 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.81 W, 444.68 W
2026/10/09 09:04:49.729, 444.23 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.21 W, 444.23 W
2026/10/09 09:04:50.729, 443.96 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.83 W, 443.96 W
2026/10/09 09:04:51.729, 444.74 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.30 W, 444.74 W
2026/10/09 09:04:52.729, 444.76 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.50 W, 444.76 W
2026/10/09 09:04:53.730, 445.07 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.31 W, 445.07 W
2026/10/09 09:04:54.730, 445.47 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.43 W, 445.47 W
2026/10/09 09:04:55.730, 445.65 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.60 W, 445.65 W
2026/10/09 09:04:56.730, 445.65 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.71 W, 445.65 W
2026/10/09 09:04:57.731, 407.83 W, 2932 MHz, 14001 MHz, 61, 100 %, 126.93 W, 407.83 W
2026/10/09 09:04:58.731, 135.89 W, 2947 MHz, 14001 MHz, 58, 0 %, 111.01 W, 135.89 W
2026/10/09 09:04:59.731, 101.01 W, 2745 MHz, 14001 MHz, 56, 0 %, 100.01 W, 101.01 W
2026/10/09 09:05:00.731, 48.27 W, 577 MHz, 7001 MHz, 55, 0 %, 48.27 W, 48.27 W
2026/10/09 09:05:01.731, 46.96 W, 360 MHz, 7001 MHz, 54, 0 %, 45.66 W, 46.96 W
2026/10/09 09:05:02.731, 44.03 W, 225 MHz, 7001 MHz, 54, 0 %, 44.03 W, 44.03 W
2026/10/09 09:05:03.732, 39.56 W, 195 MHz, 810 MHz, 53, 0 %, 39.56 W, 39.56 W
2026/10/09 09:05:04.732, 30.85 W, 195 MHz, 810 MHz, 53, 0 %, 22.13 W, 30.85 W
2026/10/09 09:05:05.732, 20.23 W, 195 MHz, 405 MHz, 53, 0 %, 20.23 W, 20.23 W
2026/10/09 09:05:06.732, 19.24 W, 195 MHz, 405 MHz, 52, 0 %, 19.24 W, 19.24 W
2026/10/09 09:05:07.733, 19.22 W, 195 MHz, 405 MHz, 52, 0 %, 19.22 W, 19.22 W
2026/10/09 09:05:08.733, 70.79 W, 2542 MHz, 13801 MHz, 53, 0 %, 79.96 W, 70.79 W
2026/10/09 09:05:09.733, 187.80 W, 2947 MHz, 13801 MHz, 61, 0 %, 225.31 W, 187.80 W
2026/10/09 09:05:10.733, 424.00 W, 2932 MHz, 13801 MHz, 63, 100 %, 443.93 W, 424.00 W
2026/10/09 09:05:11.733, 444.52 W, 2932 MHz, 13801 MHz, 63, 100 %, 445.36 W, 444.52 W
2026/10/09 09:05:12.733, 444.56 W, 2932 MHz, 13801 MHz, 64, 100 %, 444.52 W, 444.56 W
2026/10/09 09:05:13.733, 445.58 W, 2932 MHz, 13801 MHz, 64, 100 %, 446.67 W, 445.58 W
2026/10/09 09:05:14.734, 445.89 W, 2932 MHz, 13801 MHz, 64, 100 %, 446.51 W, 445.89 W
2026/10/09 09:05:15.734, 447.35 W, 2932 MHz, 13801 MHz, 64, 100 %, 448.36 W, 447.35 W
2026/10/09 09:05:16.734, 448.85 W, 2932 MHz, 13801 MHz, 64, 100 %, 449.63 W, 448.85 W
2026/10/09 09:05:17.734, 449.25 W, 2932 MHz, 13801 MHz, 64, 100 %, 450.79 W, 449.25 W
2026/10/09 09:05:18.735, 450.21 W, 2932 MHz, 13801 MHz, 65, 100 %, 449.07 W, 450.21 W
2026/10/09 09:05:19.735, 448.98 W, 2932 MHz, 13801 MHz, 65, 99 %, 447.33 W, 448.98 W
2026/10/09 09:05:20.735, 448.60 W, 2932 MHz, 13801 MHz, 65, 100 %, 448.61 W, 448.60 W
2026/10/09 09:05:21.735, 448.05 W, 2932 MHz, 13801 MHz, 65, 100 %, 449.49 W, 448.05 W
2026/10/09 09:05:22.736, 448.65 W, 2932 MHz, 13801 MHz, 65, 100 %, 449.45 W, 448.65 W
2026/10/09 09:05:23.736, 449.11 W, 2932 MHz, 13801 MHz, 65, 100 %, 449.60 W, 449.11 W
2026/10/09 09:05:24.736, 449.49 W, 2932 MHz, 13801 MHz, 65, 100 %, 449.17 W, 449.49 W
2026/10/09 09:05:25.736, 450.10 W, 2932 MHz, 13801 MHz, 65, 100 %, 450.30 W, 450.10 W
2026/10/09 09:05:26.736, 450.90 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.51 W, 450.90 W
2026/10/09 09:05:27.737, 450.71 W, 2932 MHz, 13801 MHz, 66, 100 %, 450.72 W, 450.71 W
2026/10/09 09:05:28.737, 449.71 W, 2932 MHz, 13801 MHz, 66, 100 %, 448.14 W, 449.71 W
2026/10/09 09:05:29.737, 449.14 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.00 W, 449.14 W
2026/10/09 09:05:30.737, 449.72 W, 2932 MHz, 13801 MHz, 66, 100 %, 450.51 W, 449.72 W
2026/10/09 09:05:31.738, 450.17 W, 2932 MHz, 13801 MHz, 66, 100 %, 450.90 W, 450.17 W
2026/10/09 09:05:32.738, 450.68 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.11 W, 450.68 W
2026/10/09 09:05:33.738, 451.02 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.49 W, 451.02 W
2026/10/09 09:05:34.739, 451.51 W, 2932 MHz, 13801 MHz, 66, 100 %, 450.74 W, 451.51 W
2026/10/09 09:05:35.739, 451.37 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.85 W, 451.37 W
2026/10/09 09:05:36.739, 451.36 W, 2932 MHz, 13801 MHz, 66, 100 %, 452.48 W, 451.36 W
2026/10/09 09:05:37.739, 451.91 W, 2932 MHz, 13801 MHz, 66, 100 %, 452.29 W, 451.91 W
2026/10/09 09:05:38.740, 452.93 W, 2932 MHz, 13801 MHz, 66, 100 %, 452.40 W, 452.93 W
2026/10/09 09:05:39.740, 453.42 W, 2932 MHz, 13801 MHz, 66, 100 %, 453.95 W, 453.42 W
2026/10/09 09:05:40.740, 454.61 W, 2932 MHz, 13801 MHz, 66, 100 %, 455.51 W, 454.61 W
2026/10/09 09:05:41.740, 454.51 W, 2932 MHz, 13801 MHz, 66, 100 %, 454.29 W, 454.51 W
2026/10/09 09:05:42.741, 453.07 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.37 W, 453.07 W
2026/10/09 09:05:43.741, 452.22 W, 2932 MHz, 13801 MHz, 66, 100 %, 451.75 W, 452.22 W
2026/10/09 09:05:44.741, 452.73 W, 2932 MHz, 13801 MHz, 66, 100 %, 452.96 W, 452.73 W
2026/10/09 09:05:45.741, 452.39 W, 2932 MHz, 13801 MHz, 66, 100 %, 453.17 W, 452.39 W
2026/10/09 09:05:46.742, 453.17 W, 2932 MHz, 13801 MHz, 66, 100 %, 454.08 W, 453.17 W
2026/10/09 09:05:47.742, 453.36 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.93 W, 453.36 W
2026/10/09 09:05:48.742, 454.05 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.07 W, 454.05 W
2026/10/09 09:05:49.742, 453.63 W, 2932 MHz, 13801 MHz, 67, 100 %, 454.58 W, 453.63 W
2026/10/09 09:05:50.742, 454.02 W, 2932 MHz, 13801 MHz, 67, 100 %, 454.61 W, 454.02 W
2026/10/09 09:05:51.742, 453.04 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.60 W, 453.04 W
2026/10/09 09:05:52.743, 453.03 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.70 W, 453.03 W
2026/10/09 09:05:53.743, 453.21 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.71 W, 453.21 W
2026/10/09 09:05:54.743, 454.05 W, 2932 MHz, 13801 MHz, 67, 100 %, 454.48 W, 454.05 W
2026/10/09 09:05:55.743, 453.72 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.76 W, 453.72 W
2026/10/09 09:05:56.744, 453.12 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.73 W, 453.12 W
2026/10/09 09:05:57.744, 452.35 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.10 W, 452.35 W
2026/10/09 09:05:58.744, 452.67 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.05 W, 452.67 W
2026/10/09 09:05:59.745, 452.78 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.27 W, 452.78 W
2026/10/09 09:06:00.745, 453.24 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.40 W, 453.24 W
2026/10/09 09:06:01.745, 453.58 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.06 W, 453.58 W
2026/10/09 09:06:02.745, 455.11 W, 2932 MHz, 13801 MHz, 67, 100 %, 454.90 W, 455.11 W
2026/10/09 09:06:03.746, 455.46 W, 2932 MHz, 13801 MHz, 67, 100 %, 455.09 W, 455.46 W
2026/10/09 09:06:04.746, 455.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 454.62 W, 455.17 W
2026/10/09 09:06:05.746, 454.29 W, 2932 MHz, 13801 MHz, 67, 100 %, 455.05 W, 454.29 W
2026/10/09 09:06:06.746, 453.70 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.21 W, 453.70 W
2026/10/09 09:06:07.747, 454.08 W, 2932 MHz, 13801 MHz, 67, 100 %, 453.85 W, 454.08 W
2026/10/09 09:06:08.747, 454.34 W, 2932 MHz, 13801 MHz, 67, 100 %, 455.47 W, 454.34 W
2026/10/09 09:06:09.748, 250.89 W, 2947 MHz, 14001 MHz, 59, 0 %, 114.06 W, 250.89 W
2026/10/09 09:06:10.748, 126.39 W, 2947 MHz, 14001 MHz, 59, 0 %, 112.33 W, 126.39 W
2026/10/09 09:06:11.748, 101.37 W, 2685 MHz, 7001 MHz, 57, 0 %, 101.37 W, 101.37 W
2026/10/09 09:06:12.749, 74.34 W, 405 MHz, 7001 MHz, 55, 0 %, 47.31 W, 74.34 W
2026/10/09 09:06:13.749, 46.21 W, 255 MHz, 7001 MHz, 55, 0 %, 45.11 W, 46.21 W
2026/10/09 09:06:14.749, 44.51 W, 195 MHz, 7001 MHz, 55, 0 %, 43.92 W, 44.51 W
2026/10/09 09:06:15.749, 43.05 W, 195 MHz, 7001 MHz, 54, 0 %, 43.05 W, 43.05 W
2026/10/09 09:06:16.750, 27.97 W, 195 MHz, 810 MHz, 54, 0 %, 27.97 W, 27.97 W
2026/10/09 09:06:17.750, 25.76 W, 187 MHz, 405 MHz, 53, 0 %, 23.55 W, 25.76 W
2026/10/09 09:06:18.750, 22.12 W, 195 MHz, 405 MHz, 53, 0 %, 20.69 W, 22.12 W
2026/10/09 09:06:19.750, 37.07 W, 2542 MHz, 13801 MHz, 54, 0 %, 79.31 W, 37.07 W
2026/10/09 09:06:20.751, 101.04 W, 2542 MHz, 13801 MHz, 54, 0 %, 79.43 W, 101.04 W
2026/10/09 09:06:21.751, 333.36 W, 2932 MHz, 13801 MHz, 63, 32 %, 439.39 W, 333.36 W
2026/10/09 09:06:22.751, 441.35 W, 2932 MHz, 13801 MHz, 64, 100 %, 441.81 W, 441.35 W
2026/10/09 09:06:23.751, 442.73 W, 2932 MHz, 13801 MHz, 64, 100 %, 442.85 W, 442.73 W
2026/10/09 09:06:24.751, 443.79 W, 2932 MHz, 13801 MHz, 64, 100 %, 444.89 W, 443.79 W
2026/10/09 09:06:25.752, 445.42 W, 2932 MHz, 13801 MHz, 64, 100 %, 445.86 W, 445.42 W
2026/10/09 09:06:26.752, 445.26 W, 2932 MHz, 13801 MHz, 64, 100 %, 445.82 W, 445.26 W
2026/10/09 09:06:27.752, 445.02 W, 2932 MHz, 13801 MHz, 65, 100 %, 445.17 W, 445.02 W
2026/10/09 09:06:28.752, 443.83 W, 2932 MHz, 13801 MHz, 65, 100 %, 443.74 W, 443.83 W
2026/10/09 09:06:29.752, 443.72 W, 2932 MHz, 13801 MHz, 65, 100 %, 444.03 W, 443.72 W
2026/10/09 09:06:30.752, 444.38 W, 2932 MHz, 13801 MHz, 65, 100 %, 444.92 W, 444.38 W
2026/10/09 09:06:31.753, 444.55 W, 2932 MHz, 13801 MHz, 65, 100 %, 443.57 W, 444.55 W
2026/10/09 09:06:32.753, 445.36 W, 2932 MHz, 13801 MHz, 65, 100 %, 444.74 W, 445.36 W
2026/10/09 09:06:33.753, 446.36 W, 2932 MHz, 13801 MHz, 65, 100 %, 446.05 W, 446.36 W
2026/10/09 09:06:34.753, 446.18 W, 2932 MHz, 13801 MHz, 65, 100 %, 445.78 W, 446.18 W
2026/10/09 09:06:35.753, 446.64 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.73 W, 446.64 W
2026/10/09 09:06:36.753, 445.65 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.60 W, 445.65 W
2026/10/09 09:06:37.754, 446.00 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.44 W, 446.00 W
2026/10/09 09:06:38.754, 445.88 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.62 W, 445.88 W
2026/10/09 09:06:39.754, 446.59 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.76 W, 446.59 W
2026/10/09 09:06:40.754, 447.72 W, 2932 MHz, 13801 MHz, 66, 100 %, 448.13 W, 447.72 W
2026/10/09 09:06:41.754, 446.92 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.58 W, 446.92 W
2026/10/09 09:06:42.754, 446.34 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.33 W, 446.34 W
2026/10/09 09:06:43.754, 446.13 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.84 W, 446.13 W
2026/10/09 09:06:44.755, 446.66 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.55 W, 446.66 W
2026/10/09 09:06:45.755, 446.88 W, 2932 MHz, 13801 MHz, 66, 99 %, 445.79 W, 446.88 W
2026/10/09 09:06:46.755, 448.03 W, 2932 MHz, 13801 MHz, 66, 100 %, 449.29 W, 448.03 W
2026/10/09 09:06:47.755, 448.52 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.61 W, 448.52 W
2026/10/09 09:06:48.755, 449.47 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.53 W, 449.47 W
2026/10/09 09:06:49.755, 449.48 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.53 W, 449.48 W
2026/10/09 09:06:50.755, 449.19 W, 2932 MHz, 13801 MHz, 66, 100 %, 449.24 W, 449.19 W
2026/10/09 09:06:51.756, 447.02 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.76 W, 447.02 W
2026/10/09 09:06:52.756, 446.52 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.83 W, 446.52 W
2026/10/09 09:06:53.756, 447.26 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.48 W, 447.26 W
2026/10/09 09:06:54.756, 447.77 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.68 W, 447.77 W
2026/10/09 09:06:55.756, 447.94 W, 2932 MHz, 13801 MHz, 66, 100 %, 448.02 W, 447.94 W
2026/10/09 09:06:56.756, 448.75 W, 2932 MHz, 13801 MHz, 66, 100 %, 448.10 W, 448.75 W
2026/10/09 09:06:57.756, 448.63 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.81 W, 448.63 W
2026/10/09 09:06:58.757, 448.58 W, 2932 MHz, 13801 MHz, 67, 100 %, 447.72 W, 448.58 W
2026/10/09 09:06:59.757, 448.04 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.42 W, 448.04 W
2026/10/09 09:07:00.757, 447.55 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.52 W, 447.55 W
2026/10/09 09:07:01.757, 448.64 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.75 W, 448.64 W
2026/10/09 09:07:02.757, 449.50 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.06 W, 449.50 W
2026/10/09 09:07:03.757, 449.29 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.81 W, 449.29 W
2026/10/09 09:07:04.758, 448.92 W, 2932 MHz, 13801 MHz, 67, 100 %, 446.71 W, 448.92 W
2026/10/09 09:07:05.758, 447.75 W, 2932 MHz, 13801 MHz, 67, 100 %, 447.00 W, 447.75 W
2026/10/09 09:07:06.758, 448.28 W, 2932 MHz, 13801 MHz, 67, 100 %, 447.73 W, 448.28 W
2026/10/09 09:07:07.758, 449.08 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.80 W, 449.08 W
2026/10/09 09:07:08.758, 449.29 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.00 W, 449.29 W
2026/10/09 09:07:09.758, 450.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.30 W, 450.17 W
2026/10/09 09:07:10.759, 450.92 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.67 W, 450.92 W
2026/10/09 09:07:11.759, 451.85 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.10 W, 451.85 W
2026/10/09 09:07:12.759, 450.48 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.91 W, 450.48 W
2026/10/09 09:07:13.759, 450.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.55 W, 450.17 W
2026/10/09 09:07:14.759, 449.25 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.96 W, 449.25 W
2026/10/09 09:07:15.759, 449.28 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.95 W, 449.28 W
2026/10/09 09:07:16.760, 449.70 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.92 W, 449.70 W
2026/10/09 09:07:17.760, 449.75 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.74 W, 449.75 W
2026/10/09 09:07:18.760, 450.21 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.63 W, 450.21 W
2026/10/09 09:07:19.760, 450.11 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.19 W, 450.11 W
2026/10/09 09:07:20.760, 450.69 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.33 W, 450.69 W
2026/10/09 09:07:21.760, 449.99 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.08 W, 449.99 W
2026/10/09 09:07:22.761, 323.10 W, 2947 MHz, 14001 MHz, 59, 100 %, 113.71 W, 323.10 W
2026/10/09 09:07:23.761, 115.13 W, 2947 MHz, 14001 MHz, 59, 0 %, 112.80 W, 115.13 W
2026/10/09 09:07:24.761, 102.47 W, 2220 MHz, 7001 MHz, 57, 0 %, 101.44 W, 102.47 W
2026/10/09 09:07:25.761, 74.74 W, 397 MHz, 7001 MHz, 56, 0 %, 48.04 W, 74.74 W
2026/10/09 09:07:26.761, 45.66 W, 255 MHz, 7001 MHz, 55, 0 %, 45.66 W, 45.66 W
2026/10/09 09:07:27.761, 44.83 W, 195 MHz, 7001 MHz, 55, 0 %, 44.00 W, 44.83 W
2026/10/09 09:07:28.761, 43.18 W, 195 MHz, 7001 MHz, 54, 0 %, 43.18 W, 43.18 W
2026/10/09 09:07:29.762, 28.26 W, 195 MHz, 810 MHz, 54, 0 %, 28.26 W, 28.26 W
2026/10/09 09:07:30.762, 25.25 W, 195 MHz, 405 MHz, 53, 0 %, 22.23 W, 25.25 W
2026/10/09 09:07:31.762, 19.63 W, 195 MHz, 405 MHz, 53, 0 %, 19.63 W, 19.63 W
2026/10/09 09:07:32.762, 32.82 W, 1515 MHz, 13801 MHz, 54, 0 %, 80.99 W, 32.82 W
2026/10/09 09:07:33.762, 105.47 W, 2625 MHz, 13801 MHz, 55, 0 %, 84.16 W, 105.47 W
2026/10/09 09:07:34.762, 287.73 W, 2947 MHz, 13801 MHz, 63, 100 %, 431.89 W, 287.73 W
2026/10/09 09:07:35.762, 431.51 W, 2932 MHz, 13801 MHz, 64, 100 %, 432.27 W, 431.51 W
2026/10/09 09:07:36.763, 431.86 W, 2932 MHz, 13801 MHz, 64, 100 %, 432.15 W, 431.86 W
2026/10/09 09:07:37.763, 432.58 W, 2932 MHz, 13801 MHz, 64, 100 %, 433.37 W, 432.58 W
2026/10/09 09:07:38.763, 433.05 W, 2932 MHz, 13801 MHz, 64, 100 %, 434.55 W, 433.05 W
2026/10/09 09:07:39.763, 434.25 W, 2932 MHz, 13801 MHz, 64, 100 %, 434.44 W, 434.25 W
2026/10/09 09:07:40.763, 434.67 W, 2932 MHz, 13801 MHz, 65, 100 %, 435.12 W, 434.67 W
2026/10/09 09:07:41.763, 435.87 W, 2932 MHz, 13801 MHz, 65, 100 %, 435.69 W, 435.87 W
2026/10/09 09:07:42.764, 435.36 W, 2932 MHz, 13801 MHz, 65, 100 %, 434.92 W, 435.36 W
2026/10/09 09:07:43.764, 435.63 W, 2932 MHz, 13801 MHz, 65, 100 %, 435.97 W, 435.63 W
2026/10/09 09:07:44.764, 434.61 W, 2932 MHz, 13801 MHz, 65, 100 %, 434.88 W, 434.61 W
2026/10/09 09:07:45.764, 435.49 W, 2932 MHz, 13801 MHz, 65, 100 %, 436.06 W, 435.49 W
2026/10/09 09:07:46.764, 436.51 W, 2932 MHz, 13801 MHz, 65, 100 %, 436.49 W, 436.51 W
2026/10/09 09:07:47.764, 437.37 W, 2932 MHz, 13801 MHz, 65, 100 %, 438.77 W, 437.37 W
2026/10/09 09:07:48.765, 438.38 W, 2932 MHz, 13801 MHz, 65, 100 %, 438.38 W, 438.38 W
2026/10/09 09:07:49.765, 437.87 W, 2932 MHz, 13801 MHz, 65, 100 %, 437.96 W, 437.87 W
2026/10/09 09:07:50.765, 437.02 W, 2932 MHz, 13801 MHz, 66, 100 %, 436.71 W, 437.02 W
2026/10/09 09:07:51.765, 436.85 W, 2932 MHz, 13801 MHz, 66, 100 %, 436.90 W, 436.85 W
2026/10/09 09:07:52.765, 437.46 W, 2932 MHz, 13801 MHz, 66, 100 %, 437.63 W, 437.46 W
2026/10/09 09:07:53.765, 438.19 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.63 W, 438.19 W
2026/10/09 09:07:54.766, 439.15 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.61 W, 439.15 W
2026/10/09 09:07:55.766, 440.03 W, 2932 MHz, 13801 MHz, 66, 100 %, 440.82 W, 440.03 W
2026/10/09 09:07:56.766, 441.52 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.04 W, 441.52 W
2026/10/09 09:07:57.766, 441.48 W, 2932 MHz, 13801 MHz, 66, 100 %, 441.93 W, 441.48 W
2026/10/09 09:07:58.766, 440.32 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.81 W, 440.32 W
2026/10/09 09:07:59.767, 439.43 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.90 W, 439.43 W
2026/10/09 09:08:00.767, 438.83 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.74 W, 438.83 W
2026/10/09 09:08:01.767, 439.38 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.54 W, 439.38 W
2026/10/09 09:08:02.767, 440.17 W, 2932 MHz, 13801 MHz, 66, 100 %, 440.20 W, 440.17 W
2026/10/09 09:08:03.767, 440.83 W, 2932 MHz, 13801 MHz, 66, 100 %, 440.91 W, 440.83 W
2026/10/09 09:08:04.767, 441.73 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.23 W, 441.73 W
2026/10/09 09:08:05.768, 441.68 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.91 W, 441.68 W
2026/10/09 09:08:06.768, 441.48 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.50 W, 441.48 W
2026/10/09 09:08:07.768, 440.98 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.54 W, 440.98 W
2026/10/09 09:08:08.768, 440.52 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.72 W, 440.52 W
2026/10/09 09:08:09.769, 441.14 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.49 W, 441.14 W
2026/10/09 09:08:10.769, 441.60 W, 2932 MHz, 13801 MHz, 67, 99 %, 442.66 W, 441.60 W
2026/10/09 09:08:11.769, 442.40 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.17 W, 442.40 W
2026/10/09 09:08:12.769, 441.72 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.78 W, 441.72 W
2026/10/09 09:08:13.770, 441.54 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.22 W, 441.54 W
2026/10/09 09:08:14.770, 440.85 W, 2932 MHz, 13801 MHz, 67, 100 %, 439.33 W, 440.85 W
2026/10/09 09:08:15.770, 441.36 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.17 W, 441.36 W
2026/10/09 09:08:16.770, 441.62 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.70 W, 441.62 W
2026/10/09 09:08:17.770, 442.71 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.85 W, 442.71 W
2026/10/09 09:08:18.771, 443.26 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.75 W, 443.26 W
2026/10/09 09:08:19.771, 443.99 W, 2932 MHz, 13801 MHz, 67, 100 %, 445.31 W, 443.99 W
2026/10/09 09:08:20.771, 443.76 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.97 W, 443.76 W
2026/10/09 09:08:21.771, 442.63 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.74 W, 442.63 W
2026/10/09 09:08:22.771, 442.41 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.61 W, 442.41 W
2026/10/09 09:08:23.771, 442.21 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.63 W, 442.21 W
2026/10/09 09:08:24.772, 442.44 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.43 W, 442.44 W
2026/10/09 09:08:25.772, 442.92 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.86 W, 442.92 W
2026/10/09 09:08:26.772, 442.86 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.61 W, 442.86 W
2026/10/09 09:08:27.772, 443.39 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.76 W, 443.39 W
2026/10/09 09:08:28.773, 443.30 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.92 W, 443.30 W
2026/10/09 09:08:29.773, 442.78 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.20 W, 442.78 W
2026/10/09 09:08:30.773, 442.11 W, 2932 MHz, 13801 MHz, 68, 100 %, 442.84 W, 442.11 W
2026/10/09 09:08:31.773, 442.68 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.26 W, 442.68 W
2026/10/09 09:08:32.773, 442.80 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.06 W, 442.80 W
2026/10/09 09:08:33.774, 443.60 W, 2932 MHz, 13801 MHz, 68, 100 %, 444.65 W, 443.60 W
2026/10/09 09:08:34.774, 444.33 W, 2932 MHz, 13801 MHz, 68, 100 %, 444.97 W, 444.33 W
2026/10/09 09:08:35.774, 373.14 W, 2932 MHz, 14001 MHz, 61, 100 %, 116.07 W, 373.14 W
2026/10/09 09:08:36.774, 132.74 W, 2947 MHz, 14001 MHz, 59, 0 %, 112.61 W, 132.74 W
2026/10/09 09:08:37.775, 102.82 W, 2745 MHz, 7001 MHz, 57, 0 %, 101.84 W, 102.82 W
2026/10/09 09:08:38.775, 48.40 W, 555 MHz, 7001 MHz, 56, 0 %, 48.40 W, 48.40 W
2026/10/09 09:08:39.775, 45.83 W, 345 MHz, 7001 MHz, 55, 0 %, 45.83 W, 45.83 W
2026/10/09 09:08:40.776, 45.34 W, 217 MHz, 7001 MHz, 55, 0 %, 44.84 W, 45.34 W
2026/10/09 09:08:41.776, 45.24 W, 195 MHz, 7001 MHz, 54, 0 %, 45.24 W, 45.24 W
2026/10/09 09:08:42.776, 41.72 W, 195 MHz, 810 MHz, 54, 0 %, 41.72 W, 41.72 W
2026/10/09 09:08:43.776, 33.31 W, 195 MHz, 810 MHz, 53, 0 %, 24.91 W, 33.31 W
2026/10/09 09:08:44.776, 20.40 W, 195 MHz, 405 MHz, 53, 0 %, 20.40 W, 20.40 W
2026/10/09 09:08:45.777, 20.96 W, 195 MHz, 405 MHz, 53, 0 %, 32.44 W, 20.96 W
2026/10/09 09:08:46.777, 80.04 W, 2542 MHz, 13801 MHz, 54, 0 %, 79.39 W, 80.04 W
2026/10/09 09:08:47.777, 240.92 W, 2947 MHz, 13801 MHz, 61, 6 %, 428.72 W, 240.92 W
2026/10/09 09:08:48.777, 430.50 W, 2932 MHz, 13801 MHz, 63, 100 %, 431.64 W, 430.50 W
2026/10/09 09:08:49.777, 432.03 W, 2932 MHz, 13801 MHz, 64, 100 %, 432.63 W, 432.03 W
2026/10/09 09:08:50.778, 432.95 W, 2932 MHz, 13801 MHz, 64, 100 %, 434.01 W, 432.95 W
2026/10/09 09:08:51.778, 433.56 W, 2932 MHz, 13801 MHz, 64, 100 %, 433.70 W, 433.56 W
2026/10/09 09:08:52.778, 433.02 W, 2932 MHz, 13801 MHz, 64, 100 %, 432.11 W, 433.02 W
2026/10/09 09:08:53.778, 433.28 W, 2932 MHz, 13801 MHz, 64, 100 %, 433.27 W, 433.28 W
2026/10/09 09:08:54.779, 433.47 W, 2932 MHz, 13801 MHz, 65, 100 %, 434.38 W, 433.47 W
2026/10/09 09:08:55.779, 435.03 W, 2932 MHz, 13801 MHz, 65, 100 %, 435.69 W, 435.03 W
2026/10/09 09:08:56.779, 435.24 W, 2932 MHz, 13801 MHz, 65, 100 %, 434.12 W, 435.24 W
2026/10/09 09:08:57.779, 435.92 W, 2932 MHz, 13801 MHz, 65, 100 %, 436.80 W, 435.92 W
2026/10/09 09:08:58.779, 435.40 W, 2932 MHz, 13801 MHz, 65, 100 %, 434.77 W, 435.40 W
2026/10/09 09:08:59.780, 434.63 W, 2932 MHz, 13801 MHz, 65, 100 %, 435.25 W, 434.63 W
2026/10/09 09:09:00.780, 435.78 W, 2932 MHz, 13801 MHz, 65, 100 %, 436.79 W, 435.78 W
2026/10/09 09:09:01.780, 436.27 W, 2932 MHz, 13801 MHz, 65, 100 %, 437.48 W, 436.27 W
2026/10/09 09:09:02.780, 437.70 W, 2932 MHz, 13801 MHz, 65, 100 %, 437.94 W, 437.70 W
2026/10/09 09:09:03.781, 438.49 W, 2932 MHz, 13801 MHz, 65, 100 %, 440.09 W, 438.49 W
2026/10/09 09:09:04.781, 439.33 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.28 W, 439.33 W
2026/10/09 09:09:05.781, 438.69 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.42 W, 438.69 W
2026/10/09 09:09:06.781, 438.98 W, 2932 MHz, 13801 MHz, 66, 100 %, 437.55 W, 438.98 W
2026/10/09 09:09:07.782, 437.60 W, 2932 MHz, 13801 MHz, 66, 100 %, 437.73 W, 437.60 W
2026/10/09 09:09:08.782, 437.94 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.83 W, 437.94 W
2026/10/09 09:09:09.782, 438.73 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.50 W, 438.73 W
2026/10/09 09:09:10.782, 438.90 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.25 W, 438.90 W
2026/10/09 09:09:11.783, 439.36 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.83 W, 439.36 W
2026/10/09 09:09:12.783, 439.82 W, 2932 MHz, 13801 MHz, 66, 100 %, 440.22 W, 439.82 W
2026/10/09 09:09:13.783, 439.94 W, 2932 MHz, 13801 MHz, 66, 100 %, 440.35 W, 439.94 W
2026/10/09 09:09:14.784, 440.27 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.81 W, 440.27 W
2026/10/09 09:09:15.784, 439.17 W, 2932 MHz, 13801 MHz, 66, 100 %, 438.20 W, 439.17 W
2026/10/09 09:09:16.784, 439.05 W, 2932 MHz, 13801 MHz, 66, 100 %, 439.25 W, 439.05 W
2026/10/09 09:09:17.784, 440.14 W, 2932 MHz, 13801 MHz, 66, 100 %, 442.26 W, 440.14 W
2026/10/09 09:09:18.785, 441.01 W, 2932 MHz, 13801 MHz, 67, 100 %, 439.92 W, 441.01 W
2026/10/09 09:09:19.785, 440.89 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.54 W, 440.89 W
2026/10/09 09:09:20.786, 440.82 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.58 W, 440.82 W
2026/10/09 09:09:21.786, 440.67 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.54 W, 440.67 W
2026/10/09 09:09:22.786, 440.11 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.85 W, 440.11 W
2026/10/09 09:09:23.786, 440.24 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.96 W, 440.24 W
2026/10/09 09:09:24.786, 441.01 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.83 W, 441.01 W
2026/10/09 09:09:25.786, 441.97 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.87 W, 441.97 W
2026/10/09 09:09:26.787, 443.01 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.64 W, 443.01 W
2026/10/09 09:09:27.787, 444.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.70 W, 444.17 W
2026/10/09 09:09:28.787, 443.55 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.44 W, 443.55 W
2026/10/09 09:09:29.787, 442.40 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.04 W, 442.40 W
2026/10/09 09:09:30.787, 441.92 W, 2932 MHz, 13801 MHz, 67, 100 %, 440.46 W, 441.92 W
2026/10/09 09:09:31.787, 441.91 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.30 W, 441.91 W
2026/10/09 09:09:32.788, 441.91 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.43 W, 441.91 W
2026/10/09 09:09:33.788, 442.54 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.81 W, 442.54 W
2026/10/09 09:09:34.788, 443.31 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.35 W, 443.31 W
2026/10/09 09:09:35.788, 443.45 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.74 W, 443.45 W
2026/10/09 09:09:36.788, 443.37 W, 2932 MHz, 13801 MHz, 67, 100 %, 444.04 W, 443.37 W
2026/10/09 09:09:37.788, 442.71 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.23 W, 442.71 W
2026/10/09 09:09:38.789, 442.91 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.96 W, 442.91 W
2026/10/09 09:09:39.789, 442.24 W, 2932 MHz, 13801 MHz, 67, 100 %, 441.36 W, 442.24 W
2026/10/09 09:09:40.789, 443.02 W, 2932 MHz, 13801 MHz, 67, 100 %, 442.89 W, 443.02 W
2026/10/09 09:09:41.789, 443.51 W, 2932 MHz, 13801 MHz, 67, 100 %, 443.23 W, 443.51 W
2026/10/09 09:09:42.790, 443.93 W, 2932 MHz, 13801 MHz, 68, 100 %, 444.02 W, 443.93 W
2026/10/09 09:09:43.790, 443.37 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.40 W, 443.37 W
2026/10/09 09:09:44.790, 443.07 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.29 W, 443.07 W
2026/10/09 09:09:45.790, 442.82 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.31 W, 442.82 W
2026/10/09 09:09:46.790, 443.19 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.53 W, 443.19 W
2026/10/09 09:09:47.791, 443.18 W, 2932 MHz, 13801 MHz, 68, 100 %, 443.99 W, 443.18 W
2026/10/09 09:09:48.791, 444.31 W, 2932 MHz, 13801 MHz, 68, 100 %, 444.97 W, 444.31 W
2026/10/09 09:09:49.791, 122.28 W, 2947 MHz, 14001 MHz, 59, 0 %, 114.90 W, 122.28 W
2026/10/09 09:09:50.791, 121.64 W, 2947 MHz, 14001 MHz, 59, 0 %, 115.20 W, 121.64 W
2026/10/09 09:09:51.791, 103.82 W, 795 MHz, 14001 MHz, 57, 0 %, 103.82 W, 103.82 W
2026/10/09 09:09:52.792, 42.49 W, 360 MHz, 810 MHz, 55, 0 %, 42.49 W, 42.49 W
2026/10/09 09:09:53.792, 27.18 W, 210 MHz, 810 MHz, 55, 0 %, 27.18 W, 27.18 W
2026/10/09 09:09:54.792, 24.23 W, 195 MHz, 405 MHz, 54, 0 %, 21.27 W, 24.23 W
2026/10/09 09:09:55.793, 20.13 W, 195 MHz, 405 MHz, 54, 0 %, 20.13 W, 20.13 W
2026/10/09 09:09:56.793, 20.03 W, 195 MHz, 405 MHz, 54, 0 %, 19.94 W, 20.03 W
2026/10/09 09:09:57.793, 20.29 W, 195 MHz, 405 MHz, 53, 0 %, 20.29 W, 20.29 W
2026/10/09 09:09:58.793, 20.45 W, 195 MHz, 405 MHz, 53, 0 %, 20.45 W, 20.45 W
2026/10/09 09:09:59.793, 44.67 W, 2542 MHz, 13801 MHz, 54, 0 %, 80.09 W, 44.67 W
2026/10/09 09:10:00.793, 173.43 W, 2677 MHz, 13801 MHz, 61, 6 %, 436.89 W, 173.43 W
2026/10/09 09:10:01.793, 401.91 W, 2932 MHz, 13801 MHz, 63, 100 %, 441.33 W, 401.91 W
2026/10/09 09:10:02.794, 441.88 W, 2932 MHz, 13801 MHz, 64, 100 %, 443.07 W, 441.88 W
2026/10/09 09:10:03.794, 443.09 W, 2932 MHz, 13801 MHz, 64, 100 %, 443.81 W, 443.09 W
2026/10/09 09:10:04.794, 444.19 W, 2932 MHz, 13801 MHz, 64, 100 %, 444.39 W, 444.19 W
2026/10/09 09:10:05.794, 443.87 W, 2932 MHz, 13801 MHz, 65, 100 %, 443.78 W, 443.87 W
2026/10/09 09:10:06.794, 443.51 W, 2932 MHz, 13801 MHz, 65, 100 %, 443.67 W, 443.51 W
2026/10/09 09:10:07.794, 443.74 W, 2932 MHz, 13801 MHz, 65, 100 %, 444.79 W, 443.74 W
2026/10/09 09:10:08.795, 444.57 W, 2932 MHz, 13801 MHz, 65, 100 %, 444.05 W, 444.57 W
2026/10/09 09:10:09.795, 444.35 W, 2932 MHz, 13801 MHz, 65, 100 %, 443.94 W, 444.35 W
2026/10/09 09:10:10.795, 445.52 W, 2932 MHz, 13801 MHz, 65, 100 %, 445.93 W, 445.52 W
2026/10/09 09:10:11.795, 446.57 W, 2932 MHz, 13801 MHz, 65, 100 %, 446.58 W, 446.57 W
2026/10/09 09:10:12.795, 447.46 W, 2932 MHz, 13801 MHz, 65, 100 %, 447.87 W, 447.46 W
2026/10/09 09:10:13.796, 447.70 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.51 W, 447.70 W
2026/10/09 09:10:14.796, 446.70 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.22 W, 446.70 W
2026/10/09 09:10:15.796, 446.06 W, 2932 MHz, 13801 MHz, 66, 100 %, 444.95 W, 446.06 W
2026/10/09 09:10:16.796, 445.07 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.37 W, 445.07 W
2026/10/09 09:10:17.797, 446.28 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.45 W, 446.28 W
2026/10/09 09:10:18.797, 447.26 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.87 W, 447.26 W
2026/10/09 09:10:19.797, 447.49 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.35 W, 447.49 W
2026/10/09 09:10:20.798, 448.46 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.87 W, 448.46 W
2026/10/09 09:10:21.798, 448.38 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.46 W, 448.38 W
2026/10/09 09:10:22.798, 447.71 W, 2932 MHz, 13801 MHz, 66, 100 %, 445.75 W, 447.71 W
2026/10/09 09:10:23.799, 447.69 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.90 W, 447.69 W
2026/10/09 09:10:24.799, 447.49 W, 2932 MHz, 13801 MHz, 66, 100 %, 447.74 W, 447.49 W
2026/10/09 09:10:25.799, 447.71 W, 2932 MHz, 13801 MHz, 67, 100 %, 447.89 W, 447.71 W
2026/10/09 09:10:26.799, 448.39 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.58 W, 448.39 W
2026/10/09 09:10:27.799, 448.94 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.28 W, 448.94 W
2026/10/09 09:10:28.800, 448.84 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.72 W, 448.84 W
2026/10/09 09:10:29.800, 448.24 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.42 W, 448.24 W
2026/10/09 09:10:30.800, 447.18 W, 2932 MHz, 13801 MHz, 67, 100 %, 446.22 W, 447.18 W
2026/10/09 09:10:31.800, 447.33 W, 2932 MHz, 13801 MHz, 66, 100 %, 446.87 W, 447.33 W
2026/10/09 09:10:32.800, 447.82 W, 2932 MHz, 13801 MHz, 67, 100 %, 447.50 W, 447.82 W
2026/10/09 09:10:33.800, 448.67 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.48 W, 448.67 W
2026/10/09 09:10:34.801, 450.29 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.63 W, 450.29 W
2026/10/09 09:10:35.801, 450.55 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.40 W, 450.55 W
2026/10/09 09:10:36.801, 450.43 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.27 W, 450.43 W
2026/10/09 09:10:37.801, 449.76 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.05 W, 449.76 W
2026/10/09 09:10:38.802, 448.65 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.73 W, 448.65 W
2026/10/09 09:10:39.802, 448.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.73 W, 448.17 W
2026/10/09 09:10:40.803, 448.71 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.67 W, 448.71 W
2026/10/09 09:10:41.803, 448.96 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.01 W, 448.96 W
2026/10/09 09:10:42.803, 450.33 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.11 W, 450.33 W
2026/10/09 09:10:43.803, 450.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 448.80 W, 450.17 W
2026/10/09 09:10:44.803, 450.80 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.62 W, 450.80 W
2026/10/09 09:10:45.803, 450.61 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.83 W, 450.61 W
2026/10/09 09:10:46.804, 450.00 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.20 W, 450.00 W
2026/10/09 09:10:47.804, 449.80 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.53 W, 449.80 W
2026/10/09 09:10:48.804, 450.37 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.76 W, 450.37 W
2026/10/09 09:10:49.804, 451.11 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.47 W, 451.11 W
2026/10/09 09:10:50.804, 451.54 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.77 W, 451.54 W
2026/10/09 09:10:51.804, 450.40 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.60 W, 450.40 W
2026/10/09 09:10:52.805, 450.12 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.40 W, 450.12 W
2026/10/09 09:10:53.805, 450.24 W, 2932 MHz, 13801 MHz, 67, 100 %, 449.70 W, 450.24 W
2026/10/09 09:10:54.805, 450.42 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.30 W, 450.42 W
2026/10/09 09:10:55.805, 450.95 W, 2932 MHz, 13801 MHz, 67, 100 %, 450.96 W, 450.95 W
2026/10/09 09:10:56.806, 452.20 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.73 W, 452.20 W
2026/10/09 09:10:57.806, 452.07 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.71 W, 452.07 W
2026/10/09 09:10:58.806, 453.17 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.94 W, 453.17 W
2026/10/09 09:10:59.806, 452.71 W, 2932 MHz, 13801 MHz, 67, 100 %, 452.39 W, 452.71 W
2026/10/09 09:11:00.807, 451.96 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.42 W, 451.96 W
2026/10/09 09:11:01.807, 450.69 W, 2932 MHz, 13801 MHz, 67, 100 %, 451.54 W, 450.69 W
2026/10/09 09:11:02.807, 227.35 W, 2947 MHz, 14001 MHz, 59, 0 %, 112.95 W, 227.35 W
2026/10/09 09:11:03.808, 135.24 W, 2947 MHz, 14001 MHz, 59, 0 %, 112.98 W, 135.24 W
2026/10/09 09:11:04.808, 101.36 W, 2692 MHz, 14001 MHz, 57, 0 %, 101.36 W, 101.36 W
2026/10/09 09:11:05.808, 41.78 W, 405 MHz, 810 MHz, 56, 0 %, 41.78 W, 41.78 W
2026/10/09 09:11:06.808, 35.32 W, 240 MHz, 810 MHz, 55, 0 %, 28.87 W, 35.32 W
2026/10/09 09:11:07.809, 25.38 W, 195 MHz, 405 MHz, 55, 0 %, 21.89 W, 25.38 W
2026/10/09 09:11:08.809, 21.58 W, 195 MHz, 405 MHz, 54, 0 %, 21.27 W, 21.58 W
2026/10/09 09:11:09.809, 20.70 W, 195 MHz, 405 MHz, 54, 0 %, 20.13 W, 20.70 W
2026/10/09 09:11:10.809, 19.19 W, 195 MHz, 405 MHz, 53, 0 %, 19.19 W, 19.19 W
2026/10/09 09:11:11.809, 20.04 W, 195 MHz, 405 MHz, 53, 0 %, 20.04 W, 20.04 W
1 2026/10/09 09:01:27.675 12.10 W 195 MHz 405 MHz 36 0 % 12.10 W 12.10 W
2 2026/10/09 09:01:28.680 12.55 W 195 MHz 405 MHz 36 0 % 12.55 W 12.55 W
3 2026/10/09 09:01:29.680 12.19 W 195 MHz 405 MHz 36 0 % 11.82 W 12.19 W
4 2026/10/09 09:01:30.681 11.81 W 195 MHz 405 MHz 36 0 % 11.81 W 11.81 W
5 2026/10/09 09:01:31.681 11.60 W 195 MHz 405 MHz 36 0 % 11.60 W 11.60 W
6 2026/10/09 09:01:32.681 11.69 W 195 MHz 405 MHz 36 0 % 11.78 W 11.69 W
7 2026/10/09 09:01:33.682 25.02 W 2565 MHz 13801 MHz 37 0 % 67.64 W 25.02 W
8 2026/10/09 09:01:34.682 73.28 W 2565 MHz 13801 MHz 38 0 % 68.23 W 73.28 W
9 2026/10/09 09:01:35.682 293.48 W 2955 MHz 13801 MHz 47 15 % 416.93 W 293.48 W
10 2026/10/09 09:01:36.683 416.87 W 2955 MHz 13801 MHz 48 100 % 415.79 W 416.87 W
11 2026/10/09 09:01:37.683 417.16 W 2955 MHz 13801 MHz 48 100 % 416.94 W 417.16 W
12 2026/10/09 09:01:38.683 418.13 W 2955 MHz 13801 MHz 49 100 % 420.63 W 418.13 W
13 2026/10/09 09:01:39.683 421.68 W 2955 MHz 13801 MHz 49 100 % 422.18 W 421.68 W
14 2026/10/09 09:01:40.684 421.70 W 2955 MHz 13801 MHz 49 100 % 421.38 W 421.70 W
15 2026/10/09 09:01:41.684 421.38 W 2955 MHz 13801 MHz 50 100 % 420.82 W 421.38 W
16 2026/10/09 09:01:42.684 421.28 W 2955 MHz 13801 MHz 50 100 % 421.44 W 421.28 W
17 2026/10/09 09:01:43.684 421.84 W 2955 MHz 13801 MHz 50 100 % 422.86 W 421.84 W
18 2026/10/09 09:01:44.684 422.80 W 2955 MHz 13801 MHz 51 100 % 423.64 W 422.80 W
19 2026/10/09 09:01:45.685 423.13 W 2955 MHz 13801 MHz 51 100 % 421.76 W 423.13 W
20 2026/10/09 09:01:46.685 423.09 W 2955 MHz 13801 MHz 51 100 % 422.60 W 423.09 W
21 2026/10/09 09:01:47.685 422.94 W 2955 MHz 13801 MHz 51 100 % 422.92 W 422.94 W
22 2026/10/09 09:01:48.686 422.97 W 2955 MHz 13801 MHz 52 100 % 423.77 W 422.97 W
23 2026/10/09 09:01:49.686 423.69 W 2955 MHz 13801 MHz 52 100 % 424.30 W 423.69 W
24 2026/10/09 09:01:50.686 423.93 W 2955 MHz 13801 MHz 52 99 % 424.16 W 423.93 W
25 2026/10/09 09:01:51.686 425.05 W 2955 MHz 13801 MHz 52 100 % 424.66 W 425.05 W
26 2026/10/09 09:01:52.687 426.29 W 2955 MHz 13801 MHz 53 100 % 426.79 W 426.29 W
27 2026/10/09 09:01:53.687 427.06 W 2955 MHz 13801 MHz 53 100 % 427.24 W 427.06 W
28 2026/10/09 09:01:54.687 426.36 W 2955 MHz 13801 MHz 53 100 % 426.01 W 426.36 W
29 2026/10/09 09:01:55.687 425.69 W 2940 MHz 13801 MHz 53 100 % 425.49 W 425.69 W
30 2026/10/09 09:01:56.687 424.97 W 2940 MHz 13801 MHz 54 99 % 423.61 W 424.97 W
31 2026/10/09 09:01:57.688 425.32 W 2940 MHz 13801 MHz 54 100 % 425.75 W 425.32 W
32 2026/10/09 09:01:58.688 426.20 W 2940 MHz 13801 MHz 54 100 % 426.84 W 426.20 W
33 2026/10/09 09:01:59.688 426.86 W 2940 MHz 13801 MHz 54 100 % 427.17 W 426.86 W
34 2026/10/09 09:02:00.688 427.46 W 2940 MHz 13801 MHz 55 100 % 426.36 W 427.46 W
35 2026/10/09 09:02:01.688 427.72 W 2940 MHz 13801 MHz 55 100 % 428.60 W 427.72 W
36 2026/10/09 09:02:02.688 428.31 W 2940 MHz 13801 MHz 55 100 % 428.07 W 428.31 W
37 2026/10/09 09:02:03.689 427.99 W 2940 MHz 13801 MHz 55 100 % 428.18 W 427.99 W
38 2026/10/09 09:02:04.689 427.85 W 2940 MHz 13801 MHz 56 100 % 427.46 W 427.85 W
39 2026/10/09 09:02:05.689 428.48 W 2940 MHz 13801 MHz 56 100 % 428.07 W 428.48 W
40 2026/10/09 09:02:06.689 429.82 W 2940 MHz 13801 MHz 56 100 % 430.12 W 429.82 W
41 2026/10/09 09:02:07.689 430.11 W 2940 MHz 13801 MHz 56 100 % 430.68 W 430.11 W
42 2026/10/09 09:02:08.689 430.53 W 2947 MHz 13801 MHz 56 100 % 430.64 W 430.53 W
43 2026/10/09 09:02:09.690 430.23 W 2947 MHz 13801 MHz 57 99 % 429.70 W 430.23 W
44 2026/10/09 09:02:10.690 429.68 W 2947 MHz 13801 MHz 57 100 % 428.78 W 429.68 W
45 2026/10/09 09:02:11.690 430.77 W 2947 MHz 13801 MHz 57 100 % 431.27 W 430.77 W
46 2026/10/09 09:02:12.691 431.19 W 2947 MHz 13801 MHz 57 100 % 432.40 W 431.19 W
47 2026/10/09 09:02:13.691 432.40 W 2947 MHz 13801 MHz 57 100 % 433.11 W 432.40 W
48 2026/10/09 09:02:14.691 433.90 W 2947 MHz 13801 MHz 58 100 % 434.61 W 433.90 W
49 2026/10/09 09:02:15.692 434.74 W 2947 MHz 13801 MHz 58 99 % 434.73 W 434.74 W
50 2026/10/09 09:02:16.692 435.48 W 2947 MHz 13801 MHz 58 100 % 436.87 W 435.48 W
51 2026/10/09 09:02:17.692 435.06 W 2947 MHz 13801 MHz 58 100 % 433.81 W 435.06 W
52 2026/10/09 09:02:18.693 434.31 W 2947 MHz 13801 MHz 59 100 % 433.72 W 434.31 W
53 2026/10/09 09:02:19.693 434.44 W 2947 MHz 13801 MHz 59 100 % 434.47 W 434.44 W
54 2026/10/09 09:02:20.693 435.24 W 2947 MHz 13801 MHz 59 100 % 435.70 W 435.24 W
55 2026/10/09 09:02:21.694 435.42 W 2947 MHz 13801 MHz 59 100 % 436.35 W 435.42 W
56 2026/10/09 09:02:22.694 436.33 W 2947 MHz 13801 MHz 59 100 % 437.24 W 436.33 W
57 2026/10/09 09:02:23.694 436.99 W 2947 MHz 13801 MHz 60 100 % 435.87 W 436.99 W
58 2026/10/09 09:02:24.695 437.68 W 2947 MHz 13801 MHz 60 100 % 437.16 W 437.68 W
59 2026/10/09 09:02:25.695 437.65 W 2947 MHz 13801 MHz 60 100 % 438.46 W 437.65 W
60 2026/10/09 09:02:26.695 437.80 W 2947 MHz 13801 MHz 60 100 % 437.66 W 437.80 W
61 2026/10/09 09:02:27.695 437.55 W 2947 MHz 13801 MHz 60 100 % 437.80 W 437.55 W
62 2026/10/09 09:02:28.696 438.22 W 2947 MHz 13801 MHz 60 100 % 437.90 W 438.22 W
63 2026/10/09 09:02:29.696 438.59 W 2947 MHz 13801 MHz 61 100 % 438.59 W 438.59 W
64 2026/10/09 09:02:30.696 439.52 W 2947 MHz 13801 MHz 61 100 % 440.12 W 439.52 W
65 2026/10/09 09:02:31.696 440.03 W 2947 MHz 13801 MHz 61 100 % 440.13 W 440.03 W
66 2026/10/09 09:02:32.697 439.63 W 2947 MHz 13801 MHz 61 100 % 439.97 W 439.63 W
67 2026/10/09 09:02:33.697 439.48 W 2947 MHz 13801 MHz 61 100 % 439.56 W 439.48 W
68 2026/10/09 09:02:34.697 411.56 W 2947 MHz 14001 MHz 55 100 % 152.91 W 411.56 W
69 2026/10/09 09:02:35.697 108.99 W 2947 MHz 14001 MHz 53 0 % 103.29 W 108.99 W
70 2026/10/09 09:02:36.697 88.44 W 1755 MHz 14001 MHz 51 0 % 88.44 W 88.44 W
71 2026/10/09 09:02:37.697 37.47 W 390 MHz 810 MHz 50 0 % 37.47 W 37.47 W
72 2026/10/09 09:02:38.698 29.80 W 232 MHz 810 MHz 49 0 % 22.12 W 29.80 W
73 2026/10/09 09:02:39.698 19.93 W 195 MHz 405 MHz 49 0 % 19.93 W 19.93 W
74 2026/10/09 09:02:40.698 19.13 W 195 MHz 405 MHz 49 0 % 18.33 W 19.13 W
75 2026/10/09 09:02:41.698 16.82 W 195 MHz 405 MHz 48 0 % 16.82 W 16.82 W
76 2026/10/09 09:02:42.699 16.63 W 195 MHz 405 MHz 48 0 % 16.44 W 16.63 W
77 2026/10/09 09:02:43.699 16.76 W 195 MHz 405 MHz 48 0 % 17.08 W 16.76 W
78 2026/10/09 09:02:44.699 17.15 W 187 MHz 405 MHz 48 0 % 17.15 W 17.15 W
79 2026/10/09 09:02:45.699 71.34 W 2542 MHz 13801 MHz 49 0 % 78.03 W 71.34 W
80 2026/10/09 09:02:46.699 197.86 W 2910 MHz 13801 MHz 56 1 % 424.42 W 197.86 W
81 2026/10/09 09:02:47.699 425.92 W 2947 MHz 13801 MHz 58 100 % 427.10 W 425.92 W
82 2026/10/09 09:02:48.700 426.55 W 2947 MHz 13801 MHz 59 100 % 426.89 W 426.55 W
83 2026/10/09 09:02:49.700 426.30 W 2947 MHz 13801 MHz 59 100 % 426.08 W 426.30 W
84 2026/10/09 09:02:50.700 426.45 W 2947 MHz 13801 MHz 59 100 % 426.80 W 426.45 W
85 2026/10/09 09:02:51.700 427.80 W 2947 MHz 13801 MHz 60 100 % 428.65 W 427.80 W
86 2026/10/09 09:02:52.700 427.90 W 2947 MHz 13801 MHz 60 100 % 428.29 W 427.90 W
87 2026/10/09 09:02:53.700 428.63 W 2947 MHz 13801 MHz 60 100 % 429.03 W 428.63 W
88 2026/10/09 09:02:54.701 427.99 W 2947 MHz 13801 MHz 60 100 % 426.97 W 427.99 W
89 2026/10/09 09:02:55.701 428.06 W 2947 MHz 13801 MHz 60 100 % 428.84 W 428.06 W
90 2026/10/09 09:02:56.701 428.64 W 2947 MHz 13801 MHz 60 100 % 428.87 W 428.64 W
91 2026/10/09 09:02:57.701 428.15 W 2947 MHz 13801 MHz 61 100 % 428.61 W 428.15 W
92 2026/10/09 09:02:58.701 429.37 W 2947 MHz 13801 MHz 61 100 % 429.43 W 429.37 W
93 2026/10/09 09:02:59.701 429.90 W 2947 MHz 13801 MHz 61 100 % 430.02 W 429.90 W
94 2026/10/09 09:03:00.701 431.14 W 2947 MHz 13801 MHz 61 100 % 431.48 W 431.14 W
95 2026/10/09 09:03:01.702 432.60 W 2947 MHz 13801 MHz 61 100 % 433.12 W 432.60 W
96 2026/10/09 09:03:02.702 432.68 W 2947 MHz 13801 MHz 62 100 % 432.11 W 432.68 W
97 2026/10/09 09:03:03.702 432.10 W 2947 MHz 13801 MHz 62 100 % 432.70 W 432.10 W
98 2026/10/09 09:03:04.702 431.35 W 2947 MHz 13801 MHz 62 100 % 431.08 W 431.35 W
99 2026/10/09 09:03:05.702 431.67 W 2947 MHz 13801 MHz 62 100 % 431.40 W 431.67 W
100 2026/10/09 09:03:06.703 433.02 W 2947 MHz 13801 MHz 62 100 % 434.06 W 433.02 W
101 2026/10/09 09:03:07.703 434.10 W 2947 MHz 13801 MHz 62 100 % 435.50 W 434.10 W
102 2026/10/09 09:03:08.703 433.84 W 2932 MHz 13801 MHz 62 100 % 434.48 W 433.84 W
103 2026/10/09 09:03:09.704 434.64 W 2932 MHz 13801 MHz 62 100 % 434.27 W 434.64 W
104 2026/10/09 09:03:10.704 434.77 W 2932 MHz 13801 MHz 63 100 % 434.36 W 434.77 W
105 2026/10/09 09:03:11.704 435.01 W 2932 MHz 13801 MHz 63 100 % 434.92 W 435.01 W
106 2026/10/09 09:03:12.704 434.61 W 2932 MHz 13801 MHz 63 100 % 435.66 W 434.61 W
107 2026/10/09 09:03:13.704 435.04 W 2932 MHz 13801 MHz 63 100 % 435.07 W 435.04 W
108 2026/10/09 09:03:14.704 435.81 W 2932 MHz 13801 MHz 63 100 % 435.60 W 435.81 W
109 2026/10/09 09:03:15.704 436.39 W 2932 MHz 13801 MHz 63 100 % 436.69 W 436.39 W
110 2026/10/09 09:03:16.705 436.45 W 2932 MHz 13801 MHz 63 100 % 436.79 W 436.45 W
111 2026/10/09 09:03:17.705 436.69 W 2932 MHz 13801 MHz 63 100 % 436.46 W 436.69 W
112 2026/10/09 09:03:18.706 436.60 W 2932 MHz 13801 MHz 64 100 % 436.61 W 436.60 W
113 2026/10/09 09:03:19.706 437.54 W 2932 MHz 13801 MHz 64 100 % 437.27 W 437.54 W
114 2026/10/09 09:03:20.706 437.53 W 2932 MHz 13801 MHz 64 100 % 438.38 W 437.53 W
115 2026/10/09 09:03:21.706 437.81 W 2932 MHz 13801 MHz 64 100 % 438.61 W 437.81 W
116 2026/10/09 09:03:22.707 438.83 W 2932 MHz 13801 MHz 64 100 % 440.00 W 438.83 W
117 2026/10/09 09:03:23.707 440.23 W 2932 MHz 13801 MHz 64 100 % 440.68 W 440.23 W
118 2026/10/09 09:03:24.707 441.27 W 2932 MHz 13801 MHz 64 100 % 440.99 W 441.27 W
119 2026/10/09 09:03:25.707 440.13 W 2932 MHz 13801 MHz 64 100 % 440.25 W 440.13 W
120 2026/10/09 09:03:26.708 439.44 W 2932 MHz 13801 MHz 64 100 % 440.04 W 439.44 W
121 2026/10/09 09:03:27.708 439.30 W 2932 MHz 13801 MHz 64 100 % 439.04 W 439.30 W
122 2026/10/09 09:03:28.708 439.04 W 2932 MHz 13801 MHz 65 100 % 438.36 W 439.04 W
123 2026/10/09 09:03:29.708 439.20 W 2932 MHz 13801 MHz 65 100 % 438.75 W 439.20 W
124 2026/10/09 09:03:30.709 440.70 W 2932 MHz 13801 MHz 65 100 % 441.14 W 440.70 W
125 2026/10/09 09:03:31.709 440.74 W 2932 MHz 13801 MHz 65 100 % 441.57 W 440.74 W
126 2026/10/09 09:03:32.709 440.73 W 2932 MHz 13801 MHz 65 100 % 441.76 W 440.73 W
127 2026/10/09 09:03:33.709 440.42 W 2932 MHz 13801 MHz 65 100 % 439.93 W 440.42 W
128 2026/10/09 09:03:34.710 440.55 W 2932 MHz 13801 MHz 65 100 % 439.20 W 440.55 W
129 2026/10/09 09:03:35.710 440.73 W 2932 MHz 13801 MHz 65 100 % 442.12 W 440.73 W
130 2026/10/09 09:03:36.710 441.36 W 2932 MHz 13801 MHz 65 100 % 441.66 W 441.36 W
131 2026/10/09 09:03:37.710 441.62 W 2932 MHz 13801 MHz 65 100 % 441.86 W 441.62 W
132 2026/10/09 09:03:38.711 441.79 W 2932 MHz 13801 MHz 65 100 % 442.35 W 441.79 W
133 2026/10/09 09:03:39.711 442.76 W 2932 MHz 13801 MHz 65 100 % 441.48 W 442.76 W
134 2026/10/09 09:03:40.711 442.08 W 2932 MHz 13801 MHz 65 100 % 442.65 W 442.08 W
135 2026/10/09 09:03:41.711 442.16 W 2932 MHz 13801 MHz 65 100 % 441.95 W 442.16 W
136 2026/10/09 09:03:42.711 442.17 W 2932 MHz 13801 MHz 66 100 % 442.58 W 442.17 W
137 2026/10/09 09:03:43.711 442.06 W 2932 MHz 13801 MHz 66 99 % 442.33 W 442.06 W
138 2026/10/09 09:03:44.712 442.89 W 2932 MHz 13801 MHz 66 100 % 442.69 W 442.89 W
139 2026/10/09 09:03:45.712 443.41 W 2932 MHz 13801 MHz 66 100 % 444.45 W 443.41 W
140 2026/10/09 09:03:46.712 248.86 W 2947 MHz 14001 MHz 57 1 % 112.39 W 248.86 W
141 2026/10/09 09:03:47.712 128.04 W 2947 MHz 14001 MHz 57 0 % 112.13 W 128.04 W
142 2026/10/09 09:03:48.713 100.50 W 2692 MHz 14001 MHz 55 0 % 100.50 W 100.50 W
143 2026/10/09 09:03:49.713 74.28 W 405 MHz 7001 MHz 54 0 % 48.06 W 74.28 W
144 2026/10/09 09:03:50.713 42.98 W 255 MHz 7001 MHz 53 0 % 42.98 W 42.98 W
145 2026/10/09 09:03:51.713 36.47 W 195 MHz 810 MHz 53 0 % 36.47 W 36.47 W
146 2026/10/09 09:03:52.714 29.16 W 195 MHz 810 MHz 52 0 % 21.85 W 29.16 W
147 2026/10/09 09:03:53.714 20.81 W 195 MHz 405 MHz 52 0 % 19.78 W 20.81 W
148 2026/10/09 09:03:54.714 19.20 W 195 MHz 405 MHz 52 0 % 19.20 W 19.20 W
149 2026/10/09 09:03:55.714 19.17 W 195 MHz 405 MHz 51 0 % 19.15 W 19.17 W
150 2026/10/09 09:03:56.714 36.28 W 2542 MHz 13801 MHz 52 0 % 79.08 W 36.28 W
151 2026/10/09 09:03:57.714 85.00 W 2542 MHz 13801 MHz 52 0 % 78.65 W 85.00 W
152 2026/10/09 09:03:58.715 346.57 W 2947 MHz 13801 MHz 61 99 % 431.39 W 346.57 W
153 2026/10/09 09:03:59.715 432.90 W 2947 MHz 13801 MHz 62 100 % 434.26 W 432.90 W
154 2026/10/09 09:04:00.715 434.59 W 2947 MHz 13801 MHz 62 100 % 435.41 W 434.59 W
155 2026/10/09 09:04:01.715 435.23 W 2932 MHz 13801 MHz 63 100 % 435.64 W 435.23 W
156 2026/10/09 09:04:02.716 435.07 W 2932 MHz 13801 MHz 63 100 % 434.76 W 435.07 W
157 2026/10/09 09:04:03.716 435.19 W 2932 MHz 13801 MHz 63 100 % 435.58 W 435.19 W
158 2026/10/09 09:04:04.716 435.73 W 2932 MHz 13801 MHz 63 100 % 436.82 W 435.73 W
159 2026/10/09 09:04:05.717 436.15 W 2932 MHz 13801 MHz 63 100 % 436.97 W 436.15 W
160 2026/10/09 09:04:06.717 436.35 W 2932 MHz 13801 MHz 63 100 % 435.83 W 436.35 W
161 2026/10/09 09:04:07.717 437.29 W 2932 MHz 13801 MHz 63 100 % 437.58 W 437.29 W
162 2026/10/09 09:04:08.718 438.64 W 2932 MHz 13801 MHz 64 100 % 439.95 W 438.64 W
163 2026/10/09 09:04:09.718 439.21 W 2932 MHz 13801 MHz 64 100 % 438.79 W 439.21 W
164 2026/10/09 09:04:10.718 439.24 W 2932 MHz 13801 MHz 64 100 % 439.49 W 439.24 W
165 2026/10/09 09:04:11.719 438.11 W 2932 MHz 13801 MHz 64 100 % 436.44 W 438.11 W
166 2026/10/09 09:04:12.719 437.51 W 2932 MHz 13801 MHz 64 100 % 435.73 W 437.51 W
167 2026/10/09 09:04:13.719 437.90 W 2932 MHz 13801 MHz 64 100 % 438.29 W 437.90 W
168 2026/10/09 09:04:14.720 438.62 W 2932 MHz 13801 MHz 64 100 % 438.96 W 438.62 W
169 2026/10/09 09:04:15.720 438.81 W 2932 MHz 13801 MHz 64 100 % 439.66 W 438.81 W
170 2026/10/09 09:04:16.721 439.65 W 2932 MHz 13801 MHz 64 100 % 439.38 W 439.65 W
171 2026/10/09 09:04:17.721 439.88 W 2932 MHz 13801 MHz 65 100 % 439.17 W 439.88 W
172 2026/10/09 09:04:18.721 440.35 W 2932 MHz 13801 MHz 65 100 % 441.16 W 440.35 W
173 2026/10/09 09:04:19.722 440.00 W 2932 MHz 13801 MHz 65 100 % 440.44 W 440.00 W
174 2026/10/09 09:04:20.722 440.22 W 2932 MHz 13801 MHz 65 100 % 441.16 W 440.22 W
175 2026/10/09 09:04:21.722 439.82 W 2932 MHz 13801 MHz 65 100 % 439.25 W 439.82 W
176 2026/10/09 09:04:22.722 439.92 W 2932 MHz 13801 MHz 65 100 % 440.55 W 439.92 W
177 2026/10/09 09:04:23.723 441.10 W 2932 MHz 13801 MHz 65 100 % 442.03 W 441.10 W
178 2026/10/09 09:04:24.723 441.54 W 2932 MHz 13801 MHz 65 100 % 440.96 W 441.54 W
179 2026/10/09 09:04:25.723 440.24 W 2932 MHz 13801 MHz 65 100 % 440.31 W 440.24 W
180 2026/10/09 09:04:26.723 440.48 W 2932 MHz 13801 MHz 65 100 % 439.70 W 440.48 W
181 2026/10/09 09:04:27.724 440.18 W 2932 MHz 13801 MHz 65 100 % 440.46 W 440.18 W
182 2026/10/09 09:04:28.724 441.03 W 2932 MHz 13801 MHz 66 100 % 441.43 W 441.03 W
183 2026/10/09 09:04:29.724 441.70 W 2932 MHz 13801 MHz 66 100 % 442.57 W 441.70 W
184 2026/10/09 09:04:30.724 442.33 W 2932 MHz 13801 MHz 66 100 % 442.67 W 442.33 W
185 2026/10/09 09:04:31.724 444.16 W 2932 MHz 13801 MHz 66 100 % 444.76 W 444.16 W
186 2026/10/09 09:04:32.725 444.77 W 2932 MHz 13801 MHz 66 100 % 444.96 W 444.77 W
187 2026/10/09 09:04:33.725 444.47 W 2932 MHz 13801 MHz 66 100 % 444.12 W 444.47 W
188 2026/10/09 09:04:34.725 443.55 W 2932 MHz 13801 MHz 66 100 % 443.62 W 443.55 W
189 2026/10/09 09:04:35.725 442.52 W 2932 MHz 13801 MHz 66 100 % 441.96 W 442.52 W
190 2026/10/09 09:04:36.725 443.06 W 2932 MHz 13801 MHz 66 100 % 443.63 W 443.06 W
191 2026/10/09 09:04:37.726 443.66 W 2932 MHz 13801 MHz 66 100 % 443.47 W 443.66 W
192 2026/10/09 09:04:38.726 443.55 W 2932 MHz 13801 MHz 66 100 % 443.82 W 443.55 W
193 2026/10/09 09:04:39.726 444.03 W 2932 MHz 13801 MHz 66 100 % 444.59 W 444.03 W
194 2026/10/09 09:04:40.726 444.41 W 2932 MHz 13801 MHz 66 100 % 445.14 W 444.41 W
195 2026/10/09 09:04:41.726 445.37 W 2932 MHz 13801 MHz 66 100 % 444.23 W 445.37 W
196 2026/10/09 09:04:42.727 444.19 W 2932 MHz 13801 MHz 66 100 % 444.48 W 444.19 W
197 2026/10/09 09:04:43.727 444.21 W 2932 MHz 13801 MHz 66 100 % 444.03 W 444.21 W
198 2026/10/09 09:04:44.727 443.67 W 2932 MHz 13801 MHz 66 100 % 444.24 W 443.67 W
199 2026/10/09 09:04:45.727 444.33 W 2932 MHz 13801 MHz 67 100 % 444.31 W 444.33 W
200 2026/10/09 09:04:46.728 444.77 W 2932 MHz 13801 MHz 67 100 % 444.70 W 444.77 W
201 2026/10/09 09:04:47.728 445.26 W 2932 MHz 13801 MHz 67 100 % 445.76 W 445.26 W
202 2026/10/09 09:04:48.728 444.68 W 2932 MHz 13801 MHz 67 100 % 444.81 W 444.68 W
203 2026/10/09 09:04:49.729 444.23 W 2932 MHz 13801 MHz 67 100 % 444.21 W 444.23 W
204 2026/10/09 09:04:50.729 443.96 W 2932 MHz 13801 MHz 67 100 % 442.83 W 443.96 W
205 2026/10/09 09:04:51.729 444.74 W 2932 MHz 13801 MHz 67 100 % 444.30 W 444.74 W
206 2026/10/09 09:04:52.729 444.76 W 2932 MHz 13801 MHz 66 100 % 445.50 W 444.76 W
207 2026/10/09 09:04:53.730 445.07 W 2932 MHz 13801 MHz 66 100 % 445.31 W 445.07 W
208 2026/10/09 09:04:54.730 445.47 W 2932 MHz 13801 MHz 66 100 % 445.43 W 445.47 W
209 2026/10/09 09:04:55.730 445.65 W 2932 MHz 13801 MHz 66 100 % 445.60 W 445.65 W
210 2026/10/09 09:04:56.730 445.65 W 2932 MHz 13801 MHz 66 100 % 444.71 W 445.65 W
211 2026/10/09 09:04:57.731 407.83 W 2932 MHz 14001 MHz 61 100 % 126.93 W 407.83 W
212 2026/10/09 09:04:58.731 135.89 W 2947 MHz 14001 MHz 58 0 % 111.01 W 135.89 W
213 2026/10/09 09:04:59.731 101.01 W 2745 MHz 14001 MHz 56 0 % 100.01 W 101.01 W
214 2026/10/09 09:05:00.731 48.27 W 577 MHz 7001 MHz 55 0 % 48.27 W 48.27 W
215 2026/10/09 09:05:01.731 46.96 W 360 MHz 7001 MHz 54 0 % 45.66 W 46.96 W
216 2026/10/09 09:05:02.731 44.03 W 225 MHz 7001 MHz 54 0 % 44.03 W 44.03 W
217 2026/10/09 09:05:03.732 39.56 W 195 MHz 810 MHz 53 0 % 39.56 W 39.56 W
218 2026/10/09 09:05:04.732 30.85 W 195 MHz 810 MHz 53 0 % 22.13 W 30.85 W
219 2026/10/09 09:05:05.732 20.23 W 195 MHz 405 MHz 53 0 % 20.23 W 20.23 W
220 2026/10/09 09:05:06.732 19.24 W 195 MHz 405 MHz 52 0 % 19.24 W 19.24 W
221 2026/10/09 09:05:07.733 19.22 W 195 MHz 405 MHz 52 0 % 19.22 W 19.22 W
222 2026/10/09 09:05:08.733 70.79 W 2542 MHz 13801 MHz 53 0 % 79.96 W 70.79 W
223 2026/10/09 09:05:09.733 187.80 W 2947 MHz 13801 MHz 61 0 % 225.31 W 187.80 W
224 2026/10/09 09:05:10.733 424.00 W 2932 MHz 13801 MHz 63 100 % 443.93 W 424.00 W
225 2026/10/09 09:05:11.733 444.52 W 2932 MHz 13801 MHz 63 100 % 445.36 W 444.52 W
226 2026/10/09 09:05:12.733 444.56 W 2932 MHz 13801 MHz 64 100 % 444.52 W 444.56 W
227 2026/10/09 09:05:13.733 445.58 W 2932 MHz 13801 MHz 64 100 % 446.67 W 445.58 W
228 2026/10/09 09:05:14.734 445.89 W 2932 MHz 13801 MHz 64 100 % 446.51 W 445.89 W
229 2026/10/09 09:05:15.734 447.35 W 2932 MHz 13801 MHz 64 100 % 448.36 W 447.35 W
230 2026/10/09 09:05:16.734 448.85 W 2932 MHz 13801 MHz 64 100 % 449.63 W 448.85 W
231 2026/10/09 09:05:17.734 449.25 W 2932 MHz 13801 MHz 64 100 % 450.79 W 449.25 W
232 2026/10/09 09:05:18.735 450.21 W 2932 MHz 13801 MHz 65 100 % 449.07 W 450.21 W
233 2026/10/09 09:05:19.735 448.98 W 2932 MHz 13801 MHz 65 99 % 447.33 W 448.98 W
234 2026/10/09 09:05:20.735 448.60 W 2932 MHz 13801 MHz 65 100 % 448.61 W 448.60 W
235 2026/10/09 09:05:21.735 448.05 W 2932 MHz 13801 MHz 65 100 % 449.49 W 448.05 W
236 2026/10/09 09:05:22.736 448.65 W 2932 MHz 13801 MHz 65 100 % 449.45 W 448.65 W
237 2026/10/09 09:05:23.736 449.11 W 2932 MHz 13801 MHz 65 100 % 449.60 W 449.11 W
238 2026/10/09 09:05:24.736 449.49 W 2932 MHz 13801 MHz 65 100 % 449.17 W 449.49 W
239 2026/10/09 09:05:25.736 450.10 W 2932 MHz 13801 MHz 65 100 % 450.30 W 450.10 W
240 2026/10/09 09:05:26.736 450.90 W 2932 MHz 13801 MHz 66 100 % 451.51 W 450.90 W
241 2026/10/09 09:05:27.737 450.71 W 2932 MHz 13801 MHz 66 100 % 450.72 W 450.71 W
242 2026/10/09 09:05:28.737 449.71 W 2932 MHz 13801 MHz 66 100 % 448.14 W 449.71 W
243 2026/10/09 09:05:29.737 449.14 W 2932 MHz 13801 MHz 66 100 % 447.00 W 449.14 W
244 2026/10/09 09:05:30.737 449.72 W 2932 MHz 13801 MHz 66 100 % 450.51 W 449.72 W
245 2026/10/09 09:05:31.738 450.17 W 2932 MHz 13801 MHz 66 100 % 450.90 W 450.17 W
246 2026/10/09 09:05:32.738 450.68 W 2932 MHz 13801 MHz 66 100 % 451.11 W 450.68 W
247 2026/10/09 09:05:33.738 451.02 W 2932 MHz 13801 MHz 66 100 % 451.49 W 451.02 W
248 2026/10/09 09:05:34.739 451.51 W 2932 MHz 13801 MHz 66 100 % 450.74 W 451.51 W
249 2026/10/09 09:05:35.739 451.37 W 2932 MHz 13801 MHz 66 100 % 451.85 W 451.37 W
250 2026/10/09 09:05:36.739 451.36 W 2932 MHz 13801 MHz 66 100 % 452.48 W 451.36 W
251 2026/10/09 09:05:37.739 451.91 W 2932 MHz 13801 MHz 66 100 % 452.29 W 451.91 W
252 2026/10/09 09:05:38.740 452.93 W 2932 MHz 13801 MHz 66 100 % 452.40 W 452.93 W
253 2026/10/09 09:05:39.740 453.42 W 2932 MHz 13801 MHz 66 100 % 453.95 W 453.42 W
254 2026/10/09 09:05:40.740 454.61 W 2932 MHz 13801 MHz 66 100 % 455.51 W 454.61 W
255 2026/10/09 09:05:41.740 454.51 W 2932 MHz 13801 MHz 66 100 % 454.29 W 454.51 W
256 2026/10/09 09:05:42.741 453.07 W 2932 MHz 13801 MHz 66 100 % 451.37 W 453.07 W
257 2026/10/09 09:05:43.741 452.22 W 2932 MHz 13801 MHz 66 100 % 451.75 W 452.22 W
258 2026/10/09 09:05:44.741 452.73 W 2932 MHz 13801 MHz 66 100 % 452.96 W 452.73 W
259 2026/10/09 09:05:45.741 452.39 W 2932 MHz 13801 MHz 66 100 % 453.17 W 452.39 W
260 2026/10/09 09:05:46.742 453.17 W 2932 MHz 13801 MHz 66 100 % 454.08 W 453.17 W
261 2026/10/09 09:05:47.742 453.36 W 2932 MHz 13801 MHz 67 100 % 452.93 W 453.36 W
262 2026/10/09 09:05:48.742 454.05 W 2932 MHz 13801 MHz 67 100 % 453.07 W 454.05 W
263 2026/10/09 09:05:49.742 453.63 W 2932 MHz 13801 MHz 67 100 % 454.58 W 453.63 W
264 2026/10/09 09:05:50.742 454.02 W 2932 MHz 13801 MHz 67 100 % 454.61 W 454.02 W
265 2026/10/09 09:05:51.742 453.04 W 2932 MHz 13801 MHz 67 100 % 452.60 W 453.04 W
266 2026/10/09 09:05:52.743 453.03 W 2932 MHz 13801 MHz 67 100 % 452.70 W 453.03 W
267 2026/10/09 09:05:53.743 453.21 W 2932 MHz 13801 MHz 67 100 % 453.71 W 453.21 W
268 2026/10/09 09:05:54.743 454.05 W 2932 MHz 13801 MHz 67 100 % 454.48 W 454.05 W
269 2026/10/09 09:05:55.743 453.72 W 2932 MHz 13801 MHz 67 100 % 453.76 W 453.72 W
270 2026/10/09 09:05:56.744 453.12 W 2932 MHz 13801 MHz 67 100 % 450.73 W 453.12 W
271 2026/10/09 09:05:57.744 452.35 W 2932 MHz 13801 MHz 67 100 % 452.10 W 452.35 W
272 2026/10/09 09:05:58.744 452.67 W 2932 MHz 13801 MHz 67 100 % 453.05 W 452.67 W
273 2026/10/09 09:05:59.745 452.78 W 2932 MHz 13801 MHz 67 100 % 453.27 W 452.78 W
274 2026/10/09 09:06:00.745 453.24 W 2932 MHz 13801 MHz 67 100 % 453.40 W 453.24 W
275 2026/10/09 09:06:01.745 453.58 W 2932 MHz 13801 MHz 67 100 % 453.06 W 453.58 W
276 2026/10/09 09:06:02.745 455.11 W 2932 MHz 13801 MHz 67 100 % 454.90 W 455.11 W
277 2026/10/09 09:06:03.746 455.46 W 2932 MHz 13801 MHz 67 100 % 455.09 W 455.46 W
278 2026/10/09 09:06:04.746 455.17 W 2932 MHz 13801 MHz 67 100 % 454.62 W 455.17 W
279 2026/10/09 09:06:05.746 454.29 W 2932 MHz 13801 MHz 67 100 % 455.05 W 454.29 W
280 2026/10/09 09:06:06.746 453.70 W 2932 MHz 13801 MHz 67 100 % 453.21 W 453.70 W
281 2026/10/09 09:06:07.747 454.08 W 2932 MHz 13801 MHz 67 100 % 453.85 W 454.08 W
282 2026/10/09 09:06:08.747 454.34 W 2932 MHz 13801 MHz 67 100 % 455.47 W 454.34 W
283 2026/10/09 09:06:09.748 250.89 W 2947 MHz 14001 MHz 59 0 % 114.06 W 250.89 W
284 2026/10/09 09:06:10.748 126.39 W 2947 MHz 14001 MHz 59 0 % 112.33 W 126.39 W
285 2026/10/09 09:06:11.748 101.37 W 2685 MHz 7001 MHz 57 0 % 101.37 W 101.37 W
286 2026/10/09 09:06:12.749 74.34 W 405 MHz 7001 MHz 55 0 % 47.31 W 74.34 W
287 2026/10/09 09:06:13.749 46.21 W 255 MHz 7001 MHz 55 0 % 45.11 W 46.21 W
288 2026/10/09 09:06:14.749 44.51 W 195 MHz 7001 MHz 55 0 % 43.92 W 44.51 W
289 2026/10/09 09:06:15.749 43.05 W 195 MHz 7001 MHz 54 0 % 43.05 W 43.05 W
290 2026/10/09 09:06:16.750 27.97 W 195 MHz 810 MHz 54 0 % 27.97 W 27.97 W
291 2026/10/09 09:06:17.750 25.76 W 187 MHz 405 MHz 53 0 % 23.55 W 25.76 W
292 2026/10/09 09:06:18.750 22.12 W 195 MHz 405 MHz 53 0 % 20.69 W 22.12 W
293 2026/10/09 09:06:19.750 37.07 W 2542 MHz 13801 MHz 54 0 % 79.31 W 37.07 W
294 2026/10/09 09:06:20.751 101.04 W 2542 MHz 13801 MHz 54 0 % 79.43 W 101.04 W
295 2026/10/09 09:06:21.751 333.36 W 2932 MHz 13801 MHz 63 32 % 439.39 W 333.36 W
296 2026/10/09 09:06:22.751 441.35 W 2932 MHz 13801 MHz 64 100 % 441.81 W 441.35 W
297 2026/10/09 09:06:23.751 442.73 W 2932 MHz 13801 MHz 64 100 % 442.85 W 442.73 W
298 2026/10/09 09:06:24.751 443.79 W 2932 MHz 13801 MHz 64 100 % 444.89 W 443.79 W
299 2026/10/09 09:06:25.752 445.42 W 2932 MHz 13801 MHz 64 100 % 445.86 W 445.42 W
300 2026/10/09 09:06:26.752 445.26 W 2932 MHz 13801 MHz 64 100 % 445.82 W 445.26 W
301 2026/10/09 09:06:27.752 445.02 W 2932 MHz 13801 MHz 65 100 % 445.17 W 445.02 W
302 2026/10/09 09:06:28.752 443.83 W 2932 MHz 13801 MHz 65 100 % 443.74 W 443.83 W
303 2026/10/09 09:06:29.752 443.72 W 2932 MHz 13801 MHz 65 100 % 444.03 W 443.72 W
304 2026/10/09 09:06:30.752 444.38 W 2932 MHz 13801 MHz 65 100 % 444.92 W 444.38 W
305 2026/10/09 09:06:31.753 444.55 W 2932 MHz 13801 MHz 65 100 % 443.57 W 444.55 W
306 2026/10/09 09:06:32.753 445.36 W 2932 MHz 13801 MHz 65 100 % 444.74 W 445.36 W
307 2026/10/09 09:06:33.753 446.36 W 2932 MHz 13801 MHz 65 100 % 446.05 W 446.36 W
308 2026/10/09 09:06:34.753 446.18 W 2932 MHz 13801 MHz 65 100 % 445.78 W 446.18 W
309 2026/10/09 09:06:35.753 446.64 W 2932 MHz 13801 MHz 66 100 % 446.73 W 446.64 W
310 2026/10/09 09:06:36.753 445.65 W 2932 MHz 13801 MHz 66 100 % 446.60 W 445.65 W
311 2026/10/09 09:06:37.754 446.00 W 2932 MHz 13801 MHz 66 100 % 445.44 W 446.00 W
312 2026/10/09 09:06:38.754 445.88 W 2932 MHz 13801 MHz 66 100 % 446.62 W 445.88 W
313 2026/10/09 09:06:39.754 446.59 W 2932 MHz 13801 MHz 66 100 % 447.76 W 446.59 W
314 2026/10/09 09:06:40.754 447.72 W 2932 MHz 13801 MHz 66 100 % 448.13 W 447.72 W
315 2026/10/09 09:06:41.754 446.92 W 2932 MHz 13801 MHz 66 100 % 446.58 W 446.92 W
316 2026/10/09 09:06:42.754 446.34 W 2932 MHz 13801 MHz 66 100 % 445.33 W 446.34 W
317 2026/10/09 09:06:43.754 446.13 W 2932 MHz 13801 MHz 66 100 % 445.84 W 446.13 W
318 2026/10/09 09:06:44.755 446.66 W 2932 MHz 13801 MHz 66 100 % 446.55 W 446.66 W
319 2026/10/09 09:06:45.755 446.88 W 2932 MHz 13801 MHz 66 99 % 445.79 W 446.88 W
320 2026/10/09 09:06:46.755 448.03 W 2932 MHz 13801 MHz 66 100 % 449.29 W 448.03 W
321 2026/10/09 09:06:47.755 448.52 W 2932 MHz 13801 MHz 67 100 % 448.61 W 448.52 W
322 2026/10/09 09:06:48.755 449.47 W 2932 MHz 13801 MHz 67 100 % 450.53 W 449.47 W
323 2026/10/09 09:06:49.755 449.48 W 2932 MHz 13801 MHz 67 100 % 450.53 W 449.48 W
324 2026/10/09 09:06:50.755 449.19 W 2932 MHz 13801 MHz 66 100 % 449.24 W 449.19 W
325 2026/10/09 09:06:51.756 447.02 W 2932 MHz 13801 MHz 66 100 % 446.76 W 447.02 W
326 2026/10/09 09:06:52.756 446.52 W 2932 MHz 13801 MHz 66 100 % 447.83 W 446.52 W
327 2026/10/09 09:06:53.756 447.26 W 2932 MHz 13801 MHz 66 100 % 447.48 W 447.26 W
328 2026/10/09 09:06:54.756 447.77 W 2932 MHz 13801 MHz 66 100 % 447.68 W 447.77 W
329 2026/10/09 09:06:55.756 447.94 W 2932 MHz 13801 MHz 66 100 % 448.02 W 447.94 W
330 2026/10/09 09:06:56.756 448.75 W 2932 MHz 13801 MHz 66 100 % 448.10 W 448.75 W
331 2026/10/09 09:06:57.756 448.63 W 2932 MHz 13801 MHz 67 100 % 448.81 W 448.63 W
332 2026/10/09 09:06:58.757 448.58 W 2932 MHz 13801 MHz 67 100 % 447.72 W 448.58 W
333 2026/10/09 09:06:59.757 448.04 W 2932 MHz 13801 MHz 67 100 % 448.42 W 448.04 W
334 2026/10/09 09:07:00.757 447.55 W 2932 MHz 13801 MHz 67 100 % 448.52 W 447.55 W
335 2026/10/09 09:07:01.757 448.64 W 2932 MHz 13801 MHz 67 100 % 449.75 W 448.64 W
336 2026/10/09 09:07:02.757 449.50 W 2932 MHz 13801 MHz 67 100 % 450.06 W 449.50 W
337 2026/10/09 09:07:03.757 449.29 W 2932 MHz 13801 MHz 67 100 % 449.81 W 449.29 W
338 2026/10/09 09:07:04.758 448.92 W 2932 MHz 13801 MHz 67 100 % 446.71 W 448.92 W
339 2026/10/09 09:07:05.758 447.75 W 2932 MHz 13801 MHz 67 100 % 447.00 W 447.75 W
340 2026/10/09 09:07:06.758 448.28 W 2932 MHz 13801 MHz 67 100 % 447.73 W 448.28 W
341 2026/10/09 09:07:07.758 449.08 W 2932 MHz 13801 MHz 67 100 % 448.80 W 449.08 W
342 2026/10/09 09:07:08.758 449.29 W 2932 MHz 13801 MHz 67 100 % 450.00 W 449.29 W
343 2026/10/09 09:07:09.758 450.17 W 2932 MHz 13801 MHz 67 100 % 451.30 W 450.17 W
344 2026/10/09 09:07:10.759 450.92 W 2932 MHz 13801 MHz 67 100 % 451.67 W 450.92 W
345 2026/10/09 09:07:11.759 451.85 W 2932 MHz 13801 MHz 67 100 % 452.10 W 451.85 W
346 2026/10/09 09:07:12.759 450.48 W 2932 MHz 13801 MHz 67 100 % 450.91 W 450.48 W
347 2026/10/09 09:07:13.759 450.17 W 2932 MHz 13801 MHz 67 100 % 449.55 W 450.17 W
348 2026/10/09 09:07:14.759 449.25 W 2932 MHz 13801 MHz 67 100 % 449.96 W 449.25 W
349 2026/10/09 09:07:15.759 449.28 W 2932 MHz 13801 MHz 67 100 % 448.95 W 449.28 W
350 2026/10/09 09:07:16.760 449.70 W 2932 MHz 13801 MHz 67 100 % 448.92 W 449.70 W
351 2026/10/09 09:07:17.760 449.75 W 2932 MHz 13801 MHz 67 100 % 449.74 W 449.75 W
352 2026/10/09 09:07:18.760 450.21 W 2932 MHz 13801 MHz 67 100 % 449.63 W 450.21 W
353 2026/10/09 09:07:19.760 450.11 W 2932 MHz 13801 MHz 67 100 % 451.19 W 450.11 W
354 2026/10/09 09:07:20.760 450.69 W 2932 MHz 13801 MHz 67 100 % 451.33 W 450.69 W
355 2026/10/09 09:07:21.760 449.99 W 2932 MHz 13801 MHz 67 100 % 450.08 W 449.99 W
356 2026/10/09 09:07:22.761 323.10 W 2947 MHz 14001 MHz 59 100 % 113.71 W 323.10 W
357 2026/10/09 09:07:23.761 115.13 W 2947 MHz 14001 MHz 59 0 % 112.80 W 115.13 W
358 2026/10/09 09:07:24.761 102.47 W 2220 MHz 7001 MHz 57 0 % 101.44 W 102.47 W
359 2026/10/09 09:07:25.761 74.74 W 397 MHz 7001 MHz 56 0 % 48.04 W 74.74 W
360 2026/10/09 09:07:26.761 45.66 W 255 MHz 7001 MHz 55 0 % 45.66 W 45.66 W
361 2026/10/09 09:07:27.761 44.83 W 195 MHz 7001 MHz 55 0 % 44.00 W 44.83 W
362 2026/10/09 09:07:28.761 43.18 W 195 MHz 7001 MHz 54 0 % 43.18 W 43.18 W
363 2026/10/09 09:07:29.762 28.26 W 195 MHz 810 MHz 54 0 % 28.26 W 28.26 W
364 2026/10/09 09:07:30.762 25.25 W 195 MHz 405 MHz 53 0 % 22.23 W 25.25 W
365 2026/10/09 09:07:31.762 19.63 W 195 MHz 405 MHz 53 0 % 19.63 W 19.63 W
366 2026/10/09 09:07:32.762 32.82 W 1515 MHz 13801 MHz 54 0 % 80.99 W 32.82 W
367 2026/10/09 09:07:33.762 105.47 W 2625 MHz 13801 MHz 55 0 % 84.16 W 105.47 W
368 2026/10/09 09:07:34.762 287.73 W 2947 MHz 13801 MHz 63 100 % 431.89 W 287.73 W
369 2026/10/09 09:07:35.762 431.51 W 2932 MHz 13801 MHz 64 100 % 432.27 W 431.51 W
370 2026/10/09 09:07:36.763 431.86 W 2932 MHz 13801 MHz 64 100 % 432.15 W 431.86 W
371 2026/10/09 09:07:37.763 432.58 W 2932 MHz 13801 MHz 64 100 % 433.37 W 432.58 W
372 2026/10/09 09:07:38.763 433.05 W 2932 MHz 13801 MHz 64 100 % 434.55 W 433.05 W
373 2026/10/09 09:07:39.763 434.25 W 2932 MHz 13801 MHz 64 100 % 434.44 W 434.25 W
374 2026/10/09 09:07:40.763 434.67 W 2932 MHz 13801 MHz 65 100 % 435.12 W 434.67 W
375 2026/10/09 09:07:41.763 435.87 W 2932 MHz 13801 MHz 65 100 % 435.69 W 435.87 W
376 2026/10/09 09:07:42.764 435.36 W 2932 MHz 13801 MHz 65 100 % 434.92 W 435.36 W
377 2026/10/09 09:07:43.764 435.63 W 2932 MHz 13801 MHz 65 100 % 435.97 W 435.63 W
378 2026/10/09 09:07:44.764 434.61 W 2932 MHz 13801 MHz 65 100 % 434.88 W 434.61 W
379 2026/10/09 09:07:45.764 435.49 W 2932 MHz 13801 MHz 65 100 % 436.06 W 435.49 W
380 2026/10/09 09:07:46.764 436.51 W 2932 MHz 13801 MHz 65 100 % 436.49 W 436.51 W
381 2026/10/09 09:07:47.764 437.37 W 2932 MHz 13801 MHz 65 100 % 438.77 W 437.37 W
382 2026/10/09 09:07:48.765 438.38 W 2932 MHz 13801 MHz 65 100 % 438.38 W 438.38 W
383 2026/10/09 09:07:49.765 437.87 W 2932 MHz 13801 MHz 65 100 % 437.96 W 437.87 W
384 2026/10/09 09:07:50.765 437.02 W 2932 MHz 13801 MHz 66 100 % 436.71 W 437.02 W
385 2026/10/09 09:07:51.765 436.85 W 2932 MHz 13801 MHz 66 100 % 436.90 W 436.85 W
386 2026/10/09 09:07:52.765 437.46 W 2932 MHz 13801 MHz 66 100 % 437.63 W 437.46 W
387 2026/10/09 09:07:53.765 438.19 W 2932 MHz 13801 MHz 66 100 % 438.63 W 438.19 W
388 2026/10/09 09:07:54.766 439.15 W 2932 MHz 13801 MHz 66 100 % 439.61 W 439.15 W
389 2026/10/09 09:07:55.766 440.03 W 2932 MHz 13801 MHz 66 100 % 440.82 W 440.03 W
390 2026/10/09 09:07:56.766 441.52 W 2932 MHz 13801 MHz 66 100 % 442.04 W 441.52 W
391 2026/10/09 09:07:57.766 441.48 W 2932 MHz 13801 MHz 66 100 % 441.93 W 441.48 W
392 2026/10/09 09:07:58.766 440.32 W 2932 MHz 13801 MHz 66 100 % 439.81 W 440.32 W
393 2026/10/09 09:07:59.767 439.43 W 2932 MHz 13801 MHz 66 100 % 438.90 W 439.43 W
394 2026/10/09 09:08:00.767 438.83 W 2932 MHz 13801 MHz 66 100 % 438.74 W 438.83 W
395 2026/10/09 09:08:01.767 439.38 W 2932 MHz 13801 MHz 66 100 % 439.54 W 439.38 W
396 2026/10/09 09:08:02.767 440.17 W 2932 MHz 13801 MHz 66 100 % 440.20 W 440.17 W
397 2026/10/09 09:08:03.767 440.83 W 2932 MHz 13801 MHz 66 100 % 440.91 W 440.83 W
398 2026/10/09 09:08:04.767 441.73 W 2932 MHz 13801 MHz 67 100 % 441.23 W 441.73 W
399 2026/10/09 09:08:05.768 441.68 W 2932 MHz 13801 MHz 67 100 % 441.91 W 441.68 W
400 2026/10/09 09:08:06.768 441.48 W 2932 MHz 13801 MHz 67 100 % 441.50 W 441.48 W
401 2026/10/09 09:08:07.768 440.98 W 2932 MHz 13801 MHz 67 100 % 441.54 W 440.98 W
402 2026/10/09 09:08:08.768 440.52 W 2932 MHz 13801 MHz 67 100 % 440.72 W 440.52 W
403 2026/10/09 09:08:09.769 441.14 W 2932 MHz 13801 MHz 67 100 % 441.49 W 441.14 W
404 2026/10/09 09:08:10.769 441.60 W 2932 MHz 13801 MHz 67 99 % 442.66 W 441.60 W
405 2026/10/09 09:08:11.769 442.40 W 2932 MHz 13801 MHz 67 100 % 442.17 W 442.40 W
406 2026/10/09 09:08:12.769 441.72 W 2932 MHz 13801 MHz 67 100 % 442.78 W 441.72 W
407 2026/10/09 09:08:13.770 441.54 W 2932 MHz 13801 MHz 67 100 % 440.22 W 441.54 W
408 2026/10/09 09:08:14.770 440.85 W 2932 MHz 13801 MHz 67 100 % 439.33 W 440.85 W
409 2026/10/09 09:08:15.770 441.36 W 2932 MHz 13801 MHz 67 100 % 441.17 W 441.36 W
410 2026/10/09 09:08:16.770 441.62 W 2932 MHz 13801 MHz 67 100 % 441.70 W 441.62 W
411 2026/10/09 09:08:17.770 442.71 W 2932 MHz 13801 MHz 67 100 % 442.85 W 442.71 W
412 2026/10/09 09:08:18.771 443.26 W 2932 MHz 13801 MHz 67 100 % 443.75 W 443.26 W
413 2026/10/09 09:08:19.771 443.99 W 2932 MHz 13801 MHz 67 100 % 445.31 W 443.99 W
414 2026/10/09 09:08:20.771 443.76 W 2932 MHz 13801 MHz 67 100 % 442.97 W 443.76 W
415 2026/10/09 09:08:21.771 442.63 W 2932 MHz 13801 MHz 67 100 % 442.74 W 442.63 W
416 2026/10/09 09:08:22.771 442.41 W 2932 MHz 13801 MHz 67 100 % 442.61 W 442.41 W
417 2026/10/09 09:08:23.771 442.21 W 2932 MHz 13801 MHz 67 100 % 442.63 W 442.21 W
418 2026/10/09 09:08:24.772 442.44 W 2932 MHz 13801 MHz 67 100 % 442.43 W 442.44 W
419 2026/10/09 09:08:25.772 442.92 W 2932 MHz 13801 MHz 67 100 % 440.86 W 442.92 W
420 2026/10/09 09:08:26.772 442.86 W 2932 MHz 13801 MHz 67 100 % 442.61 W 442.86 W
421 2026/10/09 09:08:27.772 443.39 W 2932 MHz 13801 MHz 67 100 % 443.76 W 443.39 W
422 2026/10/09 09:08:28.773 443.30 W 2932 MHz 13801 MHz 67 100 % 442.92 W 443.30 W
423 2026/10/09 09:08:29.773 442.78 W 2932 MHz 13801 MHz 67 100 % 443.20 W 442.78 W
424 2026/10/09 09:08:30.773 442.11 W 2932 MHz 13801 MHz 68 100 % 442.84 W 442.11 W
425 2026/10/09 09:08:31.773 442.68 W 2932 MHz 13801 MHz 68 100 % 443.26 W 442.68 W
426 2026/10/09 09:08:32.773 442.80 W 2932 MHz 13801 MHz 68 100 % 443.06 W 442.80 W
427 2026/10/09 09:08:33.774 443.60 W 2932 MHz 13801 MHz 68 100 % 444.65 W 443.60 W
428 2026/10/09 09:08:34.774 444.33 W 2932 MHz 13801 MHz 68 100 % 444.97 W 444.33 W
429 2026/10/09 09:08:35.774 373.14 W 2932 MHz 14001 MHz 61 100 % 116.07 W 373.14 W
430 2026/10/09 09:08:36.774 132.74 W 2947 MHz 14001 MHz 59 0 % 112.61 W 132.74 W
431 2026/10/09 09:08:37.775 102.82 W 2745 MHz 7001 MHz 57 0 % 101.84 W 102.82 W
432 2026/10/09 09:08:38.775 48.40 W 555 MHz 7001 MHz 56 0 % 48.40 W 48.40 W
433 2026/10/09 09:08:39.775 45.83 W 345 MHz 7001 MHz 55 0 % 45.83 W 45.83 W
434 2026/10/09 09:08:40.776 45.34 W 217 MHz 7001 MHz 55 0 % 44.84 W 45.34 W
435 2026/10/09 09:08:41.776 45.24 W 195 MHz 7001 MHz 54 0 % 45.24 W 45.24 W
436 2026/10/09 09:08:42.776 41.72 W 195 MHz 810 MHz 54 0 % 41.72 W 41.72 W
437 2026/10/09 09:08:43.776 33.31 W 195 MHz 810 MHz 53 0 % 24.91 W 33.31 W
438 2026/10/09 09:08:44.776 20.40 W 195 MHz 405 MHz 53 0 % 20.40 W 20.40 W
439 2026/10/09 09:08:45.777 20.96 W 195 MHz 405 MHz 53 0 % 32.44 W 20.96 W
440 2026/10/09 09:08:46.777 80.04 W 2542 MHz 13801 MHz 54 0 % 79.39 W 80.04 W
441 2026/10/09 09:08:47.777 240.92 W 2947 MHz 13801 MHz 61 6 % 428.72 W 240.92 W
442 2026/10/09 09:08:48.777 430.50 W 2932 MHz 13801 MHz 63 100 % 431.64 W 430.50 W
443 2026/10/09 09:08:49.777 432.03 W 2932 MHz 13801 MHz 64 100 % 432.63 W 432.03 W
444 2026/10/09 09:08:50.778 432.95 W 2932 MHz 13801 MHz 64 100 % 434.01 W 432.95 W
445 2026/10/09 09:08:51.778 433.56 W 2932 MHz 13801 MHz 64 100 % 433.70 W 433.56 W
446 2026/10/09 09:08:52.778 433.02 W 2932 MHz 13801 MHz 64 100 % 432.11 W 433.02 W
447 2026/10/09 09:08:53.778 433.28 W 2932 MHz 13801 MHz 64 100 % 433.27 W 433.28 W
448 2026/10/09 09:08:54.779 433.47 W 2932 MHz 13801 MHz 65 100 % 434.38 W 433.47 W
449 2026/10/09 09:08:55.779 435.03 W 2932 MHz 13801 MHz 65 100 % 435.69 W 435.03 W
450 2026/10/09 09:08:56.779 435.24 W 2932 MHz 13801 MHz 65 100 % 434.12 W 435.24 W
451 2026/10/09 09:08:57.779 435.92 W 2932 MHz 13801 MHz 65 100 % 436.80 W 435.92 W
452 2026/10/09 09:08:58.779 435.40 W 2932 MHz 13801 MHz 65 100 % 434.77 W 435.40 W
453 2026/10/09 09:08:59.780 434.63 W 2932 MHz 13801 MHz 65 100 % 435.25 W 434.63 W
454 2026/10/09 09:09:00.780 435.78 W 2932 MHz 13801 MHz 65 100 % 436.79 W 435.78 W
455 2026/10/09 09:09:01.780 436.27 W 2932 MHz 13801 MHz 65 100 % 437.48 W 436.27 W
456 2026/10/09 09:09:02.780 437.70 W 2932 MHz 13801 MHz 65 100 % 437.94 W 437.70 W
457 2026/10/09 09:09:03.781 438.49 W 2932 MHz 13801 MHz 65 100 % 440.09 W 438.49 W
458 2026/10/09 09:09:04.781 439.33 W 2932 MHz 13801 MHz 66 100 % 438.28 W 439.33 W
459 2026/10/09 09:09:05.781 438.69 W 2932 MHz 13801 MHz 66 100 % 438.42 W 438.69 W
460 2026/10/09 09:09:06.781 438.98 W 2932 MHz 13801 MHz 66 100 % 437.55 W 438.98 W
461 2026/10/09 09:09:07.782 437.60 W 2932 MHz 13801 MHz 66 100 % 437.73 W 437.60 W
462 2026/10/09 09:09:08.782 437.94 W 2932 MHz 13801 MHz 66 100 % 438.83 W 437.94 W
463 2026/10/09 09:09:09.782 438.73 W 2932 MHz 13801 MHz 66 100 % 439.50 W 438.73 W
464 2026/10/09 09:09:10.782 438.90 W 2932 MHz 13801 MHz 66 100 % 439.25 W 438.90 W
465 2026/10/09 09:09:11.783 439.36 W 2932 MHz 13801 MHz 66 100 % 439.83 W 439.36 W
466 2026/10/09 09:09:12.783 439.82 W 2932 MHz 13801 MHz 66 100 % 440.22 W 439.82 W
467 2026/10/09 09:09:13.783 439.94 W 2932 MHz 13801 MHz 66 100 % 440.35 W 439.94 W
468 2026/10/09 09:09:14.784 440.27 W 2932 MHz 13801 MHz 66 100 % 439.81 W 440.27 W
469 2026/10/09 09:09:15.784 439.17 W 2932 MHz 13801 MHz 66 100 % 438.20 W 439.17 W
470 2026/10/09 09:09:16.784 439.05 W 2932 MHz 13801 MHz 66 100 % 439.25 W 439.05 W
471 2026/10/09 09:09:17.784 440.14 W 2932 MHz 13801 MHz 66 100 % 442.26 W 440.14 W
472 2026/10/09 09:09:18.785 441.01 W 2932 MHz 13801 MHz 67 100 % 439.92 W 441.01 W
473 2026/10/09 09:09:19.785 440.89 W 2932 MHz 13801 MHz 67 100 % 441.54 W 440.89 W
474 2026/10/09 09:09:20.786 440.82 W 2932 MHz 13801 MHz 67 100 % 441.58 W 440.82 W
475 2026/10/09 09:09:21.786 440.67 W 2932 MHz 13801 MHz 67 100 % 440.54 W 440.67 W
476 2026/10/09 09:09:22.786 440.11 W 2932 MHz 13801 MHz 67 100 % 440.85 W 440.11 W
477 2026/10/09 09:09:23.786 440.24 W 2932 MHz 13801 MHz 67 100 % 440.96 W 440.24 W
478 2026/10/09 09:09:24.786 441.01 W 2932 MHz 13801 MHz 67 100 % 441.83 W 441.01 W
479 2026/10/09 09:09:25.786 441.97 W 2932 MHz 13801 MHz 67 100 % 442.87 W 441.97 W
480 2026/10/09 09:09:26.787 443.01 W 2932 MHz 13801 MHz 67 100 % 442.64 W 443.01 W
481 2026/10/09 09:09:27.787 444.17 W 2932 MHz 13801 MHz 67 100 % 444.70 W 444.17 W
482 2026/10/09 09:09:28.787 443.55 W 2932 MHz 13801 MHz 67 100 % 442.44 W 443.55 W
483 2026/10/09 09:09:29.787 442.40 W 2932 MHz 13801 MHz 67 100 % 441.04 W 442.40 W
484 2026/10/09 09:09:30.787 441.92 W 2932 MHz 13801 MHz 67 100 % 440.46 W 441.92 W
485 2026/10/09 09:09:31.787 441.91 W 2932 MHz 13801 MHz 67 100 % 442.30 W 441.91 W
486 2026/10/09 09:09:32.788 441.91 W 2932 MHz 13801 MHz 67 100 % 442.43 W 441.91 W
487 2026/10/09 09:09:33.788 442.54 W 2932 MHz 13801 MHz 67 100 % 442.81 W 442.54 W
488 2026/10/09 09:09:34.788 443.31 W 2932 MHz 13801 MHz 67 100 % 443.35 W 443.31 W
489 2026/10/09 09:09:35.788 443.45 W 2932 MHz 13801 MHz 67 100 % 443.74 W 443.45 W
490 2026/10/09 09:09:36.788 443.37 W 2932 MHz 13801 MHz 67 100 % 444.04 W 443.37 W
491 2026/10/09 09:09:37.788 442.71 W 2932 MHz 13801 MHz 67 100 % 443.23 W 442.71 W
492 2026/10/09 09:09:38.789 442.91 W 2932 MHz 13801 MHz 67 100 % 441.96 W 442.91 W
493 2026/10/09 09:09:39.789 442.24 W 2932 MHz 13801 MHz 67 100 % 441.36 W 442.24 W
494 2026/10/09 09:09:40.789 443.02 W 2932 MHz 13801 MHz 67 100 % 442.89 W 443.02 W
495 2026/10/09 09:09:41.789 443.51 W 2932 MHz 13801 MHz 67 100 % 443.23 W 443.51 W
496 2026/10/09 09:09:42.790 443.93 W 2932 MHz 13801 MHz 68 100 % 444.02 W 443.93 W
497 2026/10/09 09:09:43.790 443.37 W 2932 MHz 13801 MHz 68 100 % 443.40 W 443.37 W
498 2026/10/09 09:09:44.790 443.07 W 2932 MHz 13801 MHz 68 100 % 443.29 W 443.07 W
499 2026/10/09 09:09:45.790 442.82 W 2932 MHz 13801 MHz 68 100 % 443.31 W 442.82 W
500 2026/10/09 09:09:46.790 443.19 W 2932 MHz 13801 MHz 68 100 % 443.53 W 443.19 W
501 2026/10/09 09:09:47.791 443.18 W 2932 MHz 13801 MHz 68 100 % 443.99 W 443.18 W
502 2026/10/09 09:09:48.791 444.31 W 2932 MHz 13801 MHz 68 100 % 444.97 W 444.31 W
503 2026/10/09 09:09:49.791 122.28 W 2947 MHz 14001 MHz 59 0 % 114.90 W 122.28 W
504 2026/10/09 09:09:50.791 121.64 W 2947 MHz 14001 MHz 59 0 % 115.20 W 121.64 W
505 2026/10/09 09:09:51.791 103.82 W 795 MHz 14001 MHz 57 0 % 103.82 W 103.82 W
506 2026/10/09 09:09:52.792 42.49 W 360 MHz 810 MHz 55 0 % 42.49 W 42.49 W
507 2026/10/09 09:09:53.792 27.18 W 210 MHz 810 MHz 55 0 % 27.18 W 27.18 W
508 2026/10/09 09:09:54.792 24.23 W 195 MHz 405 MHz 54 0 % 21.27 W 24.23 W
509 2026/10/09 09:09:55.793 20.13 W 195 MHz 405 MHz 54 0 % 20.13 W 20.13 W
510 2026/10/09 09:09:56.793 20.03 W 195 MHz 405 MHz 54 0 % 19.94 W 20.03 W
511 2026/10/09 09:09:57.793 20.29 W 195 MHz 405 MHz 53 0 % 20.29 W 20.29 W
512 2026/10/09 09:09:58.793 20.45 W 195 MHz 405 MHz 53 0 % 20.45 W 20.45 W
513 2026/10/09 09:09:59.793 44.67 W 2542 MHz 13801 MHz 54 0 % 80.09 W 44.67 W
514 2026/10/09 09:10:00.793 173.43 W 2677 MHz 13801 MHz 61 6 % 436.89 W 173.43 W
515 2026/10/09 09:10:01.793 401.91 W 2932 MHz 13801 MHz 63 100 % 441.33 W 401.91 W
516 2026/10/09 09:10:02.794 441.88 W 2932 MHz 13801 MHz 64 100 % 443.07 W 441.88 W
517 2026/10/09 09:10:03.794 443.09 W 2932 MHz 13801 MHz 64 100 % 443.81 W 443.09 W
518 2026/10/09 09:10:04.794 444.19 W 2932 MHz 13801 MHz 64 100 % 444.39 W 444.19 W
519 2026/10/09 09:10:05.794 443.87 W 2932 MHz 13801 MHz 65 100 % 443.78 W 443.87 W
520 2026/10/09 09:10:06.794 443.51 W 2932 MHz 13801 MHz 65 100 % 443.67 W 443.51 W
521 2026/10/09 09:10:07.794 443.74 W 2932 MHz 13801 MHz 65 100 % 444.79 W 443.74 W
522 2026/10/09 09:10:08.795 444.57 W 2932 MHz 13801 MHz 65 100 % 444.05 W 444.57 W
523 2026/10/09 09:10:09.795 444.35 W 2932 MHz 13801 MHz 65 100 % 443.94 W 444.35 W
524 2026/10/09 09:10:10.795 445.52 W 2932 MHz 13801 MHz 65 100 % 445.93 W 445.52 W
525 2026/10/09 09:10:11.795 446.57 W 2932 MHz 13801 MHz 65 100 % 446.58 W 446.57 W
526 2026/10/09 09:10:12.795 447.46 W 2932 MHz 13801 MHz 65 100 % 447.87 W 447.46 W
527 2026/10/09 09:10:13.796 447.70 W 2932 MHz 13801 MHz 66 100 % 447.51 W 447.70 W
528 2026/10/09 09:10:14.796 446.70 W 2932 MHz 13801 MHz 66 100 % 447.22 W 446.70 W
529 2026/10/09 09:10:15.796 446.06 W 2932 MHz 13801 MHz 66 100 % 444.95 W 446.06 W
530 2026/10/09 09:10:16.796 445.07 W 2932 MHz 13801 MHz 66 100 % 445.37 W 445.07 W
531 2026/10/09 09:10:17.797 446.28 W 2932 MHz 13801 MHz 66 100 % 446.45 W 446.28 W
532 2026/10/09 09:10:18.797 447.26 W 2932 MHz 13801 MHz 66 100 % 447.87 W 447.26 W
533 2026/10/09 09:10:19.797 447.49 W 2932 MHz 13801 MHz 66 100 % 447.35 W 447.49 W
534 2026/10/09 09:10:20.798 448.46 W 2932 MHz 13801 MHz 66 100 % 447.87 W 448.46 W
535 2026/10/09 09:10:21.798 448.38 W 2932 MHz 13801 MHz 66 100 % 447.46 W 448.38 W
536 2026/10/09 09:10:22.798 447.71 W 2932 MHz 13801 MHz 66 100 % 445.75 W 447.71 W
537 2026/10/09 09:10:23.799 447.69 W 2932 MHz 13801 MHz 66 100 % 447.90 W 447.69 W
538 2026/10/09 09:10:24.799 447.49 W 2932 MHz 13801 MHz 66 100 % 447.74 W 447.49 W
539 2026/10/09 09:10:25.799 447.71 W 2932 MHz 13801 MHz 67 100 % 447.89 W 447.71 W
540 2026/10/09 09:10:26.799 448.39 W 2932 MHz 13801 MHz 67 100 % 449.58 W 448.39 W
541 2026/10/09 09:10:27.799 448.94 W 2932 MHz 13801 MHz 67 100 % 449.28 W 448.94 W
542 2026/10/09 09:10:28.800 448.84 W 2932 MHz 13801 MHz 67 100 % 448.72 W 448.84 W
543 2026/10/09 09:10:29.800 448.24 W 2932 MHz 13801 MHz 67 100 % 448.42 W 448.24 W
544 2026/10/09 09:10:30.800 447.18 W 2932 MHz 13801 MHz 67 100 % 446.22 W 447.18 W
545 2026/10/09 09:10:31.800 447.33 W 2932 MHz 13801 MHz 66 100 % 446.87 W 447.33 W
546 2026/10/09 09:10:32.800 447.82 W 2932 MHz 13801 MHz 67 100 % 447.50 W 447.82 W
547 2026/10/09 09:10:33.800 448.67 W 2932 MHz 13801 MHz 67 100 % 448.48 W 448.67 W
548 2026/10/09 09:10:34.801 450.29 W 2932 MHz 13801 MHz 67 100 % 450.63 W 450.29 W
549 2026/10/09 09:10:35.801 450.55 W 2932 MHz 13801 MHz 67 100 % 451.40 W 450.55 W
550 2026/10/09 09:10:36.801 450.43 W 2932 MHz 13801 MHz 67 100 % 450.27 W 450.43 W
551 2026/10/09 09:10:37.801 449.76 W 2932 MHz 13801 MHz 67 100 % 450.05 W 449.76 W
552 2026/10/09 09:10:38.802 448.65 W 2932 MHz 13801 MHz 67 100 % 448.73 W 448.65 W
553 2026/10/09 09:10:39.802 448.17 W 2932 MHz 13801 MHz 67 100 % 448.73 W 448.17 W
554 2026/10/09 09:10:40.803 448.71 W 2932 MHz 13801 MHz 67 100 % 449.67 W 448.71 W
555 2026/10/09 09:10:41.803 448.96 W 2932 MHz 13801 MHz 67 100 % 449.01 W 448.96 W
556 2026/10/09 09:10:42.803 450.33 W 2932 MHz 13801 MHz 67 100 % 450.11 W 450.33 W
557 2026/10/09 09:10:43.803 450.17 W 2932 MHz 13801 MHz 67 100 % 448.80 W 450.17 W
558 2026/10/09 09:10:44.803 450.80 W 2932 MHz 13801 MHz 67 100 % 449.62 W 450.80 W
559 2026/10/09 09:10:45.803 450.61 W 2932 MHz 13801 MHz 67 100 % 450.83 W 450.61 W
560 2026/10/09 09:10:46.804 450.00 W 2932 MHz 13801 MHz 67 100 % 450.20 W 450.00 W
561 2026/10/09 09:10:47.804 449.80 W 2932 MHz 13801 MHz 67 100 % 450.53 W 449.80 W
562 2026/10/09 09:10:48.804 450.37 W 2932 MHz 13801 MHz 67 100 % 450.76 W 450.37 W
563 2026/10/09 09:10:49.804 451.11 W 2932 MHz 13801 MHz 67 100 % 451.47 W 451.11 W
564 2026/10/09 09:10:50.804 451.54 W 2932 MHz 13801 MHz 67 100 % 451.77 W 451.54 W
565 2026/10/09 09:10:51.804 450.40 W 2932 MHz 13801 MHz 67 100 % 449.60 W 450.40 W
566 2026/10/09 09:10:52.805 450.12 W 2932 MHz 13801 MHz 67 100 % 449.40 W 450.12 W
567 2026/10/09 09:10:53.805 450.24 W 2932 MHz 13801 MHz 67 100 % 449.70 W 450.24 W
568 2026/10/09 09:10:54.805 450.42 W 2932 MHz 13801 MHz 67 100 % 450.30 W 450.42 W
569 2026/10/09 09:10:55.805 450.95 W 2932 MHz 13801 MHz 67 100 % 450.96 W 450.95 W
570 2026/10/09 09:10:56.806 452.20 W 2932 MHz 13801 MHz 67 100 % 452.73 W 452.20 W
571 2026/10/09 09:10:57.806 452.07 W 2932 MHz 13801 MHz 67 100 % 452.71 W 452.07 W
572 2026/10/09 09:10:58.806 453.17 W 2932 MHz 13801 MHz 67 100 % 452.94 W 453.17 W
573 2026/10/09 09:10:59.806 452.71 W 2932 MHz 13801 MHz 67 100 % 452.39 W 452.71 W
574 2026/10/09 09:11:00.807 451.96 W 2932 MHz 13801 MHz 67 100 % 451.42 W 451.96 W
575 2026/10/09 09:11:01.807 450.69 W 2932 MHz 13801 MHz 67 100 % 451.54 W 450.69 W
576 2026/10/09 09:11:02.807 227.35 W 2947 MHz 14001 MHz 59 0 % 112.95 W 227.35 W
577 2026/10/09 09:11:03.808 135.24 W 2947 MHz 14001 MHz 59 0 % 112.98 W 135.24 W
578 2026/10/09 09:11:04.808 101.36 W 2692 MHz 14001 MHz 57 0 % 101.36 W 101.36 W
579 2026/10/09 09:11:05.808 41.78 W 405 MHz 810 MHz 56 0 % 41.78 W 41.78 W
580 2026/10/09 09:11:06.808 35.32 W 240 MHz 810 MHz 55 0 % 28.87 W 35.32 W
581 2026/10/09 09:11:07.809 25.38 W 195 MHz 405 MHz 55 0 % 21.89 W 25.38 W
582 2026/10/09 09:11:08.809 21.58 W 195 MHz 405 MHz 54 0 % 21.27 W 21.58 W
583 2026/10/09 09:11:09.809 20.70 W 195 MHz 405 MHz 54 0 % 20.13 W 20.70 W
584 2026/10/09 09:11:10.809 19.19 W 195 MHz 405 MHz 53 0 % 19.19 W 19.19 W
585 2026/10/09 09:11:11.809 20.04 W 195 MHz 405 MHz 53 0 % 20.04 W 20.04 W

View file

@ -0,0 +1,48 @@
### run 1 x1-ctrl-ds28 start 1791536492.664017100
1791536492.977525640 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536554.304423565 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 1123 cache 1 dataset 13 hot 0 check 336 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536554.305459259 warm-up dispatch (base 0): 237.71 ms; 250 timed dispatches of 16777216 nonces: mean 237.50 ms
1791536554.306573471 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=70.640 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 1 x1-ctrl-ds28 end 1791536554.344351911
### run 2 x1-flat-ds28 start 1791536564.346794218
1791536564.567432129 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536625.832252672 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 979 cache 1 dataset 13 hot 0 check 339 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536625.833471181 warm-up dispatch (base 0): 237.81 ms; 250 timed dispatches of 16777216 nonces: mean 237.85 ms
1791536625.834629466 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=70.537 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 2 x1-flat-ds28 end 1791536625.869509559
### run 3 x1-flat-ds28 start 1791536635.872428571
1791536636.095251891 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536697.365795755 pack /root/x1/packs/x1-flat-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 976 cache 1 dataset 13 hot 0 check 343 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536697.366852920 warm-up dispatch (base 0): 237.82 ms; 250 timed dispatches of 16777216 nonces: mean 237.86 ms
1791536697.367976901 RESULT pack=/root/x1/packs/x1-flat-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=8cd11a827ac3ffe4 mhs=70.535 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 3 x1-flat-ds28 end 1791536697.394649666
### run 4 x1-ctrl-ds28 start 1791536707.396932515
1791536707.617106383 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536768.825855358 pack /root/x1/packs/x1-ctrl-ds28 on NVIDIA_GeForce_RTX_5090: nvrtc 1005 cache 1 dataset 13 hot 0 check 348 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
1791536768.826924576 warm-up dispatch (base 0): 237.46 ms; 250 timed dispatches of 16777216 nonces: mean 237.48 ms
1791536768.828150159 RESULT pack=/root/x1/packs/x1-ctrl-ds28 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=70.647 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 4 x1-ctrl-ds28 end 1791536768.867441555
### run 5 x1-ctrl-ds30 start 1791536778.869875148
1791536779.090696417 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536842.072581233 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 1000 cache 1 dataset 49 hot 0 check 345 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536842.073615876 warm-up dispatch (base 0): 244.37 ms; 250 timed dispatches of 16777216 nonces: mean 244.42 ms
1791536842.074816482 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=68.642 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 5 x1-ctrl-ds30 end 1791536842.115041759
### run 6 x1-flat-ds30 start 1791536852.117800280
1791536852.352627601 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536915.351140261 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 972 cache 1 dataset 50 hot 0 check 342 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536915.352210392 warm-up dispatch (base 0): 244.56 ms; 250 timed dispatches of 16777216 nonces: mean 244.61 ms
1791536915.353557625 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=68.587 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 6 x1-flat-ds30 end 1791536915.384215408
### run 7 x1-flat-ds30 start 1791536925.386915420
1791536925.607361864 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791536988.606138809 pack /root/x1/packs/x1-flat-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 974 cache 1 dataset 49 hot 0 check 344 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791536988.607146772 warm-up dispatch (base 0): 244.56 ms; 250 timed dispatches of 16777216 nonces: mean 244.60 ms
1791536988.608310590 RESULT pack=/root/x1/packs/x1-flat-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw+flat device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=102 blocks_per_sm=16 warps=0 resident=2720 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=18c4c6a80809c4b9 mhs=68.589 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 7 x1-flat-ds30 end 1791536988.657547081
### run 8 x1-ctrl-ds30 start 1791536998.659988637
1791536998.884943346 info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
1791537061.859024464 pack /root/x1/packs/x1-ctrl-ds30 on NVIDIA_GeForce_RTX_5090: nvrtc 997 cache 1 dataset 49 hot 0 check 344 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [1073741823] and 64 samples; 96 of 96 vector lanes)
1791537061.860077442 warm-up dispatch (base 0): 244.79 ms; 250 timed dispatches of 16777216 nonces: mean 244.40 ms
1791537061.861368339 RESULT pack=/root/x1/packs/x1-ctrl-ds30 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=96 blocks_per_sm=20 warps=0 resident=3400 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=b1f90e91cadb15b6 mhs=68.647 loads=256 bytes=1024 scratch_ops=0 time=wall
### run 8 x1-ctrl-ds30 end 1791537061.897137972

View file

@ -0,0 +1,279 @@
Compiling zmij v1.0.23
Compiling serde_core v1.0.229
Compiling serde_json v1.0.151
Checking memchr v2.8.3
Checking itoa v1.0.18
Checking igneum-pow v0.2.0 (/srv/builds/x1/x1-a99de07cd/igneum-pow)
warning: unused import: `GENERATOR_VERSION_V3`
--> src/main.rs:19:40
|
19 | use igneum_pow::generator::{EraParams, GENERATOR_VERSION_V3};
| ^^^^^^^^^^^^^^^^^^^^
|
= note: `#[warn(unused_imports)]` (part of `#[warn(unused)]`) on by default
warning: `igneum-pow` (bin "igneum-pow") generated 1 warning (run `cargo fix --bin "igneum-pow" -p igneum-pow` to apply 1 suggestion)
warning: `igneum-pow` (bin "igneum-pow" test) generated 1 warning (1 duplicate)
Finished `dev` profile [optimized + debuginfo] target(s) in 3.25s
Compiling zmij v1.0.23
Compiling serde_core v1.0.229
Compiling serde_json v1.0.151
Compiling memchr v2.8.3
Compiling itoa v1.0.18
Compiling igneum-pow v0.2.0 (/srv/builds/x1/x1-a99de07cd/igneum-pow)
warning: unused import: `GENERATOR_VERSION_V3`
--> src/main.rs:19:40
|
19 | use igneum_pow::generator::{EraParams, GENERATOR_VERSION_V3};
| ^^^^^^^^^^^^^^^^^^^^
|
= note: `#[warn(unused_imports)]` (part of `#[warn(unused)]`) on by default
warning: `igneum-pow` (bin "igneum-pow" test) generated 1 warning (run `cargo fix --bin "igneum-pow" -p igneum-pow --tests` to apply 1 suggestion)
warning: `igneum-pow` (bin "igneum-pow") generated 1 warning (1 duplicate)
Finished `release` profile [optimized] target(s) in 19.42s
Running unittests src/lib.rs (/srv/builds/x1/target-rel/release/deps/igneum_pow-bfe1b8dd991badaf)
running 81 tests
test accept::tests::base_nonces_are_aligned_and_seed_dependent ... ok
test accept::tests::distinct_bound_scales_with_the_load_count ... ok
test accept::tests::injecting_write_detection ... ok
test accept::tests::v5_attempts_census ... ignored
test accept::tests::v5_floor_on_listed_programs ... ignored
test accept::tests::v5_hot_census ... ignored
test accept::tests::stale_load_detection_is_cyclic ... ok
test bind::tests::day_bytes_layout ... ok
test bind::tests::init_bytes_layout ... ok
test bind::tests::pow256_and_target64 ... ok
test blake2b::tests::rfc_7693_vectors ... ok
test derive::tests::acceptance_rejects_degenerate_draws ... ok
test derive::tests::text_forms ... ok
test derive::tests::weights_sum_and_ops ... ok
test generator::tests::attempt_words_differ_and_are_stable ... ok
test derive::tests::soa_matches_scalar_and_is_a_bijection ... ok
test generator::tests::diag_f8_64_distinct_index_ratios ... ignored
test generator::tests::diag_f8_weak_seeds_at_2e24 ... ignored
test generator::tests::diag_p23_distinct_indices_per_site ... ignored
test derive::tests::draw_is_structural_and_accepted ... ok
test generator::tests::default_weights_unchanged ... ok
test generator::tests::load_weight_17_table ... ok
test generator::tests::era_draw_deterministic_and_bounded ... ok
test generator::tests::v1_genesis_shape ... ok
test memhard::tests::chacha_block_is_a_permutation_plus_feedforward ... ok
test generator::tests::hot_classes ... ok
test memhard::tests::growth_schedule_table ... ok
test memhard::tests::first_cache_line_matches_pack ... ok
test memhard::tests::mix_params_for_day ... ok
test packcheck::tests::attempt_words_vectors_shared_with_the_workers ... ok
test packcheck::tests::day_label_reads_the_index ... ok
test memhard::tests::layout_split_join ... ok
test generator::tests::load_classes ... ok
test generator::tests::v2_shape_and_contract ... ok
test seed::tests::day_key_2026_10_03 ... ok
test seed::tests::genesis_seed_words ... ok
test bind::tests::closed_form_bound_also_works ... ok
test generator::tests::v2_loads_are_fresh_unless_fallback ... ok
test state::tests::stream_file_round_trip_and_refusals ... ok
test verify::tests::closed_form_head_matches_pack ... ok
test state::tests::the_sample_above_the_dataset_size_is_keyed_by_the_root ... ok
test state::tests::every_item_is_keyed_and_the_leaf_wraps ... ok
test verify::reg64_mix_tests::reg64_closed_form_equals_the_reference_fold_on_every_source ... ok
test verify::tests::scratch_model ... ok
test accept::tests::v1_programs_are_mostly_rejected ... ok
test generator::tests::program_id_separates_versions_and_attempts ... ok
test verify::tests::hot_program_without_a_table_is_refused - should panic ... ok
test verify::tests::closed_form_genesis_vector_lane0 ... ok
test generator::tests::generate_returns_an_accepted_program ... ok
test memhard::tests::mixer_mult_by_hand ... ok
test packcheck::tests::epoch_34_program_is_a_later_attempt ... ok
test memhard::tests::class_v5_mixer_draw_rule ... ok
test accept::tests::generated_programs_pass ... ok
test verify::tests::wide_class_epochs_hash ... ok
test generator::tests::program_classes ... ok
test generator::tests::era_programs_are_accepted ... ok
test accept::tests::instrumented_interpreter_matches_verify ... ok
test memhard::tests::hot_table_fill_vector_and_index ... ok
test generator::tests::class_v5_shadow_redundancy_rule ... ok
test bind::tests::bound_vectors ... ok
test bind::tests::bound_hash_properties ... ok
test packcheck::tests::known_mismatched_pack_is_out_of_date ... ok
test verify::tests::fold_and_wide_fetch ... ok
test packcheck::tests::known_good_pack_of_a_later_attempt_verifies ... ok
test verify::tests::hot_epochs_hash ... ok
test packcheck::tests::inconsistent_pack_disagrees ... ok
test accept::tests::rejection_rate_and_distinct_loads_on_a_sample ... ok
test accept::tests::hot_classes_pass_and_hot_loads_are_uniform ... ok
test verify::tests::era_windows_layout_and_epochs ... ok
test accept::tests::classes_pass_and_match_verify ... ok
test state::tests::a_stateless_hasher_is_wrong_on_every_item ... ok
test generator::tests::shadow_class_leaves_the_base_program_and_class_v3_untouched ... ok
test packcheck::tests::program_class_and_era_are_checked ... ok
test generator::tests::class_v4_distinct_ratio_rejects_the_low_entropy_band ... ok
test generator::tests::program_class_v4_is_class_v3_with_the_shadow_block ... ok
test accept::tests::acceptance_executes_the_shadow_block_as_the_verifier_does ... ok
test accept::tests::class_v5_hot_set_rule_known_failed_seed_100767 ... ok
test generator::tests::class_v5_last_resort_is_verified_known_failed_adv3_steer_2 ... ok
test generator::tests::class_v5_chain_draw_is_the_amended_v4_draw ... ok
test generator::tests::latency_ladder_known_failed_a_changed_n_was_a_hard_fork_and_rungs_are_class_v4 ... ok
test generator::tests::class_v4_draw_is_total_with_the_last_resort has been running for over 60 seconds
test generator::tests::class_v4_draw_is_total_with_the_last_resort ... ok
test result: ok. 75 passed; 0 failed; 6 ignored; 0 measured; 0 filtered out; finished in 139.89s
Running unittests src/main.rs (/srv/builds/x1/target-rel/release/deps/igneum_pow-e146331a68f99fd6)
running 0 tests
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
Running tests/derivation.rs (/srv/builds/x1/target-rel/release/deps/derivation-813965abdd310d29)
running 3 tests
test print_every_pack_derivation ... ignored
test the_class_v4_derivation_states_the_suffix_and_the_plain_text_derives_another_id ... ok
test every_pinned_pack_id_rederives_from_its_own_derivation_text ... ok
test result: ok. 2 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 0.01s
Running tests/derive.rs (/srv/builds/x1/target-rel/release/deps/derive-8eaad8ae46f07f0b)
running 7 tests
test text_forms_match_scalar_reference ... ok
test v2_and_v3_are_untouched ... ok
test dataset_source_word_path ... ok
test derived_item_by_hand_and_in_batches ... ok
test stream_class_name_and_id ... ok
test stats_beside_x8 ... ok
test determinism_and_pack_text ... ok
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 1.44s
Running tests/ds55.rs (/srv/builds/x1/target-rel/release/deps/ds55-10777adbb1a47355)
running 5 tests
test mulshift_index_is_in_range_and_uniform ... ok
test cpu_verifier_and_cuda_text_agree_on_fold_and_address ... ok
test power_of_two_path_is_byte_identical_to_the_pinned_pack ... ok
test ds55_pack_fields_and_vectors ... ok
test dataset_words_power_of_two_equals_dataset_log2 ... ok
test result: ok. 5 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.99s
Running tests/fuzz_parsers.rs (/srv/builds/x1/target-rel/release/deps/fuzz_parsers-3081828a6deab4bc)
running 3 tests
test state_streams_never_panic ... ok
test class_strings_never_panic ... ok
test hex_and_era_strings_never_panic ... ok
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.01s
Running tests/mixer.rs (/srv/builds/x1/target-rel/release/deps/mixer-1534fa965651bb62)
running 4 tests
test edge_items_every_multiplier ... ok
test determinism_v3 ... ok
test stats_v3_against_v2 ... ok
test fuzz_v3_programs_cpu ... ok
test result: ok. 4 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 9.83s
Running tests/packs.rs (/srv/builds/x1/target-rel/release/deps/packs-6b5950289d40f0f7)
running 27 tests
test reg64_full_chain_cpu_verifier_and_cuda_text_agree ... ok
test item_is_independent_of_dataset_size ... ok
test genesis_program_shape ... ok
test mixer_params_match_pack ... ok
test dataset_words_match_all_packs ... ok
test spec_vectors_genesis_mh ... ok
test devnet_pack_is_the_chain_derivation ... ok
test emitted_sources_match_all_packs ... ok
test program_json_matches_all_packs ... ok
test era_program_json_matches ... ok
test a07_bound_hash_is_group_aligned_across_tails_and_rollover ... ok
test vectors_96_per_pack ... ok
test a06_program_json_hashes_every_kernel_text ... ok
test reg64_plain_path_reexports_the_pinned_devnet_pack_unchanged ... ok
test era_dataset_is_a_prefix_at_smaller_sizes ... ok
test reg64_cpu_verifier_and_cuda_text_agree ... ok
test reg64_liveness_rule_refuses_the_subset_fold_and_passes_the_full_chain ... ok
test cache_matches_vectors ... ok
test v3_packs_are_the_v2_seeds_under_mixer_x8 ... ok
test era_emitted_sources_match_and_loads_have_the_era_form ... ok
test era_dataset_words_and_vectors_match ... ok
test export_pack_matches_all_packs ... ok
test a04_a_zeroing_shadow_fails_acceptance ... ok
test era_packs_share_the_program_and_differ_in_layout ... ok
test v5_pack_is_the_v4_program_over_the_state_leaves ... ok
test hot_packs_emitted_sources_and_load_forms ... ok
test hot_packs_program_and_vectors ... ok
test result: ok. 27 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 6.57s
Running tests/recheck.rs (/srv/builds/x1/target-rel/release/deps/recheck-8d7cb13ced9adbf9)
running 2 tests
test program_ids_differ_between_class_v3_and_class_v4_of_one_seed ... ok
test cpu_recheck_equals_the_worker_reference_for_class_v3_and_class_v4 ... ok
test result: ok. 2 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 6.09s
Running tests/scratch.rs (/srv/builds/x1/target-rel/release/deps/scratch-9e8fb62a55801024)
running 7 tests
test slot_is_replayable_from_its_fold_values ... ok
test rewrite_is_a_bijection_of_the_fold_value ... ok
test edge_programs_match_the_hand_model ... ok
test fill_is_a_bijection_of_the_nonce ... ok
test fuzz_scr_programs_cpu ... ok
test scr_packs_regenerate_and_pass_the_static_scratch_check ... ok
test written_words_unbiased_and_rehit_rates ... ok
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 4.85s
Running tests/spec_readback.rs (/srv/builds/x1/target-rel/release/deps/spec_readback-c486d7a13802c5c6)
running 3 tests
test every_pinned_id_of_the_spec_derives_from_the_crate ... ok
test the_closed_form_vectors_of_the_spec_are_the_crates ... ok
test the_chain_draw_accepts_each_class_v4_row_at_its_attempt ... ok
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 4.14s
Running tests/v6fold.rs (/srv/builds/x1/target-rel/release/deps/v6fold-926a7dbf608a6c35)
running 13 tests
test fold_known_failed_seven_seeds ... ignored
test every_v6_flag_keeps_the_class_v4_acceptance_shape ... ok
test class_v6_all_flags_parse_name_and_id ... ok
test fold_and_rw_flags_parse_name_and_id ... ok
test nowin_removes_the_window_layer_and_nothing_else ... ok
test fold_form_and_the_plain_stride_unchanged ... ok
test program_class_v6_is_generator_6 ... ok
test v6_draw_connects_all_lanes_and_keeps_mad_bijective_by_construction ... ok
test rw_table_op_counts_within_2_percent ... ok
test plain_class_draw_is_byte_identical_to_the_pinned_pack ... ok
test fold_and_rw_reach_the_pack_texts ... ok
test index_bit_sigma_rows ... ok
test fold_known_failed_p4_p34 ... ok
test result: ok. 12 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 20.68s
Running tests/v7flat.rs (/srv/builds/x1/target-rel/release/deps/v7flat-d6adde4ef262ce31)
running 3 tests
test flat_names_the_v7_shape_and_leaves_the_frozen_class_alone ... ok
test the_frozen_control_keeps_its_windows ... ok
test flat_has_no_window_on_any_load_site has been running for over 60 seconds
test flat_has_no_window_on_any_load_site ... ok
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 410.72s
Doc-tests igneum_pow
running 0 tests
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
EXIT 0

View file

@ -0,0 +1,221 @@
# X2: serving-mode result compaction on the frozen control (9 October 2026)
The 1.5x programme's item X2 (the brief: `docs/plans/igneum-2.0-master/1p5x/`, sha256 74ee073286d4a6e2..., its experiment
matrix row X2: "exact output equivalence incl. overflow/sentinels; wall joules and accepted throughput; no invented
percentage"). The lane: X2 (the worker lane of the programme). Branch `x2-compaction` off class-v6 755c2dbcf. Clock 09:32 to
11:30 UK. Rows in UTC; "on an island, not a network" does not apply (no row here is taken on the devnet).
## 0. The premise, read first: the compaction is already in the control
The frozen control 1a938abe4 already carries a serving-mode compaction, ON by default, in the CUDA kit worker:
`proto-cuda/nvrtc/worker.cpp` at 12cb65cc4 (review B finding F10, landed on master as 964cdf6c; the file is unchanged from
12cb65cc4 to 1a938abe4, sha256 of the text 9bfabc716b217f5e). A tiny NVRTC kernel `igneum_select` scans the bound kernel's
per-nonce output on the GPU, writes the hits (chunk index, hash word) behind an atomic counter into a 256-entry table plus 34
sentinel words (the first 32 outputs, the middle and the last, for the stale-output detector), and the host reads back the
count, the hits and the sentinels. A chunk with more than 256 hits falls back to the full read. `--readback full` or
`IGNEUM_READBACK=full` is the uncompacted path (8 bytes per nonce over the bus, the host scans). The OpenCL worker has had
the same pass since 5 October 2026. F10 measured it at stock on a 5090 and a 3090
(`docs/analysis/review-2026-10-08-b/f10/rows.md`).
So X2 adds no flag and changes no worker code (the flag exists; turning it off by default would undo a landed fix), touches
nothing in consensus, the generator or any `.rs` or Cargo file (rule 24 is not triggered), and delivers what F10 did not:
the equivalence on the three same-work contexts against the CPU references with the sentinel and overflow cases enumerated,
the 4090 same-session pairs, and the arithmetic against the yardstick. The coordinator confirmed this shape at 09:5x UK.
What the compaction does NOT remove, read from the code: the bound kernel still writes 8 bytes per nonce to device memory
(`out[g] = ...` in every pack's `kernel_bound.cu`) and the select kernel reads them back once; fusing the compare into the
emitted kernel would change the emitter's output (`igneum-pow/src/emit.rs`), which this lane does not touch. Against the
class v6 hash's own traffic (256 dependent 4-byte loads per hash under reg64, `program.json` `loads_per_hash`, each a 32-byte
sector on NVIDIA) those 16 bytes are 16 / 8,192 = 0.2 percent of the bytes a hash moves, a byte count from the code and not
an energy figure; no row here measures it.
## 1. Software, hardware, boundary
| Item | Identity |
|---|---|
| Worker | `igneum-worker-cuda` built on the pod from 1a938abe4's `proto-cuda/nvrtc/worker.cpp` and `packfile.h` by the kit recipe's Linux line (`tools/class-v5/kits-on-box.sh` line 25: `g++ -std=c++17 -O2 -Wall -Wextra -I proto-cuda/nvrtc -I /usr/local/cuda/include ... -ldl -lpthread`), Ubuntu 24.04, g++ 13.3.0; sha256 `4152c960d14210072a5c85ae675b56ae4dab12bedfb5f1af04ea2a2c6c025032`. Not a kit-lane cut: no Linux CUDA binary on build-1 carries both generator 6 and the select pass (`/srv/artefacts/packs/igneum-worker-cuda-gen6`, 804a6f7f, is generator 6 with no `igneum_select`; the F10 binary 9b36b523 refuses generator 6 packs) |
| Packs and references | the same-work contexts on build-1 `/srv/artefacts/tas/same-work-20261008-0{1,2,3}/` (job-context.json, packs/, references/), copied whole; reference sha256 read back equal to the published `.sha256` files: 01 D c49fed11 / D1 5ae1220d, 02 D 7c7be9b5 / D1 cad7849f, 03 D 873528b1 / D1 7f8e64ae |
| Objects | 01: class v6, generator 6, the frozen-object context (pack hl-v6-all, program id 0x4de7b836cc40a4ea on day D+1); 02: class v6, the chain-seed object 0x2a1d6caab4c24564 (the brief's signing id, epoch seed af89be5d, era edc4fa84, day 20730); 03: class v5, epoch 2, 0x81fbfa3aa413173f. Dataset 2^28 words (1 GiB) in every pack, as the same-work packs were exported |
| Hardware | RTX 4090 24 GB, driver 595.91.07, NVRTC 12.8, sm_89, 128 SMs, PCIe link read at idle as gen 1 x16, RunPod secure instance lyum23xjpv4re9 (the fleet lane's fk-x2-4090), 450 W board limit |
| Power boundary | the board only: nvidia-smi `power.draw` at 1 Hz. The container exposes no host rail and no wall meter, so the WALL row is BLOCKED (section 5); the worker's own CPU seconds stand in for the host side, as in F10 |
| State | stock only. `nvidia-smi -lgc 1300` and `-pl 300` answered "does not have permission" / "Insufficient Permissions" on this host (read 10:0x UK); the knee row is NOT RUN (section 5) |
## 2. Equivalence (requirement 1): EQUAL on all three contexts
The driver `tools/1p5x/x2/x2-equiv.py` runs one worker binary in `--serve` exactly as the miner drives it (job lines on
stdin, `prepare` of pack D1 before the first day-D1 job, the worker's report of a finished prepare read before switching),
writes the normalized protocol output, and builds the EXPECTED output from the CPU references alone: for each job, every
nonce with `ref[n] <= target` in nonce order, then `done <job> <count>`. A verdict is EQUAL only when the full run, the select
run and the expected file are byte-identical, which is every nonce's verdict at every target and every found nonce's digest.
Campaign: `tools/1p5x/x2/run-equiv.sh` plus `run-prod-then-pairs.sh` (the prod plan's second take, section 2.3), on the pod
at 08:45 to 08:51 UTC.
### 2.1 The known-failed tests, first
| Test | Result |
|---|---|
| The driver's self-test (`x2-equiv.py --self-test`: a fake worker over a fake hash on all three plans) | PASS: the clean fake is EQUAL on every plan; five injected faults each compare DIFFERENT: the 257th hit of a chunk dropped (the overflow taken as a full table), one digest wrong, the previous chunk's hits returned again (the counter-reset fault), the day switch missed (D's dataset after the boundary), `<` for `<=` (the target-equality edge). Log: `evidence/self-test.log` |
| The real worker's fault run (`--readback select` with `IGNEUM_READBACK_FAULT_TEST=1`: the hit counter is not reset from the second chunk on), context 01, the kf plan (four 2,048-nonce jobs at a 1/16 target on 1,024-nonce chunks) | flagged: DIFFERENT at line 64 (`found 1 1037 00cb3ac5...` where the reference has `found 1 1053 0fa540bb...`), 368 extra lines; the same plan's full and select runs EQUAL to the references. Only then did any select row count |
A finding about the fault injection itself: once the un-reset count passes 256, every later chunk takes the full-read
fallback and prints the right answer, so the counter-reset fault is invisible on a plan whose early chunks overflow (the
fake reproduces this: the stale fault reads EQUAL on the prod and fuzz plans). The kf plan exists for that reason.
### 2.2 The rows
| Context | Plan | Jobs | Nonce evaluations | Found lines | Select overflow fallbacks | Normalized output sha256, expected = full = select |
|---|---|---|---|---|---|---|
| 01 (class v6, frozen object) | prod (2^22 chunks) | 16 | 9,437,568 | 3,146,498 | 5 of 16 chunks | f278f0594dfd566d... |
| 01 | fuzz (2^10 chunks) | 38 | 1,048,576 | 438,688 | 534 of 1,039 | 5f1e591db673f964... |
| 02 (class v6, chain-seed 0x2a1d6caab4c24564) | prod | 16 | 9,437,568 | 3,146,498 | 5 of 16 | ad091a0d49a9d3a2... |
| 02 | fuzz | 35 | 1,048,576 | 446,422 | 599 of 1,042 | 8f39a1b15b16e86f... |
| 03 (class v5, epoch 2) | prod | 16 | 9,437,568 | 3,146,498 | 5 of 16 | 2aa97d5d63e5e01c... |
| 03 | fuzz | 33 | 1,048,576 | 342,786 | 365 of 1,035 | 3a7a7cc495e2d485... |
Every verdict EQUAL; full sha256s in `evidence/*.compare.json` and `evidence/norm.sha256`; the normalized outputs (up to
103 MB each, 31 files) at build-1 `/srv/artefacts/tas/x2-20261009/x2-equiv-outputs.tar.gz` (sha256 64740f73213b9deb...).
What each plan covers. **prod** (the worker's and the miner's 2^22 batch): every nonce of [0, 3,145,728) at the all-ones
target (every digest of the context through the overflow fallback); phase 1 at the sentinel targets T256 (the 256th smallest
hash of the job: exactly 256 hits, the table full, no fallback), T257 (257 hits: overflow by one, the fallback), 0, Teq (the
job's smallest hash: one hit, the `<=` edge) and Teq - 1 (zero hits); the day switch inside phase 2 at nonce 1,572,864 by
`prepare` (the worker's `prepared` line in `evidence/*.prod.*.meta.json`); phase 3 at all-ones and at its own T256. The 5
fallbacks per select run are the five all-ones and T257 jobs, and the T256 jobs went through the table, which is the 256/257
edge read on the real worker. **fuzz** (1,024-nonce chunks): 1,048,576 nonces per context in 29 to 34 seeded random jobs (seed
`x2-fuzz/<run id>`) at targets drawn from {0, all-ones, 2^k - 1 for k in 50 to 63, 1/8, 1/4, an in-job hash, that hash minus
1}; the 1/4 target puts about 256 hits in a chunk, so overflow and table chunks alternate inside one job; plus the 8,192-nonce
boundary block ([1,568,768, 1,572,864) on D, `prepare`, [1,572,864, 1,576,960) on D1) at all-ones and 1/4.
The sentinels enumerated, each with the plan that reaches it: target 0 (prod p1-zero, fuzz fz0); all-ones, every chunk over
the table (prod p1-all, p2, p3-all; fuzz fz1 and the boundary block); exactly 256 hits (prod p1-t256, p3-t256); 257 hits
(prod p1-t257); the `<=` edge (prod p1-teq; fuzz fz5, fz6); one below it (prod p1-teq-1; fuzz fz7); overflow and table chunks
in one job (fuzz fz4 at 1/4); the day switch (prod p2; fuzz boundary block); the 34 sentinel words feeding the stale-output
detector on both paths (every chunk of 64 nonces or more). Not reached here and covered by F10's emulation check
(`proto-cuda/nvrtc/emu/select-check.sh`, green on build-7 on 8 October): the high-32 rollover, the 96-nonce tail with a
32-lane launch, two queued jobs, a mismatch error then a job.
### 2.3 Finding X2-F1: identical work twice in a row restarts the worker (both paths)
The prod plan's first take sent phase 1 [0, 2^20) six times in a row at six targets. The second job of each context was
answered `error 2 worker fault: the output buffer is unchanged since the previous dispatch (signature ef40224d5958063d): the
kernel did not run; exiting 3 so the miner restarts the worker`, on the full and the select path alike (`evidence/prod-v1/`).
The stale-output detector (`worker.cpp`, the first, middle and last output words plus an FNV of the first 32, compared with
the previous chunk's) assumes two consecutive chunks never carry the same work. A job re-sent with the same prehash and nonce
range breaks that assumption and the worker exits 3. Meaning: a miner or pool that re-sends an identical job (a reconnect
replay, a duplicated line) costs a worker restart, the NVRTC compile, cache and dataset build again (about 4 s on this card,
the `prepared` timings). Not a compaction fault and not fixed here (worker code, a separate owner); the plan's second take
puts a 64-nonce job of other nonces at target 0 between repeats. Owed: the worker lane's fix (the signature keyed with the
job's prehash and nonce base, or the check skipped when the job equals the previous one) with this repeat as its known-failed
case.
## 3. Measured rows (requirement 2)
Instrument: `tools/1p5x/x2/run-pairs.sh` driving `tools/1p5x/x2/serve-pair.sh` (F10's `proto-cuda/nvrtc/serve-bench.sh` at
1a938abe4 with nvidia-smi at 1 Hz, the batch at the worker's and the miner's 2^22, and the share check added): the worker in
`--serve` fed by a stub pool exactly as the miner feeds it (one job queued behind the one in flight), 1,024 jobs of 2^22
nonces per run (4,294,967,296 hashes, about 125 to 137 s), share target `00000fffffffffff` (one share per 2^20 nonces), every
found line's hash checked against the target at the submit point; `--race off`, variant base, 88 registers, 20 blocks per
SM. Four pairs in ABBA order (full, select / select, full / full, select / select, full), 5 s apart, 08:52 to 09:11 UTC; then
the kernel timer (`--bench --batch-log2 24 --batches 250`, the instrument behind the record's E_GPU rows) with nvidia-smi at 1
Hz around it, 09:11 to 09:13 UTC. Pack: the frozen object's own, context 02 `chain-seed-d20730` (0x2a1d6caab4c24564, day
20730, 1 GiB dataset). The card held 2,760 to 2,775 MHz SM in every run (no throttle; 270 to 290 W of a 450 W limit, the
memory chain bounds the hash on Ada as the connected-state rows found). Steady = from the worker's ready line to the last
done line; production = from the process start (setup about 4 s). `worker_cpu_s` reads 0.00 because the script reads
`/proc` of the coproc's subshell, not the worker: the host-side CPU row is not read (F10 read 2.3 to 2.6 s against 2.9 to
3.1 s per 32 jobs of 2^24 on the 5090). Generated by `python3 tools/1p5x/x2/summarize.py evidence/pairs` (the file
`evidence/pairs/summary.txt`):
| run | mode | prod_mhs | steady_mhs | steady_mean_w | nj_per_hash_steady | accepted | over_target | j_per_share_steady | steady_j_per_batch | worker_cpu_s | samples |
|---|---|---|---|---|---|---|---|---|---|---|---|
| x2-full-r1 | full | 30.78 | 31.75 | 268.4 | 8453.5 | 4223 | 0 | 8.598 | 35.5 | 0.00 | 135 |
| x2-full-r2 | full | 31.14 | 32.08 | 273.1 | 8513.1 | 4223 | 0 | 8.659 | 35.7 | 0.00 | 134 |
| x2-full-r3 | full | 30.46 | 31.37 | 269.9 | 8603.8 | 4223 | 0 | 8.750 | 36.1 | 0.00 | 136 |
| x2-full-r4 | full | 30.74 | 31.65 | 270.2 | 8537.1 | 4223 | 0 | 8.683 | 35.8 | 0.00 | 136 |
| x2-select-r1 | select | 33.66 | 34.88 | 288.0 | 8256.9 | 4223 | 0 | 8.397 | 34.6 | 0.00 | 123 |
| x2-select-r2 | select | 33.78 | 34.89 | 290.0 | 8311.8 | 4223 | 0 | 8.454 | 34.9 | 0.00 | 123 |
| x2-select-r3 | select | 33.77 | 34.89 | 289.3 | 8291.8 | 4223 | 0 | 8.434 | 34.8 | 0.00 | 123 |
| x2-select-r4 | select | 33.70 | 34.78 | 287.2 | 8257.6 | 4223 | 0 | 8.398 | 34.6 | 0.00 | 124 |
| mode | runs | steady MH/s (sd) | production MH/s | steady W | nJ per hash (sd) | J per accepted share | accepted shares per run |
|---|---|---|---|---|---|---|---|
| full | 4 | 31.71 (0.29) | 30.78 | 270.4 | 8526.9 (62.2) | 8.672 | 4223 |
| select | 4 | 34.86 (0.05) | 33.73 | 288.6 | 8279.5 (27.0) | 8.421 | 4223 |
paired g (select over full, nJ per hash) per pair: 0.9767, 0.9764, 0.9637, 0.9673; mean of means 0.9710
paired rate ratio (select over full) per pair: 1.0986, 1.0876, 1.1122, 1.0989; mean of means 1.0993
kernel timer: 35.057 MH/s, 289.8 W loaded, 8267.3 nJ per hash, fingerprint 01f51b9d4805e5e6
g against the kernel timer (select serving over --bench): 1.0015; full serving over --bench: 1.0314
| r0 (the brief's current ratio) | r_new with g = select/full | r_new with g = select/kernel timer |
|---|---|---|
| 1.6 | 1.554 | 1.602 |
| 2.0 | 1.942 | 2.003 |
| 2.4 | 2.330 | 2.404 |
(a = 1: the specialist side is not touched by a host-side result path; the identity r_new = r0 * g / a, the brief.)
What the rows say. The compacted path serves 9.9 percent more accepted shares per second (paired 1.088 to 1.112) and spends
2.9 percent fewer board joules per hash and per accepted share (paired g 0.964 to 0.977): the card draws 18 W more because
it is never idle between chunks, and finishes the same work 9.9 percent sooner. The uncompacted path's cost is visible in the
worker's own transfer line: 32 MiB read back and a host scan of 2^22 words per chunk, during which the GPU waits (the
select path reads back 4 bytes, 34 sentinel words and 16 bytes per hit). The compacted path reaches the kernel timer: 34.86
against 35.06 MH/s (99.4 percent), 8,280 against 8,267 nJ per hash. Accepted shares per run are 4,223 on both paths with 0
over the target; the equivalence of section 2 is what makes a found line on either path the same share.
Beside F10 (2^24 batch, 4 Hz, pack hl-v6-all): 5090 rate +10.5 percent and J per batch -2.8 percent; 3090 +8.8 and -6.7.
The 4090 here: +9.9 and -2.9. Three cards, one direction, the joule saving 2.8 to 6.7 percent and the rate 8.8 to 10.5.
Consequences per tier (the standing rule). A home miner on any NVIDIA card running a CUDA worker without the select pass
loses about a tenth of its serving rate and 3 to 7 percent of its joules per share to the full read; the gen-6 Linux CUDA
worker on build-1 (`/srv/artefacts/packs/igneum-worker-cuda-gen6`, 804a6f7f, built from db63e1e36 before the class-v6 merge
of 964cdf6c) carries no `igneum_select` (strings read: 0), so a class v6 kit cut from 1a938abe4 is what moves those miners
(the kit lane's cut, not this lane's). AMD and Intel on the OpenCL worker have had the pass since 5 October. Apple's Metal
worker reads from unified memory, so its read-back is not a bus transfer; it is not measured here. A pool user sees the same shares sooner; the pool
sees nothing else (the found line is unchanged).
## 4. The arithmetic (requirement 3)
The brief's identity: r_new = r0 * g / a, with g and a the new-to-old GPU and specialist energies per equivalent accepted
work. The compaction is a host-side result path; nothing in it touches the specialist, so a = 1 (stated, not measured). Two
values of g, because the yardstick matters:
| g | Value (4090, stock) | Meaning |
|---|---|---|
| select serving over full serving | 0.971 (paired 0.964 to 0.977) | what a miner on an uncompacted worker gains by moving to the compacted one |
| select serving over the kernel timer | 1.0015 | what the compaction does to the E_GPU the ratio is computed from |
| full serving over the kernel timer | 1.031 | the serving loss the full read adds above the yardstick |
| r0 (the brief's ratios) | r_new, g = select/full | r_new, g = select/kernel timer |
|---|---|---|
| 1.6 (the pure DRAM board, node-for-node) | 1.554 | 1.602 |
| 2.0 (the brief's worked row) | 1.942 | 2.003 |
| 2.4 (the stored-half hybrid, the N2 SRAM die) | 2.330 | 2.404 |
Reading. The record's E_GPU rows come from the kernel timer (`igneum-worker-cuda --bench`, 250 x 2^24, nvidia-smi 1 Hz;
connected-state.md section 4, the l8off knee rows), which never includes the read-back, so the full read's 3 percent was
never in r0. Against the ratio's own yardstick X2 moves r by nothing measurable (g = 1.0015, inside the paired spread). The
brief's 1.5x target needs g = 0.75 from a ratio of 2.0 with a = 1; the compaction supplies 0.971 only against a worse
baseline that the ratio does not use. No percentage here is invented: every figure is the measured difference above, on one
card at stock. The saving the brief asked about is real for miners and zero for the ratio.
## 5. BLOCKED and NOT RUN rows
| Row | Decision | Reason | What unblocks it |
|---|---|---|---|
| Wall joules (the brief's word) | BLOCKED | a rented container has no wall meter and no host rail; every joule here is the board's nvidia-smi reading, and the host side is the worker's CPU seconds | a host with a wall meter on the card's machine |
| The knee (the 1,300 MHz lock or a power cap) | NOT RUN | no clock lock on a rented pod (`nvidia-smi -lgc` and `-pl` refused on fk-x2-4090, and on every 8 October pod by the fleet lane's record); the house rigs unreachable (the coordinator's amendment, 10:4x UK); the CUDA worker has no in-kernel throttle | a host that permits `-lgc` |
| The 5090 and other tiers on this harness | NOT RUN | one pod for this lane; the 5090 and 3090 pairs are F10's at stock (2^24 batch, 4 Hz) | another pod on the same scripts |
| The fused compare (no per-nonce write at all) | NOT RUN | it changes the emitter's output (`emit.rs`), outside this lane | a lane that owns the emitter, after X1 |
| CPU re-check of the bench's accepted shares | NOT RUN | the bench jobs use prehash = job index, which the references do not cover; the shares are counted as found lines whose hash is at or under the share target (all of them, `over_target=0`); the hash word itself is the one section 2 proves byte-identical to the CPU reference | `igneum-pow hash-bound` for the found nonces on a box |
| X2-F1 fix | NOT RUN | worker code, separate owner | the worker lane |
| Registry | NOT RUN | `tools/1p5x/x2/registry-batch-x2-1p5x-20261009.json`, both cells NOT RUN, method GPU, evidence by file; kept out of `tools/ci/batches/` so the landing writes no registry row; the steward records | the steward |
## 6. Commands
```
# on the GPU host, under /root/x2/pids (pid files; never on the Mac)
g++ -std=c++17 -O2 -Wall -Wextra -I proto-cuda/nvrtc -I /usr/local/cuda/include -o bin/igneum-worker-cuda proto-cuda/nvrtc/worker.cpp -ldl -lpthread # tree: git archive 1a938abe4
python3 tools/1p5x/x2/x2-equiv.py --self-test
tools/1p5x/x2/run-equiv.sh bin/igneum-worker-cuda ctx out/equiv pids # kf known-failed first, then prod and fuzz per context
tools/1p5x/x2/run-pairs.sh bin/igneum-worker-cuda ctx/same-work-20261008-02/packs/chain-seed-d20730 out/pairs pids 4 1024 22
python3 tools/1p5x/x2/summarize.py out/pairs # every figure of sections 3 and 4
```

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5f1e591db673f964ff53a60ebb9ea0e8f4cad974642a2354b3cc27571d935340 equiv/same-work-20261008-01.fuzz.expected.norm
5f1e591db673f964ff53a60ebb9ea0e8f4cad974642a2354b3cc27571d935340 equiv/same-work-20261008-01.fuzz.full.norm
5f1e591db673f964ff53a60ebb9ea0e8f4cad974642a2354b3cc27571d935340 equiv/same-work-20261008-01.fuzz.select.norm
e3e8913fb6788dfbbba4d43de14d674fa411de019980e2fc543be4ed7c17303c equiv/same-work-20261008-01.kf.expected.norm
f7ad6ee87564f49abaee8e8ee64b62e41c6a45259c0cace233aecb898cbd78aa equiv/same-work-20261008-01.kf.fault.norm
e3e8913fb6788dfbbba4d43de14d674fa411de019980e2fc543be4ed7c17303c equiv/same-work-20261008-01.kf.full.norm
e3e8913fb6788dfbbba4d43de14d674fa411de019980e2fc543be4ed7c17303c equiv/same-work-20261008-01.kf.select.norm
f278f0594dfd566d48fb59ee6b2f2889c60afb341856cf9efd53cce0d57ad60f equiv/same-work-20261008-01.prod.expected.norm
f278f0594dfd566d48fb59ee6b2f2889c60afb341856cf9efd53cce0d57ad60f equiv/same-work-20261008-01.prod.full.norm
f278f0594dfd566d48fb59ee6b2f2889c60afb341856cf9efd53cce0d57ad60f equiv/same-work-20261008-01.prod.select.norm
8f39a1b15b16e86f09bedeaa9d2f811cd6329012a71139e93babd5199f468938 equiv/same-work-20261008-02.fuzz.expected.norm
8f39a1b15b16e86f09bedeaa9d2f811cd6329012a71139e93babd5199f468938 equiv/same-work-20261008-02.fuzz.full.norm
8f39a1b15b16e86f09bedeaa9d2f811cd6329012a71139e93babd5199f468938 equiv/same-work-20261008-02.fuzz.select.norm
ad091a0d49a9d3a2b6206873ab5c9639d62e76cb5e65006aa730e3444e0a24d7 equiv/same-work-20261008-02.prod.expected.norm
ad091a0d49a9d3a2b6206873ab5c9639d62e76cb5e65006aa730e3444e0a24d7 equiv/same-work-20261008-02.prod.full.norm
ad091a0d49a9d3a2b6206873ab5c9639d62e76cb5e65006aa730e3444e0a24d7 equiv/same-work-20261008-02.prod.select.norm
3a7a7cc495e2d4853f5c85b59309ccee637ae5f9d446b806c577ca904f54785f equiv/same-work-20261008-03.fuzz.expected.norm
3a7a7cc495e2d4853f5c85b59309ccee637ae5f9d446b806c577ca904f54785f equiv/same-work-20261008-03.fuzz.full.norm
3a7a7cc495e2d4853f5c85b59309ccee637ae5f9d446b806c577ca904f54785f equiv/same-work-20261008-03.fuzz.select.norm
2aa97d5d63e5e01cb9fafc2d2508ad5df1c576467dfc46cb72b714fea35c93a5 equiv/same-work-20261008-03.prod.expected.norm
2aa97d5d63e5e01cb9fafc2d2508ad5df1c576467dfc46cb72b714fea35c93a5 equiv/same-work-20261008-03.prod.full.norm
2aa97d5d63e5e01cb9fafc2d2508ad5df1c576467dfc46cb72b714fea35c93a5 equiv/same-work-20261008-03.prod.select.norm
52a0f79483ce948b83c4bcde39ce37b89fdf04091826e14f56260717e0d8fce6 equiv-prod-v1/same-work-20261008-01.prod.expected.norm
2f7f1de48a50650a50daf8835c6c86eba981a155b28cc4bc5a5990f74ea56a12 equiv-prod-v1/same-work-20261008-01.prod.full.norm
2f7f1de48a50650a50daf8835c6c86eba981a155b28cc4bc5a5990f74ea56a12 equiv-prod-v1/same-work-20261008-01.prod.select.norm
db89fbfc3a7a7b595555e9d150fa82b93ef2ecc1f0944f69f759b3ebd39cc685 equiv-prod-v1/same-work-20261008-02.prod.expected.norm
f8a898c426596d8a482139309d6d9a85493ff2d1da8ef099406d97db168bcc9f equiv-prod-v1/same-work-20261008-02.prod.full.norm
f8a898c426596d8a482139309d6d9a85493ff2d1da8ef099406d97db168bcc9f equiv-prod-v1/same-work-20261008-02.prod.select.norm
8e9c9955eda5f46377ffb0afd5e0558760019885d725d2547c1232c6fc939362 equiv-prod-v1/same-work-20261008-03.prod.expected.norm
40778c06a13e40b329f17d9899bf8bcded6e2597f22670e6925d5d7aa5adcc75 equiv-prod-v1/same-work-20261008-03.prod.full.norm
40778c06a13e40b329f17d9899bf8bcded6e2597f22670e6925d5d7aa5adcc75 equiv-prod-v1/same-work-20261008-03.prod.select.norm

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack /root/x2/out/pairs/pack-chain-seed-d20730 on NVIDIA_GeForce_RTX_4090: nvrtc 2574 cache 3 dataset 28 hot 0 check 1144 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.32 ms; 250 timed dispatches of 16777216 nonces: mean 478.57 ms
RESULT pack=/root/x2/out/pairs/pack-chain-seed-d20730 class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=88 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=01f51b9d4805e5e6 mhs=35.057 loads=256 bytes=1024 scratch_ops=0 time=wall

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kernel_mhs=35.057 loaded_mean_w=289.8 samples=120 nj_per_hash=8267.3 fingerprint=01f51b9d4805e5e6

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2026/10/09 09:11:14.106, 46.06, 210, 40
2026/10/09 09:11:15.112, 39.67, 210, 40
2026/10/09 09:11:16.112, 36.08, 210, 40
2026/10/09 09:11:17.113, 50.73, 2520, 40
2026/10/09 09:11:18.113, 86.22, 2520, 40
2026/10/09 09:11:19.113, 85.68, 2520, 40
2026/10/09 09:11:20.113, 89.37, 2520, 39
2026/10/09 09:11:21.114, 165.06, 2775, 41
2026/10/09 09:11:22.114, 265.88, 2760, 46
2026/10/09 09:11:23.114, 288.06, 2760, 47
2026/10/09 09:11:24.114, 288.38, 2760, 47
2026/10/09 09:11:25.114, 288.50, 2760, 47
2026/10/09 09:11:26.114, 288.97, 2760, 47
2026/10/09 09:11:27.115, 288.99, 2760, 47
2026/10/09 09:11:28.115, 288.36, 2760, 48
2026/10/09 09:11:29.115, 288.95, 2760, 48
2026/10/09 09:11:30.115, 289.15, 2760, 48
2026/10/09 09:11:31.116, 288.99, 2760, 48
2026/10/09 09:11:32.116, 288.85, 2760, 48
2026/10/09 09:11:33.116, 289.21, 2760, 48
2026/10/09 09:11:34.116, 289.61, 2760, 48
2026/10/09 09:11:35.117, 289.60, 2760, 48
2026/10/09 09:11:36.117, 289.54, 2760, 49
2026/10/09 09:11:37.117, 289.36, 2760, 49
2026/10/09 09:11:38.117, 289.06, 2760, 49
2026/10/09 09:11:39.118, 289.00, 2760, 49
2026/10/09 09:11:40.118, 288.92, 2760, 49
2026/10/09 09:11:41.118, 289.17, 2760, 49
2026/10/09 09:11:42.118, 289.25, 2760, 49
2026/10/09 09:11:43.118, 289.38, 2760, 49
2026/10/09 09:11:44.119, 289.35, 2760, 49
2026/10/09 09:11:45.119, 289.08, 2760, 49
2026/10/09 09:11:46.119, 289.00, 2760, 49
2026/10/09 09:11:47.119, 289.10, 2760, 49
2026/10/09 09:11:48.119, 289.25, 2760, 49
2026/10/09 09:11:49.120, 289.37, 2760, 50
2026/10/09 09:11:50.120, 289.52, 2760, 50
2026/10/09 09:11:51.120, 289.84, 2760, 50
2026/10/09 09:11:52.120, 289.88, 2760, 50
2026/10/09 09:11:53.120, 290.05, 2760, 50
2026/10/09 09:11:54.121, 289.83, 2760, 50
2026/10/09 09:11:55.121, 289.86, 2760, 50
2026/10/09 09:11:56.121, 290.22, 2760, 50
2026/10/09 09:11:57.121, 290.16, 2760, 50
2026/10/09 09:11:58.122, 289.94, 2760, 50
2026/10/09 09:11:59.122, 290.63, 2760, 50
2026/10/09 09:12:00.122, 290.45, 2760, 50
2026/10/09 09:12:01.122, 290.58, 2760, 50
2026/10/09 09:12:02.122, 291.19, 2760, 50
2026/10/09 09:12:03.123, 291.22, 2760, 50
2026/10/09 09:12:04.123, 291.30, 2760, 50
2026/10/09 09:12:05.123, 291.62, 2760, 50
2026/10/09 09:12:06.123, 291.70, 2760, 50
2026/10/09 09:12:07.124, 291.68, 2760, 51
2026/10/09 09:12:08.124, 291.31, 2760, 51
2026/10/09 09:12:09.124, 291.66, 2760, 51
2026/10/09 09:12:10.124, 291.41, 2760, 51
2026/10/09 09:12:11.125, 290.95, 2760, 51
2026/10/09 09:12:12.125, 290.96, 2760, 51
2026/10/09 09:12:13.125, 290.98, 2760, 51
2026/10/09 09:12:14.125, 291.01, 2760, 51
2026/10/09 09:12:15.126, 291.61, 2760, 51
2026/10/09 09:12:16.126, 291.45, 2760, 51
2026/10/09 09:12:17.126, 291.76, 2760, 51
2026/10/09 09:12:18.126, 291.73, 2760, 51
2026/10/09 09:12:19.127, 291.65, 2760, 51
2026/10/09 09:12:20.127, 291.78, 2760, 51
2026/10/09 09:12:21.127, 291.79, 2760, 51
2026/10/09 09:12:22.128, 291.68, 2760, 51
2026/10/09 09:12:23.128, 291.47, 2760, 51
2026/10/09 09:12:24.128, 291.69, 2760, 51
2026/10/09 09:12:25.128, 291.60, 2760, 51
2026/10/09 09:12:26.129, 291.90, 2760, 51
2026/10/09 09:12:27.129, 291.80, 2760, 51
2026/10/09 09:12:28.129, 291.42, 2760, 51
2026/10/09 09:12:29.129, 291.95, 2760, 51
2026/10/09 09:12:30.129, 291.47, 2760, 51
2026/10/09 09:12:31.130, 291.26, 2760, 51
2026/10/09 09:12:32.130, 291.78, 2760, 51
2026/10/09 09:12:33.130, 291.73, 2760, 51
2026/10/09 09:12:34.130, 291.73, 2760, 51
2026/10/09 09:12:35.131, 292.38, 2760, 51
2026/10/09 09:12:36.131, 292.33, 2760, 51
2026/10/09 09:12:37.131, 292.52, 2760, 51
2026/10/09 09:12:38.131, 292.28, 2760, 52
2026/10/09 09:12:39.132, 292.36, 2760, 52
2026/10/09 09:12:40.132, 292.54, 2760, 52
2026/10/09 09:12:41.132, 292.07, 2760, 52
2026/10/09 09:12:42.132, 291.84, 2760, 52
2026/10/09 09:12:43.132, 291.90, 2760, 52
2026/10/09 09:12:44.133, 292.01, 2760, 52
2026/10/09 09:12:45.133, 292.71, 2760, 52
2026/10/09 09:12:46.133, 291.98, 2760, 52
2026/10/09 09:12:47.133, 292.16, 2760, 52
2026/10/09 09:12:48.133, 292.44, 2760, 52
2026/10/09 09:12:49.134, 292.08, 2760, 52
2026/10/09 09:12:50.134, 292.25, 2760, 52
2026/10/09 09:12:51.134, 291.91, 2760, 52
2026/10/09 09:12:52.134, 291.98, 2760, 52
2026/10/09 09:12:53.134, 292.34, 2760, 52
2026/10/09 09:12:54.135, 292.46, 2760, 52
2026/10/09 09:12:55.135, 292.54, 2760, 52
2026/10/09 09:12:56.135, 292.18, 2760, 52
2026/10/09 09:12:57.135, 292.31, 2760, 52
2026/10/09 09:12:58.136, 292.52, 2760, 52
2026/10/09 09:12:59.136, 292.52, 2760, 52
2026/10/09 09:13:00.136, 292.69, 2760, 52
2026/10/09 09:13:01.136, 292.01, 2760, 52
2026/10/09 09:13:02.137, 292.35, 2760, 52
2026/10/09 09:13:03.137, 292.79, 2760, 52
2026/10/09 09:13:04.137, 292.60, 2760, 52
2026/10/09 09:13:05.137, 292.39, 2760, 52
2026/10/09 09:13:06.137, 291.99, 2760, 52
2026/10/09 09:13:07.138, 291.90, 2760, 52
2026/10/09 09:13:08.138, 292.00, 2760, 52
2026/10/09 09:13:09.138, 292.40, 2760, 52
2026/10/09 09:13:10.138, 292.42, 2760, 52
2026/10/09 09:13:11.138, 292.40, 2760, 52
2026/10/09 09:13:12.139, 292.14, 2760, 52
2026/10/09 09:13:13.139, 292.12, 2760, 52
2026/10/09 09:13:14.139, 291.81, 2760, 52
2026/10/09 09:13:15.139, 291.77, 2760, 52
2026/10/09 09:13:16.139, 292.57, 2760, 52
2026/10/09 09:13:17.139, 292.16, 2760, 52
2026/10/09 09:13:18.140, 291.56, 2760, 52
2026/10/09 09:13:19.140, 291.96, 2760, 52
2026/10/09 09:13:20.140, 292.07, 2760, 52
2026/10/09 09:13:21.140, 244.38, 2760, 46
2026/10/09 09:13:22.140, 107.67, 2760, 45

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| run | mode | prod_mhs | steady_mhs | steady_mean_w | nj_per_hash_steady | accepted | over_target | j_per_share_steady | steady_j_per_batch | worker_cpu_s | samples |
|---|---|---|---|---|---|---|---|---|---|---|---|
| x2-full-r1 | full | 30.78 | 31.75 | 268.4 | 8453.5 | 4223 | 0 | 8.598 | 35.5 | 0.00 | 135 |
| x2-full-r2 | full | 31.14 | 32.08 | 273.1 | 8513.1 | 4223 | 0 | 8.659 | 35.7 | 0.00 | 134 |
| x2-full-r3 | full | 30.46 | 31.37 | 269.9 | 8603.8 | 4223 | 0 | 8.750 | 36.1 | 0.00 | 136 |
| x2-full-r4 | full | 30.74 | 31.65 | 270.2 | 8537.1 | 4223 | 0 | 8.683 | 35.8 | 0.00 | 136 |
| x2-select-r1 | select | 33.66 | 34.88 | 288.0 | 8256.9 | 4223 | 0 | 8.397 | 34.6 | 0.00 | 123 |
| x2-select-r2 | select | 33.78 | 34.89 | 290.0 | 8311.8 | 4223 | 0 | 8.454 | 34.9 | 0.00 | 123 |
| x2-select-r3 | select | 33.77 | 34.89 | 289.3 | 8291.8 | 4223 | 0 | 8.434 | 34.8 | 0.00 | 123 |
| x2-select-r4 | select | 33.70 | 34.78 | 287.2 | 8257.6 | 4223 | 0 | 8.398 | 34.6 | 0.00 | 124 |
| mode | runs | steady MH/s (sd) | production MH/s | steady W | nJ per hash (sd) | J per accepted share | accepted shares per run |
|---|---|---|---|---|---|---|---|
| full | 4 | 31.71 (0.29) | 30.78 | 270.4 | 8526.9 (62.2) | 8.672 | 4223 |
| select | 4 | 34.86 (0.05) | 33.73 | 288.6 | 8279.5 (27.0) | 8.421 | 4223 |
paired g (select over full, nJ per hash) per pair: 0.9767, 0.9764, 0.9637, 0.9673; mean of means 0.9710
paired rate ratio (select over full) per pair: 1.0986, 1.0876, 1.1122, 1.0989; mean of means 1.0993
kernel timer: 35.057 MH/s, 289.8 W loaded, 8267.3 nJ per hash, fingerprint 01f51b9d4805e5e6
g against the kernel timer (select serving over --bench): 1.0015; full serving over --bench: 1.0314
| r0 (the brief's current ratio) | r_new with g = select/full | r_new with g = select/kernel timer |
|---|---|---|
| 1.6 | 1.554 | 1.602 |
| 2.0 | 1.942 | 2.003 |
| 2.4 | 2.330 | 2.404 |
(a = 1: the specialist side is not touched by a host-side result path; the identity r_new = r0 * g / a, the brief.)

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card=NVIDIA_GeForce_RTX_4090 mode=full jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.238 prod_wall_s=139.523 prod_mhs=30.78 prod_mean_w=261.1 prod_j_per_batch=35.6 prod_mh_per_w=0.1179 samples=140 steady_wall_s=135.285 steady_mhs=31.75 steady_mean_w=268.4 steady_j_per_batch=35.5 steady_mh_per_w=0.1183 samples=135 accepted=4223 over_target=0 nj_per_hash_steady=8453.5 j_per_share_steady=8.598 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback full worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 33554432 B (full, 0 full fallbacks); mean per chunk: kernel+sync 119.79 ms, select 0.000 ms, read-back 6.433 ms, scan 5.746 ms; 1024 jobs 1024 chunks

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2026/10/09 08:52:20.540, 30.54, 210, 25
2026/10/09 08:52:21.547, 30.47, 210, 25
2026/10/09 08:52:22.547, 45.67, 2520, 26
2026/10/09 08:52:23.547, 83.23, 2520, 26
2026/10/09 08:52:24.547, 83.04, 2520, 27
2026/10/09 08:52:25.547, 87.12, 2520, 27
2026/10/09 08:52:26.548, 148.98, 2790, 32
2026/10/09 08:52:27.548, 266.91, 2790, 34
2026/10/09 08:52:28.548, 268.11, 2790, 34
2026/10/09 08:52:29.548, 269.74, 2790, 35
2026/10/09 08:52:30.548, 269.69, 2790, 35
2026/10/09 08:52:31.549, 267.72, 2775, 35
2026/10/09 08:52:32.550, 267.85, 2775, 36
2026/10/09 08:52:33.550, 268.28, 2775, 36
2026/10/09 08:52:34.551, 269.81, 2775, 37
2026/10/09 08:52:35.551, 270.04, 2775, 37
2026/10/09 08:52:36.551, 269.30, 2775, 36
2026/10/09 08:52:37.551, 270.31, 2775, 38
2026/10/09 08:52:38.551, 269.85, 2775, 38
2026/10/09 08:52:39.552, 270.02, 2775, 38
2026/10/09 08:52:40.552, 270.30, 2775, 38
2026/10/09 08:52:41.552, 268.29, 2775, 39
2026/10/09 08:52:42.552, 271.12, 2775, 39
2026/10/09 08:52:43.553, 270.18, 2775, 39
2026/10/09 08:52:44.553, 271.80, 2775, 39
2026/10/09 08:52:45.553, 271.85, 2775, 39
2026/10/09 08:52:46.553, 269.38, 2775, 39
2026/10/09 08:52:47.553, 265.64, 2775, 40
2026/10/09 08:52:48.554, 272.40, 2775, 40
2026/10/09 08:52:49.554, 272.97, 2775, 41
2026/10/09 08:52:50.554, 271.62, 2775, 41
2026/10/09 08:52:51.554, 272.04, 2775, 41
2026/10/09 08:52:52.554, 270.56, 2775, 41
2026/10/09 08:52:53.554, 272.13, 2775, 41
2026/10/09 08:52:54.555, 272.28, 2775, 41
2026/10/09 08:52:55.555, 270.70, 2775, 42
2026/10/09 08:52:56.556, 272.18, 2775, 42
2026/10/09 08:52:57.556, 272.93, 2775, 41
2026/10/09 08:52:58.556, 273.05, 2775, 41
2026/10/09 08:52:59.556, 272.07, 2775, 42
2026/10/09 08:53:00.556, 267.60, 2775, 42
2026/10/09 08:53:01.557, 267.03, 2775, 43
2026/10/09 08:53:02.557, 264.08, 2775, 42
2026/10/09 08:53:03.557, 266.77, 2775, 43
2026/10/09 08:53:04.557, 265.22, 2775, 43
2026/10/09 08:53:05.558, 266.39, 2775, 43
2026/10/09 08:53:06.558, 269.08, 2775, 43
2026/10/09 08:53:07.558, 267.74, 2775, 42
2026/10/09 08:53:08.558, 265.73, 2775, 43
2026/10/09 08:53:09.558, 265.49, 2775, 44
2026/10/09 08:53:10.559, 268.00, 2775, 44
2026/10/09 08:53:11.559, 266.07, 2775, 43
2026/10/09 08:53:12.559, 262.55, 2775, 44
2026/10/09 08:53:13.559, 267.61, 2775, 44
2026/10/09 08:53:14.560, 265.51, 2775, 44
2026/10/09 08:53:15.560, 266.86, 2775, 44
2026/10/09 08:53:16.560, 267.00, 2775, 44
2026/10/09 08:53:17.560, 268.22, 2775, 44
2026/10/09 08:53:18.560, 267.46, 2775, 44
2026/10/09 08:53:19.561, 267.45, 2775, 45
2026/10/09 08:53:20.561, 268.42, 2775, 44
2026/10/09 08:53:21.561, 267.91, 2775, 45
2026/10/09 08:53:22.561, 268.11, 2775, 44
2026/10/09 08:53:23.561, 269.76, 2775, 45
2026/10/09 08:53:24.562, 269.96, 2775, 45
2026/10/09 08:53:25.562, 269.33, 2775, 45
2026/10/09 08:53:26.562, 269.21, 2775, 45
2026/10/09 08:53:27.562, 268.87, 2775, 45
2026/10/09 08:53:28.562, 268.83, 2775, 45
2026/10/09 08:53:29.562, 268.79, 2775, 46
2026/10/09 08:53:30.563, 268.98, 2775, 45
2026/10/09 08:53:31.563, 268.23, 2760, 46
2026/10/09 08:53:32.563, 270.23, 2760, 44
2026/10/09 08:53:33.563, 267.15, 2760, 46
2026/10/09 08:53:34.563, 269.11, 2760, 44
2026/10/09 08:53:35.564, 269.95, 2760, 46
2026/10/09 08:53:36.564, 269.08, 2760, 44
2026/10/09 08:53:37.564, 270.01, 2760, 46
2026/10/09 08:53:38.564, 268.91, 2760, 44
2026/10/09 08:53:39.564, 267.24, 2760, 46
2026/10/09 08:53:40.564, 271.86, 2760, 45
2026/10/09 08:53:41.565, 270.68, 2760, 46
2026/10/09 08:53:42.565, 269.88, 2760, 44
2026/10/09 08:53:43.565, 265.21, 2760, 46
2026/10/09 08:53:44.565, 270.68, 2760, 47
2026/10/09 08:53:45.565, 269.00, 2760, 47
2026/10/09 08:53:46.565, 271.45, 2760, 47
2026/10/09 08:53:47.565, 268.02, 2760, 47
2026/10/09 08:53:48.565, 270.02, 2760, 47
2026/10/09 08:53:49.565, 267.69, 2760, 47
2026/10/09 08:53:50.566, 269.66, 2760, 47
2026/10/09 08:53:51.566, 267.02, 2760, 47
2026/10/09 08:53:52.566, 271.11, 2760, 47
2026/10/09 08:53:53.566, 267.69, 2760, 47
2026/10/09 08:53:54.566, 267.08, 2760, 47
2026/10/09 08:53:55.566, 266.10, 2760, 47
2026/10/09 08:53:56.567, 274.16, 2760, 46
2026/10/09 08:53:57.567, 267.51, 2760, 47
2026/10/09 08:53:58.567, 271.89, 2760, 45
2026/10/09 08:53:59.567, 269.58, 2760, 47
2026/10/09 08:54:00.567, 268.92, 2760, 46
2026/10/09 08:54:01.567, 267.82, 2760, 47
2026/10/09 08:54:02.568, 270.53, 2760, 46
2026/10/09 08:54:03.568, 270.64, 2760, 48
2026/10/09 08:54:04.568, 269.70, 2760, 47
2026/10/09 08:54:05.568, 269.34, 2760, 48
2026/10/09 08:54:06.568, 269.92, 2760, 46
2026/10/09 08:54:07.569, 269.09, 2760, 48
2026/10/09 08:54:08.569, 270.27, 2760, 46
2026/10/09 08:54:09.569, 268.85, 2760, 48
2026/10/09 08:54:10.569, 270.02, 2760, 47
2026/10/09 08:54:11.569, 268.22, 2760, 48
2026/10/09 08:54:12.570, 269.71, 2760, 48
2026/10/09 08:54:13.570, 267.21, 2760, 48
2026/10/09 08:54:14.570, 269.69, 2760, 48
2026/10/09 08:54:15.570, 267.52, 2760, 48
2026/10/09 08:54:16.570, 270.91, 2760, 48
2026/10/09 08:54:17.571, 268.89, 2760, 48
2026/10/09 08:54:18.571, 271.63, 2760, 48
2026/10/09 08:54:19.571, 269.82, 2760, 48
2026/10/09 08:54:20.571, 272.63, 2760, 48
2026/10/09 08:54:21.572, 268.91, 2760, 48
2026/10/09 08:54:22.572, 271.44, 2760, 48
2026/10/09 08:54:23.572, 269.83, 2760, 48
2026/10/09 08:54:24.572, 271.77, 2760, 48
2026/10/09 08:54:25.572, 267.96, 2760, 48
2026/10/09 08:54:26.572, 270.92, 2760, 49
2026/10/09 08:54:27.573, 268.28, 2760, 48
2026/10/09 08:54:28.573, 272.15, 2760, 49
2026/10/09 08:54:29.573, 269.73, 2760, 48
2026/10/09 08:54:30.573, 270.32, 2760, 49
2026/10/09 08:54:31.574, 268.03, 2760, 48
2026/10/09 08:54:32.574, 271.94, 2760, 49
2026/10/09 08:54:33.574, 269.47, 2760, 48
2026/10/09 08:54:34.574, 271.02, 2760, 49
2026/10/09 08:54:35.574, 268.35, 2760, 48
2026/10/09 08:54:36.574, 271.08, 2760, 49
2026/10/09 08:54:37.575, 268.37, 2760, 49
2026/10/09 08:54:38.575, 270.39, 2760, 49
2026/10/09 08:54:39.575, 269.01, 2760, 48
2026/10/09 08:54:40.575, 270.82, 2760, 49
2026/10/09 08:54:41.575, 251.37, 2760, 44

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=full jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.005 prod_wall_s=137.908 prod_mhs=31.14 prod_mean_w=267.3 prod_j_per_batch=36.0 prod_mh_per_w=0.1165 samples=138 steady_wall_s=133.903 steady_mhs=32.08 steady_mean_w=273.1 steady_j_per_batch=35.7 steady_mh_per_w=0.1175 samples=134 accepted=4223 over_target=0 nj_per_hash_steady=8513.1 j_per_share_steady=8.659 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback full worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 33554432 B (full, 0 full fallbacks); mean per chunk: kernel+sync 119.81 ms, select 0.000 ms, read-back 5.661 ms, scan 5.148 ms; 1024 jobs 1024 chunks

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@ -0,0 +1,140 @@
2026/10/09 08:59:19.764, 43.64, 210, 41
2026/10/09 08:59:20.770, 37.96, 210, 41
2026/10/09 08:59:21.770, 73.96, 2520, 41
2026/10/09 08:59:22.770, 87.36, 2520, 41
2026/10/09 08:59:23.771, 88.89, 2520, 41
2026/10/09 08:59:24.771, 87.73, 2520, 40
2026/10/09 08:59:25.771, 250.12, 2760, 46
2026/10/09 08:59:26.771, 266.11, 2760, 47
2026/10/09 08:59:27.772, 269.29, 2760, 47
2026/10/09 08:59:28.772, 267.14, 2760, 48
2026/10/09 08:59:29.772, 268.56, 2760, 46
2026/10/09 08:59:30.772, 269.14, 2760, 48
2026/10/09 08:59:31.773, 274.80, 2760, 48
2026/10/09 08:59:32.773, 275.35, 2760, 48
2026/10/09 08:59:33.773, 275.62, 2760, 48
2026/10/09 08:59:34.773, 276.48, 2760, 48
2026/10/09 08:59:35.773, 277.81, 2760, 48
2026/10/09 08:59:36.773, 276.80, 2760, 48
2026/10/09 08:59:37.774, 276.76, 2760, 49
2026/10/09 08:59:38.774, 274.29, 2760, 49
2026/10/09 08:59:39.774, 277.00, 2760, 48
2026/10/09 08:59:40.774, 278.54, 2760, 49
2026/10/09 08:59:41.774, 275.21, 2760, 48
2026/10/09 08:59:42.775, 273.17, 2760, 49
2026/10/09 08:59:43.775, 278.83, 2760, 49
2026/10/09 08:59:44.775, 277.56, 2760, 49
2026/10/09 08:59:45.775, 276.35, 2760, 48
2026/10/09 08:59:46.775, 276.63, 2760, 49
2026/10/09 08:59:47.776, 275.16, 2760, 49
2026/10/09 08:59:48.776, 276.64, 2760, 49
2026/10/09 08:59:49.776, 277.37, 2760, 49
2026/10/09 08:59:50.776, 276.12, 2760, 49
2026/10/09 08:59:51.776, 274.44, 2760, 49
2026/10/09 08:59:52.776, 278.67, 2760, 49
2026/10/09 08:59:53.776, 278.99, 2760, 49
2026/10/09 08:59:54.777, 277.74, 2760, 49
2026/10/09 08:59:55.777, 276.41, 2760, 50
2026/10/09 08:59:56.777, 277.59, 2760, 49
2026/10/09 08:59:57.777, 278.42, 2760, 49
2026/10/09 08:59:58.777, 278.40, 2760, 49
2026/10/09 08:59:59.778, 277.53, 2760, 49
2026/10/09 09:00:00.778, 278.25, 2760, 50
2026/10/09 09:00:01.778, 277.84, 2760, 50
2026/10/09 09:00:02.778, 279.25, 2760, 50
2026/10/09 09:00:03.779, 279.76, 2760, 50
2026/10/09 09:00:04.779, 278.89, 2760, 49
2026/10/09 09:00:05.779, 276.09, 2760, 50
2026/10/09 09:00:06.779, 276.98, 2760, 50
2026/10/09 09:00:07.779, 279.90, 2760, 50
2026/10/09 09:00:08.780, 279.15, 2760, 50
2026/10/09 09:00:09.780, 271.14, 2760, 50
2026/10/09 09:00:10.780, 271.12, 2760, 49
2026/10/09 09:00:11.780, 271.34, 2760, 50
2026/10/09 09:00:12.780, 271.80, 2760, 49
2026/10/09 09:00:13.781, 266.54, 2760, 50
2026/10/09 09:00:14.781, 271.71, 2760, 48
2026/10/09 09:00:15.781, 270.75, 2760, 50
2026/10/09 09:00:16.781, 273.28, 2760, 49
2026/10/09 09:00:17.781, 269.96, 2760, 50
2026/10/09 09:00:18.781, 270.51, 2760, 48
2026/10/09 09:00:19.782, 271.05, 2760, 50
2026/10/09 09:00:20.782, 270.49, 2760, 50
2026/10/09 09:00:21.782, 274.32, 2760, 50
2026/10/09 09:00:22.782, 271.95, 2760, 49
2026/10/09 09:00:23.783, 276.32, 2760, 50
2026/10/09 09:00:24.783, 276.05, 2760, 50
2026/10/09 09:00:25.783, 272.14, 2760, 50
2026/10/09 09:00:26.783, 271.11, 2760, 50
2026/10/09 09:00:27.783, 271.23, 2760, 50
2026/10/09 09:00:28.784, 272.54, 2760, 50
2026/10/09 09:00:29.784, 272.16, 2760, 50
2026/10/09 09:00:30.784, 272.93, 2760, 50
2026/10/09 09:00:31.784, 273.94, 2760, 50
2026/10/09 09:00:32.784, 273.90, 2760, 50
2026/10/09 09:00:33.785, 273.38, 2760, 48
2026/10/09 09:00:34.786, 277.19, 2760, 50
2026/10/09 09:00:35.786, 275.67, 2760, 50
2026/10/09 09:00:36.786, 278.14, 2760, 49
2026/10/09 09:00:37.789, 278.08, 2760, 50
2026/10/09 09:00:38.790, 276.65, 2760, 50
2026/10/09 09:00:39.790, 277.18, 2760, 50
2026/10/09 09:00:40.790, 279.41, 2760, 50
2026/10/09 09:00:41.791, 279.42, 2760, 50
2026/10/09 09:00:42.791, 278.47, 2760, 50
2026/10/09 09:00:43.792, 275.61, 2760, 50
2026/10/09 09:00:44.792, 277.53, 2760, 50
2026/10/09 09:00:45.792, 277.70, 2760, 50
2026/10/09 09:00:46.795, 281.01, 2760, 49
2026/10/09 09:00:47.795, 278.59, 2760, 50
2026/10/09 09:00:48.797, 277.35, 2760, 50
2026/10/09 09:00:49.797, 278.25, 2760, 50
2026/10/09 09:00:50.797, 280.28, 2760, 50
2026/10/09 09:00:51.798, 279.47, 2760, 49
2026/10/09 09:00:52.798, 278.68, 2760, 51
2026/10/09 09:00:53.798, 279.03, 2760, 51
2026/10/09 09:00:54.800, 279.01, 2760, 50
2026/10/09 09:00:55.800, 280.40, 2760, 50
2026/10/09 09:00:56.800, 279.44, 2760, 50
2026/10/09 09:00:57.801, 278.99, 2760, 51
2026/10/09 09:00:58.801, 277.81, 2760, 51
2026/10/09 09:00:59.801, 274.94, 2760, 50
2026/10/09 09:01:00.801, 271.38, 2760, 51
2026/10/09 09:01:01.802, 274.13, 2760, 51
2026/10/09 09:01:02.802, 276.82, 2760, 50
2026/10/09 09:01:03.802, 274.14, 2760, 51
2026/10/09 09:01:04.802, 271.94, 2760, 50
2026/10/09 09:01:05.802, 274.88, 2760, 51
2026/10/09 09:01:06.803, 270.42, 2760, 50
2026/10/09 09:01:07.803, 274.53, 2760, 51
2026/10/09 09:01:08.803, 270.30, 2760, 50
2026/10/09 09:01:09.803, 273.16, 2760, 51
2026/10/09 09:01:10.804, 271.37, 2760, 50
2026/10/09 09:01:11.804, 275.66, 2760, 50
2026/10/09 09:01:12.804, 274.66, 2760, 50
2026/10/09 09:01:13.804, 274.17, 2760, 50
2026/10/09 09:01:14.805, 276.41, 2760, 50
2026/10/09 09:01:15.805, 270.87, 2760, 50
2026/10/09 09:01:16.805, 275.81, 2760, 50
2026/10/09 09:01:17.805, 272.57, 2760, 50
2026/10/09 09:01:18.805, 271.96, 2760, 50
2026/10/09 09:01:19.806, 271.33, 2760, 50
2026/10/09 09:01:20.806, 271.43, 2760, 49
2026/10/09 09:01:21.806, 271.50, 2760, 50
2026/10/09 09:01:22.806, 271.99, 2760, 49
2026/10/09 09:01:23.807, 271.64, 2760, 50
2026/10/09 09:01:24.807, 271.47, 2760, 49
2026/10/09 09:01:25.807, 271.04, 2760, 50
2026/10/09 09:01:26.807, 272.60, 2760, 49
2026/10/09 09:01:27.807, 271.10, 2760, 50
2026/10/09 09:01:28.808, 272.94, 2760, 50
2026/10/09 09:01:29.808, 274.18, 2760, 50
2026/10/09 09:01:30.808, 271.37, 2760, 50
2026/10/09 09:01:31.808, 271.38, 2760, 50
2026/10/09 09:01:32.809, 271.23, 2760, 48
2026/10/09 09:01:33.809, 272.70, 2760, 50
2026/10/09 09:01:34.809, 270.80, 2760, 48
2026/10/09 09:01:35.809, 270.57, 2760, 50
2026/10/09 09:01:36.809, 270.28, 2760, 51
2026/10/09 09:01:37.810, 268.51, 2760, 50
2026/10/09 09:01:38.810, 260.61, 2760, 46

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=full jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.100 prod_wall_s=141.006 prod_mhs=30.46 prod_mean_w=262.8 prod_j_per_batch=36.2 prod_mh_per_w=0.1159 samples=141 steady_wall_s=136.906 steady_mhs=31.37 steady_mean_w=269.9 steady_j_per_batch=36.1 steady_mh_per_w=0.1162 samples=136 accepted=4223 over_target=0 nj_per_hash_steady=8603.8 j_per_share_steady=8.750 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback full worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 33554432 B (full, 0 full fallbacks); mean per chunk: kernel+sync 119.80 ms, select 0.000 ms, read-back 8.203 ms, scan 5.549 ms; 1024 jobs 1024 chunks

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@ -0,0 +1,144 @@
2026/10/09 09:01:45.776, 40.33, 210, 40
2026/10/09 09:01:46.783, 35.33, 210, 39
2026/10/09 09:01:47.783, 54.14, 2520, 40
2026/10/09 09:01:48.784, 84.70, 2520, 40
2026/10/09 09:01:49.784, 87.41, 2520, 40
2026/10/09 09:01:50.784, 90.21, 2520, 39
2026/10/09 09:01:51.784, 220.66, 2775, 46
2026/10/09 09:01:52.784, 268.13, 2760, 46
2026/10/09 09:01:53.785, 268.84, 2760, 47
2026/10/09 09:01:54.785, 270.12, 2760, 47
2026/10/09 09:01:55.785, 266.54, 2760, 47
2026/10/09 09:01:56.785, 265.58, 2760, 46
2026/10/09 09:01:57.786, 267.10, 2760, 47
2026/10/09 09:01:58.786, 267.89, 2760, 46
2026/10/09 09:01:59.786, 267.24, 2760, 47
2026/10/09 09:02:00.786, 271.65, 2760, 46
2026/10/09 09:02:01.787, 269.01, 2760, 47
2026/10/09 09:02:02.787, 253.90, 2760, 47
2026/10/09 09:02:03.787, 270.11, 2760, 48
2026/10/09 09:02:04.787, 266.46, 2760, 47
2026/10/09 09:02:05.788, 268.82, 2760, 48
2026/10/09 09:02:06.788, 268.61, 2760, 47
2026/10/09 09:02:07.789, 271.86, 2760, 48
2026/10/09 09:02:08.789, 269.28, 2760, 48
2026/10/09 09:02:09.789, 269.18, 2760, 48
2026/10/09 09:02:10.789, 269.39, 2760, 48
2026/10/09 09:02:11.790, 269.63, 2760, 48
2026/10/09 09:02:12.790, 267.38, 2760, 48
2026/10/09 09:02:13.790, 275.61, 2760, 48
2026/10/09 09:02:14.790, 270.16, 2760, 48
2026/10/09 09:02:15.790, 269.68, 2760, 47
2026/10/09 09:02:16.791, 269.80, 2760, 48
2026/10/09 09:02:17.791, 273.93, 2760, 48
2026/10/09 09:02:18.791, 269.80, 2760, 48
2026/10/09 09:02:19.791, 269.18, 2760, 48
2026/10/09 09:02:20.791, 269.68, 2760, 48
2026/10/09 09:02:21.792, 270.30, 2760, 48
2026/10/09 09:02:22.792, 270.76, 2760, 49
2026/10/09 09:02:23.792, 270.15, 2760, 48
2026/10/09 09:02:24.792, 270.67, 2760, 49
2026/10/09 09:02:25.792, 270.31, 2760, 48
2026/10/09 09:02:26.793, 269.45, 2760, 49
2026/10/09 09:02:27.793, 268.52, 2760, 48
2026/10/09 09:02:28.793, 270.55, 2760, 49
2026/10/09 09:02:29.793, 268.88, 2760, 49
2026/10/09 09:02:30.793, 271.43, 2760, 49
2026/10/09 09:02:31.794, 269.86, 2760, 49
2026/10/09 09:02:32.794, 270.83, 2760, 49
2026/10/09 09:02:33.794, 269.42, 2760, 49
2026/10/09 09:02:34.794, 271.53, 2760, 49
2026/10/09 09:02:35.794, 269.46, 2760, 49
2026/10/09 09:02:36.795, 271.12, 2760, 49
2026/10/09 09:02:37.795, 268.79, 2760, 49
2026/10/09 09:02:38.795, 270.62, 2760, 49
2026/10/09 09:02:39.796, 270.08, 2760, 49
2026/10/09 09:02:40.796, 270.69, 2760, 49
2026/10/09 09:02:41.796, 270.19, 2760, 49
2026/10/09 09:02:42.796, 270.93, 2760, 49
2026/10/09 09:02:43.796, 266.50, 2760, 47
2026/10/09 09:02:44.797, 275.51, 2760, 49
2026/10/09 09:02:45.797, 270.53, 2760, 49
2026/10/09 09:02:46.797, 273.10, 2760, 49
2026/10/09 09:02:47.797, 273.92, 2760, 49
2026/10/09 09:02:48.797, 273.39, 2760, 49
2026/10/09 09:02:49.798, 272.48, 2760, 49
2026/10/09 09:02:50.798, 272.67, 2760, 49
2026/10/09 09:02:51.799, 277.55, 2760, 49
2026/10/09 09:02:52.799, 278.97, 2760, 49
2026/10/09 09:02:53.799, 277.76, 2760, 48
2026/10/09 09:02:54.799, 231.03, 2760, 49
2026/10/09 09:02:55.800, 177.83, 2760, 49
2026/10/09 09:02:56.800, 275.73, 2760, 48
2026/10/09 09:02:57.800, 259.11, 2760, 49
2026/10/09 09:02:58.800, 277.54, 2760, 49
2026/10/09 09:02:59.800, 275.70, 2760, 49
2026/10/09 09:03:00.801, 271.41, 2760, 49
2026/10/09 09:03:01.801, 271.92, 2760, 48
2026/10/09 09:03:02.801, 277.60, 2760, 49
2026/10/09 09:03:03.801, 278.35, 2760, 49
2026/10/09 09:03:04.801, 177.28, 2760, 43
2026/10/09 09:03:05.802, 222.23, 2760, 49
2026/10/09 09:03:06.802, 276.97, 2760, 49
2026/10/09 09:03:07.802, 277.18, 2760, 49
2026/10/09 09:03:08.802, 277.03, 2760, 49
2026/10/09 09:03:09.802, 277.30, 2760, 49
2026/10/09 09:03:10.803, 277.23, 2760, 49
2026/10/09 09:03:11.803, 272.37, 2760, 49
2026/10/09 09:03:12.803, 277.38, 2760, 49
2026/10/09 09:03:13.803, 280.21, 2760, 49
2026/10/09 09:03:14.803, 278.21, 2760, 49
2026/10/09 09:03:15.804, 278.60, 2760, 49
2026/10/09 09:03:16.804, 277.48, 2760, 50
2026/10/09 09:03:17.804, 278.17, 2760, 50
2026/10/09 09:03:18.804, 275.38, 2760, 49
2026/10/09 09:03:19.804, 280.10, 2760, 49
2026/10/09 09:03:20.805, 275.29, 2760, 50
2026/10/09 09:03:21.805, 278.37, 2760, 50
2026/10/09 09:03:22.805, 279.24, 2760, 50
2026/10/09 09:03:23.805, 277.31, 2760, 49
2026/10/09 09:03:24.805, 228.04, 2760, 49
2026/10/09 09:03:25.806, 277.83, 2760, 49
2026/10/09 09:03:26.806, 271.42, 2760, 50
2026/10/09 09:03:27.806, 272.81, 2760, 49
2026/10/09 09:03:28.806, 272.29, 2760, 50
2026/10/09 09:03:29.806, 273.03, 2760, 49
2026/10/09 09:03:30.807, 272.48, 2760, 50
2026/10/09 09:03:31.807, 271.74, 2760, 49
2026/10/09 09:03:32.807, 271.24, 2760, 50
2026/10/09 09:03:33.807, 271.99, 2760, 49
2026/10/09 09:03:34.808, 277.48, 2760, 49
2026/10/09 09:03:35.808, 276.23, 2760, 50
2026/10/09 09:03:36.808, 277.36, 2760, 50
2026/10/09 09:03:37.808, 279.18, 2760, 50
2026/10/09 09:03:38.808, 279.06, 2760, 50
2026/10/09 09:03:39.809, 275.63, 2760, 50
2026/10/09 09:03:40.809, 276.58, 2760, 50
2026/10/09 09:03:41.809, 277.23, 2760, 50
2026/10/09 09:03:42.809, 278.42, 2760, 50
2026/10/09 09:03:43.809, 277.19, 2760, 50
2026/10/09 09:03:44.809, 278.62, 2760, 50
2026/10/09 09:03:45.810, 278.46, 2760, 50
2026/10/09 09:03:46.810, 278.76, 2760, 50
2026/10/09 09:03:47.810, 277.82, 2760, 49
2026/10/09 09:03:48.810, 271.36, 2760, 50
2026/10/09 09:03:49.811, 272.60, 2760, 49
2026/10/09 09:03:50.811, 271.71, 2760, 50
2026/10/09 09:03:51.811, 273.16, 2760, 50
2026/10/09 09:03:52.811, 270.83, 2760, 50
2026/10/09 09:03:53.812, 274.01, 2760, 50
2026/10/09 09:03:54.812, 274.69, 2760, 49
2026/10/09 09:03:55.812, 271.38, 2760, 50
2026/10/09 09:03:56.812, 277.30, 2760, 49
2026/10/09 09:03:57.812, 272.29, 2760, 50
2026/10/09 09:03:58.813, 272.25, 2760, 50
2026/10/09 09:03:59.813, 270.46, 2760, 50
2026/10/09 09:04:00.813, 271.41, 2760, 50
2026/10/09 09:04:01.813, 269.86, 2760, 50
2026/10/09 09:04:02.814, 273.04, 2760, 50
2026/10/09 09:04:03.814, 271.18, 2760, 50
2026/10/09 09:04:04.814, 274.47, 2760, 50
2026/10/09 09:04:05.814, 271.48, 2760, 50
2026/10/09 09:04:06.815, 272.30, 2760, 50
2026/10/09 09:04:07.815, 266.81, 2760, 50
2026/10/09 09:04:08.815, 115.79, 2760, 44

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=full jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.010 prod_wall_s=139.724 prod_mhs=30.74 prod_mean_w=264.4 prod_j_per_batch=36.1 prod_mh_per_w=0.1163 samples=140 steady_wall_s=135.714 steady_mhs=31.65 steady_mean_w=270.2 steady_j_per_batch=35.8 steady_mh_per_w=0.1171 samples=136 accepted=4223 over_target=0 nj_per_hash_steady=8537.1 j_per_share_steady=8.683 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback full worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 33554432 B (full, 0 full fallbacks); mean per chunk: kernel+sync 119.79 ms, select 0.000 ms, read-back 6.631 ms, scan 5.962 ms; 1024 jobs 1024 chunks

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@ -0,0 +1,142 @@
2026/10/09 09:08:46.093, 48.60, 210, 41
2026/10/09 09:08:47.100, 42.60, 210, 41
2026/10/09 09:08:48.100, 51.20, 2520, 41
2026/10/09 09:08:49.100, 86.16, 2520, 41
2026/10/09 09:08:50.100, 85.30, 2520, 40
2026/10/09 09:08:51.101, 89.17, 2520, 40
2026/10/09 09:08:52.101, 192.27, 2760, 46
2026/10/09 09:08:53.101, 267.11, 2760, 47
2026/10/09 09:08:54.101, 264.91, 2760, 47
2026/10/09 09:08:55.102, 267.42, 2760, 47
2026/10/09 09:08:56.102, 269.58, 2760, 47
2026/10/09 09:08:57.102, 272.19, 2760, 48
2026/10/09 09:08:58.103, 268.53, 2760, 47
2026/10/09 09:08:59.103, 271.72, 2760, 48
2026/10/09 09:09:00.103, 274.45, 2760, 48
2026/10/09 09:09:01.103, 270.29, 2760, 46
2026/10/09 09:09:02.103, 268.87, 2760, 48
2026/10/09 09:09:03.104, 271.18, 2760, 47
2026/10/09 09:09:04.104, 268.76, 2760, 48
2026/10/09 09:09:05.104, 270.62, 2760, 47
2026/10/09 09:09:06.107, 267.92, 2760, 48
2026/10/09 09:09:07.107, 271.64, 2760, 47
2026/10/09 09:09:08.107, 273.08, 2760, 48
2026/10/09 09:09:09.107, 271.49, 2760, 48
2026/10/09 09:09:10.108, 273.38, 2760, 49
2026/10/09 09:09:11.108, 269.46, 2760, 48
2026/10/09 09:09:12.108, 271.59, 2760, 49
2026/10/09 09:09:13.108, 270.44, 2760, 48
2026/10/09 09:09:14.109, 272.31, 2760, 49
2026/10/09 09:09:15.109, 270.35, 2760, 48
2026/10/09 09:09:16.109, 270.74, 2760, 49
2026/10/09 09:09:17.109, 271.14, 2760, 49
2026/10/09 09:09:18.110, 271.72, 2760, 49
2026/10/09 09:09:19.110, 269.78, 2760, 49
2026/10/09 09:09:20.110, 272.89, 2760, 49
2026/10/09 09:09:21.110, 269.07, 2760, 49
2026/10/09 09:09:22.111, 269.73, 2760, 49
2026/10/09 09:09:23.111, 269.46, 2760, 49
2026/10/09 09:09:24.111, 272.11, 2760, 49
2026/10/09 09:09:25.111, 269.24, 2760, 49
2026/10/09 09:09:26.112, 272.83, 2760, 49
2026/10/09 09:09:27.112, 275.31, 2760, 49
2026/10/09 09:09:28.112, 273.48, 2760, 49
2026/10/09 09:09:29.112, 272.01, 2760, 49
2026/10/09 09:09:30.112, 270.89, 2760, 49
2026/10/09 09:09:31.113, 276.31, 2760, 49
2026/10/09 09:09:32.113, 268.75, 2760, 48
2026/10/09 09:09:33.113, 268.81, 2760, 49
2026/10/09 09:09:34.113, 270.31, 2760, 49
2026/10/09 09:09:35.114, 272.23, 2760, 49
2026/10/09 09:09:36.114, 271.67, 2760, 49
2026/10/09 09:09:37.114, 270.68, 2760, 49
2026/10/09 09:09:38.114, 271.38, 2760, 49
2026/10/09 09:09:39.115, 273.43, 2760, 50
2026/10/09 09:09:40.115, 272.61, 2760, 49
2026/10/09 09:09:41.115, 272.01, 2760, 49
2026/10/09 09:09:42.115, 270.87, 2760, 49
2026/10/09 09:09:43.116, 272.57, 2760, 50
2026/10/09 09:09:44.116, 270.46, 2760, 49
2026/10/09 09:09:45.116, 271.03, 2760, 50
2026/10/09 09:09:46.116, 269.90, 2760, 49
2026/10/09 09:09:47.116, 271.55, 2760, 50
2026/10/09 09:09:48.117, 271.51, 2760, 49
2026/10/09 09:09:49.117, 270.86, 2760, 50
2026/10/09 09:09:50.117, 269.92, 2760, 49
2026/10/09 09:09:51.118, 271.20, 2760, 50
2026/10/09 09:09:52.118, 271.03, 2760, 49
2026/10/09 09:09:53.118, 273.02, 2760, 50
2026/10/09 09:09:54.118, 270.91, 2760, 49
2026/10/09 09:09:55.119, 270.29, 2760, 50
2026/10/09 09:09:56.119, 270.75, 2760, 49
2026/10/09 09:09:57.119, 272.93, 2760, 50
2026/10/09 09:09:58.119, 273.64, 2760, 49
2026/10/09 09:09:59.119, 271.74, 2760, 50
2026/10/09 09:10:00.120, 271.17, 2760, 50
2026/10/09 09:10:01.120, 276.41, 2760, 50
2026/10/09 09:10:02.120, 270.75, 2760, 50
2026/10/09 09:10:03.120, 272.01, 2760, 49
2026/10/09 09:10:04.120, 268.45, 2760, 50
2026/10/09 09:10:05.121, 272.12, 2760, 49
2026/10/09 09:10:06.121, 268.86, 2760, 50
2026/10/09 09:10:07.121, 272.10, 2760, 49
2026/10/09 09:10:08.121, 270.48, 2760, 50
2026/10/09 09:10:09.121, 273.45, 2760, 50
2026/10/09 09:10:10.122, 273.44, 2760, 50
2026/10/09 09:10:11.122, 271.70, 2760, 49
2026/10/09 09:10:12.122, 272.21, 2760, 50
2026/10/09 09:10:13.122, 271.68, 2760, 49
2026/10/09 09:10:14.123, 271.94, 2760, 50
2026/10/09 09:10:15.123, 272.64, 2760, 50
2026/10/09 09:10:16.123, 271.32, 2760, 50
2026/10/09 09:10:17.123, 270.38, 2760, 49
2026/10/09 09:10:18.124, 274.93, 2760, 50
2026/10/09 09:10:19.124, 275.93, 2760, 50
2026/10/09 09:10:20.124, 278.30, 2760, 50
2026/10/09 09:10:21.124, 280.29, 2760, 50
2026/10/09 09:10:22.124, 276.02, 2760, 50
2026/10/09 09:10:23.125, 277.16, 2760, 50
2026/10/09 09:10:24.125, 277.49, 2760, 50
2026/10/09 09:10:25.125, 279.40, 2760, 50
2026/10/09 09:10:26.125, 278.73, 2760, 50
2026/10/09 09:10:27.125, 277.20, 2760, 50
2026/10/09 09:10:28.126, 277.27, 2760, 50
2026/10/09 09:10:29.126, 280.17, 2760, 50
2026/10/09 09:10:30.126, 276.92, 2760, 50
2026/10/09 09:10:31.126, 274.90, 2760, 50
2026/10/09 09:10:32.126, 279.08, 2760, 50
2026/10/09 09:10:33.127, 278.64, 2760, 50
2026/10/09 09:10:34.127, 270.81, 2760, 50
2026/10/09 09:10:35.127, 269.88, 2760, 50
2026/10/09 09:10:36.127, 270.61, 2760, 50
2026/10/09 09:10:37.127, 270.97, 2760, 50
2026/10/09 09:10:38.128, 272.65, 2760, 50
2026/10/09 09:10:39.128, 270.78, 2760, 50
2026/10/09 09:10:40.128, 272.94, 2760, 50
2026/10/09 09:10:41.128, 269.43, 2760, 50
2026/10/09 09:10:42.129, 272.37, 2760, 50
2026/10/09 09:10:43.129, 271.11, 2760, 50
2026/10/09 09:10:44.129, 272.56, 2760, 51
2026/10/09 09:10:45.129, 269.55, 2760, 50
2026/10/09 09:10:46.130, 276.54, 2760, 50
2026/10/09 09:10:47.130, 274.40, 2760, 50
2026/10/09 09:10:48.130, 274.00, 2760, 50
2026/10/09 09:10:49.130, 271.61, 2760, 50
2026/10/09 09:10:50.130, 274.79, 2760, 50
2026/10/09 09:10:51.131, 271.59, 2760, 50
2026/10/09 09:10:52.131, 271.37, 2760, 50
2026/10/09 09:10:53.131, 271.76, 2760, 50
2026/10/09 09:10:54.131, 272.44, 2760, 50
2026/10/09 09:10:55.132, 270.05, 2760, 50
2026/10/09 09:10:56.132, 271.91, 2760, 50
2026/10/09 09:10:57.132, 269.70, 2760, 50
2026/10/09 09:10:58.132, 272.08, 2760, 50
2026/10/09 09:10:59.132, 269.64, 2760, 50
2026/10/09 09:11:00.133, 271.48, 2760, 49
2026/10/09 09:11:01.133, 270.46, 2760, 50
2026/10/09 09:11:02.133, 271.80, 2760, 49
2026/10/09 09:11:03.133, 271.23, 2760, 50
2026/10/09 09:11:04.133, 272.28, 2760, 49
2026/10/09 09:11:05.134, 275.50, 2760, 51
2026/10/09 09:11:06.134, 273.62, 2760, 50
2026/10/09 09:11:07.134, 267.10, 2760, 49

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card=NVIDIA_GeForce_RTX_4090 mode=select jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.465 prod_wall_s=127.590 prod_mhs=33.66 prod_mean_w=279.5 prod_j_per_batch=34.8 prod_mh_per_w=0.1204 samples=128 steady_wall_s=123.125 steady_mhs=34.88 steady_mean_w=288.0 steady_j_per_batch=34.6 steady_mh_per_w=0.1211 samples=123 accepted=4223 over_target=0 nj_per_hash_steady=8256.9 j_per_share_steady=8.397 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback select worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 342 B (select, 0 full fallbacks); mean per chunk: kernel+sync 119.76 ms, select 0.161 ms, read-back 0.198 ms, scan 0.008 ms; 1024 jobs 1024 chunks

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@ -0,0 +1,130 @@
2026/10/09 08:54:48.491, 42.31, 210, 39
2026/10/09 08:54:49.504, 36.65, 210, 38
2026/10/09 08:54:50.504, 47.61, 2520, 39
2026/10/09 08:54:51.504, 85.52, 2520, 39
2026/10/09 08:54:52.504, 85.55, 2520, 38
2026/10/09 08:54:53.505, 89.41, 2520, 38
2026/10/09 08:54:54.505, 114.60, 2775, 43
2026/10/09 08:54:55.505, 281.13, 2775, 45
2026/10/09 08:54:56.506, 286.29, 2775, 45
2026/10/09 08:54:57.506, 286.60, 2775, 46
2026/10/09 08:54:58.506, 286.12, 2760, 46
2026/10/09 08:54:59.506, 286.28, 2760, 46
2026/10/09 08:55:00.507, 286.65, 2760, 46
2026/10/09 08:55:01.507, 285.75, 2760, 46
2026/10/09 08:55:02.507, 286.23, 2760, 46
2026/10/09 08:55:03.507, 286.75, 2760, 47
2026/10/09 08:55:04.507, 287.24, 2760, 47
2026/10/09 08:55:05.508, 287.42, 2760, 47
2026/10/09 08:55:06.508, 288.01, 2760, 47
2026/10/09 08:55:07.508, 287.94, 2760, 47
2026/10/09 08:55:08.508, 286.65, 2760, 47
2026/10/09 08:55:09.508, 286.43, 2760, 47
2026/10/09 08:55:10.508, 286.93, 2760, 47
2026/10/09 08:55:11.509, 288.09, 2760, 48
2026/10/09 08:55:12.509, 287.40, 2760, 48
2026/10/09 08:55:13.509, 287.36, 2760, 48
2026/10/09 08:55:14.509, 287.72, 2760, 48
2026/10/09 08:55:15.509, 288.10, 2760, 48
2026/10/09 08:55:16.510, 288.64, 2760, 48
2026/10/09 08:55:17.510, 287.92, 2760, 48
2026/10/09 08:55:18.510, 288.29, 2760, 48
2026/10/09 08:55:19.510, 288.70, 2760, 48
2026/10/09 08:55:20.511, 288.62, 2760, 48
2026/10/09 08:55:21.511, 289.16, 2760, 48
2026/10/09 08:55:22.511, 288.77, 2760, 48
2026/10/09 08:55:23.511, 289.04, 2760, 48
2026/10/09 08:55:24.511, 288.48, 2760, 49
2026/10/09 08:55:25.512, 288.80, 2760, 49
2026/10/09 08:55:26.512, 288.63, 2760, 49
2026/10/09 08:55:27.512, 288.83, 2760, 49
2026/10/09 08:55:28.512, 288.81, 2760, 49
2026/10/09 08:55:29.512, 288.97, 2760, 49
2026/10/09 08:55:30.513, 288.92, 2760, 49
2026/10/09 08:55:31.513, 288.83, 2760, 49
2026/10/09 08:55:32.513, 289.32, 2760, 49
2026/10/09 08:55:33.513, 289.20, 2760, 49
2026/10/09 08:55:34.514, 289.13, 2760, 49
2026/10/09 08:55:35.514, 289.06, 2760, 49
2026/10/09 08:55:36.514, 289.03, 2760, 49
2026/10/09 08:55:37.514, 289.23, 2760, 49
2026/10/09 08:55:38.514, 289.83, 2760, 49
2026/10/09 08:55:39.515, 289.76, 2760, 49
2026/10/09 08:55:40.515, 289.39, 2760, 49
2026/10/09 08:55:41.515, 289.59, 2760, 50
2026/10/09 08:55:42.515, 289.90, 2760, 50
2026/10/09 08:55:43.515, 289.95, 2760, 50
2026/10/09 08:55:44.516, 289.68, 2760, 50
2026/10/09 08:55:45.516, 289.62, 2760, 50
2026/10/09 08:55:46.516, 290.47, 2760, 50
2026/10/09 08:55:47.516, 290.23, 2760, 50
2026/10/09 08:55:48.516, 290.11, 2760, 50
2026/10/09 08:55:49.517, 290.14, 2760, 50
2026/10/09 08:55:50.517, 289.96, 2760, 50
2026/10/09 08:55:51.517, 289.99, 2760, 50
2026/10/09 08:55:52.517, 289.92, 2760, 50
2026/10/09 08:55:53.517, 290.20, 2760, 50
2026/10/09 08:55:54.518, 290.35, 2760, 50
2026/10/09 08:55:55.518, 289.38, 2760, 50
2026/10/09 08:55:56.518, 289.65, 2760, 50
2026/10/09 08:55:57.518, 289.79, 2760, 50
2026/10/09 08:55:58.519, 290.11, 2760, 50
2026/10/09 08:55:59.519, 290.22, 2760, 50
2026/10/09 08:56:00.519, 290.59, 2760, 50
2026/10/09 08:56:01.519, 290.39, 2760, 50
2026/10/09 08:56:02.519, 289.80, 2760, 50
2026/10/09 08:56:03.520, 290.12, 2760, 50
2026/10/09 08:56:04.520, 290.18, 2760, 50
2026/10/09 08:56:05.520, 290.65, 2760, 50
2026/10/09 08:56:06.520, 290.63, 2760, 50
2026/10/09 08:56:07.520, 290.66, 2760, 50
2026/10/09 08:56:08.521, 290.36, 2760, 51
2026/10/09 08:56:09.521, 290.08, 2760, 51
2026/10/09 08:56:10.521, 289.06, 2760, 51
2026/10/09 08:56:11.521, 288.95, 2760, 51
2026/10/09 08:56:12.521, 290.25, 2760, 51
2026/10/09 08:56:13.522, 290.21, 2760, 51
2026/10/09 08:56:14.522, 290.04, 2760, 51
2026/10/09 08:56:15.522, 289.89, 2760, 51
2026/10/09 08:56:16.522, 290.12, 2760, 51
2026/10/09 08:56:17.522, 290.35, 2760, 51
2026/10/09 08:56:18.523, 289.20, 2760, 51
2026/10/09 08:56:19.523, 289.27, 2760, 51
2026/10/09 08:56:20.523, 290.30, 2760, 51
2026/10/09 08:56:21.523, 291.06, 2760, 51
2026/10/09 08:56:22.523, 291.29, 2760, 51
2026/10/09 08:56:23.524, 290.65, 2760, 51
2026/10/09 08:56:24.524, 290.69, 2760, 51
2026/10/09 08:56:25.524, 290.79, 2760, 51
2026/10/09 08:56:26.524, 289.90, 2760, 51
2026/10/09 08:56:27.524, 290.38, 2760, 51
2026/10/09 08:56:28.525, 291.15, 2760, 51
2026/10/09 08:56:29.525, 290.25, 2760, 51
2026/10/09 08:56:30.525, 290.68, 2760, 51
2026/10/09 08:56:31.525, 290.37, 2760, 51
2026/10/09 08:56:32.525, 290.05, 2760, 51
2026/10/09 08:56:33.526, 290.67, 2760, 51
2026/10/09 08:56:34.526, 290.63, 2760, 51
2026/10/09 08:56:35.526, 291.04, 2760, 51
2026/10/09 08:56:36.526, 291.01, 2760, 51
2026/10/09 08:56:37.527, 290.50, 2760, 51
2026/10/09 08:56:38.527, 290.62, 2760, 51
2026/10/09 08:56:39.527, 290.85, 2760, 51
2026/10/09 08:56:40.527, 290.54, 2760, 51
2026/10/09 08:56:41.527, 290.46, 2760, 51
2026/10/09 08:56:42.528, 290.48, 2760, 51
2026/10/09 08:56:43.528, 290.63, 2760, 51
2026/10/09 08:56:44.528, 290.48, 2760, 51
2026/10/09 08:56:45.528, 291.11, 2760, 51
2026/10/09 08:56:46.529, 291.37, 2760, 51
2026/10/09 08:56:47.529, 291.30, 2760, 51
2026/10/09 08:56:48.529, 291.26, 2760, 51
2026/10/09 08:56:49.529, 290.99, 2760, 51
2026/10/09 08:56:50.529, 290.97, 2760, 51
2026/10/09 08:56:51.530, 290.49, 2760, 51
2026/10/09 08:56:52.530, 290.57, 2760, 51
2026/10/09 08:56:53.530, 290.66, 2760, 51
2026/10/09 08:56:54.530, 291.03, 2760, 51
2026/10/09 08:56:55.531, 290.34, 2760, 51
2026/10/09 08:56:56.531, 291.44, 2760, 51
2026/10/09 08:56:57.531, 264.60, 2760, 46

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=select jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.041 prod_wall_s=127.155 prod_mhs=33.78 prod_mean_w=281.5 prod_j_per_batch=35.0 prod_mh_per_w=0.1200 samples=128 steady_wall_s=123.114 steady_mhs=34.89 steady_mean_w=290.0 steady_j_per_batch=34.9 steady_mh_per_w=0.1203 samples=123 accepted=4223 over_target=0 nj_per_hash_steady=8311.8 j_per_share_steady=8.454 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback select worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 342 B (select, 0 full fallbacks); mean per chunk: kernel+sync 119.76 ms, select 0.142 ms, read-back 0.200 ms, scan 0.008 ms; 1024 jobs 1024 chunks

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@ -0,0 +1,130 @@
2026/10/09 08:57:04.291, 43.37, 210, 41
2026/10/09 08:57:05.297, 37.35, 210, 40
2026/10/09 08:57:06.297, 54.78, 2520, 41
2026/10/09 08:57:07.298, 85.57, 2520, 41
2026/10/09 08:57:08.298, 88.14, 2520, 40
2026/10/09 08:57:09.298, 90.74, 2520, 40
2026/10/09 08:57:10.298, 238.95, 2760, 47
2026/10/09 08:57:11.298, 287.73, 2760, 47
2026/10/09 08:57:12.299, 287.92, 2760, 47
2026/10/09 08:57:13.299, 288.22, 2760, 48
2026/10/09 08:57:14.299, 288.50, 2760, 48
2026/10/09 08:57:15.299, 288.53, 2760, 48
2026/10/09 08:57:16.300, 288.30, 2760, 48
2026/10/09 08:57:17.300, 288.55, 2760, 48
2026/10/09 08:57:18.300, 288.53, 2760, 48
2026/10/09 08:57:19.300, 288.08, 2760, 48
2026/10/09 08:57:20.300, 287.88, 2760, 49
2026/10/09 08:57:21.301, 288.58, 2760, 49
2026/10/09 08:57:22.301, 289.67, 2760, 49
2026/10/09 08:57:23.301, 289.51, 2760, 49
2026/10/09 08:57:24.301, 289.55, 2760, 49
2026/10/09 08:57:25.301, 289.42, 2760, 49
2026/10/09 08:57:26.301, 289.40, 2760, 49
2026/10/09 08:57:27.302, 289.13, 2760, 49
2026/10/09 08:57:28.302, 289.39, 2760, 49
2026/10/09 08:57:29.302, 289.71, 2760, 49
2026/10/09 08:57:30.302, 289.77, 2760, 49
2026/10/09 08:57:31.302, 289.40, 2760, 49
2026/10/09 08:57:32.302, 289.86, 2760, 49
2026/10/09 08:57:33.303, 289.52, 2760, 50
2026/10/09 08:57:34.303, 289.32, 2760, 50
2026/10/09 08:57:35.303, 289.63, 2760, 50
2026/10/09 08:57:36.303, 289.65, 2760, 50
2026/10/09 08:57:37.303, 289.27, 2760, 50
2026/10/09 08:57:38.304, 289.15, 2760, 50
2026/10/09 08:57:39.304, 290.16, 2760, 50
2026/10/09 08:57:40.304, 289.35, 2760, 50
2026/10/09 08:57:41.304, 290.01, 2760, 50
2026/10/09 08:57:42.304, 289.80, 2760, 50
2026/10/09 08:57:43.305, 290.64, 2760, 50
2026/10/09 08:57:44.305, 290.66, 2760, 50
2026/10/09 08:57:45.305, 290.47, 2760, 50
2026/10/09 08:57:46.305, 290.35, 2760, 50
2026/10/09 08:57:47.305, 290.53, 2760, 50
2026/10/09 08:57:48.306, 290.34, 2760, 50
2026/10/09 08:57:49.306, 289.97, 2760, 50
2026/10/09 08:57:50.306, 289.87, 2760, 50
2026/10/09 08:57:51.306, 289.86, 2760, 50
2026/10/09 08:57:52.306, 290.66, 2760, 50
2026/10/09 08:57:53.307, 290.26, 2760, 50
2026/10/09 08:57:54.307, 290.52, 2760, 50
2026/10/09 08:57:55.307, 290.12, 2760, 51
2026/10/09 08:57:56.307, 290.63, 2760, 51
2026/10/09 08:57:57.307, 290.57, 2760, 50
2026/10/09 08:57:58.308, 288.60, 2760, 51
2026/10/09 08:57:59.308, 290.34, 2760, 51
2026/10/09 08:58:00.308, 290.98, 2760, 51
2026/10/09 08:58:01.309, 291.02, 2760, 51
2026/10/09 08:58:02.309, 290.73, 2760, 51
2026/10/09 08:58:03.309, 290.92, 2760, 51
2026/10/09 08:58:04.309, 290.75, 2760, 51
2026/10/09 08:58:05.310, 290.38, 2760, 51
2026/10/09 08:58:06.310, 290.19, 2760, 51
2026/10/09 08:58:07.310, 290.68, 2760, 51
2026/10/09 08:58:08.310, 290.88, 2760, 51
2026/10/09 08:58:09.311, 290.61, 2760, 51
2026/10/09 08:58:10.311, 290.69, 2760, 51
2026/10/09 08:58:11.311, 290.67, 2760, 51
2026/10/09 08:58:12.311, 290.86, 2760, 51
2026/10/09 08:58:13.312, 290.58, 2760, 51
2026/10/09 08:58:14.312, 290.67, 2760, 51
2026/10/09 08:58:15.312, 290.85, 2760, 51
2026/10/09 08:58:16.312, 290.23, 2760, 51
2026/10/09 08:58:17.313, 290.90, 2760, 51
2026/10/09 08:58:18.313, 290.91, 2760, 51
2026/10/09 08:58:19.313, 290.74, 2760, 51
2026/10/09 08:58:20.313, 290.69, 2760, 51
2026/10/09 08:58:21.313, 290.86, 2760, 51
2026/10/09 08:58:22.314, 290.93, 2760, 51
2026/10/09 08:58:23.314, 291.05, 2760, 51
2026/10/09 08:58:24.314, 291.16, 2760, 51
2026/10/09 08:58:25.314, 290.88, 2760, 51
2026/10/09 08:58:26.314, 291.01, 2760, 51
2026/10/09 08:58:27.315, 290.85, 2760, 51
2026/10/09 08:58:28.315, 291.21, 2760, 51
2026/10/09 08:58:29.315, 291.38, 2760, 51
2026/10/09 08:58:30.316, 291.03, 2760, 51
2026/10/09 08:58:31.316, 291.05, 2760, 51
2026/10/09 08:58:32.316, 291.02, 2760, 52
2026/10/09 08:58:33.316, 290.71, 2760, 52
2026/10/09 08:58:34.316, 290.43, 2760, 51
2026/10/09 08:58:35.316, 289.99, 2760, 52
2026/10/09 08:58:36.317, 290.21, 2760, 52
2026/10/09 08:58:37.317, 290.23, 2760, 52
2026/10/09 08:58:38.317, 290.24, 2760, 52
2026/10/09 08:58:39.317, 290.71, 2760, 52
2026/10/09 08:58:40.317, 290.89, 2760, 52
2026/10/09 08:58:41.318, 290.68, 2760, 52
2026/10/09 08:58:42.318, 291.02, 2760, 52
2026/10/09 08:58:43.318, 290.83, 2760, 52
2026/10/09 08:58:44.318, 291.05, 2760, 52
2026/10/09 08:58:45.318, 291.52, 2760, 52
2026/10/09 08:58:46.319, 291.56, 2760, 52
2026/10/09 08:58:47.319, 291.40, 2760, 52
2026/10/09 08:58:48.319, 291.61, 2760, 52
2026/10/09 08:58:49.319, 291.38, 2760, 52
2026/10/09 08:58:50.319, 291.18, 2760, 52
2026/10/09 08:58:51.320, 290.96, 2760, 52
2026/10/09 08:58:52.320, 291.10, 2760, 52
2026/10/09 08:58:53.320, 291.06, 2760, 52
2026/10/09 08:58:54.320, 291.56, 2760, 52
2026/10/09 08:58:55.321, 291.08, 2760, 52
2026/10/09 08:58:56.321, 291.49, 2760, 52
2026/10/09 08:58:57.321, 291.82, 2760, 52
2026/10/09 08:58:58.321, 291.87, 2760, 52
2026/10/09 08:58:59.321, 291.57, 2760, 52
2026/10/09 08:59:00.321, 291.37, 2760, 52
2026/10/09 08:59:01.322, 291.48, 2760, 52
2026/10/09 08:59:02.322, 291.90, 2760, 52
2026/10/09 08:59:03.322, 291.97, 2760, 52
2026/10/09 08:59:04.322, 291.98, 2760, 52
2026/10/09 08:59:05.323, 291.81, 2760, 52
2026/10/09 08:59:06.323, 291.60, 2760, 52
2026/10/09 08:59:07.323, 291.63, 2760, 52
2026/10/09 08:59:08.323, 291.86, 2760, 52
2026/10/09 08:59:09.323, 291.78, 2760, 52
2026/10/09 08:59:10.324, 291.52, 2760, 52
2026/10/09 08:59:11.324, 291.64, 2760, 52
2026/10/09 08:59:12.324, 291.52, 2760, 52
2026/10/09 08:59:13.324, 148.19, 2760, 45

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=select jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=4.067 prod_wall_s=127.175 prod_mhs=33.77 prod_mean_w=280.8 prod_j_per_batch=34.9 prod_mh_per_w=0.1203 samples=128 steady_wall_s=123.107 steady_mhs=34.89 steady_mean_w=289.3 steady_j_per_batch=34.8 steady_mh_per_w=0.1206 samples=123 accepted=4223 over_target=0 nj_per_hash_steady=8291.8 j_per_share_steady=8.434 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback select worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 342 B (select, 0 full fallbacks); mean per chunk: kernel+sync 119.76 ms, select 0.147 ms, read-back 0.189 ms, scan 0.009 ms; 1024 jobs 1024 chunks

View file

@ -0,0 +1,130 @@
2026/10/09 09:04:14.899, 48.76, 210, 40
2026/10/09 09:04:15.904, 42.46, 210, 40
2026/10/09 09:04:16.904, 54.87, 2520, 40
2026/10/09 09:04:17.904, 84.82, 2520, 40
2026/10/09 09:04:18.904, 87.76, 2520, 39
2026/10/09 09:04:19.904, 89.72, 2520, 39
2026/10/09 09:04:20.905, 222.88, 2775, 46
2026/10/09 09:04:21.905, 286.65, 2760, 46
2026/10/09 09:04:22.905, 286.91, 2760, 47
2026/10/09 09:04:23.905, 287.32, 2760, 47
2026/10/09 09:04:24.905, 287.44, 2760, 47
2026/10/09 09:04:25.905, 287.60, 2760, 47
2026/10/09 09:04:26.906, 287.79, 2760, 47
2026/10/09 09:04:27.906, 287.96, 2760, 47
2026/10/09 09:04:28.906, 288.30, 2760, 48
2026/10/09 09:04:29.906, 287.69, 2760, 48
2026/10/09 09:04:30.906, 287.48, 2760, 48
2026/10/09 09:04:31.907, 287.43, 2760, 48
2026/10/09 09:04:32.907, 288.22, 2760, 48
2026/10/09 09:04:33.907, 288.42, 2760, 48
2026/10/09 09:04:34.907, 288.41, 2760, 48
2026/10/09 09:04:35.907, 288.15, 2760, 48
2026/10/09 09:04:36.908, 287.89, 2760, 48
2026/10/09 09:04:37.908, 287.44, 2760, 48
2026/10/09 09:04:38.908, 288.52, 2760, 49
2026/10/09 09:04:39.908, 288.28, 2760, 48
2026/10/09 09:04:40.908, 288.32, 2760, 49
2026/10/09 09:04:41.909, 288.69, 2760, 49
2026/10/09 09:04:42.909, 288.70, 2760, 49
2026/10/09 09:04:43.909, 288.60, 2760, 49
2026/10/09 09:04:44.909, 288.77, 2760, 49
2026/10/09 09:04:45.910, 289.64, 2760, 49
2026/10/09 09:04:46.910, 289.48, 2760, 49
2026/10/09 09:04:47.910, 289.59, 2760, 49
2026/10/09 09:04:48.910, 289.46, 2760, 49
2026/10/09 09:04:49.911, 289.35, 2760, 49
2026/10/09 09:04:50.911, 289.64, 2760, 49
2026/10/09 09:04:51.911, 289.61, 2760, 49
2026/10/09 09:04:52.911, 289.65, 2760, 49
2026/10/09 09:04:53.911, 289.59, 2760, 49
2026/10/09 09:04:54.912, 289.69, 2760, 50
2026/10/09 09:04:55.912, 289.47, 2760, 50
2026/10/09 09:04:56.912, 289.22, 2760, 50
2026/10/09 09:04:57.912, 289.80, 2760, 50
2026/10/09 09:04:58.912, 289.83, 2760, 50
2026/10/09 09:04:59.913, 289.71, 2760, 50
2026/10/09 09:05:00.913, 290.00, 2760, 50
2026/10/09 09:05:01.913, 290.13, 2760, 50
2026/10/09 09:05:02.913, 289.75, 2760, 50
2026/10/09 09:05:03.913, 288.27, 2760, 50
2026/10/09 09:05:04.914, 289.55, 2760, 50
2026/10/09 09:05:05.914, 289.89, 2760, 50
2026/10/09 09:05:06.914, 290.35, 2760, 50
2026/10/09 09:05:07.914, 290.35, 2760, 50
2026/10/09 09:05:08.914, 290.32, 2760, 50
2026/10/09 09:05:09.915, 290.39, 2760, 50
2026/10/09 09:05:10.915, 289.82, 2760, 50
2026/10/09 09:05:11.915, 289.72, 2760, 50
2026/10/09 09:05:12.915, 288.72, 2760, 50
2026/10/09 09:05:13.915, 289.57, 2760, 50
2026/10/09 09:05:14.916, 289.82, 2760, 50
2026/10/09 09:05:15.916, 290.28, 2760, 50
2026/10/09 09:05:16.916, 290.31, 2760, 50
2026/10/09 09:05:17.916, 290.17, 2760, 50
2026/10/09 09:05:18.917, 290.23, 2760, 50
2026/10/09 09:05:19.917, 290.01, 2760, 51
2026/10/09 09:05:20.917, 290.30, 2760, 51
2026/10/09 09:05:21.918, 290.05, 2760, 51
2026/10/09 09:05:22.919, 290.46, 2760, 51
2026/10/09 09:05:23.919, 290.11, 2760, 51
2026/10/09 09:05:24.919, 288.57, 2760, 51
2026/10/09 09:05:25.920, 290.10, 2760, 51
2026/10/09 09:05:26.920, 289.63, 2760, 51
2026/10/09 09:05:27.920, 289.60, 2760, 51
2026/10/09 09:05:28.920, 289.39, 2760, 51
2026/10/09 09:05:29.920, 290.67, 2760, 51
2026/10/09 09:05:30.921, 290.54, 2760, 51
2026/10/09 09:05:31.921, 290.12, 2760, 51
2026/10/09 09:05:32.921, 290.22, 2760, 51
2026/10/09 09:05:33.921, 290.17, 2760, 51
2026/10/09 09:05:34.922, 289.95, 2760, 51
2026/10/09 09:05:35.922, 289.98, 2760, 51
2026/10/09 09:05:36.922, 290.30, 2760, 51
2026/10/09 09:05:37.922, 290.22, 2760, 51
2026/10/09 09:05:38.922, 290.47, 2760, 51
2026/10/09 09:05:39.923, 290.92, 2760, 51
2026/10/09 09:05:40.923, 290.81, 2760, 51
2026/10/09 09:05:41.923, 290.47, 2760, 51
2026/10/09 09:05:42.923, 290.46, 2760, 51
2026/10/09 09:05:43.923, 290.53, 2760, 51
2026/10/09 09:05:44.924, 290.53, 2760, 51
2026/10/09 09:05:45.924, 291.22, 2760, 51
2026/10/09 09:05:46.924, 291.36, 2760, 51
2026/10/09 09:05:47.924, 291.02, 2760, 51
2026/10/09 09:05:48.924, 291.05, 2760, 51
2026/10/09 09:05:49.925, 290.76, 2760, 51
2026/10/09 09:05:50.925, 290.75, 2760, 51
2026/10/09 09:05:51.925, 290.26, 2760, 51
2026/10/09 09:05:52.925, 289.95, 2760, 51
2026/10/09 09:05:53.926, 289.96, 2760, 51
2026/10/09 09:05:54.926, 290.65, 2760, 51
2026/10/09 09:05:55.926, 290.92, 2760, 51
2026/10/09 09:05:56.927, 290.37, 2760, 51
2026/10/09 09:05:57.927, 290.81, 2760, 51
2026/10/09 09:05:58.927, 290.69, 2760, 51
2026/10/09 09:05:59.927, 290.45, 2760, 51
2026/10/09 09:06:00.927, 290.52, 2760, 51
2026/10/09 09:06:01.928, 290.82, 2760, 51
2026/10/09 09:06:02.928, 290.64, 2760, 51
2026/10/09 09:06:03.928, 290.74, 2760, 51
2026/10/09 09:06:04.928, 291.16, 2760, 51
2026/10/09 09:06:05.928, 291.35, 2760, 51
2026/10/09 09:06:06.929, 291.37, 2760, 51
2026/10/09 09:06:07.929, 291.70, 2760, 51
2026/10/09 09:06:08.929, 291.63, 2760, 51
2026/10/09 09:06:09.929, 291.39, 2760, 51
2026/10/09 09:06:10.929, 291.13, 2760, 51
2026/10/09 09:06:11.929, 290.65, 2760, 51
2026/10/09 09:06:12.930, 291.24, 2760, 52
2026/10/09 09:06:13.930, 291.12, 2760, 52
2026/10/09 09:06:14.930, 291.26, 2760, 52
2026/10/09 09:06:15.930, 291.19, 2760, 52
2026/10/09 09:06:16.930, 290.99, 2760, 52
2026/10/09 09:06:17.931, 289.77, 2760, 52
2026/10/09 09:06:18.931, 290.39, 2760, 52
2026/10/09 09:06:19.931, 290.64, 2760, 52
2026/10/09 09:06:20.931, 290.93, 2760, 52
2026/10/09 09:06:21.932, 291.03, 2760, 52
2026/10/09 09:06:22.932, 291.53, 2760, 52
2026/10/09 09:06:23.932, 176.32, 2760, 45

File diff suppressed because it is too large Load diff

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@ -0,0 +1,3 @@
card=NVIDIA_GeForce_RTX_4090 mode=select jobs=1024 batch_log2=22 hashes=4294967296 found=4223 setup_s=3.970 prod_wall_s=127.457 prod_mhs=33.70 prod_mean_w=280.5 prod_j_per_batch=34.9 prod_mh_per_w=0.1201 samples=128 steady_wall_s=123.487 steady_mhs=34.78 steady_mean_w=287.2 steady_j_per_batch=34.6 steady_mh_per_w=0.1211 samples=124 accepted=4223 over_target=0 nj_per_hash_steady=8257.6 j_per_share_steady=8.398 smi_ms=1000 worker_cpu_s=0.00 worker_sha=4152c960d1421007
ready: ready cuda NVIDIA_GeForce_RTX_4090 pack igneum-epoch/af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3/day/69676e65756d2d6461792ffa50000000000000 dataset-log2 28 batch 4194304 regs 88 prepare 1 path nvrtc 12.8 driver 13.2 arch sm_89 variant base race off readback select worker 1.0 (4 October 2026)
transfers: transfers per chunk: down 342 B (select, 0 full fallbacks); mean per chunk: kernel+sync 119.76 ms, select 0.428 ms, read-back 0.196 ms, scan 0.008 ms; 1024 jobs 1024 chunks

View file

@ -0,0 +1,130 @@
2026/10/09 09:06:30.330, 43.10, 210, 40
2026/10/09 09:06:31.338, 36.20, 210, 40
2026/10/09 09:06:32.338, 72.60, 2520, 41
2026/10/09 09:06:33.338, 86.35, 2520, 41
2026/10/09 09:06:34.339, 88.61, 2520, 40
2026/10/09 09:06:35.339, 85.50, 2520, 40
2026/10/09 09:06:36.339, 246.34, 2760, 47
2026/10/09 09:06:37.339, 287.22, 2760, 47
2026/10/09 09:06:38.340, 287.41, 2760, 47
2026/10/09 09:06:39.340, 286.68, 2760, 48
2026/10/09 09:06:40.340, 287.94, 2760, 48
2026/10/09 09:06:41.340, 287.66, 2760, 48
2026/10/09 09:06:42.340, 286.96, 2760, 48
2026/10/09 09:06:43.341, 288.18, 2760, 48
2026/10/09 09:06:44.341, 287.74, 2760, 48
2026/10/09 09:06:45.341, 287.61, 2760, 48
2026/10/09 09:06:46.341, 287.92, 2760, 48
2026/10/09 09:06:47.342, 287.86, 2760, 49
2026/10/09 09:06:48.342, 288.05, 2760, 49
2026/10/09 09:06:49.342, 287.85, 2760, 49
2026/10/09 09:06:50.342, 287.85, 2760, 49
2026/10/09 09:06:51.342, 287.73, 2760, 49
2026/10/09 09:06:52.343, 287.94, 2760, 49
2026/10/09 09:06:53.343, 288.28, 2760, 49
2026/10/09 09:06:54.343, 288.35, 2760, 49
2026/10/09 09:06:55.343, 289.17, 2760, 49
2026/10/09 09:06:56.344, 289.32, 2760, 49
2026/10/09 09:06:57.344, 289.35, 2760, 49
2026/10/09 09:06:58.344, 289.09, 2760, 49
2026/10/09 09:06:59.344, 288.91, 2760, 49
2026/10/09 09:07:00.345, 289.24, 2760, 49
2026/10/09 09:07:01.345, 289.90, 2760, 49
2026/10/09 09:07:02.345, 290.05, 2760, 50
2026/10/09 09:07:03.345, 290.09, 2760, 50
2026/10/09 09:07:04.345, 289.90, 2760, 50
2026/10/09 09:07:05.346, 289.67, 2760, 50
2026/10/09 09:07:06.346, 289.64, 2760, 50
2026/10/09 09:07:07.346, 289.58, 2760, 50
2026/10/09 09:07:08.346, 288.11, 2760, 50
2026/10/09 09:07:09.346, 273.31, 2760, 50
2026/10/09 09:07:10.347, 289.66, 2760, 50
2026/10/09 09:07:11.347, 289.07, 2760, 50
2026/10/09 09:07:12.347, 290.07, 2760, 50
2026/10/09 09:07:13.347, 289.72, 2760, 50
2026/10/09 09:07:14.347, 289.39, 2760, 50
2026/10/09 09:07:15.348, 261.93, 2760, 50
2026/10/09 09:07:16.348, 289.57, 2760, 50
2026/10/09 09:07:17.348, 289.11, 2760, 50
2026/10/09 09:07:18.348, 288.75, 2760, 50
2026/10/09 09:07:19.348, 289.74, 2760, 50
2026/10/09 09:07:20.348, 290.37, 2760, 50
2026/10/09 09:07:21.349, 290.27, 2760, 50
2026/10/09 09:07:22.349, 289.96, 2760, 50
2026/10/09 09:07:23.349, 290.61, 2760, 50
2026/10/09 09:07:24.349, 290.35, 2760, 50
2026/10/09 09:07:25.349, 290.05, 2760, 50
2026/10/09 09:07:26.350, 289.29, 2760, 51
2026/10/09 09:07:27.350, 288.93, 2760, 51
2026/10/09 09:07:28.350, 290.18, 2760, 51
2026/10/09 09:07:29.350, 290.11, 2760, 51
2026/10/09 09:07:30.350, 289.72, 2760, 51
2026/10/09 09:07:31.351, 288.96, 2760, 51
2026/10/09 09:07:32.351, 289.16, 2760, 51
2026/10/09 09:07:33.351, 289.38, 2760, 51
2026/10/09 09:07:34.351, 290.03, 2760, 51
2026/10/09 09:07:35.351, 289.74, 2760, 51
2026/10/09 09:07:36.352, 289.46, 2760, 51
2026/10/09 09:07:37.352, 289.91, 2760, 51
2026/10/09 09:07:38.352, 289.81, 2760, 51
2026/10/09 09:07:39.352, 289.53, 2760, 51
2026/10/09 09:07:40.352, 289.55, 2760, 51
2026/10/09 09:07:41.353, 289.54, 2760, 51
2026/10/09 09:07:42.353, 289.95, 2760, 51
2026/10/09 09:07:43.353, 289.73, 2760, 51
2026/10/09 09:07:44.353, 289.90, 2760, 51
2026/10/09 09:07:45.353, 290.21, 2760, 51
2026/10/09 09:07:46.353, 290.23, 2760, 51
2026/10/09 09:07:47.354, 290.85, 2760, 51
2026/10/09 09:07:48.354, 290.55, 2760, 51
2026/10/09 09:07:49.354, 290.43, 2760, 51
2026/10/09 09:07:50.354, 290.41, 2760, 51
2026/10/09 09:07:51.354, 290.09, 2760, 51
2026/10/09 09:07:52.355, 289.08, 2760, 51
2026/10/09 09:07:53.355, 290.65, 2760, 51
2026/10/09 09:07:54.355, 290.55, 2760, 51
2026/10/09 09:07:55.355, 275.14, 2760, 51
2026/10/09 09:07:56.355, 289.65, 2760, 51
2026/10/09 09:07:57.356, 289.93, 2760, 51
2026/10/09 09:07:58.356, 290.65, 2760, 51
2026/10/09 09:07:59.356, 290.93, 2760, 51
2026/10/09 09:08:00.356, 290.75, 2760, 51
2026/10/09 09:08:01.356, 291.05, 2760, 51
2026/10/09 09:08:02.357, 290.93, 2760, 51
2026/10/09 09:08:03.357, 290.65, 2760, 51
2026/10/09 09:08:04.357, 290.62, 2760, 51
2026/10/09 09:08:05.357, 290.72, 2760, 51
2026/10/09 09:08:06.357, 290.60, 2760, 51
2026/10/09 09:08:07.358, 290.71, 2760, 51
2026/10/09 09:08:08.358, 289.42, 2760, 51
2026/10/09 09:08:09.358, 290.10, 2760, 51
2026/10/09 09:08:10.358, 290.76, 2760, 51
2026/10/09 09:08:11.358, 290.32, 2760, 51
2026/10/09 09:08:12.359, 290.59, 2760, 51
2026/10/09 09:08:13.359, 290.76, 2760, 51
2026/10/09 09:08:14.359, 290.71, 2760, 51
2026/10/09 09:08:15.359, 291.16, 2760, 51
2026/10/09 09:08:16.360, 290.92, 2760, 51
2026/10/09 09:08:17.360, 290.89, 2760, 52
2026/10/09 09:08:18.360, 290.86, 2760, 51
2026/10/09 09:08:19.360, 290.56, 2760, 52
2026/10/09 09:08:20.360, 290.18, 2760, 52
2026/10/09 09:08:21.361, 290.49, 2760, 52
2026/10/09 09:08:22.361, 290.16, 2760, 52
2026/10/09 09:08:23.361, 290.18, 2760, 52
2026/10/09 09:08:24.361, 290.26, 2760, 52
2026/10/09 09:08:25.362, 290.56, 2760, 52
2026/10/09 09:08:26.362, 290.67, 2760, 52
2026/10/09 09:08:27.362, 290.38, 2760, 52
2026/10/09 09:08:28.362, 289.80, 2760, 52
2026/10/09 09:08:29.363, 290.32, 2760, 52
2026/10/09 09:08:30.363, 290.32, 2760, 52
2026/10/09 09:08:31.363, 290.53, 2760, 52
2026/10/09 09:08:32.363, 290.40, 2760, 52
2026/10/09 09:08:33.363, 290.35, 2760, 52
2026/10/09 09:08:34.364, 290.34, 2760, 52
2026/10/09 09:08:35.364, 290.40, 2760, 52
2026/10/09 09:08:36.364, 290.26, 2760, 52
2026/10/09 09:08:37.364, 290.37, 2760, 52
2026/10/09 09:08:38.364, 290.26, 2760, 52
2026/10/09 09:08:39.365, 200.92, 2760, 45

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@ -0,0 +1,32 @@
{
"ctx": "same-work-20261008-01",
"shape": "prod",
"expected_sha256": "52a0f79483ce948b83c4bcde39ce37b89fdf04091826e14f56260717e0d8fce6",
"modes": {
"fault": "NOT RUN",
"full": {
"sha256": "2f7f1de48a50650a50daf8835c6c86eba981a155b28cc4bc5a5990f74ea56a12",
"equal_to_expected": false,
"first_difference": {
"line": 1048578,
"expected": "found 2 5379 0010510133e9ba59",
"got": "error 2 error"
},
"lines_missing": 2097931,
"lines_extra": 1
},
"select": {
"sha256": "2f7f1de48a50650a50daf8835c6c86eba981a155b28cc4bc5a5990f74ea56a12",
"equal_to_expected": false,
"first_difference": {
"line": 1048578,
"expected": "found 2 5379 0010510133e9ba59",
"got": "error 2 error"
},
"lines_missing": 2097931,
"lines_extra": 1
}
},
"known_failed_flagged": null,
"verdict": "DIFFERENT"
}

Some files were not shown because too many files have changed in this diff Show more