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# X4: byte-identical implementation forms of the reg64c layer (the 1.5x programme, 9 October 2026)
Lane: the k lane (X4). Item in the founder's brief (sha256 74ee0732...): "Byte-identical reg64 implementation
alternatives: direct/generated/prefix alternative performance; state/storage/port update costs on both sides".
The frozen control: the class v6 generator tree 1a938abe4 (igneum-pow fingerprint 5f4d6dc6...), the class string
mx8-erad810f22d+sh256x27+state+reg64c+fold+rw. This document claims no pass. It changes nothing on the chain and
activates nothing.
## 1. The layer and the four forms
The reg64c layer is defined in `igneum-pow/src/verify.rs`, `step`'s `addr_src`. Every load's address source is
`r[s] ^ m`, where `m = r[k0]; m = rotl(m, 1) ^ r[k1]; ...` runs over the 63 registers other than the source `s`, in
index order. The fold stays the definition. Each form below computes the same 32-bit word on every register state and
every source.
| Form | What it computes | State beyond the 64-register window | Source |
|---|---|---|---|
| fold (frozen) | the 63-term dependent chain per load | none | `emit.rs` `reg64_mix_line` (the frozen text) |
| direct | the closed sum `XOR_{k<s} rotl(r[k], (62-k) mod 32) ^ XOR_{k>s} rotl(r[k], (63-k) mod 32)` as a balanced tree, depth 6 | none | `reg64form::direct`, `emit.rs` `reg64_direct_mix_line` |
| generated | 8 group sums `g_j = XOR_{k in 8j..8j+7} rotl(r[k], (63-k) mod 32)`. Before each load the generator recomputes only the groups the static schedule wrote since the last load (`reg64form::generated_plan`). Then `r[s] ^ ror(P,1) ^ S ^ P ^ a[s]`, with `S` the 8 groups and `P` the whole groups before `s`'s group plus the in-group partial | 8 x 32 bits per lane | `reg64form::grouped`, `emit.rs` `reg64_generated_mix_line` |
| prefix | review B's F05 text as landed: a running `S` updated after every write (main list and shadow), and `P_s` recomputed per load | 1 x 32 bits per lane | `verify::reg64_address_source`, `emit.rs` `reg64_prefix_mix_line` |
| grouped incremental (chip only) | the generated form's query, with groups 1..7 kept up to date on the base program's writes to r8..r63, and group 0 recomputed at each load | 8 x 32 bits per lane | modelled only; no GPU text |
The fact that makes the generated and grouped forms cheap: the shadow block draws its destination as
`dst = rng.below(8)` (`generator.rs`, the shadow draw). So all 55,296 shadow writes per hash land in r0..r7 (group 0),
and the shadow moves no other group. `tools/1p5x/x4/chip_rows.py` asserts this on the exported text.
Code, on branch 1p5x-x4:
- b51d8c04b: the crate's forms.
- `igneum-pow/src/reg64form.rs`: new.
- `verify.rs`: an override hook in `step`. It is off unless `--reg64-cpu-form` names a form other than the fold.
- `emit.rs`: `--reg64-form`. It changes only the CUDA text, and `--reg64-prefix` is the same as `prefix`.
- `main.rs`: the two switches.
- The tools: `tools/1p5x/x4/` (`differential.sh`, `pod-x4.sh`, `chip_rows.py`, `gpu_rows.py`, `arith.py`).
The texts, exported on build-9 from the frozen object by the b51d8c04b binary (`igneum-pow` sha256 ccb1bf0e...):
| Form | kernel.cu sha256 | kernel_bound.cu sha256 | kernel.cu blake2b-256 (identity.json) | bytes |
|---|---|---|---|---|
| fold | b73ed77eb55d1b49 | 77cabb0602ee7ad5 | 368068868cbff44f | 86,027 |
| direct | 1fdd27fb8eff2bf5 | 010ae3a6dea7d431 | 895f573979f37b51 | 77,035 |
| generated | c1935ca84e7626dd | c39ff235fdff09ad | 6994fbdafe8e4bd1 | 54,664 |
| prefix | 3fe78c3928ba9b77 | 23fb860b5a258b52 | a859b9d88dc4a731 | 84,948 |
The four packs, as one tarball: x4-packs.tgz, sha256 6666d915.... It holds the frozen pack and the three alternatives.
## 2. Equivalence verdicts
| Test | Result | Evidence |
|---|---|---|
| Fold text check: `export` with no switch on b51d8c04b, compared with the frozen tarball hl-v6-all.tgz (91314310...) | kernel.cu, kernel_bound.cu, program.h and identity.json byte-identical | build-9 `/srv/builds/igneum-wt-1p5x-x4/ex/` |
| Prefix text check: `--reg64-form prefix`, compared with hl-v6-all-prefix.tgz (d4b07747...) | all 14 files byte-identical | as above |
| Unit test, known-failed first (`reg64form::tests::x4_forms_equal_the_fold_and_the_wrong_form_is_refused`): the wrong form (`r[s] ^ S ^ a[s]`) must disagree with the fold. Then direct, grouped and prefix must equal the fold on every source, over 4,096 random states, all zero, all ones, 2,048 single-bit states and the init rule's registers | PASS | `rows/suite-b51d8c04b.txt` |
| The crate suite on build-9 (rule 24) | green: 76 lib tests plus 12 test binaries, 0 failed | `rows/suite-b51d8c04b.txt` |
| CPU differential, whole hashes (`tools/1p5x/x4/differential.sh out 4096 32`): the CPU interpreter runs each form and keeps its state per form (the generated plan's stale groups, the prefix's running S) | **EQUIVALENT**. The known-failed form is refused on all 8 reg64c windows and all 32 fuzz seeds. Direct, generated and prefix agree on 44 of 44 checks each: 12 same-work windows, plus 32 fuzz seeds against the fold. Context 03 (class v5, no reg64) is the no-op control: every form agrees there, the wrong one too | `rows/VERDICT`, `rows/verdicts.txt` |
| GPU, the pack self-test and the 2^24 fingerprint at base nonce 0: the gen-6 worker 804a6f7f on an RTX 4090, eight runs | **EQUIVALENT**. check=PASS (96 of 96 vector lanes) and fingerprint e8f4f3289c6ee1fc on all four texts in both passes | `pod-s1/bench-*.log` |
The same-work windows: contexts 01 and 02 (`docs/analysis/class-v6/same-work/same-work-20261008-0{1,2}`), days D and
D+1. Each window is 4,096 nonces: nonce 0, the last 4,096 before the boundary 1,572,864, the first 4,096 after it, and
the last 4,096 of D+1. Each window is checked against that context's own `references/ref-D*.txt` from build-1. Context
03 (`same-work-20261008-03`, class v5) uses the same four windows.
The fuzz set: 32 seeds `i`. Each seed takes the epoch, era and prehash from `sha256("x4-fuzz-i")`, `"x4-era-i"` and
`"x4-pre-i"`, a nonce from `"x4-nonce-i"`, and runs 1,024 nonces on the class v6 string over the node1 state stream
(abb58003...).
## 3. The GPU side (measured)
The recipe is the hash lane's (build-1:/srv/artefacts/1p5x/gpu-row-recipe.md, sha256 cbab453c...):
- Run: worker `--bench`, 250 x 2^24, block-warps 1.
- Rate: the worker's own `mhs=`.
- Power: board power, `power.draw` mean from 8 s in to the end of the timed dispatches. No wall meter; idle is not
subtracted.
- The sampler read power.draw, clocks.sm, utilization.gpu and temperature.gpu at 1 Hz. The recipe's instant and average
fields were not read.
Hardware: one rented RTX 4090 (fk-x4-4090: a RunPod container, driver 595.91.07, CUDA 12.8 image, 450 W limit), at
stock. Worker igneum-worker-cuda-gen6, sha256 804a6f7fea10a62e (the class v6 zip 3 worker).
Session 1 ran 2026-10-09 08:45:43Z to 09:05Z in the order A B C D D C B A (`tools/1p5x/x4/pod-x4.sh`). On an island,
not a network.
| Run | Pack | MH/s | W | nJ per hash | Registers | Blocks per SM | Fingerprint |
|---|---|---|---|---|---|---|---|
| 1 | hl-v6-all (frozen fold) | 35.080 | 285.4 | 8,134 | 93 | 20 | e8f4f3289c6ee1fc |
| 2 | direct | 35.021 | 274.5 | 7,839 | 182 | 8 | e8f4f3289c6ee1fc |
| 3 | generated | 35.053 | 274.2 | 7,824 | 142 | 12 | e8f4f3289c6ee1fc |
| 4 | prefix | 35.056 | 277.1 | 7,905 | 154 | 12 | e8f4f3289c6ee1fc |
| 5 | prefix | 35.053 | 277.8 | 7,926 | 154 | 12 | e8f4f3289c6ee1fc |
| 6 | generated | 35.056 | 274.8 | 7,840 | 142 | 12 | e8f4f3289c6ee1fc |
| 7 | direct | 35.020 | 274.9 | 7,851 | 182 | 8 | e8f4f3289c6ee1fc |
| 8 | hl-v6-all (frozen fold) | 35.054 | 287.4 | 8,199 | 93 | 20 | e8f4f3289c6ee1fc |
Pass 1 compares runs 2 to 4 with run 1. Pass 2 compares runs 5 to 7 with run 8. g is the mean of the two joules-per-hash
ratios.
| Pair | Pass 1 rate / J per hash | Pass 2 rate / J per hash | Mean rate / J per hash | g |
|---|---|---|---|---|
| A/A: frozen run 8 against run 1 | -0.07% / +0.80% | | | (noise floor) |
| direct | -0.17% / -3.63% | -0.10% / -4.25% | -0.13% / -3.94% | 0.961 |
| generated | -0.08% / -3.82% | +0.01% / -4.38% | -0.04% / -4.10% | 0.959 |
| prefix | -0.07% / -2.82% | -0.00% / -3.33% | -0.04% / -3.07% | 0.969 |
Session 2 is the replicate: the same pod, 09:05:41Z to 09:25Z, the same order (`pod-s2/`, `rows/gpu-rows-s2.txt`).
| Pair (session 2) | Mean rate | Mean J per hash | g |
|---|---|---|---|
| A/A: frozen run 8 against run 1 | +0.00% | +0.15% | (noise floor) |
| direct | -0.17% | -3.97% | 0.960 |
| generated | -0.08% | -4.08% | 0.959 |
| prefix | -0.20% | -3.11% | 0.969 |
The two sessions agree to 0.001 in g on every form. Session 2's frozen runs read 35.081 MH/s at 8,172 and 8,184 nJ per
hash.
What the rows say: on the 4090 at stock, every form keeps the rate within 0.2 percent. Every form cuts board joules per
hash by 3 to 4 percent, about four times the A/A spread (0.15 to 0.8 percent), in both passes of both sessions.
The confound, open (BLOCKED row B2 below): nvcc gives the frozen fold 93 registers and 20 resident blocks per SM, and
the alternatives 142 to 182 registers and 8 to 12 blocks. The kernel is memory-bound: the rate is equal at every
occupancy. So the saving may come from fewer resident warps rather than from the form. Yesterday's F05 rows point the
other way on the other card (`docs/analysis/class-v6/rows/fleet-f05-20261008.md`): on the 5090 the prefix text halved
the blocks and cost 14 percent more joules per hash.
What it means per tier:
- A 24 GB card (4090) with a generated or direct pack would mine at the same rate for about 4 percent less board power.
That is about 11 W of 285.
- 8, 12 and 16 GB cards, AMD (OpenCL) and Apple (Metal) are not measured. The OpenCL and Metal texts keep the fold.
- No pack ships from this. A form change is a text change to a fleet kit, and it would go through the hash lane and
the kit lane.
## 4. The chip side (modelled)
Every row is modelled; no chip was measured. The counts come from the exported texts
(`tools/1p5x/x4/chip_rows.py ex`, `rows/chip-rows.txt`).
The constants are the adversary lane's calibrated row (its message of 09:4x UK; class-v6-adversary 43c9f7cd8
`tools/chip-model/mf/`):
- e_op: 6.55 pJ per lane-op at N5 (band 6.01 to 7.77). An xor-rotate that does not pass the slot's macro read costs
about 1.0 pJ.
- e_rf: 3.5 pJ per 256-bit macro access shared by 8 lanes (band 2.0 to 7.0).
- Flop bits written: 0.03 pJ per bit.
- The slot already reads 3 and writes 1 window register per instruction.
- The machine: 1.528 microjoules per hash (N5, GDDR7 board), of which the shadow is 0.672.
Counted from the texts: 256 executed loads per hash (32 per iteration x 8; the worker's RESULT line also says
loads=256). 128 base writes per iteration, 112 of them to r8..r63. 256 shadow writes per pass, all to r0..r7.
Two pricings are given. "Slot" prices each mix op as a full lane-op at 6.55 pJ, the adversary's literal-fold row.
"Datapath" prices each mix op as an xor at 1.0 pJ, the adversary's running-total row. In both, every extra window read
costs e_rf / 8.
| Form | Mix ops per hash | Extra window reads per hash | Flop bits written per hash | State per lane | Ports | nJ per hash, slot (lo / c / hi) | nJ per hash, datapath (lo / c / hi) | pJ per lane-op delta at N5 (slot / datapath) |
|---|---|---|---|---|---|---|---|---|
| fold (frozen) | 16,128 | 16,128 | 0 | 64 registers | 63 reads per load | 101.0 / 112.7 / 139.4 | 20.2 / 23.2 / 30.2 | +1.10 / +0.23 |
| direct | 15,872 | 16,128 | 0 | 64 registers | 63 reads per load (tree) | 99.4 / 111.0 / 137.4 | 19.9 / 22.9 / 30.0 | +1.08 / +0.22 |
| generated | 8,400 | 5,792 | 20,224 | +32 B (8 flop registers) | 8 reads per recomputed group | 52.5 / 58.2 / 70.9 | 10.5 / 11.5 / 14.1 | +0.57 / +0.11 |
| prefix (F05) | 121,320 | 8,160 | 1,802,240 | +4 B | a read-modify-write of S on every write, shadow included | 785.2 / 852.3 / 1003.9 | 177.4 / 179.0 / 182.5 | +8.31 / +1.74 |
| grouped incremental | 7,560 | 2,784 | 36,864 | +32 B | 1 group RMW per base write to r8..r63, 8 reads per load | 47.2 / 51.8 / 62.3 | 9.4 / 9.9 / 11.1 | +0.50 / +0.10 |
The per-lane-op delta spreads the mix's energy over the 102,612 shadow and base lane-ops.
Readings:
- The specialist's cheapest byte-identical form is the grouped incremental one: 10 to 52 nJ per hash, against 23 to
113 nJ for the literal fold.
- The adversary lane's 7 nJ running-total figure (5 to 10) counts 128 loads, and it leaves out the prefix `P_s` that
every load needs. It is corrected here and sent back to that lane.
- The adversary's section 17 Fenwick tree costs more on every reading. Its seven read-modify-writes land on every
write, the shadow's included.
## 5. The arithmetic (`tools/1p5x/x4/arith.py`, `rows/arith.txt`)
`r_new = r0 * g / a`. g comes from section 3. a is the specialist's machine energy with a form, divided by its energy
on a reference, at 1.528 microjoules. Two references:
- fold: a specialist that implements the frozen literal fold.
- model: the served machine, which carries no address-mix term at all. Against it, any form raises the specialist's
energy; that is a model correction, not a design gain.
Each side picks its cheapest form on its own. The card takes generated (g 0.959). The specialist takes grouped
incremental.
| r0 | vs fold, slot | vs fold, datapath | vs model, slot | vs model, datapath |
|---|---|---|---|---|
| 2.0 | a 0.963, r_new 1.99 | a 0.991, r_new 1.94 | a 1.034, r_new 1.86 | a 1.007, r_new 1.91 |
| 1.9 | 1.89 | 1.84 | 1.76 | 1.81 |
| 2.1 | 2.09 | 2.03 | 1.95 | 2.00 |
Per form, with both sides on the same form, from 2.0:
| Form | g | r_new vs fold (slot / datapath) | r_new vs model (slot / datapath) |
|---|---|---|---|
| direct | 0.961 | 1.92 / 1.92 | 1.79 / 1.89 |
| generated | 0.959 | 1.98 / 1.93 | 1.85 / 1.90 |
| prefix | 0.969 | 1.34 / 1.76 | 1.24 / 1.74 |
The prefix rows are not a credible opponent: no specialist would choose the costlier form.
Reaching 1.5 from 2.0 needs g / a = 0.75. The best credible pair gives 0.93 to 1.00. **X4 does not reach 1.5x**, and
no pass is claimed. What X4 does move:
- The card side: a 3 to 4 percent cut in board joules per hash on the 4090, open on the occupancy confound.
- The model side: the served chip omits a 10 to 52 nJ per hash term, worth 0.7 to 3.4 percent of the machine.
- Together, about 0.05 to 0.15 off a 2.0x ratio.
## 6. BLOCKED and NOT RUN rows
| Row | Status | Reason | What it needs |
|---|---|---|---|
| B1: the knee (the 4090 locked), every form | NOT RUN | The rented container refuses `nvidia-smi -lgc` and `-pl`. The worker has no duty-cycle throttle. The house rigs are blocked for every lane (the brief's amendment 2) | a pod host that grants clock locks, or the rigs after the relay lane's "agent back" line |
| B2: the occupancy control (the frozen fold text at 12 and 8 blocks per SM) | BLOCKED | The worker sets no register or occupancy cap for a base-variant pack (`--warps` applies to variant 5 only) | a worker flag or a `__launch_bounds__` text variant from the hash lane. It decides whether g is the form or the occupancy |
| B3: the RTX 5090 pairs (and the 5080, the cohort cards) | NOT RUN | one pod in this item's clock | a 5090 pod from the fleet lane. The F05 row says the sign can flip there |
| B4: OpenCL and Metal texts of the alternatives | NOT RUN | the switch is CUDA-only by design | emitter work in the three dialects, if a form is adopted |
| B5: the grouped incremental form as an executable text | NOT RUN | a chip-side design. Its equivalence rests on the prefix form's tested update rule and the generated form's tested query, and was not emulated on its own | a FormState arm in `reg64form.rs` and the differential, if the adversary lane carries the row |
| B6: the chip rows on the adversary lane's placed core run | BLOCKED | the model has no input file for an address-form row (its own answer). The rows above are this script's arithmetic on its constants | the adversary lane taking `rows/chip-rows.txt` into its section 17 |
## 7. Reproduce
All on a build box, never the Mac:
1. Build: `cargo build --release` in `igneum-pow` at 1p5x-x4.
2. Fetch the inputs from build-1 (the paths are in `differential.sh`'s header).
3. Export: `igneum-pow export --epoch-hex edc4fa84... --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw --era 0:edc4fa84... --era-widths 4 --state node1-state.igsd1 --reg64-form <form> --out <form>`.
4. Differential: `tools/1p5x/x4/differential.sh out 4096 32`.
5. Chip rows: `tools/1p5x/x4/chip_rows.py ex > chip-rows.txt`.
6. On the pod: `pod-x4.sh` with the worker and the packs, then `gpu_rows.py out out-run.log > gpu-rows.txt`.
7. Arithmetic: `arith.py gpu-rows.txt chip-rows.txt`.
The registry batch is `registry-batch-1p5x-x4-20261009.json` beside this file, every cell NOT RUN. It names the cell `rows:1p5x-x4`, which is not in the test map; the steward records it through `tools/ci/test-record.mjs`.

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2644 cache 2 dataset 29 hot 0 check 1352 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.25 ms
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.080 loads=256 bytes=1024 scratch_ops=0 time=wall

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1486 cache 2 dataset 29 hot 0 check 1168 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.90 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.021 loads=256 bytes=1024 scratch_ops=0 time=wall

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1426 cache 3 dataset 29 hot 0 check 1119 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1745 cache 2 dataset 29 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.73 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall

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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.50 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall

4
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 28 hot 0 check 1170 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s1/bench-07-x4-direct.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1646 cache 8 dataset 47 hot 0 check 1147 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 479.00 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.020 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s1/bench-08-hl-v6-all.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2367 cache 3 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.61 ms
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.054 loads=256 bytes=1024 scratch_ops=0 time=wall

35
docs/analysis/class-v6/1p5x/x4/pod-s1/out-run.log Normal file
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@ -0,0 +1,35 @@
RESULT start 2026-10-09T08:45:43Z NVIDIA GeForce RTX 4090, 595.91.07, 450.00 W, 3105 MHz
RESULT worker sha256 804a6f7fea10a62e
RESULT run 01-hl-v6-all rc=0 secs=125 t0=1791535543 t1=1791535668
BENCH 01-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2644 cache 2 dataset 29 hot 0 check 1352 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 01-hl-v6-all | warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.25 ms
BENCH 01-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.080 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 02-x4-direct rc=0 secs=123 t0=1791535688 t1=1791535811
BENCH 02-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1486 cache 2 dataset 29 hot 0 check 1168 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 02-x4-direct | warm-up dispatch (base 0): 478.90 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
BENCH 02-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.021 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 03-x4-generated rc=0 secs=124 t0=1791535831 t1=1791535955
BENCH 03-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1426 cache 3 dataset 29 hot 0 check 1119 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 03-x4-generated | warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
BENCH 03-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 04-x4-prefix rc=0 secs=124 t0=1791535975 t1=1791536099
BENCH 04-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1745 cache 2 dataset 29 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 04-x4-prefix | warm-up dispatch (base 0): 478.73 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
BENCH 04-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 05-x4-prefix rc=0 secs=123 t0=1791536119 t1=1791536242
BENCH 05-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 05-x4-prefix | warm-up dispatch (base 0): 478.50 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
BENCH 05-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 06-x4-generated rc=0 secs=124 t0=1791536262 t1=1791536386
BENCH 06-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 28 hot 0 check 1170 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 06-x4-generated | warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
BENCH 06-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 07-x4-direct rc=0 secs=124 t0=1791536406 t1=1791536530
BENCH 07-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1646 cache 8 dataset 47 hot 0 check 1147 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 07-x4-direct | warm-up dispatch (base 0): 479.00 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
BENCH 07-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.020 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 08-hl-v6-all rc=0 secs=124 t0=1791536550 t1=1791536674
BENCH 08-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2367 cache 3 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 08-hl-v6-all | warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.61 ms
BENCH 08-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.054 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT end 2026-10-09T09:04:54Z

118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-01-hl-v6-all.csv Normal file
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@ -0,0 +1,118 @@
1791535543,25.73,210,0,23
1791535544,41.92,2520,0,24
1791535545,80.03,2520,0,24
1791535546,79.72,2520,0,24
1791535547,83.98,2520,0,25
1791535548,214.87,2655,100,30
1791535549,280.28,2655,100,31
1791535551,280.39,2655,100,32
1791535552,280.38,2655,100,32
1791535553,280.40,2655,100,33
1791535554,280.54,2655,100,33
1791535555,280.64,2655,100,34
1791535556,280.79,2655,100,34
1791535557,280.88,2655,100,34
1791535558,280.84,2655,100,35
1791535559,281.21,2685,100,35
1791535560,281.50,2685,100,35
1791535561,281.46,2685,100,36
1791535562,281.81,2685,100,36
1791535563,282.10,2685,100,36
1791535564,282.20,2685,100,37
1791535565,282.20,2685,100,37
1791535566,282.62,2685,100,37
1791535567,282.67,2685,100,37
1791535568,282.63,2685,100,38
1791535570,282.77,2685,100,38
1791535571,282.88,2685,100,38
1791535572,282.96,2685,100,38
1791535573,282.77,2685,100,38
1791535574,283.22,2685,100,39
1791535575,283.19,2685,100,39
1791535576,283.71,2685,100,39
1791535577,283.31,2685,99,39
1791535578,283.61,2685,100,39
1791535579,283.69,2685,100,40
1791535580,283.76,2685,100,40
1791535581,284.29,2685,100,40
1791535582,284.29,2685,100,40
1791535583,284.29,2685,100,40
1791535584,284.29,2685,100,40
1791535585,284.08,2685,100,41
1791535586,284.09,2685,100,41
1791535587,284.27,2685,100,41
1791535589,284.52,2685,100,41
1791535590,284.69,2685,100,41
1791535591,285.17,2685,100,41
1791535592,284.58,2685,100,41
1791535593,284.85,2685,100,42
1791535594,285.05,2685,100,42
1791535595,285.57,2685,100,42
1791535596,285.45,2685,100,42
1791535597,285.14,2685,100,42
1791535598,285.25,2685,100,42
1791535599,285.37,2685,100,42
1791535600,285.58,2685,100,42
1791535601,285.74,2685,100,43
1791535602,285.55,2685,100,43
1791535603,285.70,2685,100,43
1791535605,285.65,2685,100,43
1791535606,285.56,2685,100,43
1791535607,285.64,2685,100,43
1791535608,286.10,2685,100,43
1791535609,285.48,2685,100,43
1791535610,285.57,2685,100,43
1791535611,285.86,2685,100,43
1791535612,285.49,2685,100,43
1791535613,285.84,2685,100,44
1791535614,286.10,2685,100,44
1791535615,286.06,2685,100,44
1791535616,285.77,2685,100,44
1791535617,285.92,2685,100,44
1791535618,286.16,2685,100,44
1791535619,286.63,2685,100,44
1791535620,286.40,2685,100,44
1791535621,286.33,2685,100,44
1791535623,286.91,2685,100,44
1791535624,286.25,2685,100,44
1791535625,286.94,2685,100,44
1791535626,287.21,2685,100,44
1791535627,287.43,2685,100,44
1791535628,287.06,2685,100,45
1791535629,287.04,2685,100,45
1791535630,287.20,2685,100,45
1791535631,287.46,2685,100,45
1791535632,287.78,2685,100,45
1791535633,288.03,2685,100,45
1791535634,287.81,2685,100,45
1791535635,287.69,2685,100,45
1791535636,288.01,2685,100,45
1791535637,287.39,2685,100,45
1791535638,287.20,2670,100,45
1791535639,287.27,2670,100,45
1791535640,287.52,2670,100,45
1791535641,287.89,2670,100,45
1791535643,287.58,2670,100,45
1791535644,287.44,2670,100,45
1791535645,287.64,2670,100,45
1791535646,287.27,2670,100,45
1791535647,287.41,2670,100,45
1791535648,287.34,2670,100,45
1791535649,287.58,2670,100,45
1791535650,287.78,2670,100,46
1791535651,287.32,2670,100,46
1791535652,287.36,2670,100,46
1791535653,287.67,2670,100,46
1791535654,287.97,2670,100,46
1791535655,287.86,2670,100,46
1791535656,287.72,2670,100,46
1791535658,288.10,2670,100,46
1791535659,287.65,2670,100,46
1791535660,288.01,2670,100,46
1791535661,287.50,2670,100,46
1791535662,287.42,2670,100,46
1791535663,288.01,2670,100,46
1791535664,287.81,2670,100,46
1791535665,287.93,2670,100,46
1791535666,287.92,2670,100,46
1791535667,287.99,2670,100,46
1 1791535543 25.73 210 0 23
2 1791535544 41.92 2520 0 24
3 1791535545 80.03 2520 0 24
4 1791535546 79.72 2520 0 24
5 1791535547 83.98 2520 0 25
6 1791535548 214.87 2655 100 30
7 1791535549 280.28 2655 100 31
8 1791535551 280.39 2655 100 32
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10 1791535553 280.40 2655 100 33
11 1791535554 280.54 2655 100 33
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14 1791535557 280.88 2655 100 34
15 1791535558 280.84 2655 100 35
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20 1791535563 282.10 2685 100 36
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31 1791535575 283.19 2685 100 39
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33 1791535577 283.31 2685 99 39
34 1791535578 283.61 2685 100 39
35 1791535579 283.69 2685 100 40
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40 1791535584 284.29 2685 100 40
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50 1791535595 285.57 2685 100 42
51 1791535596 285.45 2685 100 42
52 1791535597 285.14 2685 100 42
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57 1791535602 285.55 2685 100 43
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100 1791535648 287.34 2670 100 45
101 1791535649 287.58 2670 100 45
102 1791535650 287.78 2670 100 46
103 1791535651 287.32 2670 100 46
104 1791535652 287.36 2670 100 46
105 1791535653 287.67 2670 100 46
106 1791535654 287.97 2670 100 46
107 1791535655 287.86 2670 100 46
108 1791535656 287.72 2670 100 46
109 1791535658 288.10 2670 100 46
110 1791535659 287.65 2670 100 46
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13 1791536563 285.45 2685 100 41
14 1791536564 285.45 2685 100 41
15 1791536565 285.62 2685 100 42
16 1791536566 285.60 2685 100 42
17 1791536567 285.28 2685 100 42
18 1791536568 285.67 2685 100 42
19 1791536569 285.45 2685 100 42
20 1791536570 286.00 2685 100 42
21 1791536571 286.44 2685 100 42
22 1791536572 286.33 2685 100 43
23 1791536573 285.72 2685 100 43
24 1791536574 270.98 2685 100 43
25 1791536575 286.06 2685 100 43
26 1791536576 286.34 2685 100 43
27 1791536577 286.22 2685 100 43
28 1791536578 286.79 2685 100 43
29 1791536580 286.43 2685 100 43
30 1791536581 286.62 2685 100 43
31 1791536582 286.93 2685 100 43
32 1791536583 286.74 2685 100 44
33 1791536584 286.87 2685 100 44
34 1791536585 287.43 2685 100 44
35 1791536586 287.43 2685 100 44
36 1791536587 287.36 2685 100 44
37 1791536588 287.42 2685 100 44
38 1791536589 287.30 2685 99 44
39 1791536590 286.99 2685 100 44
40 1791536591 287.13 2685 100 44
41 1791536592 287.50 2685 100 44
42 1791536593 287.59 2670 100 44
43 1791536594 287.57 2670 100 44
44 1791536595 287.72 2670 100 44
45 1791536596 287.69 2670 100 45
46 1791536597 287.35 2670 100 45
47 1791536598 287.59 2670 100 45
48 1791536600 287.33 2670 100 45
49 1791536601 287.55 2670 100 45
50 1791536602 287.71 2670 100 45
51 1791536603 288.11 2670 100 45
52 1791536604 287.80 2670 100 45
53 1791536605 288.04 2670 100 45
54 1791536606 287.35 2670 100 45
55 1791536607 287.53 2670 100 45
56 1791536608 287.66 2670 100 45
57 1791536609 287.89 2670 100 45
58 1791536610 287.96 2670 100 45
59 1791536611 288.00 2670 100 45
60 1791536612 288.10 2670 100 45
61 1791536613 287.76 2670 100 45
62 1791536614 287.67 2670 100 45
63 1791536615 287.89 2670 100 45
64 1791536616 287.79 2670 100 45
65 1791536617 287.85 2670 100 45
66 1791536619 287.77 2670 100 46
67 1791536620 288.14 2670 100 46
68 1791536621 287.73 2670 100 46
69 1791536622 287.70 2670 100 46
70 1791536623 286.94 2670 100 46
71 1791536624 288.00 2670 100 46
72 1791536625 287.60 2670 100 46
73 1791536626 288.13 2670 100 46
74 1791536627 287.82 2670 100 46
75 1791536628 288.33 2670 100 46
76 1791536629 287.87 2670 100 46
77 1791536630 288.07 2670 100 46
78 1791536631 287.86 2670 100 46
79 1791536632 287.82 2670 100 46
80 1791536633 287.90 2670 100 46
81 1791536634 287.91 2670 100 46
82 1791536635 288.30 2670 100 46
83 1791536636 288.10 2670 100 46
84 1791536638 287.83 2670 100 46
85 1791536639 287.74 2670 100 46
86 1791536640 287.73 2670 100 46
87 1791536641 287.73 2670 100 46
88 1791536642 288.01 2670 100 46
89 1791536643 288.17 2670 100 46
90 1791536644 288.14 2670 100 46
91 1791536645 288.11 2670 100 46
92 1791536646 288.37 2670 100 46
93 1791536647 288.34 2670 100 46
94 1791536648 288.06 2670 100 46
95 1791536649 288.03 2670 100 46
96 1791536650 288.05 2670 100 46
97 1791536651 288.24 2670 100 46
98 1791536652 287.95 2670 100 46
99 1791536653 288.25 2670 100 46
100 1791536654 288.16 2670 100 46
101 1791536656 288.24 2670 100 46
102 1791536657 288.70 2670 100 46
103 1791536658 289.14 2670 100 46
104 1791536659 289.04 2670 100 46
105 1791536660 289.00 2670 100 46
106 1791536661 288.88 2670 100 46
107 1791536662 288.70 2670 100 46
108 1791536663 288.77 2670 100 47
109 1791536664 288.74 2670 100 47
110 1791536665 289.04 2670 100 47
111 1791536666 288.94 2670 100 47
112 1791536667 288.78 2670 100 47
113 1791536668 288.69 2670 100 47
114 1791536669 288.47 2670 100 47
115 1791536670 289.04 2670 100 47
116 1791536672 289.11 2670 100 47
117 1791536673 289.05 2670 100 47
118 1791536674 288.86 2670 100 47

4
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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2347 cache 2 dataset 29 hot 0 check 1092 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 477.97 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall

4
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1626 cache 3 dataset 28 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 479.01 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-03-x4-generated.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1479 cache 2 dataset 29 hot 0 check 1190 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.44 ms; 250 timed dispatches of 16777216 nonces: mean 478.59 ms
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.055 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-04-x4-prefix.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1676 cache 3 dataset 28 hot 0 check 1158 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.39 ms; 250 timed dispatches of 16777216 nonces: mean 479.74 ms
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=34.971 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-05-x4-prefix.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1552 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.53 ms; 250 timed dispatches of 16777216 nonces: mean 478.66 ms
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.050 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-06-x4-generated.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1566 cache 2 dataset 29 hot 0 check 1652 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.47 ms; 250 timed dispatches of 16777216 nonces: mean 478.63 ms
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-07-x4-direct.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1454 cache 2 dataset 29 hot 0 check 1187 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 479.02 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall

4
docs/analysis/class-v6/1p5x/x4/pod-s2/bench-08-hl-v6-all.log Normal file
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@ -0,0 +1,4 @@
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2538 cache 2 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
warm-up dispatch (base 0): 478.21 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall

35
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@ -0,0 +1,35 @@
RESULT start 2026-10-09T09:05:41Z NVIDIA GeForce RTX 4090, 595.91.07, 450.00 W, 3105 MHz
RESULT worker sha256 804a6f7fea10a62e
RESULT run 01-hl-v6-all rc=0 secs=124 t0=1791536741 t1=1791536865
BENCH 01-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2347 cache 2 dataset 29 hot 0 check 1092 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 01-hl-v6-all | warm-up dispatch (base 0): 477.97 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
BENCH 01-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 02-x4-direct rc=0 secs=124 t0=1791536885 t1=1791537009
BENCH 02-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1626 cache 3 dataset 28 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 02-x4-direct | warm-up dispatch (base 0): 479.01 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
BENCH 02-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 03-x4-generated rc=0 secs=123 t0=1791537029 t1=1791537152
BENCH 03-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1479 cache 2 dataset 29 hot 0 check 1190 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 03-x4-generated | warm-up dispatch (base 0): 478.44 ms; 250 timed dispatches of 16777216 nonces: mean 478.59 ms
BENCH 03-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.055 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 04-x4-prefix rc=0 secs=124 t0=1791537172 t1=1791537296
BENCH 04-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1676 cache 3 dataset 28 hot 0 check 1158 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 04-x4-prefix | warm-up dispatch (base 0): 478.39 ms; 250 timed dispatches of 16777216 nonces: mean 479.74 ms
BENCH 04-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=34.971 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 05-x4-prefix rc=0 secs=124 t0=1791537316 t1=1791537440
BENCH 05-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1552 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 05-x4-prefix | warm-up dispatch (base 0): 478.53 ms; 250 timed dispatches of 16777216 nonces: mean 478.66 ms
BENCH 05-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.050 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 06-x4-generated rc=0 secs=124 t0=1791537460 t1=1791537584
BENCH 06-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1566 cache 2 dataset 29 hot 0 check 1652 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 06-x4-generated | warm-up dispatch (base 0): 478.47 ms; 250 timed dispatches of 16777216 nonces: mean 478.63 ms
BENCH 06-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 07-x4-direct rc=0 secs=123 t0=1791537604 t1=1791537727
BENCH 07-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1454 cache 2 dataset 29 hot 0 check 1187 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 07-x4-direct | warm-up dispatch (base 0): 479.02 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
BENCH 07-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT run 08-hl-v6-all rc=0 secs=125 t0=1791537747 t1=1791537872
BENCH 08-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2538 cache 2 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
BENCH 08-hl-v6-all | warm-up dispatch (base 0): 478.21 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
BENCH 08-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
RESULT end 2026-10-09T09:24:52Z

118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-01-hl-v6-all.csv Normal file
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@ -0,0 +1,118 @@
1791536741,27.54,210,0,26
1791536742,56.07,2520,0,27
1791536743,82.60,2520,0,27
1791536744,85.62,2520,11,28
1791536745,90.67,2520,57,27
1791536746,251.28,2655,100,34
1791536747,281.96,2685,100,35
1791536748,282.36,2685,100,35
1791536749,282.45,2685,100,35
1791536750,282.71,2685,100,36
1791536751,282.52,2685,100,36
1791536752,282.61,2685,100,36
1791536753,282.40,2685,100,37
1791536754,282.54,2685,100,37
1791536756,282.72,2685,100,37
1791536757,283.36,2685,100,38
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118
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117
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44 1791537650 275.23 2685 100 44
45 1791537651 275.10 2685 100 44
46 1791537652 275.18 2685 100 44
47 1791537653 275.02 2685 100 44
48 1791537654 275.15 2670 100 44
49 1791537655 274.88 2670 100 44
50 1791537656 275.16 2670 100 44
51 1791537657 275.14 2670 100 44
52 1791537658 275.09 2670 100 44
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54 1791537660 274.87 2670 100 44
55 1791537661 275.16 2670 100 44
56 1791537662 275.24 2670 100 44
57 1791537663 274.98 2670 100 44
58 1791537664 274.68 2670 100 44
59 1791537666 274.64 2670 100 44
60 1791537667 275.03 2670 100 44
61 1791537668 275.03 2670 100 44
62 1791537669 274.77 2670 100 44
63 1791537670 274.99 2670 100 45
64 1791537671 275.12 2670 100 45
65 1791537672 275.27 2670 100 45
66 1791537673 275.44 2670 100 45
67 1791537674 275.14 2670 100 45
68 1791537675 275.09 2670 100 45
69 1791537676 275.39 2670 100 45
70 1791537677 275.51 2670 100 45
71 1791537678 275.53 2670 100 45
72 1791537679 275.66 2670 100 45
73 1791537680 275.76 2670 100 45
74 1791537681 275.70 2670 100 45
75 1791537682 276.13 2670 100 45
76 1791537684 275.75 2670 100 45
77 1791537685 275.75 2670 100 45
78 1791537686 275.86 2670 100 45
79 1791537687 275.65 2670 100 45
80 1791537688 275.73 2670 100 45
81 1791537689 275.67 2670 100 45
82 1791537690 275.65 2670 100 45
83 1791537691 275.67 2670 100 45
84 1791537692 275.95 2670 100 45
85 1791537693 276.16 2670 100 45
86 1791537694 275.87 2670 100 45
87 1791537695 276.40 2670 100 45
88 1791537696 275.88 2670 100 45
89 1791537697 275.58 2670 100 45
90 1791537698 275.83 2670 100 45
91 1791537699 275.79 2670 100 45
92 1791537701 275.62 2670 100 45
93 1791537702 275.62 2670 100 45
94 1791537703 275.67 2670 100 45
95 1791537704 275.69 2670 100 45
96 1791537705 275.80 2670 100 45
97 1791537706 275.79 2670 100 45
98 1791537707 275.96 2670 100 45
99 1791537708 275.91 2670 100 45
100 1791537709 276.00 2670 100 45
101 1791537710 276.33 2670 100 45
102 1791537711 276.05 2670 100 45
103 1791537712 275.82 2670 100 45
104 1791537713 275.83 2670 100 45
105 1791537714 275.79 2670 100 45
106 1791537715 275.68 2670 100 45
107 1791537716 276.52 2670 100 45
108 1791537717 276.24 2670 100 45
109 1791537719 275.78 2670 100 45
110 1791537720 276.03 2670 100 46
111 1791537721 276.27 2670 100 46
112 1791537722 276.12 2670 100 46
113 1791537723 276.33 2670 100 46
114 1791537724 276.52 2670 100 46
115 1791537725 276.54 2670 100 46
116 1791537726 276.20 2670 100 46
117 1791537727 276.32 2670 100 46

118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-08-hl-v6-all.csv Normal file
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@ -0,0 +1,118 @@
1791537747,27.40,210,0,33
1791537749,46.65,2520,0,33
1791537750,81.12,2520,0,33
1791537751,81.00,2520,0,33
1791537752,130.12,2685,100,38
1791537753,253.26,2685,100,39
1791537754,284.53,2685,100,40
1791537755,284.60,2685,100,40
1791537756,284.13,2685,100,40
1791537757,284.60,2685,100,41
1791537758,285.18,2685,100,41
1791537759,285.54,2685,100,41
1791537760,285.55,2685,100,41
1791537761,285.42,2685,100,42
1791537762,285.53,2685,100,42
1791537763,285.24,2685,100,42
1791537764,285.26,2685,100,42
1791537765,285.26,2685,100,42
1791537767,285.40,2685,100,42
1791537768,285.45,2685,100,42
1791537769,285.73,2685,100,43
1791537770,286.00,2685,100,43
1791537771,285.87,2685,100,43
1791537772,286.22,2685,100,43
1791537773,285.95,2685,100,43
1791537774,285.96,2685,100,43
1791537775,285.92,2685,100,43
1791537776,286.01,2685,100,43
1791537777,285.96,2685,100,44
1791537778,286.32,2685,100,44
1791537779,286.23,2685,100,44
1791537780,286.25,2685,100,44
1791537781,286.63,2670,100,44
1791537782,286.44,2670,100,44
1791537783,286.19,2670,100,44
1791537785,286.31,2670,100,44
1791537786,286.45,2670,100,44
1791537787,286.55,2670,100,44
1791537788,286.82,2670,100,44
1791537789,286.51,2670,100,44
1791537790,286.82,2670,100,44
1791537791,286.42,2670,100,45
1791537792,286.90,2670,100,45
1791537793,286.84,2670,100,45
1791537794,286.63,2670,100,45
1791537795,286.54,2670,100,45
1791537796,286.65,2670,100,45
1791537797,286.94,2670,100,45
1791537798,287.28,2670,100,45
1791537799,287.34,2670,100,45
1791537800,287.54,2670,100,45
1791537801,287.22,2670,100,45
1791537802,287.30,2670,100,45
1791537804,287.25,2670,100,45
1791537805,287.18,2670,100,45
1791537806,287.52,2670,100,45
1791537807,287.50,2670,100,45
1791537808,287.69,2670,100,45
1791537809,287.54,2670,100,45
1791537810,287.32,2670,100,46
1791537811,287.32,2670,100,46
1791537812,287.42,2670,100,46
1791537813,287.60,2670,100,46
1791537814,287.20,2670,100,46
1791537815,287.45,2670,100,46
1791537816,287.47,2670,100,46
1791537817,287.26,2670,100,46
1791537818,287.34,2670,100,46
1791537819,287.37,2670,100,46
1791537820,287.47,2670,100,46
1791537822,287.50,2670,100,46
1791537823,287.43,2670,100,46
1791537824,287.26,2670,100,46
1791537825,287.65,2670,100,46
1791537826,287.80,2670,100,46
1791537827,287.65,2670,100,46
1791537828,287.52,2670,100,46
1791537829,287.68,2670,100,46
1791537830,287.58,2670,100,46
1791537831,287.68,2670,100,46
1791537832,287.86,2670,100,46
1791537833,287.38,2670,100,46
1791537834,287.53,2670,100,46
1791537835,287.71,2670,100,46
1791537836,287.42,2670,100,46
1791537837,287.53,2670,100,46
1791537838,287.72,2670,100,46
1791537840,287.56,2670,100,46
1791537841,287.89,2670,100,46
1791537842,287.81,2670,100,46
1791537843,287.87,2670,100,46
1791537844,287.82,2670,100,46
1791537845,287.81,2670,100,46
1791537846,287.95,2670,100,46
1791537847,288.20,2670,100,46
1791537848,288.24,2670,100,46
1791537849,288.27,2670,100,46
1791537850,288.44,2670,100,46
1791537851,288.34,2670,100,46
1791537852,288.13,2670,100,47
1791537853,288.21,2670,100,47
1791537854,288.27,2670,100,47
1791537855,287.92,2670,100,47
1791537856,288.00,2670,100,47
1791537857,287.95,2670,100,47
1791537859,287.98,2670,100,47
1791537860,287.47,2670,100,46
1791537861,287.57,2670,100,47
1791537862,288.09,2670,100,47
1791537863,288.23,2670,100,47
1791537864,288.52,2670,100,47
1791537865,288.55,2670,100,47
1791537866,288.64,2670,100,47
1791537867,288.74,2670,100,47
1791537868,288.98,2670,100,47
1791537869,288.61,2670,100,47
1791537870,288.70,2670,100,47
1791537871,288.71,2670,100,47
1 1791537747 27.40 210 0 33
2 1791537749 46.65 2520 0 33
3 1791537750 81.12 2520 0 33
4 1791537751 81.00 2520 0 33
5 1791537752 130.12 2685 100 38
6 1791537753 253.26 2685 100 39
7 1791537754 284.53 2685 100 40
8 1791537755 284.60 2685 100 40
9 1791537756 284.13 2685 100 40
10 1791537757 284.60 2685 100 41
11 1791537758 285.18 2685 100 41
12 1791537759 285.54 2685 100 41
13 1791537760 285.55 2685 100 41
14 1791537761 285.42 2685 100 42
15 1791537762 285.53 2685 100 42
16 1791537763 285.24 2685 100 42
17 1791537764 285.26 2685 100 42
18 1791537765 285.26 2685 100 42
19 1791537767 285.40 2685 100 42
20 1791537768 285.45 2685 100 42
21 1791537769 285.73 2685 100 43
22 1791537770 286.00 2685 100 43
23 1791537771 285.87 2685 100 43
24 1791537772 286.22 2685 100 43
25 1791537773 285.95 2685 100 43
26 1791537774 285.96 2685 100 43
27 1791537775 285.92 2685 100 43
28 1791537776 286.01 2685 100 43
29 1791537777 285.96 2685 100 44
30 1791537778 286.32 2685 100 44
31 1791537779 286.23 2685 100 44
32 1791537780 286.25 2685 100 44
33 1791537781 286.63 2670 100 44
34 1791537782 286.44 2670 100 44
35 1791537783 286.19 2670 100 44
36 1791537785 286.31 2670 100 44
37 1791537786 286.45 2670 100 44
38 1791537787 286.55 2670 100 44
39 1791537788 286.82 2670 100 44
40 1791537789 286.51 2670 100 44
41 1791537790 286.82 2670 100 44
42 1791537791 286.42 2670 100 45
43 1791537792 286.90 2670 100 45
44 1791537793 286.84 2670 100 45
45 1791537794 286.63 2670 100 45
46 1791537795 286.54 2670 100 45
47 1791537796 286.65 2670 100 45
48 1791537797 286.94 2670 100 45
49 1791537798 287.28 2670 100 45
50 1791537799 287.34 2670 100 45
51 1791537800 287.54 2670 100 45
52 1791537801 287.22 2670 100 45
53 1791537802 287.30 2670 100 45
54 1791537804 287.25 2670 100 45
55 1791537805 287.18 2670 100 45
56 1791537806 287.52 2670 100 45
57 1791537807 287.50 2670 100 45
58 1791537808 287.69 2670 100 45
59 1791537809 287.54 2670 100 45
60 1791537810 287.32 2670 100 46
61 1791537811 287.32 2670 100 46
62 1791537812 287.42 2670 100 46
63 1791537813 287.60 2670 100 46
64 1791537814 287.20 2670 100 46
65 1791537815 287.45 2670 100 46
66 1791537816 287.47 2670 100 46
67 1791537817 287.26 2670 100 46
68 1791537818 287.34 2670 100 46
69 1791537819 287.37 2670 100 46
70 1791537820 287.47 2670 100 46
71 1791537822 287.50 2670 100 46
72 1791537823 287.43 2670 100 46
73 1791537824 287.26 2670 100 46
74 1791537825 287.65 2670 100 46
75 1791537826 287.80 2670 100 46
76 1791537827 287.65 2670 100 46
77 1791537828 287.52 2670 100 46
78 1791537829 287.68 2670 100 46
79 1791537830 287.58 2670 100 46
80 1791537831 287.68 2670 100 46
81 1791537832 287.86 2670 100 46
82 1791537833 287.38 2670 100 46
83 1791537834 287.53 2670 100 46
84 1791537835 287.71 2670 100 46
85 1791537836 287.42 2670 100 46
86 1791537837 287.53 2670 100 46
87 1791537838 287.72 2670 100 46
88 1791537840 287.56 2670 100 46
89 1791537841 287.89 2670 100 46
90 1791537842 287.81 2670 100 46
91 1791537843 287.87 2670 100 46
92 1791537844 287.82 2670 100 46
93 1791537845 287.81 2670 100 46
94 1791537846 287.95 2670 100 46
95 1791537847 288.20 2670 100 46
96 1791537848 288.24 2670 100 46
97 1791537849 288.27 2670 100 46
98 1791537850 288.44 2670 100 46
99 1791537851 288.34 2670 100 46
100 1791537852 288.13 2670 100 47
101 1791537853 288.21 2670 100 47
102 1791537854 288.27 2670 100 47
103 1791537855 287.92 2670 100 47
104 1791537856 288.00 2670 100 47
105 1791537857 287.95 2670 100 47
106 1791537859 287.98 2670 100 47
107 1791537860 287.47 2670 100 46
108 1791537861 287.57 2670 100 47
109 1791537862 288.09 2670 100 47
110 1791537863 288.23 2670 100 47
111 1791537864 288.52 2670 100 47
112 1791537865 288.55 2670 100 47
113 1791537866 288.64 2670 100 47
114 1791537867 288.74 2670 100 47
115 1791537868 288.98 2670 100 47
116 1791537869 288.61 2670 100 47
117 1791537870 288.70 2670 100 47
118 1791537871 288.71 2670 100 47

24
docs/analysis/class-v6/1p5x/x4/registry-batch-1p5x-x4-20261009.json Normal file
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{
"run_id": "1p5x-x4-20261009",
"manifest_sha": "1a938abe4 (the frozen control); the forms on 1p5x-x4 b51d8c04b",
"evidence_dir": "docs/analysis/class-v6/1p5x/x4/README.md",
"boxes": [
"build-9",
"runpod:fk-x4-4090"
],
"cells": [
{
"cell": "rows:1p5x-x4",
"status": "NOT RUN",
"evidence": "docs/analysis/class-v6/1p5x/x4/README.md",
"note": "X4 of the 1.5x programme: three byte-identical reg64c address-mix forms (direct, generated, prefix). Equivalence measured: CPU differential EQUIVALENT (rows/VERDICT; the known-failed form refused first) and GPU self-test plus fingerprint e8f4f3289c6ee1fc on all forms. GPU pairs: RTX 4090 at stock only, g 0.959 to 0.969 at equal rate, with an occupancy confound. Chip rows modelled: 10 to 52 nJ per hash for the cheapest form. Arithmetic from 2.0x: r_new 1.86 to 1.99. No pass claimed. NOT RUN by the brief's rule (rows stay NOT RUN until the steward's X6). The knee, the 5090 and the occupancy control are BLOCKED or NOT RUN (README section 6). Island: the 4090 rows are on an island, not a network."
}
],
"method": "GPU",
"release_identity": {
"commit": "b51d8c04b (branch 1p5x-x4 off master a7f81d9a9)",
"binary": "igneum-pow ccb1bf0efebce4bb (build-9 release build of b51d8c04b); igneum-worker-cuda-gen6 804a6f7fea10a62e",
"network_object": "none (packs exported from the frozen object, program id 0x4de7b836cc40a4ea; no network)",
"activation": "none"
}
}

3
docs/analysis/class-v6/1p5x/x4/rows/VERDICT Normal file
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tally {('direct', 'AGREE'): 44, ('fold', 'AGREE'): 12, ('generated', 'AGREE'): 44, ('prefix', 'AGREE'): 44, ('wrong', 'DISAGREE'): 40, ('wrong', 'AGREE'): 4}
known-failed refused on every reg64c window and seed: True
VERDICT EQUIVALENT mismatches 0

12
docs/analysis/class-v6/1p5x/x4/rows/arith.txt Normal file
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form g a vs fold (slot, datapath) a vs model (slot, datapath) r_new at r0 2.0, same form both sides (vs fold slot, dp; vs model slot, dp)
direct 0.9606 0.9990, 0.9998 1.0726, 1.0150 1.923, 1.922, 1.791, 1.893
generated 0.9590 0.9668, 0.9925 1.0381, 1.0075 1.984, 1.933, 1.848, 1.904
prefix 0.9693 1.4508, 1.1004 1.5578, 1.1171 1.336, 1.762, 1.244, 1.735
grouped incremental 1.0000 (no GPU text) 0.9629, 0.9914 1.0339, 1.0065 2.077, 2.017, 1.934, 1.987
best pair: the card on 'generated' (g 0.9590), the specialist on 'grouped incremental'
r0 2.0: vs fold slot: a 0.9629 r_new 1.992; vs fold datapath: a 0.9914 r_new 1.935; vs model slot: a 1.0339 r_new 1.855; vs model datapath: a 1.0065 r_new 1.906
r0 1.9: vs fold slot: a 0.9629 r_new 1.892; vs fold datapath: a 0.9914 r_new 1.838; vs model slot: a 1.0339 r_new 1.762; vs model datapath: a 1.0065 r_new 1.810
r0 2.1: vs fold slot: a 0.9629 r_new 2.092; vs fold datapath: a 0.9914 r_new 2.031; vs model slot: a 1.0339 r_new 1.948; vs model datapath: a 1.0065 r_new 2.001
the yardstick: from 2.0, 1.5 needs g / a = 0.75

19
docs/analysis/class-v6/1p5x/x4/rows/chip-rows.txt Normal file
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# loads per hash executed 256 (32 per iteration x 8); base writes per iteration 128 (112 to r8..r63); shadow writes per pass 256, all in r0..r7
form mix ops X extra reads A flop bits F state bits per lane slot nJ (lo c hi) datapath nJ (lo c hi) state ports
fold (frozen) 16128 16128 0 0 101.0 112.7 139.4 20.2 23.2 30.2 the 64 x 32-bit window only 63 window reads per load
direct 15872 16128 0 0 99.4 111.0 137.4 19.9 22.9 30.0 the window only 63 window reads per load (a tree: depth 6, same reads)
generated (GPU text: recompute at load) 8400 5792 20224 256 52.5 58.2 70.9 10.5 11.5 14.1 +8 x 32-bit group sums per lane (32 B, flops) group recomputes read 8 registers each; the in-group partial reads up to 7
prefix (F05 text: running S on every write) 121320 8160 1802240 32 785.2 852.3 1003.9 177.4 179.0 182.5 +1 x 32-bit running total per lane (flops) the old value of every written register (main and shadow) rotated into S
grouped incremental (chip only, by the same identity) 7560 2784 36864 256 47.2 51.8 62.3 9.4 9.9 11.1 +8 x 32-bit group sums per lane (32 B) groups 1..7 move on base writes to r8..r63; group 0 recomputed at each load (8 reads)
# a = (machine + form) / machine, machine 1.528 microjoules (N5, GDDR7 board, no mix term); per-lane-op delta over the 102,612 shadow+base lane-ops
fold (frozen) slot +112.7 nJ a 1.0738 per lane-op +1.098 pJ of the shadow +16.8 percent
fold (frozen) dp +23.2 nJ a 1.0152 per lane-op +0.226 pJ of the shadow +3.5 percent
direct slot +111.0 nJ a 1.0727 per lane-op +1.082 pJ of the shadow +16.5 percent
direct dp +22.9 nJ a 1.0150 per lane-op +0.223 pJ of the shadow +3.4 percent
generated (GPU text: recompute at load) slot +58.2 nJ a 1.0381 per lane-op +0.567 pJ of the shadow +8.7 percent
generated (GPU text: recompute at load) dp +11.5 nJ a 1.0076 per lane-op +0.112 pJ of the shadow +1.7 percent
prefix (F05 text: running S on every write) slot +852.3 nJ a 1.5578 per lane-op +8.306 pJ of the shadow +126.8 percent
prefix (F05 text: running S on every write) dp +179.0 nJ a 1.1171 per lane-op +1.744 pJ of the shadow +26.6 percent
grouped incremental (chip only, by the same identity) slot +51.8 nJ a 1.0339 per lane-op +0.505 pJ of the shadow +7.7 percent
grouped incremental (chip only, by the same identity) dp +9.9 nJ a 1.0065 per lane-op +0.096 pJ of the shadow +1.5 percent

15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows-s2.txt Normal file
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run pack MH/s W nJ per hash sm MHz util samples regs blocks/SM fingerprint check
01-hl-v6-all hl-v6-all 35.081 286.7 8172 2678 100 110 93 20 e8f4f3289c6ee1fc PASS
02-x4-direct x4-direct 35.022 275.2 7857 2676 100 109 182 8 e8f4f3289c6ee1fc PASS
03-x4-generated x4-generated 35.055 275.1 7847 2675 100 109 142 12 e8f4f3289c6ee1fc PASS
04-x4-prefix x4-prefix 34.971 277.2 7926 2675 100 111 154 12 e8f4f3289c6ee1fc PASS
05-x4-prefix x4-prefix 35.050 277.7 7922 2674 100 110 154 12 e8f4f3289c6ee1fc PASS
06-x4-generated x4-generated 35.053 274.9 7842 2676 100 109 142 12 e8f4f3289c6ee1fc PASS
07-x4-direct x4-direct 35.022 274.9 7850 2675 100 109 182 8 e8f4f3289c6ee1fc PASS
08-hl-v6-all hl-v6-all 35.081 287.1 8184 2673 100 111 93 20 e8f4f3289c6ee1fc PASS
pair form pass 1 rate % pass 1 J/hash % pass 2 rate % pass 2 J/hash % mean rate % mean J/hash % g (J/hash ratio)
A/A hl-v6-all run 8 vs run 1 +0.00 +0.15
pair x4-direct -0.17 -3.85 -0.17 -4.08 -0.17 -3.97 0.9603
pair x4-generated -0.07 -3.98 -0.08 -4.18 -0.08 -4.08 0.9592
pair x4-prefix -0.31 -3.01 -0.09 -3.21 -0.20 -3.11 0.9689

15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows.txt Normal file
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@ -0,0 +1,15 @@
run pack MH/s W nJ per hash sm MHz util samples regs blocks/SM fingerprint check
01-hl-v6-all hl-v6-all 35.080 285.4 8134 2679 100 111 93 20 e8f4f3289c6ee1fc PASS
02-x4-direct x4-direct 35.021 274.5 7839 2681 100 109 182 8 e8f4f3289c6ee1fc PASS
03-x4-generated x4-generated 35.053 274.2 7824 2680 100 110 142 12 e8f4f3289c6ee1fc PASS
04-x4-prefix x4-prefix 35.056 277.1 7905 2680 100 109 154 12 e8f4f3289c6ee1fc PASS
05-x4-prefix x4-prefix 35.053 277.8 7926 2679 100 110 154 12 e8f4f3289c6ee1fc PASS
06-x4-generated x4-generated 35.056 274.8 7840 2678 100 109 142 12 e8f4f3289c6ee1fc PASS
07-x4-direct x4-direct 35.020 274.9 7851 2677 100 111 182 8 e8f4f3289c6ee1fc PASS
08-hl-v6-all hl-v6-all 35.054 287.4 8199 2674 100 110 93 20 e8f4f3289c6ee1fc PASS
pair form pass 1 rate % pass 1 J/hash % pass 2 rate % pass 2 J/hash % mean rate % mean J/hash % g (J/hash ratio)
A/A hl-v6-all run 8 vs run 1 -0.07 +0.80
pair x4-direct -0.17 -3.63 -0.10 -4.25 -0.13 -3.94 0.9606
pair x4-generated -0.08 -3.82 +0.01 -4.38 -0.04 -4.10 0.9590
pair x4-prefix -0.07 -2.82 -0.00 -3.33 -0.04 -3.07 0.9693

15
docs/analysis/class-v6/1p5x/x4/rows/suite-b51d8c04b.txt Normal file
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@ -0,0 +1,15 @@
test reg64form::tests::x4_forms_equal_the_fold_and_the_wrong_form_is_refused ... ok
test result: ok. 76 passed; 0 failed; 6 ignored; 0 measured; 0 filtered out; finished in 140.72s
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
test result: ok. 2 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 0.01s
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 1.42s
test result: ok. 5 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.99s
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.01s
test result: ok. 4 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 9.80s
test result: ok. 27 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 8.37s
test result: ok. 2 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 6.03s
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 4.85s
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 7.01s
test result: ok. 12 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 20.99s
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
EXIT 0

188
docs/analysis/class-v6/1p5x/x4/rows/verdicts.txt Normal file
View file

@ -0,0 +1,188 @@
ctx01 direct D@0 AGREE
ctx01 direct D1@1572864 AGREE
ctx01 direct D1@3141632 AGREE
ctx01 direct D@1568768 AGREE
ctx01 fold D@0 AGREE
ctx01 fold D1@1572864 AGREE
ctx01 fold D1@3141632 AGREE
ctx01 fold D@1568768 AGREE
ctx01 generated D@0 AGREE
ctx01 generated D1@1572864 AGREE
ctx01 generated D1@3141632 AGREE
ctx01 generated D@1568768 AGREE
ctx01 prefix D@0 AGREE
ctx01 prefix D1@1572864 AGREE
ctx01 prefix D1@3141632 AGREE
ctx01 prefix D@1568768 AGREE
ctx01 wrong D@0 DISAGREE
ctx01 wrong D1@1572864 DISAGREE
ctx01 wrong D1@3141632 DISAGREE
ctx01 wrong D@1568768 DISAGREE
ctx02 direct D@0 AGREE
ctx02 direct D1@1572864 AGREE
ctx02 direct D1@3141632 AGREE
ctx02 direct D@1568768 AGREE
ctx02 fold D@0 AGREE
ctx02 fold D1@1572864 AGREE
ctx02 fold D1@3141632 AGREE
ctx02 fold D@1568768 AGREE
ctx02 generated D@0 AGREE
ctx02 generated D1@1572864 AGREE
ctx02 generated D1@3141632 AGREE
ctx02 generated D@1568768 AGREE
ctx02 prefix D@0 AGREE
ctx02 prefix D1@1572864 AGREE
ctx02 prefix D1@3141632 AGREE
ctx02 prefix D@1568768 AGREE
ctx02 wrong D@0 DISAGREE
ctx02 wrong D1@1572864 DISAGREE
ctx02 wrong D1@3141632 DISAGREE
ctx02 wrong D@1568768 DISAGREE
ctx03 direct D@0 AGREE
ctx03 direct D1@1572864 AGREE
ctx03 direct D1@3141632 AGREE
ctx03 direct D@1568768 AGREE
ctx03 fold D@0 AGREE
ctx03 fold D1@1572864 AGREE
ctx03 fold D1@3141632 AGREE
ctx03 fold D@1568768 AGREE
ctx03 generated D@0 AGREE
ctx03 generated D1@1572864 AGREE
ctx03 generated D1@3141632 AGREE
ctx03 generated D@1568768 AGREE
ctx03 prefix D@0 AGREE
ctx03 prefix D1@1572864 AGREE
ctx03 prefix D1@3141632 AGREE
ctx03 prefix D@1568768 AGREE
ctx03 wrong D@0 AGREE
ctx03 wrong D1@1572864 AGREE
ctx03 wrong D1@3141632 AGREE
ctx03 wrong D@1568768 AGREE
fuzz0 direct AGREE
fuzz0 generated AGREE
fuzz0 prefix AGREE
fuzz0 wrong DISAGREE
fuzz10 direct AGREE
fuzz10 generated AGREE
fuzz10 prefix AGREE
fuzz10 wrong DISAGREE
fuzz11 direct AGREE
fuzz11 generated AGREE
fuzz11 prefix AGREE
fuzz11 wrong DISAGREE
fuzz12 direct AGREE
fuzz12 generated AGREE
fuzz12 prefix AGREE
fuzz12 wrong DISAGREE
fuzz13 direct AGREE
fuzz13 generated AGREE
fuzz13 prefix AGREE
fuzz13 wrong DISAGREE
fuzz14 direct AGREE
fuzz14 generated AGREE
fuzz14 prefix AGREE
fuzz14 wrong DISAGREE
fuzz15 direct AGREE
fuzz15 generated AGREE
fuzz15 prefix AGREE
fuzz15 wrong DISAGREE
fuzz16 direct AGREE
fuzz16 generated AGREE
fuzz16 prefix AGREE
fuzz16 wrong DISAGREE
fuzz17 direct AGREE
fuzz17 generated AGREE
fuzz17 prefix AGREE
fuzz17 wrong DISAGREE
fuzz18 direct AGREE
fuzz18 generated AGREE
fuzz18 prefix AGREE
fuzz18 wrong DISAGREE
fuzz19 direct AGREE
fuzz19 generated AGREE
fuzz19 prefix AGREE
fuzz19 wrong DISAGREE
fuzz1 direct AGREE
fuzz1 generated AGREE
fuzz1 prefix AGREE
fuzz1 wrong DISAGREE
fuzz20 direct AGREE
fuzz20 generated AGREE
fuzz20 prefix AGREE
fuzz20 wrong DISAGREE
fuzz21 direct AGREE
fuzz21 generated AGREE
fuzz21 prefix AGREE
fuzz21 wrong DISAGREE
fuzz22 direct AGREE
fuzz22 generated AGREE
fuzz22 prefix AGREE
fuzz22 wrong DISAGREE
fuzz23 direct AGREE
fuzz23 generated AGREE
fuzz23 prefix AGREE
fuzz23 wrong DISAGREE
fuzz24 direct AGREE
fuzz24 generated AGREE
fuzz24 prefix AGREE
fuzz24 wrong DISAGREE
fuzz25 direct AGREE
fuzz25 generated AGREE
fuzz25 prefix AGREE
fuzz25 wrong DISAGREE
fuzz26 direct AGREE
fuzz26 generated AGREE
fuzz26 prefix AGREE
fuzz26 wrong DISAGREE
fuzz27 direct AGREE
fuzz27 generated AGREE
fuzz27 prefix AGREE
fuzz27 wrong DISAGREE
fuzz28 direct AGREE
fuzz28 generated AGREE
fuzz28 prefix AGREE
fuzz28 wrong DISAGREE
fuzz29 direct AGREE
fuzz29 generated AGREE
fuzz29 prefix AGREE
fuzz29 wrong DISAGREE
fuzz2 direct AGREE
fuzz2 generated AGREE
fuzz2 prefix AGREE
fuzz2 wrong DISAGREE
fuzz30 direct AGREE
fuzz30 generated AGREE
fuzz30 prefix AGREE
fuzz30 wrong DISAGREE
fuzz31 direct AGREE
fuzz31 generated AGREE
fuzz31 prefix AGREE
fuzz31 wrong DISAGREE
fuzz3 direct AGREE
fuzz3 generated AGREE
fuzz3 prefix AGREE
fuzz3 wrong DISAGREE
fuzz4 direct AGREE
fuzz4 generated AGREE
fuzz4 prefix AGREE
fuzz4 wrong DISAGREE
fuzz5 direct AGREE
fuzz5 generated AGREE
fuzz5 prefix AGREE
fuzz5 wrong DISAGREE
fuzz6 direct AGREE
fuzz6 generated AGREE
fuzz6 prefix AGREE
fuzz6 wrong DISAGREE
fuzz7 direct AGREE
fuzz7 generated AGREE
fuzz7 prefix AGREE
fuzz7 wrong DISAGREE
fuzz8 direct AGREE
fuzz8 generated AGREE
fuzz8 prefix AGREE
fuzz8 wrong DISAGREE
fuzz9 direct AGREE
fuzz9 generated AGREE
fuzz9 prefix AGREE
fuzz9 wrong DISAGREE

83
igneum-pow/src/emit.rs
View file

@ -1174,7 +1174,9 @@ fn reg_decl(p: &Program, ty: &str) -> String {
}
let names: Vec<String> = (0..p.registers()).map(|k| format!("r{k}")).collect();
let m = if p.address_mix() {
if ty == "uint32_t" && reg64_prefix() {
if ty == "uint32_t" && reg64_form() == crate::reg64form::Reg64Form::Generated {
format!("\n {ty} m, S, p_, g0, g1, g2, g3, g4, g5, g6, g7; // reg64 full chain in the X4 generated form: the eight group sums, recomputed where the schedule wrote")
} else if ty == "uint32_t" && reg64_prefix() {
format!("\n {ty} m, S, p_, t_; // reg64 full chain in the F05 prefix form: S the running xor of the rotated registers, p_ the prefix, t_ the old term")
} else {
format!("\n {ty} m; // reg64 full chain: the address mix of all 64 registers before every load")
@ -1194,14 +1196,65 @@ fn reg_decl(p: &Program, ty: &str) -> String {
/// `r[s] ^ ror(P_s, 1) ^ (S ^ P_s ^ a[s])` with `P_s` the xor of the first `s` terms. The same hash, the same vectors
/// (`verify::reg64_address_source`); a measurement text for the fleet, never the definition. OpenCL and Metal keep
/// the fold.
static REG64_PREFIX: std::sync::atomic::AtomicBool = std::sync::atomic::AtomicBool::new(false);
/// X4 of the 1.5x programme (9 October 2026): the switch is one value of the CUDA text's form
/// (`crate::reg64form`, `igneum-pow export --reg64-form fold|direct|generated|prefix`); `--reg64-prefix` is `prefix`.
pub fn set_reg64_prefix(on: bool) {
REG64_PREFIX.store(on, std::sync::atomic::Ordering::Relaxed);
crate::reg64form::set_gpu_form(if on { crate::reg64form::Reg64Form::Prefix } else { crate::reg64form::Reg64Form::Fold });
}
pub fn reg64_prefix() -> bool {
REG64_PREFIX.load(std::sync::atomic::Ordering::Relaxed)
crate::reg64form::gpu_form() == crate::reg64form::Reg64Form::Prefix
}
/// The CUDA text's form of the reg64 address mix (the fold unless `--reg64-form` names another).
fn reg64_form() -> crate::reg64form::Reg64Form {
crate::reg64form::gpu_form()
}
/// X4 direct form: the mix statement before a load of source `src` as the definition's closed sum, one rotation
/// per term (`rotl(rK, (62 - k) mod 32)` before the source, `(63 - k) mod 32` after it), xored as a balanced tree.
fn reg64_direct_mix_line(src: u8) -> String {
let s = src as usize;
let terms: Vec<String> = (0..64)
.filter(|&k| k != s)
.map(|k| {
let n = crate::reg64form::direct_rot(k, s);
if n == 0 { format!("r{k}") } else { format!("rotl_imm(r{k}, {n}u)") }
})
.collect();
format!("m = {};", xor_tree(&terms))
}
/// A balanced xor tree of `terms` as text (parenthesised so the compiler is handed the tree, not a chain).
fn xor_tree(terms: &[String]) -> String {
match terms.len() {
0 => "0u".to_string(),
1 => terms[0].clone(),
n => format!("({} ^ {})", xor_tree(&terms[..n / 2]), xor_tree(&terms[n / 2..])),
}
}
/// X4 generated form: one group sum `gJ = a[8J] ^ ... ^ a[8J + 7]` as a statement.
fn reg64_group_line(j: usize) -> String {
let terms: Vec<String> = (j * 8..j * 8 + 8).map(reg64_term).collect();
format!("g{j} = {};", xor_tree(&terms))
}
/// X4 generated form: the statements before a load of source `src` (the plan's stale groups recomputed, then
/// `m = ror(P, 1) ^ S ^ P ^ a[src]` with `S` the eight groups and `P` the groups before src's plus the partial).
fn reg64_generated_mix_line(recompute: &[usize], src: u8) -> String {
let s = src as usize;
let mut out = String::new();
for &j in recompute {
out.push_str(&reg64_group_line(j));
out.push(' ');
}
let groups: Vec<String> = (0..8).map(|j| format!("g{j}")).collect();
let jj = s / 8;
let mut prefix: Vec<String> = (0..jj).map(|j| format!("g{j}")).collect();
prefix.extend((jj * 8..s).map(reg64_term));
out.push_str(&format!("S = {}; p_ = {}; m = rotr_var(p_, 1u) ^ S ^ p_ ^ {};", xor_tree(&groups), xor_tree(&prefix), reg64_term(s)));
out
}
/// `rotl(rK, (63 - k) mod 32)` as text; a rotation of 0 is the register itself (`rotl_imm` takes 1..31).
@ -1220,6 +1273,13 @@ fn reg64_prefix_mix_line(src: u8) -> String {
/// The prefix form's running total after the register init: `S = a[0] ^ ... ^ a[63]`.
fn reg64_prefix_init(p: &Program) -> String {
if p.class.reg64 && p.address_mix() && reg64_form() == crate::reg64form::Reg64Form::Generated {
let mut s = String::from(" // X4 generated form: the eight group sums of the rotated registers\n");
for j in 0..8 {
s.push_str(&format!(" {}\n", reg64_group_line(j)));
}
return s;
}
if !p.class.reg64 || !p.address_mix() || !reg64_prefix() {
return String::new();
}
@ -1278,13 +1338,22 @@ fn cuda_instr_lines(p: &Program, geom: DatasetGeom) -> String {
// just before the load (the verifier's addr_src, the same chain)
let address_mix = p.address_mix();
let addr_src = |a: &str| -> String { if address_mix { format!("({a} ^ m)") } else { a.to_string() } };
for (k, ins) in p.scheduled().iter().enumerate() {
let scheduled = p.scheduled();
let form = reg64_form();
let plan = if address_mix && form == crate::reg64form::Reg64Form::Generated { crate::reg64form::generated_plan(&scheduled, &p.shadow) } else { Vec::new() };
for (k, ins) in scheduled.iter().enumerate() {
let d = format!("r{}", ins.dst);
let a = format!("r{}", ins.src);
let b = format!("r{}", ins.src2);
let prefix = address_mix && reg64_prefix();
if address_mix && ins.op == Op::Load {
s.push_str(&format!(" {}\n", if prefix { reg64_prefix_mix_line(ins.src) } else { reg64_mix_line(p, ins.src) }));
let line = match form {
crate::reg64form::Reg64Form::Prefix => reg64_prefix_mix_line(ins.src),
crate::reg64form::Reg64Form::Direct => reg64_direct_mix_line(ins.src),
crate::reg64form::Reg64Form::Generated => reg64_generated_mix_line(&plan[k], ins.src),
_ => reg64_mix_line(p, ins.src),
};
s.push_str(&format!(" {line}\n"));
}
if prefix {
// the old term of the destination, so S can drop it after the write

1
igneum-pow/src/lib.rs
View file

@ -30,6 +30,7 @@ pub mod emit;
pub mod generator;
pub mod memhard;
pub mod packcheck;
pub mod reg64form;
pub mod seed;
pub mod state;
pub mod verify;

9
igneum-pow/src/main.rs
View file

@ -123,7 +123,9 @@ fn usage() -> ! {
\x20 --dataset-words N research class ds55: the dataset at N words (a multiple of 65,536 in 2^28 ..= 2^31; 1476395008 = 5.5 GiB); a non-power-of-two uses idx = (src * N) >> 32 in every load (spec 01 section 1.13.3), a power of two is --dataset-log2\n\\
\x20 --reg64 the 64-register window per lane over the class (research; the same as --class <class>+reg64; CUDA, OpenCL and Metal texts)\n\
\x20 --reg64-chain reg64 with the full-chain address mix: every load's address consumes all 64 registers (the same as --class <class>+reg64c)\n\
\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)"
\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)\n\
\x20 --reg64-form <f> export: the CUDA texts' reg64 address-mix form, fold (the default), direct, generated or prefix (X4, 1.5x programme; the same hash)\n\
\x20 --reg64-cpu-form <f> the CPU interpreter computes the reg64 address mix in form f (fold, direct, generated, prefix, or wrong: the known-failed form), the X4 differential only"
);
std::process::exit(2)
}
@ -191,6 +193,11 @@ fn parse() -> Args {
a.reg64_chain = true;
}
"--reg64-prefix" => igneum_pow::emit::set_reg64_prefix(true),
"--reg64-form" => match igneum_pow::reg64form::Reg64Form::parse(&val()) {
Some(igneum_pow::reg64form::Reg64Form::Wrong) | None => usage(),
Some(f) => igneum_pow::reg64form::set_gpu_form(f),
},
"--reg64-cpu-form" => igneum_pow::reg64form::set_cpu_form(igneum_pow::reg64form::Reg64Form::parse(&val()).unwrap_or_else(|| usage())),
_ => usage(),
}
}

322
igneum-pow/src/reg64form.rs Normal file
View file

@ -0,0 +1,322 @@
//! X4 of the 1.5x programme (9 October 2026, the k lane): byte-identical implementation forms of the class v6
//! reg64c address mix (`docs/analysis/class-v6/1p5x/x4/README.md`). The DEFINITION stays the verifier's fold
//! (`verify::step`'s `addr_src`: `m = r[k0]; m = rotl(m, 1) ^ r[k1]; ...` over the 63 registers other than the load's
//! source `s`, in index order, the address source `r[s] ^ m`). Every form here computes the same 32-bit word on every
//! register state and every source; none of them is a consensus change, and the default everywhere is the fold.
//!
//! * `Fold`: the frozen text (the 63-term dependent chain per load).
//! * `Direct`: the definition's closed sum written directly, `m = XOR_{k<s} rotl(r[k], (62 - k) mod 32) ^
//! XOR_{k>s} rotl(r[k], (63 - k) mod 32)`, a balanced XOR tree with no carried chain and no state.
//! * `Generated`: a code-generated form over eight group sums `g_j = XOR_{k in 8j..8j+7} a[k]`, `a[k] = rotl(r[k],
//! (63 - k) mod 32)`. The generator reads the static schedule and recomputes, before each load, only the groups
//! written since the previous load ([`generated_plan`]); the shadow block draws its registers from r0..r7
//! (`generator.rs`, `dst = rng.below(8)`), so the 55,296 shadow writes dirty group 0 only. A load's source is
//! `r[s] ^ ror(P_s, 1) ^ S ^ P_s ^ a[s]` with `S = XOR g_j` and `P_s` the whole groups before `s`'s group plus the
//! in-group partial (review B's F05 identity, `verify::reg64_address_source`).
//! * `Prefix`: review B's F05 text as landed (`--reg64-prefix`): a running `S` updated after every write (main and
//! shadow), `P_s` recomputed per load.
//! * `Wrong`: the known-failed variant for the differential test only (`r[s] ^ S ^ a[s]`, every term rotated as if it
//! sat after the source); the differential must refuse it. Never emitted.
use std::sync::atomic::{AtomicU8, Ordering};
use crate::generator::{Instr, Op, LANES};
/// Registers per group of the generated form.
pub const GROUP: usize = 8;
/// Groups of the generated form (64 registers).
pub const GROUPS: usize = 8;
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
pub enum Reg64Form {
Fold,
Direct,
Generated,
Prefix,
Wrong,
}
impl Reg64Form {
pub fn parse(s: &str) -> Option<Reg64Form> {
Some(match s {
"fold" => Reg64Form::Fold,
"direct" => Reg64Form::Direct,
"generated" => Reg64Form::Generated,
"prefix" => Reg64Form::Prefix,
"wrong" => Reg64Form::Wrong,
_ => return None,
})
}
pub fn name(self) -> &'static str {
match self {
Reg64Form::Fold => "fold",
Reg64Form::Direct => "direct",
Reg64Form::Generated => "generated",
Reg64Form::Prefix => "prefix",
Reg64Form::Wrong => "wrong",
}
}
fn code(self) -> u8 {
self as u8
}
fn from_code(c: u8) -> Reg64Form {
[Reg64Form::Fold, Reg64Form::Direct, Reg64Form::Generated, Reg64Form::Prefix, Reg64Form::Wrong][c as usize]
}
}
static GPU_FORM: AtomicU8 = AtomicU8::new(0);
static CPU_FORM: AtomicU8 = AtomicU8::new(0);
/// The CUDA text's form (`igneum-pow export --reg64-form <form>`; `--reg64-prefix` is `prefix`). `Wrong` is refused.
pub fn set_gpu_form(f: Reg64Form) {
assert!(f != Reg64Form::Wrong, "the known-failed form is never emitted");
GPU_FORM.store(f.code(), Ordering::Relaxed);
}
pub fn gpu_form() -> Reg64Form {
Reg64Form::from_code(GPU_FORM.load(Ordering::Relaxed))
}
/// The CPU interpreter's form (`--reg64-cpu-form <form>`, the differential test's switch). The fold is the
/// definition and the default; every other form runs beside it only in the X4 differential.
pub fn set_cpu_form(f: Reg64Form) {
CPU_FORM.store(f.code(), Ordering::Relaxed);
}
pub fn cpu_form() -> Reg64Form {
Reg64Form::from_code(CPU_FORM.load(Ordering::Relaxed))
}
/// `a[k] = rotl(r[k], (63 - k) mod 32)`: register k's rotation in the full 64-register chain.
#[inline(always)]
pub fn term(r: &[u32; 64], k: usize) -> u32 {
r[k].rotate_left(((63 - k) % 32) as u32)
}
/// The rotation register `k` carries in the chain of a load whose source is `s` (k != s).
#[inline(always)]
pub fn direct_rot(k: usize, s: usize) -> u32 {
if k < s { ((62 - k) % 32) as u32 } else { ((63 - k) % 32) as u32 }
}
/// The definition, one lane: `r[s] ^ m` with the 63-term chain (the same loop as `verify::step`).
pub fn fold(r: &[u32; 64], s: usize) -> u32 {
let mut m = 0u32;
let mut started = false;
for (k, &v) in r.iter().enumerate() {
if k == s {
continue;
}
m = if started { m.rotate_left(1) ^ v } else { v };
started = true;
}
r[s] ^ m
}
/// The direct form: the closed sum, one rotation per term.
pub fn direct(r: &[u32; 64], s: usize) -> u32 {
let mut m = 0u32;
for k in 0..64 {
if k != s {
m ^= r[k].rotate_left(direct_rot(k, s));
}
}
r[s] ^ m
}
/// One group sum of the generated form.
#[inline(always)]
pub fn group(r: &[u32; 64], j: usize) -> u32 {
let mut g = 0u32;
for k in j * GROUP..(j + 1) * GROUP {
g ^= term(r, k);
}
g
}
/// The generated form's query from the cached group sums `g` (stale groups give a wrong word: the plan's job).
pub fn grouped(g: &[u32; GROUPS], r: &[u32; 64], s: usize) -> u32 {
let total = g.iter().fold(0u32, |x, y| x ^ y);
let j = s / GROUP;
let mut p = g[..j].iter().fold(0u32, |x, y| x ^ y);
for k in j * GROUP..s {
p ^= term(r, k);
}
r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
}
/// The prefix form's query from a running total `total` (= XOR of every `a[k]` when kept fresh).
pub fn prefixed(total: u32, r: &[u32; 64], s: usize) -> u32 {
let mut p = 0u32;
for k in 0..s {
p ^= term(r, k);
}
r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
}
/// The known-failed form (the F05 test's wrong variant).
pub fn wrong(r: &[u32; 64], s: usize) -> u32 {
let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
r[s] ^ total ^ term(r, s)
}
/// The generated form's static plan: for each statement of the scheduled list, the groups to recompute just before
/// it (non-empty only at loads). The groups entering an iteration are those written after the last load of the
/// previous iteration's list plus every group the shadow block writes (group 0 on the shipped class); the kernel
/// computes all eight after the register init, so iteration 0 recomputes a superset (idempotent).
pub fn generated_plan(scheduled: &[Instr], shadow: &[Instr]) -> Vec<Vec<usize>> {
let all: u8 = 0xff;
let bit = |ins: &Instr| 1u8 << (ins.dst as usize / GROUP);
let mut dirty = all;
for ins in scheduled {
if ins.op == Op::Load {
dirty = 0;
}
dirty |= bit(ins);
}
let shadow_groups = shadow.iter().fold(0u8, |m, ins| m | bit(ins));
let mut dirty = dirty | shadow_groups;
let mut plan = Vec::with_capacity(scheduled.len());
for ins in scheduled {
if ins.op == Op::Load {
plan.push((0..GROUPS).filter(|j| dirty & (1 << j) != 0).collect());
dirty = 0;
} else {
plan.push(Vec::new());
}
dirty |= bit(ins);
}
plan
}
/// The groups the shadow block writes (a bit per group).
pub fn shadow_group_mask(shadow: &[Instr]) -> u8 {
shadow.iter().fold(0u8, |m, ins| m | (1u8 << (ins.dst as usize / GROUP)))
}
/// Counts of the generated plan per iteration: (loads, group recomputes) — the op count's input.
pub fn plan_counts(plan: &[Vec<usize>], scheduled: &[Instr]) -> (usize, usize) {
let loads = scheduled.iter().filter(|i| i.op == Op::Load).count();
let recomputes = plan.iter().map(|v| v.len()).sum();
(loads, recomputes)
}
/// The CPU interpreter's state for a form (the differential's emulation of each kernel text): the generated
/// form's eight cached group sums per lane, recomputed only where [`generated_plan`] says; the prefix form's running
/// total per lane, updated after every write (main list and shadow), as the F05 text does.
pub struct FormState {
form: Reg64Form,
plan: Vec<Vec<usize>>,
groups: [[u32; LANES]; GROUPS],
total: [u32; LANES],
}
fn lane_regs(r: &[[u32; LANES]], lane: usize) -> [u32; 64] {
std::array::from_fn(|k| r[k][lane])
}
impl FormState {
pub fn new(form: Reg64Form, plan: Vec<Vec<usize>>) -> FormState {
FormState { form, plan, groups: [[0; LANES]; GROUPS], total: [0; LANES] }
}
/// After the register init (and the probe's flip): every group and the running total from the live registers.
pub fn init(&mut self, r: &[[u32; LANES]]) {
for lane in 0..LANES {
let regs = lane_regs(r, lane);
for j in 0..GROUPS {
self.groups[j][lane] = group(&regs, j);
}
self.total[lane] = (0..64).map(|k| term(&regs, k)).fold(0, |x, y| x ^ y);
}
}
/// After a write of register `d` whose value before the write was `old`: the prefix form's running total moves
/// by the term's change; the generated form keeps its groups stale until the plan recomputes them.
pub fn after_write(&mut self, r: &[[u32; LANES]], d: usize, old: &[u32; LANES]) {
if self.form == Reg64Form::Prefix {
let rot = ((63 - d) % 32) as u32;
for lane in 0..LANES {
self.total[lane] ^= old[lane].rotate_left(rot) ^ r[d][lane].rotate_left(rot);
}
}
}
/// The address source of the load at scheduled position `k` with source `s`, per lane, in this form.
pub fn source(&mut self, r: &[[u32; LANES]], k: usize, s: usize) -> [u32; LANES] {
if self.form == Reg64Form::Generated {
for &j in &self.plan[k] {
for lane in 0..LANES {
let regs = lane_regs(r, lane);
self.groups[j][lane] = group(&regs, j);
}
}
}
std::array::from_fn(|lane| {
let regs = lane_regs(r, lane);
match self.form {
Reg64Form::Fold => fold(&regs, s),
Reg64Form::Direct => direct(&regs, s),
Reg64Form::Generated => grouped(&std::array::from_fn(|j| self.groups[j][lane]), &regs, s),
Reg64Form::Prefix => prefixed(self.total[lane], &regs, s),
Reg64Form::Wrong => wrong(&regs, s),
}
})
}
}
#[cfg(test)]
mod tests {
use super::*;
fn stream(seed: u64) -> impl FnMut() -> u32 {
let mut x = seed;
move || {
x = x.wrapping_add(0x9e37_79b9_7f4a_7c15);
let mut z = x;
z = (z ^ (z >> 30)).wrapping_mul(0xbf58_476d_1ce4_e5b9);
z = (z ^ (z >> 27)).wrapping_mul(0x94d0_49bb_1331_11eb);
(z ^ (z >> 31)) as u32
}
}
/// Known-failed first: the wrong form must disagree with the fold somewhere; then the three forms agree with the
/// fold on every source over 4,096 random states and on the structured states (all zero, all ones, one bit,
/// the init rule's registers).
#[test]
fn x4_forms_equal_the_fold_and_the_wrong_form_is_refused() {
let mut next = stream(0x1505_0004);
let mut wrong_differs = 0usize;
let mut states: Vec<[u32; 64]> = Vec::new();
for _ in 0..4096 {
let mut r = [0u32; 64];
for v in r.iter_mut() {
*v = next();
}
states.push(r);
}
states.push([0u32; 64]);
states.push([u32::MAX; 64]);
for b in 0..64 * 32 {
let mut r = [0u32; 64];
r[b / 32] = 1 << (b % 32);
states.push(r);
}
let mut r = [0u32; 64];
for k in 0..8 {
r[k] = next();
}
for k in 8..64 {
r[k] = r[k & 7].wrapping_mul(0x9e37_79b9).wrapping_add(k as u32);
}
states.push(r);
for r in &states {
let g: [u32; GROUPS] = std::array::from_fn(|j| group(r, j));
let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
for s in 0..64 {
let want = fold(r, s);
if wrong(r, s) != want {
wrong_differs += 1;
}
assert_eq!(direct(r, s), want, "direct, source r{s}");
assert_eq!(grouped(&g, r, s), want, "generated, source r{s}");
assert_eq!(prefixed(total, r, s), want, "prefix, source r{s}");
}
}
assert!(wrong_differs > 0, "the known-failed form must be refused");
}
}

29
igneum-pow/src/verify.rs
View file

@ -581,6 +581,10 @@ fn interpret_warp_core(
// the iteration's statements: the drawn program, or its interleaved two-window form under reg64
let scheduled = program.scheduled();
let address_mix = program.address_mix();
// X4: a byte-identical form of the address mix beside the definition (crate::reg64form), off by default
let cpu_form = crate::reg64form::cpu_form();
let form_on = address_mix && cpu_form != crate::reg64form::Reg64Form::Fold;
let mut fs = crate::reg64form::FormState::new(cpu_form, if form_on { crate::reg64form::generated_plan(&scheduled, &program.shadow) } else { Vec::new() });
let mut items_derived = 0usize;
let mut idx = [0u32; LANES];
let mut val = [0u32; LANES];
@ -606,9 +610,15 @@ fn interpret_warp_core(
}
}
}
if it == 0 && form_on {
// X4: the form's state from the registers as iteration 0 sees them (after the init and any probe flip)
fs.init(&r);
}
let sel = r[0];
for ins in &scheduled {
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
for (k, ins) in scheduled.iter().enumerate() {
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
let ovr = if form_on && ins.op == Op::Load { Some(fs.source(&r, k, ins.src as usize)) } else { None };
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, ovr.as_ref());
if it == 0 && ins.op == Op::Load {
if let Some(pr) = probe.as_deref_mut() {
if !pr.seen_first_load {
@ -625,12 +635,19 @@ fn interpret_warp_core(
r[d][lane] = m.rmw(&program.seed, base_nonce, lane, slot, r[d][lane]);
}
}
if form_on {
fs.after_write(&r, ins.dst as usize, &old);
}
}
// Latency-shadow block (Counter ASIC 3.0 item 8): the block runs `reps` times after instruction 63 with the
// iteration's `sel`; it is empty on every class without a shadow, so version 2 and class v3 run nothing here.
for _ in 0..program.shadow_reps() {
for ins in &program.shadow {
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, None);
if form_on {
fs.after_write(&r, ins.dst as usize, &old);
}
}
}
}
@ -668,6 +685,7 @@ fn step(
val: &mut [u32; LANES],
items_derived: &mut usize,
address_mix: bool,
src_override: Option<&[u32; LANES]>,
) {
let d = ins.dst as usize;
let a = ins.src as usize;
@ -679,6 +697,11 @@ fn step(
if !address_mix {
return r[a][lane];
}
// X4 (1.5x programme): a byte-identical form computed by the caller; never set unless the differential's
// `--reg64-cpu-form` names a form other than the fold (crate::reg64form)
if let Some(o) = src_override {
return o[lane];
}
let mut m = 0u32;
let mut started = false;
for k in 0..r.len() {

33
tools/1p5x/x4/arith.py Normal file
View file

@ -0,0 +1,33 @@
#!/usr/bin/env python3
"""X4 (1.5x programme): r_new = r0 * g / a from the GPU pairs (gpu_rows.py output) and the chip rows (chip_rows.py
output). g: the card's joules per hash with the form over the frozen text's, the mean of the two same-session passes.
a: the specialist's machine energy with a form over the reference, at the adversary lane's 1.528 microjoules (N5, GDDR7
board), two references: (fold) a specialist that implements the frozen literal fold, (model) the served machine, which
carries no address-mix term. Each side picks its cheapest form on its own; the per-form rows (both sides on one form) are
printed for the record. Usage: arith.py <gpu-rows.txt> <chip-rows.txt> [r0 ...] (default r0 2.0, 1.9, 2.1)."""
import re, sys
gtxt, ctxt = open(sys.argv[1]).read(), open(sys.argv[2]).read()
r0s = [float(x) for x in sys.argv[3:]] or [2.0, 1.9, 2.1]
M = 1528.0
g = {m.group(1).replace("x4-", ""): float(m.group(2)) for m in re.finditer(r"^pair\t(x4-\S+)\t.*\t([0-9.]+)$", gtxt, re.M)}
chip = {}
for line in ctxt.splitlines():
p = line.split("\t")
if len(p) >= 7 and re.match(r"[\d.]+ [\d.]+ [\d.]+$", p[5]):
chip[p[0].split(" (")[0]] = (float(p[5].split()[1]), float(p[6].split()[1]))
fold_s, fold_d = chip["fold"]
print("form\tg\ta vs fold (slot, datapath)\ta vs model (slot, datapath)\tr_new at r0 2.0, same form both sides (vs fold slot, dp; vs model slot, dp)")
for k in ("direct", "generated", "prefix", "grouped incremental"):
s, d = chip[k]
gg = g.get(k, 1.0)
af = ((M + s) / (M + fold_s), (M + d) / (M + fold_d)); am = ((M + s) / M, (M + d) / M)
print(f"{k}\t{gg:.4f}{'' if k in g else ' (no GPU text)'}\t{af[0]:.4f}, {af[1]:.4f}\t{am[0]:.4f}, {am[1]:.4f}\t" + ", ".join(f"{2.0*gg/a:.3f}" for a in (*af, *am)))
gk = min(g, key=g.get); ck = min((k for k in chip if k != "fold"), key=lambda k: chip[k][0])
s, d = chip[ck]
print(f"\nbest pair: the card on '{gk}' (g {g[gk]:.4f}), the specialist on '{ck}'")
for r0 in r0s:
out = []
for lab, a in (("vs fold slot", (M + s) / (M + fold_s)), ("vs fold datapath", (M + d) / (M + fold_d)), ("vs model slot", (M + s) / M), ("vs model datapath", (M + d) / M)):
out.append(f"{lab}: a {a:.4f} r_new {r0 * g[gk] / a:.3f}")
print(f"r0 {r0}: " + "; ".join(out))
print("\nthe yardstick: from 2.0, 1.5 needs g / a = 0.75")

102
tools/1p5x/x4/chip_rows.py Normal file
View file

@ -0,0 +1,102 @@
#!/usr/bin/env python3
"""X4 (1.5x programme): the chip-side cost of each byte-identical reg64c address-mix form, counted from the exported
kernel texts of the frozen object and priced with the adversary lane's calibrated constants (its message of 09:4x UK,
9 October 2026, on class-v6-adversary 43c9f7cd8 tools/chip-model/mf/: e_op 6.55 pJ per lane-op at N5, band 6.01 to
7.77; an xor-rotate that does not pass the slot's macro read about 1.0 pJ; e_rf 3.5 pJ per 256-bit macro access shared by
8 lanes, band 2.0 to 7.0; flop state 0.03 pJ per bit written; the slot reads 3 and writes 1 window register per
instruction already; the chip's shadow 0.672 microjoules and the GDDR7 machine 1.528 microjoules per hash at N5).
Counts per hash per lane: X = xor or rotate-xor ops of the mix, A = window reads beyond the slot's own, F = flop bits
written for the form's state. Two pricings: 'slot' (each mix op a full lane-op, the adversary's literal-fold row) and
'datapath' (each mix op an xor at 1.0 pJ, the running-total row). Usage: chip_rows.py <ex dir with fold/ generated/
prefix/ direct/> [--tsv out.tsv]. Modelled, no chip measured."""
import re, sys
EX = sys.argv[1]
ITS, REPS = 8, 27
E_OP = {"lo": 6.01, "c": 6.55, "hi": 7.77}
E_X_DP = 1.0
E_RF = {"lo": 2.0, "c": 3.5, "hi": 7.0}
E_FLOP_BIT = 0.03
SHADOW_UJ, MACHINE_UJ = 0.672, 1.528
def loop_body(path):
t = open(path).read()
k = t.index("__global__ void igneum_hash(")
t = t[k:]
a = t.index("for (uint32_t it = 0u;")
b = t.index("latency-shadow block", a)
c = t.index("for (uint32_t sh = 0u;", b)
d = t.index("\n }\n", c)
return t[a:b], t[c:d], t[:a]
def terms(expr):
return len(re.findall(r"rotl_imm\(r\d+, \d+u\)|\br\d+\b|\bg\d\b", expr))
def writes(body):
return [int(m.group(1)) for m in re.finditer(r"^\s+r(\d+) = .*//\s*s?\d+ \w+$", body, re.M)]
rows = []
main_f, shadow_f, _ = loop_body(f"{EX}/fold/kernel.cu")
loads_per_it = len(re.findall(r"// \d+ load", main_f))
main_w = writes(main_f)
shadow_w = writes(shadow_f)
assert all(d < 8 for d in shadow_w), "a shadow write outside r0..r7"
L = loads_per_it * ITS
# fold and direct: 63 terms, 63 reads, 63 (fold: rotl(m,1)^r) or 62 (tree) ops per load
rows.append(("fold (frozen)", 63 * L, 63 * L, 0, 0, "the 64 x 32-bit window only", "63 window reads per load"))
rows.append(("direct", 62 * L, 63 * L, 0, 0, "the window only", "63 window reads per load (a tree: depth 6, same reads)"))
# generated: parse each load's statement line
gm, _, ginit = loop_body(f"{EX}/generated/kernel.cu")
X = A = F = 0
for line in gm.splitlines():
if "S = " not in line:
continue
n_groups = len(re.findall(r"\bg\d = \(", line))
X += n_groups * 7; A += n_groups * 8; F += n_groups * 32
p = re.search(r"p_ = (.*?); m =", line).group(1)
pt = terms(p); pr = len(re.findall(r"\br\d+\b", p))
X += 7 + max(pt - 1, 0) + 3
A += pr
X *= ITS; A *= ITS; F *= ITS
rows.append(("generated (GPU text: recompute at load)", X, A, F, 8 * 32, "+8 x 32-bit group sums per lane (32 B, flops)", "group recomputes read 8 registers each; the in-group partial reads up to 7"))
# prefix (F05 text): every write moves S; per load p_ over the first s terms
pm, ps, _ = loop_body(f"{EX}/prefix/kernel.cu")
nw = len(writes(pm)) * ITS + len(writes(ps)) * REPS * ITS
X = 2 * nw; F = 32 * nw; A = 0
for line in pm.splitlines():
m = re.search(r"p_ = (.*?); m =", line)
if m:
pt = terms(m.group(1)); X += (max(pt - 1, 0) + 3) * ITS; A += len(re.findall(r"\br\d+\b", m.group(1))) * ITS
rows.append(("prefix (F05 text: running S on every write)", X, A, F, 32, "+1 x 32-bit running total per lane (flops)", "the old value of every written register (main and shadow) rotated into S"))
# the chip's best: group sums 1..7 kept on main-program writes (dst >= 8), group 0 recomputed at each load
# (the shadow's 55,296 writes land in r0..r7 only, so they move nothing kept)
upd = sum(1 for d in main_w if d >= 8) * ITS
X = 2 * upd; F = 32 * upd; A = 0
for line in gm.splitlines():
m = re.search(r"p_ = (.*?); m =", line)
if m:
p = m.group(1)
X += (7 + 7 + max(terms(p) - 1, 0) + 3) * ITS
A += (8 + len(re.findall(r"\br\d+\b", p))) * ITS
F += 32 * ITS
rows.append(("grouped incremental (chip only, by the same identity)", X, A, F, 8 * 32, "+8 x 32-bit group sums per lane (32 B)", "groups 1..7 move on base writes to r8..r63; group 0 recomputed at each load (8 reads)"))
def price(X, A, F, pr, b):
e_x = E_OP[b] if pr == "slot" else E_X_DP
return (X * e_x + A * E_RF[b] / 8 + F * E_FLOP_BIT) / 1000.0 # nJ
out = []
hdr = "form\tmix ops X\textra reads A\tflop bits F\tstate bits per lane\tslot nJ (lo c hi)\tdatapath nJ (lo c hi)\tstate\tports"
out.append(hdr)
for name, X, A, F, sb, state, ports in rows:
s = [price(X, A, F, "slot", b) for b in ("lo", "c", "hi")]
d = [price(X, A, F, "dp", b) for b in ("lo", "c", "hi")]
out.append(f"{name}\t{X}\t{A}\t{F}\t{sb}\t{s[0]:.1f} {s[1]:.1f} {s[2]:.1f}\t{d[0]:.1f} {d[1]:.1f} {d[2]:.1f}\t{state}\t{ports}")
print(f"# loads per hash executed {L} ({loads_per_it} per iteration x {ITS}); base writes per iteration {len(main_w)} ({sum(1 for d in main_w if d >= 8)} to r8..r63); shadow writes per pass {len(shadow_w)}, all in r0..r7")
print("\n".join(out))
# per-lane-op delta and a: machine energy with the form against the model's machine (which carries no mix cost)
print("\n# a = (machine + form) / machine, machine 1.528 microjoules (N5, GDDR7 board, no mix term); per-lane-op delta over the 102,612 shadow+base lane-ops")
for name, X, A, F, sb, *_ in rows:
for pr in ("slot", "dp"):
e = price(X, A, F, pr, "c")
print(f"{name}\t{pr}\t+{e:.1f} nJ\ta {(MACHINE_UJ*1000 + e)/(MACHINE_UJ*1000):.4f}\tper lane-op +{e*1000/102612:.3f} pJ\tof the shadow +{100*e/(SHADOW_UJ*1000):.1f} percent")

84
tools/1p5x/x4/differential.sh Executable file
View file

@ -0,0 +1,84 @@
#!/usr/bin/env bash
# X4 (1.5x programme): the CPU differential of the reg64c address-mix forms against the frozen definition.
# Runs on a build box (never the Mac), from the box worktree root holding igneum-pow/ (built --release) and in/:
# in/node1-state.igsd1 (sha256 abb58003...), in/state-epoch2.igsd1 (f36e6bba...),
# in/ref0{1,2,3}/{ref-D.txt,ref-D1.txt,job-context.json} (build-1:/srv/artefacts/tas/same-work-20261008-0N/).
# Order: the known-failed form first (it must disagree on every reg64c context, or the test is void), then the
# forms fold, direct, generated and prefix must equal the same-work references on every sampled nonce, then the
# fuzz set (random epoch, era and prehash on the class v6 string) where each form must equal the fold.
# Usage: tools/1p5x/x4/differential.sh <out dir> [count per window, default 4096] [fuzz seeds, default 32]
set -u
OUT=${1:?out dir}; N=${2:-4096}; FZ=${3:-32}
B=igneum-pow/target/release/igneum-pow
mkdir -p "$OUT"
PRE=0000000000000000000000000000000000000000000000000000000000000001
G=edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07
CS=af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3
V5E=3c3fab434f7fd894ce6db0b09f298c3865726253e4fc68fd77acd163ccea8221
V5ERA=7c36b83374a673e990213be462509dcb08bcfc85144306aa9517cf3ad66faf6e
day() { printf '69676e65756d2d6461792f%s' "$(python3 -c "import struct,sys; print(struct.pack('<Q', int(sys.argv[1])).hex())" "$1")"; }
args_for() { # context day-index
case $1 in
01) echo "--epoch-hex $G --day-hex $(day $2) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$G --era-widths 4 --state in/node1-state.igsd1" ;;
02) echo "--epoch-hex $CS --day-hex $(day $2) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$G --era-widths 4 --state in/node1-state.igsd1" ;;
03) echo "--epoch-hex $V5E --day-hex $(day $2) --program-class v5 --era-hex $V5ERA --state in/state-epoch2.igsd1" ;;
esac
}
# windows: (context, day index offset, ref file, start nonce)
JOBS=$OUT/jobs.txt; : > "$JOBS"
for c in 01 02 03; do
d0=$( [ $c = 03 ] && echo 20734 || echo 20730 )
for form in wrong fold direct generated prefix; do
for w in "D 0" "D $((1572864 - N))" "D1 1572864" "D1 $((3145728 - N))"; do
set -- $w; dd=$([ $1 = D ] && echo $d0 || echo $((d0 + 1)))
echo "ctx $c $form $1 $2 $dd" >> "$JOBS"
done
done
done
for i in $(seq 0 $((FZ - 1))); do
for form in wrong fold direct generated prefix; do echo "fuzz $i $form" >> "$JOBS"; done
done
run_job() {
set -- $1
if [ "$1" = ctx ]; then
local c=$2 form=$3 ref=$4 start=$5 dd=$6
local f=$OUT/ctx$c-$form-$ref-$start.txt
$B hash-bound $(args_for $c $dd) --prehash $PRE --nonce $start --count $N --reg64-cpu-form $form > $f 2>$f.err
local lineno
[ "$ref" = D ] && lineno=$((start + 1)) || lineno=$((start - 1572864 + 1))
if tail -n +$lineno in/ref$c/ref-$ref.txt | head -n $N | cmp -s - $f; then echo "ctx$c $form $ref@$start AGREE"; else echo "ctx$c $form $ref@$start DISAGREE"; fi
else
local i=$2 form=$3
local h=$(printf 'x4-fuzz-%d' $i | sha256sum | cut -c1-64)
local era=$(printf 'x4-era-%d' $i | sha256sum | cut -c1-64)
local pre=$(printf 'x4-pre-%d' $i | sha256sum | cut -c1-64)
local nonce=$(( 0x$(printf 'x4-nonce-%d' $i | sha256sum | cut -c1-6) * 32 ))
$B hash-bound --epoch-hex $h --day-hex $(day 20730) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$era --era-widths 4 --state in/node1-state.igsd1 --prehash $pre --nonce $nonce --count 1024 --reg64-cpu-form $form > $OUT/fuzz$i-$form.txt 2>$OUT/fuzz$i-$form.txt.err
echo "fuzz$i $form DONE"
fi
}
export -f run_job args_for day; export B OUT N PRE G CS V5E V5ERA
xargs -P ${PAR:-24} -I{} bash -c 'run_job "{}"' < "$JOBS" > "$OUT/runs.txt"
# fuzz verdicts against the fold
for i in $(seq 0 $((FZ - 1))); do
for form in wrong direct generated prefix; do
if cmp -s $OUT/fuzz$i-fold.txt $OUT/fuzz$i-$form.txt; then echo "fuzz$i $form AGREE"; else echo "fuzz$i $form DISAGREE"; fi
done
done >> "$OUT/runs.txt"
grep -v DONE "$OUT/runs.txt" | sort > "$OUT/verdicts.txt"
# the verdict: known-failed refused on every reg64c window and fuzz seed; every other form agrees everywhere;
# context 03 (class v5, no reg64) is the no-op control: every form, the wrong one too, agrees with the reference
python3 - "$OUT/verdicts.txt" <<'PY' | tee "$OUT/VERDICT"
import sys, collections
rows=[l.split() for l in open(sys.argv[1])]
bad=[]; t=collections.Counter()
for key, form, *rest in rows:
v=rest[-1]; t[(form,v)]+=1
reg64 = not key.startswith("ctx03")
want = "DISAGREE" if (form=="wrong" and reg64) else "AGREE"
if v!=want: bad.append(" ".join([key,form]+rest))
print("tally", dict(t))
print("known-failed refused on every reg64c window and seed:", all(r[-1]=="DISAGREE" for r in rows if r[1]=="wrong" and not r[0].startswith("ctx03")))
print("VERDICT", "EQUIVALENT" if not bad else "FAIL", "mismatches", len(bad))
for b in bad[:20]: print(" ", b)
PY

43
tools/1p5x/x4/gpu_rows.py Normal file
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@ -0,0 +1,43 @@
#!/usr/bin/env python3
"""X4 (1.5x programme): the GPU rows of a pod-x4.sh run (the hash lane's recipe, build-1:/srv/artefacts/1p5x/
gpu-row-recipe.md sha cbab453c: rate = the worker's own mhs=, watts = mean power.draw from 8 s in to the end of the
timed dispatches, nJ per hash = W / MH/s x 1,000, check=PASS and the fingerprint gate the row; pairs inside one
session). Usage: gpu_rows.py <pod out dir> <out-run.log>. Prints the per-run rows, then each form against the frozen
pack: pass 1 against run 1, pass 2 against run 8 (the order A B C D D C B A), and the mean of the two."""
import re, sys, glob, os, statistics as st
d, runlog = sys.argv[1], sys.argv[2]
times = {m.group(1): (int(m.group(2)), int(m.group(3))) for m in re.finditer(r"RESULT run (\S+) rc=0 secs=\d+ t0=(\d+) t1=(\d+)", open(runlog).read())}
rows = {}
for name, (t0, t1) in sorted(times.items()):
log = open(f"{d}/bench-{name}.log").read()
r = re.search(r"^RESULT (.*)$", log, re.M).group(1)
f = dict(kv.split("=", 1) for kv in r.split() if "=" in kv)
w, clk, util = [], [], []
for line in open(f"{d}/smi-{name}.csv"):
p = line.strip().split(",")
if len(p) < 5 or not p[1].replace(".", "").isdigit():
continue
t = int(p[0])
if t0 + 8 <= t <= t1:
w.append(float(p[1])); clk.append(float(p[2])); util.append(float(p[3]))
mhs = float(f["mhs"]); W = st.mean(w)
rows[name] = dict(pack=name.split("-", 1)[1], mhs=mhs, W=W, nj=W / mhs * 1000, fp=f["fingerprint"], check=f["check"], regs=f["regs"], bps=f["blocks_per_sm"], sm=st.mean(clk), util=st.mean(util), n=len(w))
print("run\tpack\tMH/s\tW\tnJ per hash\tsm MHz\tutil\tsamples\tregs\tblocks/SM\tfingerprint\tcheck")
for k, r in rows.items():
print(f"{k}\t{r['pack']}\t{r['mhs']:.3f}\t{r['W']:.1f}\t{r['nj']:.0f}\t{r['sm']:.0f}\t{r['util']:.0f}\t{r['n']}\t{r['regs']}\t{r['bps']}\t{r['fp']}\t{r['check']}")
ks = list(rows)
frozen = [k for k in ks if k.endswith("hl-v6-all")]
print("\npair\tform\tpass 1 rate %\tpass 1 J/hash %\tpass 2 rate %\tpass 2 J/hash %\tmean rate %\tmean J/hash %\tg (J/hash ratio)")
f1, f2 = rows[frozen[0]], rows[frozen[-1]]
aa_r = 100 * (f2["mhs"] / f1["mhs"] - 1); aa_e = 100 * (f2["nj"] / f1["nj"] - 1)
print(f"A/A\thl-v6-all run 8 vs run 1\t{aa_r:+.2f}\t{aa_e:+.2f}\t\t\t\t\t")
for form in ("x4-direct", "x4-generated", "x4-prefix"):
rs = [k for k in ks if k.endswith(form)]
if len(rs) < 2:
continue
a, b = rows[rs[0]], rows[rs[1]]
p1r, p1e = 100 * (a["mhs"] / f1["mhs"] - 1), 100 * (a["nj"] / f1["nj"] - 1)
p2r, p2e = 100 * (b["mhs"] / f2["mhs"] - 1), 100 * (b["nj"] / f2["nj"] - 1)
g = ((a["nj"] / f1["nj"]) + (b["nj"] / f2["nj"])) / 2
print(f"pair\t{form}\t{p1r:+.2f}\t{p1e:+.2f}\t{p2r:+.2f}\t{p2e:+.2f}\t{(p1r+p2r)/2:+.2f}\t{(p1e+p2e)/2:+.2f}\t{g:.4f}")

28
tools/1p5x/x4/pod-x4.sh Executable file
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#!/usr/bin/env bash
# X4 (1.5x programme) on one rented card: same-session pairs of the frozen pack against the three alternative
# packs, stock clocks, the gen-6 worker --bench (250 x 2^24, block-warps 1, the pack self-test first: check=PASS and
# the 2^24 fingerprint), nvidia-smi power.draw at 1 Hz for each run. Order A B C D D C B A (the second pass reversed,
# so drift and heat land on both sides of every pair). Logs under /root/x4/out. Started under /root/x4/pids/bench.pid.
set -u
cd /root/x4
W=${W:-/root/x4/igneum-worker-cuda-gen6}
mkdir -p out pids
echo $$ > pids/bench.pid
echo "RESULT start $(date -u +%FT%TZ) $(nvidia-smi --query-gpu=name,driver_version,power.limit,clocks.max.sm --format=csv,noheader -i 0)"
echo "RESULT worker sha256 $(sha256sum $W | cut -c1-16)"
ORDER=${ORDER:-"hl-v6-all x4-direct x4-generated x4-prefix x4-prefix x4-generated x4-direct hl-v6-all"}
i=0
for P in $ORDER; do
i=$((i + 1)); N=$(printf '%02d-%s' $i $P)
( while :; do echo "$(date -u +%s),$(nvidia-smi --query-gpu=power.draw,clocks.sm,utilization.gpu,temperature.gpu --format=csv,noheader,nounits -i 0 | tr -d ' ')"; sleep 1; done ) > out/smi-$N.csv 2>/dev/null &
SMI=$!; echo $SMI > pids/smi.pid
T0=$(date +%s)
timeout 900 $W --bench --pack packs/$P --batches ${BATCHES:-250} --batch-log2 24 --block-warps 1 --device 0 > out/bench-$N.log 2>&1; RC=$?
T1=$(date +%s)
kill $SMI 2>/dev/null; rm -f pids/smi.pid
echo "RESULT run $N rc=$RC secs=$((T1 - T0)) t0=$T0 t1=$T1"
grep -E "^RESULT|self-test|timed dispatches" out/bench-$N.log | sed "s/^/BENCH $N | /"
sleep ${GAP:-20}
done
echo "RESULT end $(date -u +%FT%TZ)"
rm -f pids/bench.pid

3
tools/ci/export-exclude.txt
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@ -36,6 +36,9 @@ docs/analysis/class-v6/history.md
docs/analysis/class-v6/invention.md
docs/analysis/class-v6/mixed-fp32.md
docs/analysis/class-v6/multi-family-adversary.md
# 9 October 2026: the 1.5x programme X4, the reg64c implementation forms (research documents and their generators)
docs/analysis/class-v6/1p5x/x4
tools/1p5x/x4
# 8 October 2026: the miner window audit (an internal design record: the founder's order, lane ids, the build plan)
docs/design/app-audit-2026-10-08.md
# 8 October 2026: the public shape of the pre-2.0 ledger, kept as history at the Igneum 2.0 reset (not served, not linked;