X4 (1.5x): byte-identical reg64c address-mix forms (direct, generated, prefix) behind --reg64-form and --reg64-cpu-form; the fold stays the definition and the default
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
igneum-labs
parent
688904914f
commit
e1a910c7fc
5 changed files with 433 additions and 11 deletions
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@ -1174,7 +1174,9 @@ fn reg_decl(p: &Program, ty: &str) -> String {
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}
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let names: Vec<String> = (0..p.registers()).map(|k| format!("r{k}")).collect();
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let m = if p.address_mix() {
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if ty == "uint32_t" && reg64_prefix() {
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if ty == "uint32_t" && reg64_form() == crate::reg64form::Reg64Form::Generated {
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format!("\n {ty} m, S, p_, g0, g1, g2, g3, g4, g5, g6, g7; // reg64 full chain in the X4 generated form: the eight group sums, recomputed where the schedule wrote")
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} else if ty == "uint32_t" && reg64_prefix() {
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format!("\n {ty} m, S, p_, t_; // reg64 full chain in the F05 prefix form: S the running xor of the rotated registers, p_ the prefix, t_ the old term")
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} else {
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format!("\n {ty} m; // reg64 full chain: the address mix of all 64 registers before every load")
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@ -1194,14 +1196,65 @@ fn reg_decl(p: &Program, ty: &str) -> String {
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/// `r[s] ^ ror(P_s, 1) ^ (S ^ P_s ^ a[s])` with `P_s` the xor of the first `s` terms. The same hash, the same vectors
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/// (`verify::reg64_address_source`); a measurement text for the fleet, never the definition. OpenCL and Metal keep
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/// the fold.
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static REG64_PREFIX: std::sync::atomic::AtomicBool = std::sync::atomic::AtomicBool::new(false);
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/// X4 of the 1.5x programme (9 October 2026): the switch is one value of the CUDA text's form
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/// (`crate::reg64form`, `igneum-pow export --reg64-form fold|direct|generated|prefix`); `--reg64-prefix` is `prefix`.
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pub fn set_reg64_prefix(on: bool) {
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REG64_PREFIX.store(on, std::sync::atomic::Ordering::Relaxed);
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crate::reg64form::set_gpu_form(if on { crate::reg64form::Reg64Form::Prefix } else { crate::reg64form::Reg64Form::Fold });
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}
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pub fn reg64_prefix() -> bool {
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REG64_PREFIX.load(std::sync::atomic::Ordering::Relaxed)
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crate::reg64form::gpu_form() == crate::reg64form::Reg64Form::Prefix
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}
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/// The CUDA text's form of the reg64 address mix (the fold unless `--reg64-form` names another).
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fn reg64_form() -> crate::reg64form::Reg64Form {
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crate::reg64form::gpu_form()
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}
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/// X4 direct form: the mix statement before a load of source `src` as the definition's closed sum, one rotation
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/// per term (`rotl(rK, (62 - k) mod 32)` before the source, `(63 - k) mod 32` after it), xored as a balanced tree.
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fn reg64_direct_mix_line(src: u8) -> String {
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let s = src as usize;
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let terms: Vec<String> = (0..64)
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.filter(|&k| k != s)
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.map(|k| {
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let n = crate::reg64form::direct_rot(k, s);
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if n == 0 { format!("r{k}") } else { format!("rotl_imm(r{k}, {n}u)") }
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})
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.collect();
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format!("m = {};", xor_tree(&terms))
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}
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/// A balanced xor tree of `terms` as text (parenthesised so the compiler is handed the tree, not a chain).
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fn xor_tree(terms: &[String]) -> String {
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match terms.len() {
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0 => "0u".to_string(),
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1 => terms[0].clone(),
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n => format!("({} ^ {})", xor_tree(&terms[..n / 2]), xor_tree(&terms[n / 2..])),
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}
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}
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/// X4 generated form: one group sum `gJ = a[8J] ^ ... ^ a[8J + 7]` as a statement.
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fn reg64_group_line(j: usize) -> String {
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let terms: Vec<String> = (j * 8..j * 8 + 8).map(reg64_term).collect();
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format!("g{j} = {};", xor_tree(&terms))
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}
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/// X4 generated form: the statements before a load of source `src` (the plan's stale groups recomputed, then
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/// `m = ror(P, 1) ^ S ^ P ^ a[src]` with `S` the eight groups and `P` the groups before src's plus the partial).
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fn reg64_generated_mix_line(recompute: &[usize], src: u8) -> String {
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let s = src as usize;
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let mut out = String::new();
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for &j in recompute {
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out.push_str(®64_group_line(j));
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out.push(' ');
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}
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let groups: Vec<String> = (0..8).map(|j| format!("g{j}")).collect();
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let jj = s / 8;
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let mut prefix: Vec<String> = (0..jj).map(|j| format!("g{j}")).collect();
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prefix.extend((jj * 8..s).map(reg64_term));
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out.push_str(&format!("S = {}; p_ = {}; m = rotr_var(p_, 1u) ^ S ^ p_ ^ {};", xor_tree(&groups), xor_tree(&prefix), reg64_term(s)));
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out
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}
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/// `rotl(rK, (63 - k) mod 32)` as text; a rotation of 0 is the register itself (`rotl_imm` takes 1..31).
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@ -1220,6 +1273,13 @@ fn reg64_prefix_mix_line(src: u8) -> String {
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/// The prefix form's running total after the register init: `S = a[0] ^ ... ^ a[63]`.
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fn reg64_prefix_init(p: &Program) -> String {
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if p.class.reg64 && p.address_mix() && reg64_form() == crate::reg64form::Reg64Form::Generated {
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let mut s = String::from(" // X4 generated form: the eight group sums of the rotated registers\n");
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for j in 0..8 {
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s.push_str(&format!(" {}\n", reg64_group_line(j)));
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}
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return s;
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}
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if !p.class.reg64 || !p.address_mix() || !reg64_prefix() {
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return String::new();
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}
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@ -1278,13 +1338,22 @@ fn cuda_instr_lines(p: &Program, geom: DatasetGeom) -> String {
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// just before the load (the verifier's addr_src, the same chain)
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let address_mix = p.address_mix();
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let addr_src = |a: &str| -> String { if address_mix { format!("({a} ^ m)") } else { a.to_string() } };
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for (k, ins) in p.scheduled().iter().enumerate() {
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let scheduled = p.scheduled();
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let form = reg64_form();
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let plan = if address_mix && form == crate::reg64form::Reg64Form::Generated { crate::reg64form::generated_plan(&scheduled, &p.shadow) } else { Vec::new() };
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for (k, ins) in scheduled.iter().enumerate() {
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let d = format!("r{}", ins.dst);
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let a = format!("r{}", ins.src);
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let b = format!("r{}", ins.src2);
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let prefix = address_mix && reg64_prefix();
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if address_mix && ins.op == Op::Load {
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s.push_str(&format!(" {}\n", if prefix { reg64_prefix_mix_line(ins.src) } else { reg64_mix_line(p, ins.src) }));
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let line = match form {
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crate::reg64form::Reg64Form::Prefix => reg64_prefix_mix_line(ins.src),
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crate::reg64form::Reg64Form::Direct => reg64_direct_mix_line(ins.src),
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crate::reg64form::Reg64Form::Generated => reg64_generated_mix_line(&plan[k], ins.src),
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_ => reg64_mix_line(p, ins.src),
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};
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s.push_str(&format!(" {line}\n"));
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}
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if prefix {
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// the old term of the destination, so S can drop it after the write
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@ -30,6 +30,7 @@ pub mod emit;
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pub mod generator;
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pub mod memhard;
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pub mod packcheck;
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pub mod reg64form;
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pub mod seed;
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pub mod state;
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pub mod verify;
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@ -123,7 +123,9 @@ fn usage() -> ! {
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\x20 --dataset-words N research class ds55: the dataset at N words (a multiple of 65,536 in 2^28 ..= 2^31; 1476395008 = 5.5 GiB); a non-power-of-two uses idx = (src * N) >> 32 in every load (spec 01 section 1.13.3), a power of two is --dataset-log2\n\\
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\x20 --reg64 the 64-register window per lane over the class (research; the same as --class <class>+reg64; CUDA, OpenCL and Metal texts)\n\
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\x20 --reg64-chain reg64 with the full-chain address mix: every load's address consumes all 64 registers (the same as --class <class>+reg64c)\n\
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\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)"
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\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)\n\
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\x20 --reg64-form <f> export: the CUDA texts' reg64 address-mix form, fold (the default), direct, generated or prefix (X4, 1.5x programme; the same hash)\n\
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\x20 --reg64-cpu-form <f> the CPU interpreter computes the reg64 address mix in form f (fold, direct, generated, prefix, or wrong: the known-failed form), the X4 differential only"
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);
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std::process::exit(2)
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}
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@ -191,6 +193,11 @@ fn parse() -> Args {
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a.reg64_chain = true;
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}
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"--reg64-prefix" => igneum_pow::emit::set_reg64_prefix(true),
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"--reg64-form" => match igneum_pow::reg64form::Reg64Form::parse(&val()) {
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Some(igneum_pow::reg64form::Reg64Form::Wrong) | None => usage(),
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Some(f) => igneum_pow::reg64form::set_gpu_form(f),
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},
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"--reg64-cpu-form" => igneum_pow::reg64form::set_cpu_form(igneum_pow::reg64form::Reg64Form::parse(&val()).unwrap_or_else(|| usage())),
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_ => usage(),
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}
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}
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322
igneum-pow/src/reg64form.rs
Normal file
322
igneum-pow/src/reg64form.rs
Normal file
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@ -0,0 +1,322 @@
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//! X4 of the 1.5x programme (9 October 2026, the k lane): byte-identical implementation forms of the class v6
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//! reg64c address mix (`docs/analysis/class-v6/1p5x/x4/README.md`). The DEFINITION stays the verifier's fold
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//! (`verify::step`'s `addr_src`: `m = r[k0]; m = rotl(m, 1) ^ r[k1]; ...` over the 63 registers other than the load's
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//! source `s`, in index order, the address source `r[s] ^ m`). Every form here computes the same 32-bit word on every
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//! register state and every source; none of them is a consensus change, and the default everywhere is the fold.
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//!
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//! * `Fold`: the frozen text (the 63-term dependent chain per load).
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//! * `Direct`: the definition's closed sum written directly, `m = XOR_{k<s} rotl(r[k], (62 - k) mod 32) ^
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//! XOR_{k>s} rotl(r[k], (63 - k) mod 32)`, a balanced XOR tree with no carried chain and no state.
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//! * `Generated`: a code-generated form over eight group sums `g_j = XOR_{k in 8j..8j+7} a[k]`, `a[k] = rotl(r[k],
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//! (63 - k) mod 32)`. The generator reads the static schedule and recomputes, before each load, only the groups
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//! written since the previous load ([`generated_plan`]); the shadow block draws its registers from r0..r7
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//! (`generator.rs`, `dst = rng.below(8)`), so the 55,296 shadow writes dirty group 0 only. A load's source is
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//! `r[s] ^ ror(P_s, 1) ^ S ^ P_s ^ a[s]` with `S = XOR g_j` and `P_s` the whole groups before `s`'s group plus the
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//! in-group partial (review B's F05 identity, `verify::reg64_address_source`).
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//! * `Prefix`: review B's F05 text as landed (`--reg64-prefix`): a running `S` updated after every write (main and
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//! shadow), `P_s` recomputed per load.
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//! * `Wrong`: the known-failed variant for the differential test only (`r[s] ^ S ^ a[s]`, every term rotated as if it
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//! sat after the source); the differential must refuse it. Never emitted.
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use std::sync::atomic::{AtomicU8, Ordering};
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use crate::generator::{Instr, Op, LANES};
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/// Registers per group of the generated form.
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pub const GROUP: usize = 8;
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/// Groups of the generated form (64 registers).
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pub const GROUPS: usize = 8;
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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pub enum Reg64Form {
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Fold,
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Direct,
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Generated,
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Prefix,
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Wrong,
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}
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impl Reg64Form {
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pub fn parse(s: &str) -> Option<Reg64Form> {
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Some(match s {
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"fold" => Reg64Form::Fold,
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"direct" => Reg64Form::Direct,
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"generated" => Reg64Form::Generated,
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"prefix" => Reg64Form::Prefix,
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"wrong" => Reg64Form::Wrong,
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_ => return None,
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})
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}
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pub fn name(self) -> &'static str {
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match self {
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Reg64Form::Fold => "fold",
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Reg64Form::Direct => "direct",
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Reg64Form::Generated => "generated",
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Reg64Form::Prefix => "prefix",
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Reg64Form::Wrong => "wrong",
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}
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}
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fn code(self) -> u8 {
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self as u8
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}
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fn from_code(c: u8) -> Reg64Form {
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[Reg64Form::Fold, Reg64Form::Direct, Reg64Form::Generated, Reg64Form::Prefix, Reg64Form::Wrong][c as usize]
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}
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}
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static GPU_FORM: AtomicU8 = AtomicU8::new(0);
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static CPU_FORM: AtomicU8 = AtomicU8::new(0);
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/// The CUDA text's form (`igneum-pow export --reg64-form <form>`; `--reg64-prefix` is `prefix`). `Wrong` is refused.
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pub fn set_gpu_form(f: Reg64Form) {
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assert!(f != Reg64Form::Wrong, "the known-failed form is never emitted");
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GPU_FORM.store(f.code(), Ordering::Relaxed);
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}
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pub fn gpu_form() -> Reg64Form {
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Reg64Form::from_code(GPU_FORM.load(Ordering::Relaxed))
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}
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/// The CPU interpreter's form (`--reg64-cpu-form <form>`, the differential test's switch). The fold is the
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/// definition and the default; every other form runs beside it only in the X4 differential.
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pub fn set_cpu_form(f: Reg64Form) {
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CPU_FORM.store(f.code(), Ordering::Relaxed);
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}
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pub fn cpu_form() -> Reg64Form {
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Reg64Form::from_code(CPU_FORM.load(Ordering::Relaxed))
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}
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/// `a[k] = rotl(r[k], (63 - k) mod 32)`: register k's rotation in the full 64-register chain.
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#[inline(always)]
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pub fn term(r: &[u32; 64], k: usize) -> u32 {
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r[k].rotate_left(((63 - k) % 32) as u32)
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}
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/// The rotation register `k` carries in the chain of a load whose source is `s` (k != s).
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#[inline(always)]
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pub fn direct_rot(k: usize, s: usize) -> u32 {
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if k < s { ((62 - k) % 32) as u32 } else { ((63 - k) % 32) as u32 }
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}
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/// The definition, one lane: `r[s] ^ m` with the 63-term chain (the same loop as `verify::step`).
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pub fn fold(r: &[u32; 64], s: usize) -> u32 {
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let mut m = 0u32;
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let mut started = false;
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for (k, &v) in r.iter().enumerate() {
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if k == s {
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continue;
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}
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m = if started { m.rotate_left(1) ^ v } else { v };
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started = true;
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}
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r[s] ^ m
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}
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/// The direct form: the closed sum, one rotation per term.
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pub fn direct(r: &[u32; 64], s: usize) -> u32 {
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let mut m = 0u32;
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for k in 0..64 {
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if k != s {
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m ^= r[k].rotate_left(direct_rot(k, s));
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}
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}
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r[s] ^ m
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}
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/// One group sum of the generated form.
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#[inline(always)]
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pub fn group(r: &[u32; 64], j: usize) -> u32 {
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let mut g = 0u32;
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for k in j * GROUP..(j + 1) * GROUP {
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g ^= term(r, k);
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}
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g
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}
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/// The generated form's query from the cached group sums `g` (stale groups give a wrong word: the plan's job).
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pub fn grouped(g: &[u32; GROUPS], r: &[u32; 64], s: usize) -> u32 {
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let total = g.iter().fold(0u32, |x, y| x ^ y);
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let j = s / GROUP;
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let mut p = g[..j].iter().fold(0u32, |x, y| x ^ y);
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for k in j * GROUP..s {
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p ^= term(r, k);
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}
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r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
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}
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/// The prefix form's query from a running total `total` (= XOR of every `a[k]` when kept fresh).
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pub fn prefixed(total: u32, r: &[u32; 64], s: usize) -> u32 {
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let mut p = 0u32;
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for k in 0..s {
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p ^= term(r, k);
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}
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r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
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}
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/// The known-failed form (the F05 test's wrong variant).
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pub fn wrong(r: &[u32; 64], s: usize) -> u32 {
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let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
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r[s] ^ total ^ term(r, s)
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}
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/// The generated form's static plan: for each statement of the scheduled list, the groups to recompute just before
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/// it (non-empty only at loads). The groups entering an iteration are those written after the last load of the
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/// previous iteration's list plus every group the shadow block writes (group 0 on the shipped class); the kernel
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/// computes all eight after the register init, so iteration 0 recomputes a superset (idempotent).
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pub fn generated_plan(scheduled: &[Instr], shadow: &[Instr]) -> Vec<Vec<usize>> {
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let all: u8 = 0xff;
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let bit = |ins: &Instr| 1u8 << (ins.dst as usize / GROUP);
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let mut dirty = all;
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for ins in scheduled {
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if ins.op == Op::Load {
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dirty = 0;
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}
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dirty |= bit(ins);
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}
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let shadow_groups = shadow.iter().fold(0u8, |m, ins| m | bit(ins));
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let mut dirty = dirty | shadow_groups;
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let mut plan = Vec::with_capacity(scheduled.len());
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for ins in scheduled {
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if ins.op == Op::Load {
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plan.push((0..GROUPS).filter(|j| dirty & (1 << j) != 0).collect());
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dirty = 0;
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} else {
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plan.push(Vec::new());
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}
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dirty |= bit(ins);
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}
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plan
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}
|
||||
|
||||
/// The groups the shadow block writes (a bit per group).
|
||||
pub fn shadow_group_mask(shadow: &[Instr]) -> u8 {
|
||||
shadow.iter().fold(0u8, |m, ins| m | (1u8 << (ins.dst as usize / GROUP)))
|
||||
}
|
||||
|
||||
/// Counts of the generated plan per iteration: (loads, group recomputes) — the op count's input.
|
||||
pub fn plan_counts(plan: &[Vec<usize>], scheduled: &[Instr]) -> (usize, usize) {
|
||||
let loads = scheduled.iter().filter(|i| i.op == Op::Load).count();
|
||||
let recomputes = plan.iter().map(|v| v.len()).sum();
|
||||
(loads, recomputes)
|
||||
}
|
||||
|
||||
/// The CPU interpreter's state for a form (the differential's emulation of each kernel text): the generated
|
||||
/// form's eight cached group sums per lane, recomputed only where [`generated_plan`] says; the prefix form's running
|
||||
/// total per lane, updated after every write (main list and shadow), as the F05 text does.
|
||||
pub struct FormState {
|
||||
form: Reg64Form,
|
||||
plan: Vec<Vec<usize>>,
|
||||
groups: [[u32; LANES]; GROUPS],
|
||||
total: [u32; LANES],
|
||||
}
|
||||
|
||||
fn lane_regs(r: &[[u32; LANES]], lane: usize) -> [u32; 64] {
|
||||
std::array::from_fn(|k| r[k][lane])
|
||||
}
|
||||
|
||||
impl FormState {
|
||||
pub fn new(form: Reg64Form, plan: Vec<Vec<usize>>) -> FormState {
|
||||
FormState { form, plan, groups: [[0; LANES]; GROUPS], total: [0; LANES] }
|
||||
}
|
||||
/// After the register init (and the probe's flip): every group and the running total from the live registers.
|
||||
pub fn init(&mut self, r: &[[u32; LANES]]) {
|
||||
for lane in 0..LANES {
|
||||
let regs = lane_regs(r, lane);
|
||||
for j in 0..GROUPS {
|
||||
self.groups[j][lane] = group(®s, j);
|
||||
}
|
||||
self.total[lane] = (0..64).map(|k| term(®s, k)).fold(0, |x, y| x ^ y);
|
||||
}
|
||||
}
|
||||
/// After a write of register `d` whose value before the write was `old`: the prefix form's running total moves
|
||||
/// by the term's change; the generated form keeps its groups stale until the plan recomputes them.
|
||||
pub fn after_write(&mut self, r: &[[u32; LANES]], d: usize, old: &[u32; LANES]) {
|
||||
if self.form == Reg64Form::Prefix {
|
||||
let rot = ((63 - d) % 32) as u32;
|
||||
for lane in 0..LANES {
|
||||
self.total[lane] ^= old[lane].rotate_left(rot) ^ r[d][lane].rotate_left(rot);
|
||||
}
|
||||
}
|
||||
}
|
||||
/// The address source of the load at scheduled position `k` with source `s`, per lane, in this form.
|
||||
pub fn source(&mut self, r: &[[u32; LANES]], k: usize, s: usize) -> [u32; LANES] {
|
||||
if self.form == Reg64Form::Generated {
|
||||
for &j in &self.plan[k] {
|
||||
for lane in 0..LANES {
|
||||
let regs = lane_regs(r, lane);
|
||||
self.groups[j][lane] = group(®s, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
std::array::from_fn(|lane| {
|
||||
let regs = lane_regs(r, lane);
|
||||
match self.form {
|
||||
Reg64Form::Fold => fold(®s, s),
|
||||
Reg64Form::Direct => direct(®s, s),
|
||||
Reg64Form::Generated => grouped(&std::array::from_fn(|j| self.groups[j][lane]), ®s, s),
|
||||
Reg64Form::Prefix => prefixed(self.total[lane], ®s, s),
|
||||
Reg64Form::Wrong => wrong(®s, s),
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
fn stream(seed: u64) -> impl FnMut() -> u32 {
|
||||
let mut x = seed;
|
||||
move || {
|
||||
x = x.wrapping_add(0x9e37_79b9_7f4a_7c15);
|
||||
let mut z = x;
|
||||
z = (z ^ (z >> 30)).wrapping_mul(0xbf58_476d_1ce4_e5b9);
|
||||
z = (z ^ (z >> 27)).wrapping_mul(0x94d0_49bb_1331_11eb);
|
||||
(z ^ (z >> 31)) as u32
|
||||
}
|
||||
}
|
||||
|
||||
/// Known-failed first: the wrong form must disagree with the fold somewhere; then the three forms agree with the
|
||||
/// fold on every source over 4,096 random states and on the structured states (all zero, all ones, one bit,
|
||||
/// the init rule's registers).
|
||||
#[test]
|
||||
fn x4_forms_equal_the_fold_and_the_wrong_form_is_refused() {
|
||||
let mut next = stream(0x1505_0004);
|
||||
let mut wrong_differs = 0usize;
|
||||
let mut states: Vec<[u32; 64]> = Vec::new();
|
||||
for _ in 0..4096 {
|
||||
let mut r = [0u32; 64];
|
||||
for v in r.iter_mut() {
|
||||
*v = next();
|
||||
}
|
||||
states.push(r);
|
||||
}
|
||||
states.push([0u32; 64]);
|
||||
states.push([u32::MAX; 64]);
|
||||
for b in 0..64 * 32 {
|
||||
let mut r = [0u32; 64];
|
||||
r[b / 32] = 1 << (b % 32);
|
||||
states.push(r);
|
||||
}
|
||||
let mut r = [0u32; 64];
|
||||
for k in 0..8 {
|
||||
r[k] = next();
|
||||
}
|
||||
for k in 8..64 {
|
||||
r[k] = r[k & 7].wrapping_mul(0x9e37_79b9).wrapping_add(k as u32);
|
||||
}
|
||||
states.push(r);
|
||||
for r in &states {
|
||||
let g: [u32; GROUPS] = std::array::from_fn(|j| group(r, j));
|
||||
let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
|
||||
for s in 0..64 {
|
||||
let want = fold(r, s);
|
||||
if wrong(r, s) != want {
|
||||
wrong_differs += 1;
|
||||
}
|
||||
assert_eq!(direct(r, s), want, "direct, source r{s}");
|
||||
assert_eq!(grouped(&g, r, s), want, "generated, source r{s}");
|
||||
assert_eq!(prefixed(total, r, s), want, "prefix, source r{s}");
|
||||
}
|
||||
}
|
||||
assert!(wrong_differs > 0, "the known-failed form must be refused");
|
||||
}
|
||||
}
|
||||
|
|
@ -581,6 +581,10 @@ fn interpret_warp_core(
|
|||
// the iteration's statements: the drawn program, or its interleaved two-window form under reg64
|
||||
let scheduled = program.scheduled();
|
||||
let address_mix = program.address_mix();
|
||||
// X4: a byte-identical form of the address mix beside the definition (crate::reg64form), off by default
|
||||
let cpu_form = crate::reg64form::cpu_form();
|
||||
let form_on = address_mix && cpu_form != crate::reg64form::Reg64Form::Fold;
|
||||
let mut fs = crate::reg64form::FormState::new(cpu_form, if form_on { crate::reg64form::generated_plan(&scheduled, &program.shadow) } else { Vec::new() });
|
||||
let mut items_derived = 0usize;
|
||||
let mut idx = [0u32; LANES];
|
||||
let mut val = [0u32; LANES];
|
||||
|
|
@ -606,9 +610,15 @@ fn interpret_warp_core(
|
|||
}
|
||||
}
|
||||
}
|
||||
if it == 0 && form_on {
|
||||
// X4: the form's state from the registers as iteration 0 sees them (after the init and any probe flip)
|
||||
fs.init(&r);
|
||||
}
|
||||
let sel = r[0];
|
||||
for ins in &scheduled {
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
|
||||
for (k, ins) in scheduled.iter().enumerate() {
|
||||
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
|
||||
let ovr = if form_on && ins.op == Op::Load { Some(fs.source(&r, k, ins.src as usize)) } else { None };
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, ovr.as_ref());
|
||||
if it == 0 && ins.op == Op::Load {
|
||||
if let Some(pr) = probe.as_deref_mut() {
|
||||
if !pr.seen_first_load {
|
||||
|
|
@ -625,12 +635,19 @@ fn interpret_warp_core(
|
|||
r[d][lane] = m.rmw(&program.seed, base_nonce, lane, slot, r[d][lane]);
|
||||
}
|
||||
}
|
||||
if form_on {
|
||||
fs.after_write(&r, ins.dst as usize, &old);
|
||||
}
|
||||
}
|
||||
// Latency-shadow block (Counter ASIC 3.0 item 8): the block runs `reps` times after instruction 63 with the
|
||||
// iteration's `sel`; it is empty on every class without a shadow, so version 2 and class v3 run nothing here.
|
||||
for _ in 0..program.shadow_reps() {
|
||||
for ins in &program.shadow {
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
|
||||
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, None);
|
||||
if form_on {
|
||||
fs.after_write(&r, ins.dst as usize, &old);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -668,6 +685,7 @@ fn step(
|
|||
val: &mut [u32; LANES],
|
||||
items_derived: &mut usize,
|
||||
address_mix: bool,
|
||||
src_override: Option<&[u32; LANES]>,
|
||||
) {
|
||||
let d = ins.dst as usize;
|
||||
let a = ins.src as usize;
|
||||
|
|
@ -679,6 +697,11 @@ fn step(
|
|||
if !address_mix {
|
||||
return r[a][lane];
|
||||
}
|
||||
// X4 (1.5x programme): a byte-identical form computed by the caller; never set unless the differential's
|
||||
// `--reg64-cpu-form` names a form other than the fold (crate::reg64form)
|
||||
if let Some(o) = src_override {
|
||||
return o[lane];
|
||||
}
|
||||
let mut m = 0u32;
|
||||
let mut started = false;
|
||||
for k in 0..r.len() {
|
||||
|
|
|
|||
Loading…
Reference in a new issue