Merge master 0653f8d60 into mhpow-b3 under the master-landing lock
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docs/analysis/class-v6/1p5x/x4/README.md
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# X4: byte-identical implementation forms of the reg64c layer (the 1.5x programme, 9 October 2026)
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Lane: the k lane (X4). Item in the founder's brief (sha256 74ee0732...): "Byte-identical reg64 implementation
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alternatives: direct/generated/prefix alternative performance; state/storage/port update costs on both sides".
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The frozen control: the class v6 generator tree 1a938abe4 (igneum-pow fingerprint 5f4d6dc6...), the class string
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mx8-erad810f22d+sh256x27+state+reg64c+fold+rw. This document claims no pass. It changes nothing on the chain and
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activates nothing.
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## 1. The layer and the four forms
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The reg64c layer is defined in `igneum-pow/src/verify.rs`, `step`'s `addr_src`. Every load's address source is
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`r[s] ^ m`, where `m = r[k0]; m = rotl(m, 1) ^ r[k1]; ...` runs over the 63 registers other than the source `s`, in
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index order. The fold stays the definition. Each form below computes the same 32-bit word on every register state and
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every source.
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| Form | What it computes | State beyond the 64-register window | Source |
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|---|---|---|---|
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| fold (frozen) | the 63-term dependent chain per load | none | `emit.rs` `reg64_mix_line` (the frozen text) |
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| direct | the closed sum `XOR_{k<s} rotl(r[k], (62-k) mod 32) ^ XOR_{k>s} rotl(r[k], (63-k) mod 32)` as a balanced tree, depth 6 | none | `reg64form::direct`, `emit.rs` `reg64_direct_mix_line` |
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| generated | 8 group sums `g_j = XOR_{k in 8j..8j+7} rotl(r[k], (63-k) mod 32)`. Before each load the generator recomputes only the groups the static schedule wrote since the last load (`reg64form::generated_plan`). Then `r[s] ^ ror(P,1) ^ S ^ P ^ a[s]`, with `S` the 8 groups and `P` the whole groups before `s`'s group plus the in-group partial | 8 x 32 bits per lane | `reg64form::grouped`, `emit.rs` `reg64_generated_mix_line` |
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| prefix | review B's F05 text as landed: a running `S` updated after every write (main list and shadow), and `P_s` recomputed per load | 1 x 32 bits per lane | `verify::reg64_address_source`, `emit.rs` `reg64_prefix_mix_line` |
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| grouped incremental (chip only) | the generated form's query, with groups 1..7 kept up to date on the base program's writes to r8..r63, and group 0 recomputed at each load | 8 x 32 bits per lane | modelled only; no GPU text |
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The fact that makes the generated and grouped forms cheap: the shadow block draws its destination as
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`dst = rng.below(8)` (`generator.rs`, the shadow draw). So all 55,296 shadow writes per hash land in r0..r7 (group 0),
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and the shadow moves no other group. `tools/1p5x/x4/chip_rows.py` asserts this on the exported text.
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Code, on branch 1p5x-x4:
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- b51d8c04b: the crate's forms.
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- `igneum-pow/src/reg64form.rs`: new.
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- `verify.rs`: an override hook in `step`. It is off unless `--reg64-cpu-form` names a form other than the fold.
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- `emit.rs`: `--reg64-form`. It changes only the CUDA text, and `--reg64-prefix` is the same as `prefix`.
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- `main.rs`: the two switches.
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- The tools: `tools/1p5x/x4/` (`differential.sh`, `pod-x4.sh`, `chip_rows.py`, `gpu_rows.py`, `arith.py`).
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The texts, exported on build-9 from the frozen object by the b51d8c04b binary (`igneum-pow` sha256 ccb1bf0e...):
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| Form | kernel.cu sha256 | kernel_bound.cu sha256 | kernel.cu blake2b-256 (identity.json) | bytes |
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|---|---|---|---|---|
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| fold | b73ed77eb55d1b49 | 77cabb0602ee7ad5 | 368068868cbff44f | 86,027 |
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| direct | 1fdd27fb8eff2bf5 | 010ae3a6dea7d431 | 895f573979f37b51 | 77,035 |
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| generated | c1935ca84e7626dd | c39ff235fdff09ad | 6994fbdafe8e4bd1 | 54,664 |
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| prefix | 3fe78c3928ba9b77 | 23fb860b5a258b52 | a859b9d88dc4a731 | 84,948 |
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The four packs, as one tarball: x4-packs.tgz, sha256 6666d915.... It holds the frozen pack and the three alternatives.
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## 2. Equivalence verdicts
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| Test | Result | Evidence |
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|---|---|---|
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| Fold text check: `export` with no switch on b51d8c04b, compared with the frozen tarball hl-v6-all.tgz (91314310...) | kernel.cu, kernel_bound.cu, program.h and identity.json byte-identical | build-9 `/srv/builds/igneum-wt-1p5x-x4/ex/` |
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| Prefix text check: `--reg64-form prefix`, compared with hl-v6-all-prefix.tgz (d4b07747...) | all 14 files byte-identical | as above |
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| Unit test, known-failed first (`reg64form::tests::x4_forms_equal_the_fold_and_the_wrong_form_is_refused`): the wrong form (`r[s] ^ S ^ a[s]`) must disagree with the fold. Then direct, grouped and prefix must equal the fold on every source, over 4,096 random states, all zero, all ones, 2,048 single-bit states and the init rule's registers | PASS | `rows/suite-b51d8c04b.txt` |
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| The crate suite on build-9 (rule 24) | green: 76 lib tests plus 12 test binaries, 0 failed | `rows/suite-b51d8c04b.txt` |
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| CPU differential, whole hashes (`tools/1p5x/x4/differential.sh out 4096 32`): the CPU interpreter runs each form and keeps its state per form (the generated plan's stale groups, the prefix's running S) | **EQUIVALENT**. The known-failed form is refused on all 8 reg64c windows and all 32 fuzz seeds. Direct, generated and prefix agree on 44 of 44 checks each: 12 same-work windows, plus 32 fuzz seeds against the fold. Context 03 (class v5, no reg64) is the no-op control: every form agrees there, the wrong one too | `rows/VERDICT`, `rows/verdicts.txt` |
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| GPU, the pack self-test and the 2^24 fingerprint at base nonce 0: the gen-6 worker 804a6f7f on an RTX 4090, eight runs | **EQUIVALENT**. check=PASS (96 of 96 vector lanes) and fingerprint e8f4f3289c6ee1fc on all four texts in both passes | `pod-s1/bench-*.log` |
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The same-work windows: contexts 01 and 02 (`docs/analysis/class-v6/same-work/same-work-20261008-0{1,2}`), days D and
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D+1. Each window is 4,096 nonces: nonce 0, the last 4,096 before the boundary 1,572,864, the first 4,096 after it, and
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the last 4,096 of D+1. Each window is checked against that context's own `references/ref-D*.txt` from build-1. Context
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03 (`same-work-20261008-03`, class v5) uses the same four windows.
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The fuzz set: 32 seeds `i`. Each seed takes the epoch, era and prehash from `sha256("x4-fuzz-i")`, `"x4-era-i"` and
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`"x4-pre-i"`, a nonce from `"x4-nonce-i"`, and runs 1,024 nonces on the class v6 string over the node1 state stream
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(abb58003...).
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## 3. The GPU side (measured)
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The recipe is the hash lane's (build-1:/srv/artefacts/1p5x/gpu-row-recipe.md, sha256 cbab453c...):
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- Run: worker `--bench`, 250 x 2^24, block-warps 1.
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- Rate: the worker's own `mhs=`.
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- Power: board power, `power.draw` mean from 8 s in to the end of the timed dispatches. No wall meter; idle is not
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subtracted.
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- The sampler read power.draw, clocks.sm, utilization.gpu and temperature.gpu at 1 Hz. The recipe's instant and average
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fields were not read.
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Hardware: one rented RTX 4090 (fk-x4-4090: a RunPod container, driver 595.91.07, CUDA 12.8 image, 450 W limit), at
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stock. Worker igneum-worker-cuda-gen6, sha256 804a6f7fea10a62e (the class v6 zip 3 worker).
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Session 1 ran 2026-10-09 08:45:43Z to 09:05Z in the order A B C D D C B A (`tools/1p5x/x4/pod-x4.sh`). On an island,
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not a network.
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| Run | Pack | MH/s | W | nJ per hash | Registers | Blocks per SM | Fingerprint |
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|---|---|---|---|---|---|---|---|
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| 1 | hl-v6-all (frozen fold) | 35.080 | 285.4 | 8,134 | 93 | 20 | e8f4f3289c6ee1fc |
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| 2 | direct | 35.021 | 274.5 | 7,839 | 182 | 8 | e8f4f3289c6ee1fc |
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| 3 | generated | 35.053 | 274.2 | 7,824 | 142 | 12 | e8f4f3289c6ee1fc |
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| 4 | prefix | 35.056 | 277.1 | 7,905 | 154 | 12 | e8f4f3289c6ee1fc |
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| 5 | prefix | 35.053 | 277.8 | 7,926 | 154 | 12 | e8f4f3289c6ee1fc |
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| 6 | generated | 35.056 | 274.8 | 7,840 | 142 | 12 | e8f4f3289c6ee1fc |
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| 7 | direct | 35.020 | 274.9 | 7,851 | 182 | 8 | e8f4f3289c6ee1fc |
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| 8 | hl-v6-all (frozen fold) | 35.054 | 287.4 | 8,199 | 93 | 20 | e8f4f3289c6ee1fc |
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Pass 1 compares runs 2 to 4 with run 1. Pass 2 compares runs 5 to 7 with run 8. g is the mean of the two joules-per-hash
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ratios.
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| Pair | Pass 1 rate / J per hash | Pass 2 rate / J per hash | Mean rate / J per hash | g |
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|---|---|---|---|---|
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| A/A: frozen run 8 against run 1 | -0.07% / +0.80% | | | (noise floor) |
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| direct | -0.17% / -3.63% | -0.10% / -4.25% | -0.13% / -3.94% | 0.961 |
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| generated | -0.08% / -3.82% | +0.01% / -4.38% | -0.04% / -4.10% | 0.959 |
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| prefix | -0.07% / -2.82% | -0.00% / -3.33% | -0.04% / -3.07% | 0.969 |
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Session 2 is the replicate: the same pod, 09:05:41Z to 09:25Z, the same order (`pod-s2/`, `rows/gpu-rows-s2.txt`).
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| Pair (session 2) | Mean rate | Mean J per hash | g |
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|---|---|---|---|
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| A/A: frozen run 8 against run 1 | +0.00% | +0.15% | (noise floor) |
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| direct | -0.17% | -3.97% | 0.960 |
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| generated | -0.08% | -4.08% | 0.959 |
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| prefix | -0.20% | -3.11% | 0.969 |
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The two sessions agree to 0.001 in g on every form. Session 2's frozen runs read 35.081 MH/s at 8,172 and 8,184 nJ per
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hash.
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What the rows say: on the 4090 at stock, every form keeps the rate within 0.2 percent. Every form cuts board joules per
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hash by 3 to 4 percent, about four times the A/A spread (0.15 to 0.8 percent), in both passes of both sessions.
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The confound, open (BLOCKED row B2 below): nvcc gives the frozen fold 93 registers and 20 resident blocks per SM, and
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the alternatives 142 to 182 registers and 8 to 12 blocks. The kernel is memory-bound: the rate is equal at every
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occupancy. So the saving may come from fewer resident warps rather than from the form. Yesterday's F05 rows point the
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other way on the other card (`docs/analysis/class-v6/rows/fleet-f05-20261008.md`): on the 5090 the prefix text halved
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the blocks and cost 14 percent more joules per hash.
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What it means per tier:
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- A 24 GB card (4090) with a generated or direct pack would mine at the same rate for about 4 percent less board power.
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That is about 11 W of 285.
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- 8, 12 and 16 GB cards, AMD (OpenCL) and Apple (Metal) are not measured. The OpenCL and Metal texts keep the fold.
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- No pack ships from this. A form change is a text change to a fleet kit, and it would go through the hash lane and
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the kit lane.
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## 4. The chip side (modelled)
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Every row is modelled; no chip was measured. The counts come from the exported texts
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(`tools/1p5x/x4/chip_rows.py ex`, `rows/chip-rows.txt`).
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The constants are the adversary lane's calibrated row (its message of 09:4x UK; class-v6-adversary 43c9f7cd8
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`tools/chip-model/mf/`):
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- e_op: 6.55 pJ per lane-op at N5 (band 6.01 to 7.77). An xor-rotate that does not pass the slot's macro read costs
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about 1.0 pJ.
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- e_rf: 3.5 pJ per 256-bit macro access shared by 8 lanes (band 2.0 to 7.0).
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- Flop bits written: 0.03 pJ per bit.
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- The slot already reads 3 and writes 1 window register per instruction.
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- The machine: 1.528 microjoules per hash (N5, GDDR7 board), of which the shadow is 0.672.
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Counted from the texts: 256 executed loads per hash (32 per iteration x 8; the worker's RESULT line also says
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loads=256). 128 base writes per iteration, 112 of them to r8..r63. 256 shadow writes per pass, all to r0..r7.
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Two pricings are given. "Slot" prices each mix op as a full lane-op at 6.55 pJ, the adversary's literal-fold row.
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"Datapath" prices each mix op as an xor at 1.0 pJ, the adversary's running-total row. In both, every extra window read
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costs e_rf / 8.
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| Form | Mix ops per hash | Extra window reads per hash | Flop bits written per hash | State per lane | Ports | nJ per hash, slot (lo / c / hi) | nJ per hash, datapath (lo / c / hi) | pJ per lane-op delta at N5 (slot / datapath) |
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|---|---|---|---|---|---|---|---|---|
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| fold (frozen) | 16,128 | 16,128 | 0 | 64 registers | 63 reads per load | 101.0 / 112.7 / 139.4 | 20.2 / 23.2 / 30.2 | +1.10 / +0.23 |
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| direct | 15,872 | 16,128 | 0 | 64 registers | 63 reads per load (tree) | 99.4 / 111.0 / 137.4 | 19.9 / 22.9 / 30.0 | +1.08 / +0.22 |
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| generated | 8,400 | 5,792 | 20,224 | +32 B (8 flop registers) | 8 reads per recomputed group | 52.5 / 58.2 / 70.9 | 10.5 / 11.5 / 14.1 | +0.57 / +0.11 |
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| prefix (F05) | 121,320 | 8,160 | 1,802,240 | +4 B | a read-modify-write of S on every write, shadow included | 785.2 / 852.3 / 1003.9 | 177.4 / 179.0 / 182.5 | +8.31 / +1.74 |
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| grouped incremental | 7,560 | 2,784 | 36,864 | +32 B | 1 group RMW per base write to r8..r63, 8 reads per load | 47.2 / 51.8 / 62.3 | 9.4 / 9.9 / 11.1 | +0.50 / +0.10 |
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The per-lane-op delta spreads the mix's energy over the 102,612 shadow and base lane-ops.
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Readings:
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- The specialist's cheapest byte-identical form is the grouped incremental one: 10 to 52 nJ per hash, against 23 to
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113 nJ for the literal fold.
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- The adversary lane's 7 nJ running-total figure (5 to 10) counts 128 loads, and it leaves out the prefix `P_s` that
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every load needs. It is corrected here and sent back to that lane.
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- The adversary's section 17 Fenwick tree costs more on every reading. Its seven read-modify-writes land on every
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write, the shadow's included.
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## 5. The arithmetic (`tools/1p5x/x4/arith.py`, `rows/arith.txt`)
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`r_new = r0 * g / a`. g comes from section 3. a is the specialist's machine energy with a form, divided by its energy
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on a reference, at 1.528 microjoules. Two references:
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- fold: a specialist that implements the frozen literal fold.
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- model: the served machine, which carries no address-mix term at all. Against it, any form raises the specialist's
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energy; that is a model correction, not a design gain.
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Each side picks its cheapest form on its own. The card takes generated (g 0.959). The specialist takes grouped
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incremental.
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| r0 | vs fold, slot | vs fold, datapath | vs model, slot | vs model, datapath |
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|---|---|---|---|---|
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| 2.0 | a 0.963, r_new 1.99 | a 0.991, r_new 1.94 | a 1.034, r_new 1.86 | a 1.007, r_new 1.91 |
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| 1.9 | 1.89 | 1.84 | 1.76 | 1.81 |
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| 2.1 | 2.09 | 2.03 | 1.95 | 2.00 |
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Per form, with both sides on the same form, from 2.0:
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| Form | g | r_new vs fold (slot / datapath) | r_new vs model (slot / datapath) |
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|---|---|---|---|
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| direct | 0.961 | 1.92 / 1.92 | 1.79 / 1.89 |
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| generated | 0.959 | 1.98 / 1.93 | 1.85 / 1.90 |
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| prefix | 0.969 | 1.34 / 1.76 | 1.24 / 1.74 |
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The prefix rows are not a credible opponent: no specialist would choose the costlier form.
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Reaching 1.5 from 2.0 needs g / a = 0.75. The best credible pair gives 0.93 to 1.00. **X4 does not reach 1.5x**, and
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no pass is claimed. What X4 does move:
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- The card side: a 3 to 4 percent cut in board joules per hash on the 4090, open on the occupancy confound.
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- The model side: the served chip omits a 10 to 52 nJ per hash term, worth 0.7 to 3.4 percent of the machine.
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- Together, about 0.05 to 0.15 off a 2.0x ratio.
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## 6. BLOCKED and NOT RUN rows
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| Row | Status | Reason | What it needs |
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|---|---|---|---|
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| B1: the knee (the 4090 locked), every form | NOT RUN | The rented container refuses `nvidia-smi -lgc` and `-pl`. The worker has no duty-cycle throttle. The house rigs are blocked for every lane (the brief's amendment 2) | a pod host that grants clock locks, or the rigs after the relay lane's "agent back" line |
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| B2: the occupancy control (the frozen fold text at 12 and 8 blocks per SM) | BLOCKED | The worker sets no register or occupancy cap for a base-variant pack (`--warps` applies to variant 5 only) | a worker flag or a `__launch_bounds__` text variant from the hash lane. It decides whether g is the form or the occupancy |
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| B3: the RTX 5090 pairs (and the 5080, the cohort cards) | NOT RUN | one pod in this item's clock | a 5090 pod from the fleet lane. The F05 row says the sign can flip there |
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| B4: OpenCL and Metal texts of the alternatives | NOT RUN | the switch is CUDA-only by design | emitter work in the three dialects, if a form is adopted |
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| B5: the grouped incremental form as an executable text | NOT RUN | a chip-side design. Its equivalence rests on the prefix form's tested update rule and the generated form's tested query, and was not emulated on its own | a FormState arm in `reg64form.rs` and the differential, if the adversary lane carries the row |
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| B6: the chip rows on the adversary lane's placed core run | BLOCKED | the model has no input file for an address-form row (its own answer). The rows above are this script's arithmetic on its constants | the adversary lane taking `rows/chip-rows.txt` into its section 17 |
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## 7. Reproduce
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All on a build box, never the Mac:
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1. Build: `cargo build --release` in `igneum-pow` at 1p5x-x4.
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2. Fetch the inputs from build-1 (the paths are in `differential.sh`'s header).
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3. Export: `igneum-pow export --epoch-hex edc4fa84... --day-hex 69676e65756d2d6461792ffa50000000000000 --class mx8+sh256x27+state+reg64c+fold+rw --era 0:edc4fa84... --era-widths 4 --state node1-state.igsd1 --reg64-form <form> --out <form>`.
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4. Differential: `tools/1p5x/x4/differential.sh out 4096 32`.
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5. Chip rows: `tools/1p5x/x4/chip_rows.py ex > chip-rows.txt`.
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6. On the pod: `pod-x4.sh` with the worker and the packs, then `gpu_rows.py out out-run.log > gpu-rows.txt`.
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7. Arithmetic: `arith.py gpu-rows.txt chip-rows.txt`.
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The registry batch is `registry-batch-1p5x-x4-20261009.json` beside this file, every cell NOT RUN. It names the cell `rows:1p5x-x4`, which is not in the test map; the steward records it through `tools/ci/test-record.mjs`.
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@ -0,0 +1,4 @@
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info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
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pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2644 cache 2 dataset 29 hot 0 check 1352 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
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warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.25 ms
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RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.080 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1486 cache 2 dataset 29 hot 0 check 1168 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.90 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
|
||||
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.021 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1426 cache 3 dataset 29 hot 0 check 1119 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
|
||||
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1745 cache 2 dataset 29 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.73 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
|
||||
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.50 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
|
||||
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 28 hot 0 check 1170 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
|
||||
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1646 cache 8 dataset 47 hot 0 check 1147 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 479.00 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
|
||||
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.020 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2367 cache 3 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.61 ms
|
||||
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.054 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
35
docs/analysis/class-v6/1p5x/x4/pod-s1/out-run.log
Normal file
35
docs/analysis/class-v6/1p5x/x4/pod-s1/out-run.log
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
RESULT start 2026-10-09T08:45:43Z NVIDIA GeForce RTX 4090, 595.91.07, 450.00 W, 3105 MHz
|
||||
RESULT worker sha256 804a6f7fea10a62e
|
||||
RESULT run 01-hl-v6-all rc=0 secs=125 t0=1791535543 t1=1791535668
|
||||
BENCH 01-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2644 cache 2 dataset 29 hot 0 check 1352 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 01-hl-v6-all | warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.25 ms
|
||||
BENCH 01-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.080 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 02-x4-direct rc=0 secs=123 t0=1791535688 t1=1791535811
|
||||
BENCH 02-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1486 cache 2 dataset 29 hot 0 check 1168 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 02-x4-direct | warm-up dispatch (base 0): 478.90 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
|
||||
BENCH 02-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.021 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 03-x4-generated rc=0 secs=124 t0=1791535831 t1=1791535955
|
||||
BENCH 03-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1426 cache 3 dataset 29 hot 0 check 1119 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 03-x4-generated | warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
|
||||
BENCH 03-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 04-x4-prefix rc=0 secs=124 t0=1791535975 t1=1791536099
|
||||
BENCH 04-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1745 cache 2 dataset 29 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 04-x4-prefix | warm-up dispatch (base 0): 478.73 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
|
||||
BENCH 04-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 05-x4-prefix rc=0 secs=123 t0=1791536119 t1=1791536242
|
||||
BENCH 05-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 05-x4-prefix | warm-up dispatch (base 0): 478.50 ms; 250 timed dispatches of 16777216 nonces: mean 478.62 ms
|
||||
BENCH 05-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 06-x4-generated rc=0 secs=124 t0=1791536262 t1=1791536386
|
||||
BENCH 06-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1588 cache 2 dataset 28 hot 0 check 1170 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 06-x4-generated | warm-up dispatch (base 0): 478.37 ms; 250 timed dispatches of 16777216 nonces: mean 478.58 ms
|
||||
BENCH 06-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.056 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 07-x4-direct rc=0 secs=124 t0=1791536406 t1=1791536530
|
||||
BENCH 07-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1646 cache 8 dataset 47 hot 0 check 1147 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 07-x4-direct | warm-up dispatch (base 0): 479.00 ms; 250 timed dispatches of 16777216 nonces: mean 479.07 ms
|
||||
BENCH 07-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.020 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 08-hl-v6-all rc=0 secs=124 t0=1791536550 t1=1791536674
|
||||
BENCH 08-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2367 cache 3 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 08-hl-v6-all | warm-up dispatch (base 0): 478.05 ms; 250 timed dispatches of 16777216 nonces: mean 478.61 ms
|
||||
BENCH 08-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.054 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT end 2026-10-09T09:04:54Z
|
||||
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-01-hl-v6-all.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-01-hl-v6-all.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791535543,25.73,210,0,23
|
||||
1791535544,41.92,2520,0,24
|
||||
1791535545,80.03,2520,0,24
|
||||
1791535546,79.72,2520,0,24
|
||||
1791535547,83.98,2520,0,25
|
||||
1791535548,214.87,2655,100,30
|
||||
1791535549,280.28,2655,100,31
|
||||
1791535551,280.39,2655,100,32
|
||||
1791535552,280.38,2655,100,32
|
||||
1791535553,280.40,2655,100,33
|
||||
1791535554,280.54,2655,100,33
|
||||
1791535555,280.64,2655,100,34
|
||||
1791535556,280.79,2655,100,34
|
||||
1791535557,280.88,2655,100,34
|
||||
1791535558,280.84,2655,100,35
|
||||
1791535559,281.21,2685,100,35
|
||||
1791535560,281.50,2685,100,35
|
||||
1791535561,281.46,2685,100,36
|
||||
1791535562,281.81,2685,100,36
|
||||
1791535563,282.10,2685,100,36
|
||||
1791535564,282.20,2685,100,37
|
||||
1791535565,282.20,2685,100,37
|
||||
1791535566,282.62,2685,100,37
|
||||
1791535567,282.67,2685,100,37
|
||||
1791535568,282.63,2685,100,38
|
||||
1791535570,282.77,2685,100,38
|
||||
1791535571,282.88,2685,100,38
|
||||
1791535572,282.96,2685,100,38
|
||||
1791535573,282.77,2685,100,38
|
||||
1791535574,283.22,2685,100,39
|
||||
1791535575,283.19,2685,100,39
|
||||
1791535576,283.71,2685,100,39
|
||||
1791535577,283.31,2685,99,39
|
||||
1791535578,283.61,2685,100,39
|
||||
1791535579,283.69,2685,100,40
|
||||
1791535580,283.76,2685,100,40
|
||||
1791535581,284.29,2685,100,40
|
||||
1791535582,284.29,2685,100,40
|
||||
1791535583,284.29,2685,100,40
|
||||
1791535584,284.29,2685,100,40
|
||||
1791535585,284.08,2685,100,41
|
||||
1791535586,284.09,2685,100,41
|
||||
1791535587,284.27,2685,100,41
|
||||
1791535589,284.52,2685,100,41
|
||||
1791535590,284.69,2685,100,41
|
||||
1791535591,285.17,2685,100,41
|
||||
1791535592,284.58,2685,100,41
|
||||
1791535593,284.85,2685,100,42
|
||||
1791535594,285.05,2685,100,42
|
||||
1791535595,285.57,2685,100,42
|
||||
1791535596,285.45,2685,100,42
|
||||
1791535597,285.14,2685,100,42
|
||||
1791535598,285.25,2685,100,42
|
||||
1791535599,285.37,2685,100,42
|
||||
1791535600,285.58,2685,100,42
|
||||
1791535601,285.74,2685,100,43
|
||||
1791535602,285.55,2685,100,43
|
||||
1791535603,285.70,2685,100,43
|
||||
1791535605,285.65,2685,100,43
|
||||
1791535606,285.56,2685,100,43
|
||||
1791535607,285.64,2685,100,43
|
||||
1791535608,286.10,2685,100,43
|
||||
1791535609,285.48,2685,100,43
|
||||
1791535610,285.57,2685,100,43
|
||||
1791535611,285.86,2685,100,43
|
||||
1791535612,285.49,2685,100,43
|
||||
1791535613,285.84,2685,100,44
|
||||
1791535614,286.10,2685,100,44
|
||||
1791535615,286.06,2685,100,44
|
||||
1791535616,285.77,2685,100,44
|
||||
1791535617,285.92,2685,100,44
|
||||
1791535618,286.16,2685,100,44
|
||||
1791535619,286.63,2685,100,44
|
||||
1791535620,286.40,2685,100,44
|
||||
1791535621,286.33,2685,100,44
|
||||
1791535623,286.91,2685,100,44
|
||||
1791535624,286.25,2685,100,44
|
||||
1791535625,286.94,2685,100,44
|
||||
1791535626,287.21,2685,100,44
|
||||
1791535627,287.43,2685,100,44
|
||||
1791535628,287.06,2685,100,45
|
||||
1791535629,287.04,2685,100,45
|
||||
1791535630,287.20,2685,100,45
|
||||
1791535631,287.46,2685,100,45
|
||||
1791535632,287.78,2685,100,45
|
||||
1791535633,288.03,2685,100,45
|
||||
1791535634,287.81,2685,100,45
|
||||
1791535635,287.69,2685,100,45
|
||||
1791535636,288.01,2685,100,45
|
||||
1791535637,287.39,2685,100,45
|
||||
1791535638,287.20,2670,100,45
|
||||
1791535639,287.27,2670,100,45
|
||||
1791535640,287.52,2670,100,45
|
||||
1791535641,287.89,2670,100,45
|
||||
1791535643,287.58,2670,100,45
|
||||
1791535644,287.44,2670,100,45
|
||||
1791535645,287.64,2670,100,45
|
||||
1791535646,287.27,2670,100,45
|
||||
1791535647,287.41,2670,100,45
|
||||
1791535648,287.34,2670,100,45
|
||||
1791535649,287.58,2670,100,45
|
||||
1791535650,287.78,2670,100,46
|
||||
1791535651,287.32,2670,100,46
|
||||
1791535652,287.36,2670,100,46
|
||||
1791535653,287.67,2670,100,46
|
||||
1791535654,287.97,2670,100,46
|
||||
1791535655,287.86,2670,100,46
|
||||
1791535656,287.72,2670,100,46
|
||||
1791535658,288.10,2670,100,46
|
||||
1791535659,287.65,2670,100,46
|
||||
1791535660,288.01,2670,100,46
|
||||
1791535661,287.50,2670,100,46
|
||||
1791535662,287.42,2670,100,46
|
||||
1791535663,288.01,2670,100,46
|
||||
1791535664,287.81,2670,100,46
|
||||
1791535665,287.93,2670,100,46
|
||||
1791535666,287.92,2670,100,46
|
||||
1791535667,287.99,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-02-x4-direct.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-02-x4-direct.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791535688,27.52,210,0,33
|
||||
1791535689,69.40,2520,0,33
|
||||
1791535690,85.81,2520,11,33
|
||||
1791535691,80.89,2520,1,35
|
||||
1791535692,217.63,2685,100,38
|
||||
1791535693,271.20,2685,100,39
|
||||
1791535694,272.12,2685,100,39
|
||||
1791535695,272.26,2685,100,39
|
||||
1791535696,272.58,2685,100,40
|
||||
1791535697,273.06,2685,100,40
|
||||
1791535698,272.48,2685,100,40
|
||||
1791535700,272.13,2685,100,40
|
||||
1791535701,272.77,2685,100,40
|
||||
1791535702,273.29,2685,100,41
|
||||
1791535703,273.24,2685,100,41
|
||||
1791535704,273.06,2685,100,41
|
||||
1791535705,273.71,2685,100,41
|
||||
1791535706,273.73,2685,100,41
|
||||
1791535707,273.53,2685,100,41
|
||||
1791535708,273.34,2685,100,41
|
||||
1791535709,273.05,2685,100,42
|
||||
1791535710,273.11,2685,100,42
|
||||
1791535711,273.22,2685,100,42
|
||||
1791535712,273.33,2685,100,42
|
||||
1791535713,273.39,2685,100,42
|
||||
1791535714,273.43,2685,100,42
|
||||
1791535715,273.09,2685,100,42
|
||||
1791535716,273.15,2685,100,42
|
||||
1791535718,273.32,2685,100,42
|
||||
1791535719,273.34,2685,100,42
|
||||
1791535720,273.08,2685,100,42
|
||||
1791535721,273.26,2685,100,43
|
||||
1791535722,273.36,2685,100,43
|
||||
1791535723,273.81,2685,100,43
|
||||
1791535724,273.88,2685,100,43
|
||||
1791535725,274.15,2685,100,43
|
||||
1791535726,274.29,2685,100,43
|
||||
1791535727,274.35,2685,100,43
|
||||
1791535728,274.49,2685,100,43
|
||||
1791535729,274.58,2685,100,43
|
||||
1791535730,274.31,2685,100,43
|
||||
1791535731,273.94,2685,100,43
|
||||
1791535732,274.05,2685,100,43
|
||||
1791535734,274.08,2685,100,43
|
||||
1791535735,274.50,2685,100,43
|
||||
1791535736,274.56,2685,100,43
|
||||
1791535737,274.41,2685,100,43
|
||||
1791535738,274.16,2685,100,44
|
||||
1791535739,274.39,2685,100,44
|
||||
1791535740,274.76,2685,100,44
|
||||
1791535741,274.97,2685,100,44
|
||||
1791535742,274.87,2685,100,44
|
||||
1791535743,274.46,2685,100,44
|
||||
1791535744,274.72,2685,100,44
|
||||
1791535745,274.83,2685,100,44
|
||||
1791535746,275.01,2685,100,44
|
||||
1791535747,274.87,2685,100,44
|
||||
1791535748,274.77,2685,100,44
|
||||
1791535749,274.91,2685,100,44
|
||||
1791535751,274.91,2685,100,44
|
||||
1791535752,275.30,2685,100,44
|
||||
1791535753,275.23,2685,100,44
|
||||
1791535754,275.14,2685,100,44
|
||||
1791535755,275.17,2685,100,44
|
||||
1791535756,275.04,2685,100,44
|
||||
1791535757,274.95,2685,100,44
|
||||
1791535758,274.85,2685,100,44
|
||||
1791535759,274.61,2685,100,44
|
||||
1791535760,274.70,2685,100,44
|
||||
1791535761,274.73,2685,100,44
|
||||
1791535762,274.67,2685,100,45
|
||||
1791535763,274.85,2685,100,45
|
||||
1791535764,274.88,2685,100,45
|
||||
1791535765,275.33,2685,100,45
|
||||
1791535766,275.20,2685,100,45
|
||||
1791535768,275.22,2685,100,45
|
||||
1791535769,274.88,2685,100,45
|
||||
1791535770,275.15,2685,100,45
|
||||
1791535771,275.35,2685,100,45
|
||||
1791535772,275.56,2685,100,45
|
||||
1791535773,275.42,2685,100,45
|
||||
1791535774,275.36,2685,100,45
|
||||
1791535775,275.31,2685,100,45
|
||||
1791535776,275.20,2685,100,45
|
||||
1791535777,274.76,2685,100,45
|
||||
1791535778,275.26,2685,100,45
|
||||
1791535779,275.42,2685,100,45
|
||||
1791535780,275.17,2685,100,45
|
||||
1791535781,275.35,2685,100,45
|
||||
1791535782,275.11,2670,100,45
|
||||
1791535783,275.03,2670,100,45
|
||||
1791535784,275.04,2670,100,45
|
||||
1791535786,275.02,2670,100,45
|
||||
1791535787,275.10,2670,100,45
|
||||
1791535788,275.11,2670,100,45
|
||||
1791535789,275.12,2670,100,45
|
||||
1791535790,275.40,2670,100,45
|
||||
1791535791,275.03,2670,100,45
|
||||
1791535792,275.15,2670,100,45
|
||||
1791535793,275.04,2670,100,45
|
||||
1791535794,275.05,2670,100,45
|
||||
1791535795,275.22,2670,100,45
|
||||
1791535796,274.60,2670,100,45
|
||||
1791535797,275.23,2670,100,45
|
||||
1791535798,275.25,2670,100,45
|
||||
1791535799,275.49,2670,100,45
|
||||
1791535800,275.52,2670,100,45
|
||||
1791535801,275.48,2670,100,45
|
||||
1791535802,275.28,2670,100,45
|
||||
1791535803,275.30,2670,100,45
|
||||
1791535805,275.35,2670,100,45
|
||||
1791535806,275.39,2670,100,45
|
||||
1791535807,275.68,2670,100,45
|
||||
1791535808,275.70,2670,100,45
|
||||
1791535809,275.25,2670,100,45
|
||||
1791535810,274.96,2670,100,45
|
||||
1791535811,275.22,2670,100,45
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-03-x4-generated.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-03-x4-generated.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791535831,27.25,210,0,32
|
||||
1791535833,49.74,2520,0,33
|
||||
1791535834,85.31,2520,22,33
|
||||
1791535835,88.45,2520,64,33
|
||||
1791535836,224.31,2685,100,38
|
||||
1791535837,271.14,2685,100,39
|
||||
1791535838,271.38,2685,100,39
|
||||
1791535839,271.62,2685,100,40
|
||||
1791535840,272.30,2685,100,40
|
||||
1791535841,272.25,2685,100,40
|
||||
1791535842,272.54,2685,100,40
|
||||
1791535843,272.06,2685,100,40
|
||||
1791535844,272.07,2685,100,41
|
||||
1791535845,272.16,2685,100,41
|
||||
1791535846,272.17,2685,100,41
|
||||
1791535847,272.37,2685,100,41
|
||||
1791535848,272.78,2685,100,41
|
||||
1791535849,272.36,2685,100,41
|
||||
1791535851,272.49,2685,100,41
|
||||
1791535852,272.80,2685,100,42
|
||||
1791535853,272.65,2685,100,42
|
||||
1791535854,273.15,2685,100,42
|
||||
1791535855,272.84,2685,100,42
|
||||
1791535856,272.83,2685,100,42
|
||||
1791535857,272.61,2685,100,42
|
||||
1791535858,272.90,2685,100,42
|
||||
1791535859,272.84,2685,100,42
|
||||
1791535860,272.77,2685,100,42
|
||||
1791535861,273.01,2685,100,42
|
||||
1791535862,273.06,2685,100,42
|
||||
1791535863,273.05,2685,100,43
|
||||
1791535864,273.18,2685,100,43
|
||||
1791535865,273.01,2685,100,43
|
||||
1791535866,273.25,2685,100,43
|
||||
1791535867,273.29,2685,100,43
|
||||
1791535869,273.23,2685,100,43
|
||||
1791535870,273.46,2685,100,43
|
||||
1791535871,273.69,2685,100,43
|
||||
1791535872,273.69,2685,100,43
|
||||
1791535873,273.89,2685,100,43
|
||||
1791535874,274.04,2685,100,43
|
||||
1791535875,273.84,2685,100,43
|
||||
1791535876,273.99,2685,100,43
|
||||
1791535877,273.86,2685,100,43
|
||||
1791535878,273.83,2685,100,44
|
||||
1791535879,273.71,2685,100,44
|
||||
1791535880,273.68,2685,100,44
|
||||
1791535881,273.66,2685,100,44
|
||||
1791535882,274.34,2685,100,44
|
||||
1791535883,274.34,2685,100,44
|
||||
1791535885,274.30,2685,100,44
|
||||
1791535886,274.42,2685,100,44
|
||||
1791535887,274.77,2685,100,44
|
||||
1791535888,273.87,2685,100,44
|
||||
1791535889,274.47,2685,100,44
|
||||
1791535890,274.31,2685,100,44
|
||||
1791535891,274.41,2685,100,44
|
||||
1791535892,274.47,2685,100,44
|
||||
1791535893,274.72,2685,100,44
|
||||
1791535894,274.63,2685,100,44
|
||||
1791535895,274.57,2685,100,44
|
||||
1791535896,274.82,2685,100,44
|
||||
1791535897,274.97,2685,100,44
|
||||
1791535898,275.07,2685,100,44
|
||||
1791535899,274.86,2685,100,44
|
||||
1791535900,275.02,2685,100,44
|
||||
1791535901,275.05,2685,100,44
|
||||
1791535903,274.89,2685,100,44
|
||||
1791535904,274.55,2685,100,44
|
||||
1791535905,274.19,2685,100,45
|
||||
1791535906,274.60,2685,100,45
|
||||
1791535907,274.92,2685,100,45
|
||||
1791535908,274.77,2685,100,45
|
||||
1791535909,274.70,2685,100,45
|
||||
1791535910,274.42,2685,100,45
|
||||
1791535911,274.79,2685,100,45
|
||||
1791535912,274.67,2685,100,45
|
||||
1791535913,274.90,2685,100,45
|
||||
1791535914,274.70,2685,100,45
|
||||
1791535915,274.62,2685,100,45
|
||||
1791535916,275.07,2685,100,45
|
||||
1791535917,275.22,2685,100,45
|
||||
1791535918,274.96,2670,100,45
|
||||
1791535919,274.87,2670,100,45
|
||||
1791535921,275.05,2670,100,45
|
||||
1791535922,275.33,2670,100,45
|
||||
1791535923,275.34,2670,100,45
|
||||
1791535924,275.29,2670,100,45
|
||||
1791535925,275.45,2670,100,45
|
||||
1791535926,275.76,2670,100,45
|
||||
1791535927,275.78,2670,100,45
|
||||
1791535928,275.33,2670,100,45
|
||||
1791535929,275.23,2670,100,45
|
||||
1791535930,275.19,2670,100,45
|
||||
1791535931,275.16,2670,100,45
|
||||
1791535932,275.17,2670,100,45
|
||||
1791535933,275.62,2670,100,45
|
||||
1791535934,275.60,2670,100,45
|
||||
1791535935,275.57,2670,100,45
|
||||
1791535936,275.15,2670,100,45
|
||||
1791535937,275.25,2670,100,45
|
||||
1791535939,275.21,2670,100,45
|
||||
1791535940,275.23,2670,100,45
|
||||
1791535941,275.19,2670,100,45
|
||||
1791535942,275.31,2670,100,45
|
||||
1791535943,275.45,2670,100,45
|
||||
1791535944,275.72,2670,100,45
|
||||
1791535945,275.94,2670,100,45
|
||||
1791535946,275.33,2670,100,45
|
||||
1791535947,275.23,2670,100,45
|
||||
1791535948,274.83,2670,100,45
|
||||
1791535949,274.60,2670,100,45
|
||||
1791535950,274.83,2670,100,45
|
||||
1791535951,275.42,2670,100,45
|
||||
1791535952,275.43,2670,100,45
|
||||
1791535953,275.14,2670,100,45
|
||||
1791535954,275.43,2670,100,45
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-04-x4-prefix.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-04-x4-prefix.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791535975,27.63,210,0,33
|
||||
1791535976,70.46,2520,0,33
|
||||
1791535977,84.48,2520,0,35
|
||||
1791535978,84.79,2520,0,33
|
||||
1791535979,184.00,2685,38,37
|
||||
1791535980,274.23,2685,100,39
|
||||
1791535981,274.58,2685,100,39
|
||||
1791535982,274.89,2685,100,40
|
||||
1791535983,274.91,2685,100,40
|
||||
1791535984,274.85,2685,100,40
|
||||
1791535985,274.90,2685,100,40
|
||||
1791535987,275.24,2685,100,41
|
||||
1791535988,275.67,2685,100,41
|
||||
1791535989,275.32,2685,100,41
|
||||
1791535990,275.45,2685,100,41
|
||||
1791535991,275.68,2685,100,41
|
||||
1791535992,275.32,2685,100,41
|
||||
1791535993,275.49,2685,100,41
|
||||
1791535994,275.38,2685,100,42
|
||||
1791535995,275.61,2685,100,42
|
||||
1791535996,275.51,2685,100,42
|
||||
1791535997,275.56,2685,100,42
|
||||
1791535998,275.83,2685,100,42
|
||||
1791535999,276.10,2685,100,42
|
||||
1791536000,276.18,2685,100,42
|
||||
1791536001,276.22,2685,100,42
|
||||
1791536002,275.97,2685,100,42
|
||||
1791536003,275.76,2685,100,42
|
||||
1791536005,275.83,2685,100,43
|
||||
1791536006,276.27,2685,100,43
|
||||
1791536007,276.33,2685,100,43
|
||||
1791536008,276.27,2685,100,43
|
||||
1791536009,276.44,2685,100,43
|
||||
1791536010,276.55,2685,100,43
|
||||
1791536011,276.41,2685,100,43
|
||||
1791536012,276.32,2685,100,43
|
||||
1791536013,276.25,2685,100,43
|
||||
1791536014,276.77,2685,100,43
|
||||
1791536015,276.57,2685,100,43
|
||||
1791536016,276.93,2685,100,43
|
||||
1791536017,276.51,2685,100,43
|
||||
1791536018,276.32,2685,100,43
|
||||
1791536019,276.52,2685,100,43
|
||||
1791536020,276.63,2685,100,44
|
||||
1791536022,276.20,2685,100,44
|
||||
1791536023,276.42,2685,100,44
|
||||
1791536024,276.52,2685,100,44
|
||||
1791536025,276.70,2685,100,44
|
||||
1791536026,276.72,2685,100,44
|
||||
1791536027,277.21,2685,100,44
|
||||
1791536028,277.27,2685,100,44
|
||||
1791536029,277.52,2685,100,44
|
||||
1791536030,277.48,2685,100,44
|
||||
1791536031,277.17,2685,100,44
|
||||
1791536032,277.19,2685,100,44
|
||||
1791536033,277.62,2685,100,44
|
||||
1791536034,277.53,2685,100,44
|
||||
1791536035,277.41,2685,100,44
|
||||
1791536036,277.33,2685,100,44
|
||||
1791536037,277.19,2685,100,44
|
||||
1791536038,277.43,2685,100,44
|
||||
1791536040,277.14,2685,100,44
|
||||
1791536041,276.92,2685,100,44
|
||||
1791536042,277.00,2685,100,44
|
||||
1791536043,277.45,2685,100,44
|
||||
1791536044,277.70,2685,100,44
|
||||
1791536045,277.84,2685,100,44
|
||||
1791536046,277.77,2685,100,44
|
||||
1791536047,277.65,2685,100,45
|
||||
1791536048,277.70,2685,100,45
|
||||
1791536049,277.43,2685,100,45
|
||||
1791536050,277.80,2685,100,45
|
||||
1791536051,277.65,2685,100,45
|
||||
1791536052,277.70,2685,100,45
|
||||
1791536053,277.70,2685,100,45
|
||||
1791536054,277.76,2685,100,45
|
||||
1791536055,277.66,2685,100,45
|
||||
1791536057,277.46,2685,100,45
|
||||
1791536058,277.61,2685,100,45
|
||||
1791536059,277.44,2685,100,45
|
||||
1791536060,277.64,2685,100,45
|
||||
1791536061,277.70,2685,100,45
|
||||
1791536062,277.62,2685,100,45
|
||||
1791536063,277.50,2685,100,45
|
||||
1791536064,277.41,2670,100,45
|
||||
1791536065,277.47,2670,100,45
|
||||
1791536066,277.35,2670,100,45
|
||||
1791536067,277.39,2670,100,45
|
||||
1791536068,277.63,2670,100,45
|
||||
1791536069,277.67,2670,100,45
|
||||
1791536070,277.78,2670,100,45
|
||||
1791536071,277.88,2670,100,45
|
||||
1791536072,277.93,2670,100,45
|
||||
1791536073,278.37,2670,100,45
|
||||
1791536075,278.32,2670,100,45
|
||||
1791536076,278.23,2670,100,45
|
||||
1791536077,278.16,2670,100,45
|
||||
1791536078,277.95,2670,100,45
|
||||
1791536079,277.93,2670,100,45
|
||||
1791536080,278.41,2670,100,45
|
||||
1791536081,278.61,2670,100,45
|
||||
1791536082,278.41,2670,100,45
|
||||
1791536083,278.26,2670,100,45
|
||||
1791536084,278.21,2670,100,45
|
||||
1791536085,278.17,2670,100,45
|
||||
1791536086,278.15,2670,100,45
|
||||
1791536087,278.33,2670,100,45
|
||||
1791536088,278.08,2670,100,45
|
||||
1791536089,278.18,2670,100,45
|
||||
1791536090,278.43,2670,100,45
|
||||
1791536091,278.36,2670,100,45
|
||||
1791536093,278.36,2670,100,45
|
||||
1791536094,278.60,2670,100,45
|
||||
1791536095,278.60,2670,100,45
|
||||
1791536096,278.50,2670,100,45
|
||||
1791536097,278.64,2670,100,45
|
||||
1791536098,278.22,2670,100,45
|
||||
|
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-05-x4-prefix.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-05-x4-prefix.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791536119,27.42,210,0,32
|
||||
1791536120,46.44,2520,0,33
|
||||
1791536121,80.51,2520,0,33
|
||||
1791536122,84.09,2520,0,33
|
||||
1791536123,162.79,2685,0,35
|
||||
1791536124,252.19,2685,100,39
|
||||
1791536125,274.83,2685,100,39
|
||||
1791536126,275.12,2685,100,40
|
||||
1791536127,275.51,2685,100,40
|
||||
1791536128,275.73,2685,100,40
|
||||
1791536129,275.47,2685,100,40
|
||||
1791536130,275.54,2685,100,40
|
||||
1791536131,275.97,2685,100,41
|
||||
1791536132,276.06,2685,100,41
|
||||
1791536133,275.98,2685,100,41
|
||||
1791536134,276.30,2685,100,41
|
||||
1791536136,276.28,2685,100,41
|
||||
1791536137,276.26,2685,100,41
|
||||
1791536138,276.54,2685,100,41
|
||||
1791536139,276.40,2685,100,42
|
||||
1791536140,276.72,2685,100,42
|
||||
1791536141,276.51,2685,100,42
|
||||
1791536142,276.54,2685,100,42
|
||||
1791536143,276.39,2685,100,42
|
||||
1791536144,276.48,2685,100,42
|
||||
1791536145,276.59,2685,100,42
|
||||
1791536146,277.00,2685,100,42
|
||||
1791536147,276.94,2685,100,42
|
||||
1791536148,276.95,2685,100,42
|
||||
1791536149,276.96,2685,100,43
|
||||
1791536150,277.07,2685,100,43
|
||||
1791536151,277.21,2685,100,43
|
||||
1791536152,277.40,2685,100,43
|
||||
1791536154,277.45,2685,100,43
|
||||
1791536155,277.56,2685,100,43
|
||||
1791536156,277.65,2685,100,43
|
||||
1791536157,277.60,2685,100,43
|
||||
1791536158,277.47,2685,100,43
|
||||
1791536159,277.64,2685,100,43
|
||||
1791536160,277.66,2685,100,43
|
||||
1791536161,278.01,2685,100,43
|
||||
1791536162,278.20,2685,100,43
|
||||
1791536163,278.12,2685,100,43
|
||||
1791536164,278.05,2685,100,44
|
||||
1791536165,277.90,2685,100,44
|
||||
1791536166,278.01,2685,100,44
|
||||
1791536167,278.00,2685,100,44
|
||||
1791536168,278.24,2685,100,44
|
||||
1791536169,278.14,2685,100,44
|
||||
1791536170,278.00,2685,100,44
|
||||
1791536171,277.94,2685,100,44
|
||||
1791536173,277.95,2685,100,44
|
||||
1791536174,278.15,2685,100,44
|
||||
1791536175,278.29,2685,100,44
|
||||
1791536176,278.26,2685,100,44
|
||||
1791536177,278.58,2685,100,44
|
||||
1791536178,278.41,2685,100,44
|
||||
1791536179,278.51,2685,100,44
|
||||
1791536180,278.36,2685,100,44
|
||||
1791536181,277.93,2685,100,44
|
||||
1791536182,278.20,2685,100,44
|
||||
1791536183,278.05,2685,100,44
|
||||
1791536184,277.98,2685,100,44
|
||||
1791536185,277.91,2685,100,44
|
||||
1791536186,278.07,2685,100,45
|
||||
1791536187,278.10,2685,100,45
|
||||
1791536188,278.10,2685,100,45
|
||||
1791536189,278.35,2685,100,45
|
||||
1791536190,278.29,2685,100,45
|
||||
1791536191,278.22,2685,100,45
|
||||
1791536192,278.36,2685,100,45
|
||||
1791536194,278.56,2685,100,45
|
||||
1791536195,278.19,2685,100,45
|
||||
1791536196,278.21,2685,100,45
|
||||
1791536197,278.46,2685,100,45
|
||||
1791536198,278.67,2670,100,45
|
||||
1791536199,278.57,2670,100,45
|
||||
1791536200,278.30,2670,100,45
|
||||
1791536201,278.27,2670,100,45
|
||||
1791536202,278.49,2670,100,45
|
||||
1791536203,278.13,2670,100,45
|
||||
1791536204,278.25,2670,100,45
|
||||
1791536205,278.53,2670,100,45
|
||||
1791536206,278.37,2670,100,45
|
||||
1791536207,278.25,2670,100,45
|
||||
1791536208,278.35,2670,100,45
|
||||
1791536209,278.34,2670,100,45
|
||||
1791536210,278.46,2670,100,45
|
||||
1791536211,278.27,2670,100,45
|
||||
1791536213,278.51,2670,100,45
|
||||
1791536214,278.33,2670,100,45
|
||||
1791536215,278.56,2670,100,45
|
||||
1791536216,278.57,2670,100,45
|
||||
1791536217,278.54,2670,100,45
|
||||
1791536218,278.68,2670,100,45
|
||||
1791536219,278.48,2670,100,45
|
||||
1791536220,278.57,2670,100,45
|
||||
1791536221,278.55,2670,100,45
|
||||
1791536222,278.15,2670,100,45
|
||||
1791536223,278.38,2670,100,45
|
||||
1791536224,278.28,2670,100,45
|
||||
1791536225,277.98,2670,100,45
|
||||
1791536226,278.02,2670,100,45
|
||||
1791536227,278.02,2670,100,45
|
||||
1791536228,278.19,2670,100,46
|
||||
1791536229,278.29,2670,100,46
|
||||
1791536231,278.26,2670,100,46
|
||||
1791536232,278.38,2670,100,46
|
||||
1791536233,278.38,2670,100,46
|
||||
1791536234,278.29,2670,100,46
|
||||
1791536235,278.22,2670,100,46
|
||||
1791536236,278.52,2670,100,46
|
||||
1791536237,278.37,2670,100,46
|
||||
1791536238,278.84,2670,100,46
|
||||
1791536239,278.82,2670,100,46
|
||||
1791536240,278.72,2670,100,46
|
||||
1791536241,278.38,2670,100,46
|
||||
1791536242,278.26,2670,100,46
|
||||
|
116
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-06-x4-generated.csv
Normal file
116
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-06-x4-generated.csv
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
1791536262,28.12,210,0,33
|
||||
1791536263,45.22,2520,0,33
|
||||
1791536264,86.39,2520,13,33
|
||||
1791536266,83.65,2520,27,33
|
||||
1791536267,221.16,2685,100,38
|
||||
1791536268,271.83,2685,100,39
|
||||
1791536269,271.62,2685,100,40
|
||||
1791536270,271.83,2685,100,40
|
||||
1791536271,271.95,2685,100,40
|
||||
1791536272,272.41,2685,100,40
|
||||
1791536274,272.62,2685,100,41
|
||||
1791536275,273.05,2685,100,41
|
||||
1791536276,272.71,2685,100,41
|
||||
1791536277,272.42,2685,100,41
|
||||
1791536278,273.08,2685,100,41
|
||||
1791536279,273.56,2685,100,41
|
||||
1791536280,273.76,2685,100,41
|
||||
1791536281,273.98,2685,100,42
|
||||
1791536282,273.49,2685,100,42
|
||||
1791536283,273.72,2685,100,42
|
||||
1791536284,273.59,2685,100,42
|
||||
1791536285,274.44,2685,100,42
|
||||
1791536286,274.20,2685,100,42
|
||||
1791536288,274.36,2685,100,42
|
||||
1791536289,274.20,2685,100,42
|
||||
1791536290,274.58,2685,100,42
|
||||
1791536291,274.60,2685,100,43
|
||||
1791536292,274.28,2685,100,43
|
||||
1791536293,274.16,2685,100,43
|
||||
1791536294,274.61,2685,100,43
|
||||
1791536295,274.58,2685,100,43
|
||||
1791536296,274.69,2685,100,43
|
||||
1791536297,274.48,2685,100,43
|
||||
1791536298,274.05,2685,100,43
|
||||
1791536299,274.47,2685,100,43
|
||||
1791536300,274.74,2685,100,43
|
||||
1791536301,274.72,2685,100,43
|
||||
1791536302,274.21,2685,100,43
|
||||
1791536303,274.35,2685,100,43
|
||||
1791536305,274.51,2685,100,43
|
||||
1791536306,274.27,2685,100,44
|
||||
1791536307,274.30,2685,100,44
|
||||
1791536308,274.39,2685,100,44
|
||||
1791536309,274.46,2685,100,44
|
||||
1791536310,274.56,2685,100,44
|
||||
1791536311,274.28,2685,100,44
|
||||
1791536312,274.35,2685,100,44
|
||||
1791536313,274.34,2685,100,44
|
||||
1791536314,274.94,2685,100,44
|
||||
1791536315,274.96,2685,100,44
|
||||
1791536316,275.16,2685,100,44
|
||||
1791536317,274.94,2685,100,44
|
||||
1791536318,275.14,2685,100,44
|
||||
1791536319,275.30,2685,100,44
|
||||
1791536320,275.43,2685,100,44
|
||||
1791536321,275.68,2685,100,44
|
||||
1791536323,275.28,2685,100,44
|
||||
1791536324,275.09,2685,100,44
|
||||
1791536325,275.04,2685,100,44
|
||||
1791536326,275.32,2685,100,44
|
||||
1791536327,275.37,2685,100,45
|
||||
1791536328,275.01,2685,100,45
|
||||
1791536329,275.25,2685,100,45
|
||||
1791536330,275.58,2685,100,45
|
||||
1791536331,275.47,2685,100,45
|
||||
1791536332,275.31,2670,100,45
|
||||
1791536333,274.92,2670,100,45
|
||||
1791536334,275.14,2670,100,45
|
||||
1791536335,275.06,2670,100,45
|
||||
1791536336,274.90,2670,100,45
|
||||
1791536337,274.87,2670,100,45
|
||||
1791536338,274.95,2670,100,45
|
||||
1791536339,275.16,2670,100,45
|
||||
1791536341,275.11,2670,100,45
|
||||
1791536342,275.24,2670,100,45
|
||||
1791536343,275.62,2670,100,45
|
||||
1791536344,275.53,2670,100,45
|
||||
1791536345,275.52,2670,100,45
|
||||
1791536346,275.66,2670,100,45
|
||||
1791536347,275.52,2670,100,45
|
||||
1791536348,275.30,2670,100,45
|
||||
1791536349,275.38,2670,100,45
|
||||
1791536350,275.12,2670,100,45
|
||||
1791536351,275.18,2670,100,45
|
||||
1791536352,275.64,2670,100,45
|
||||
1791536353,275.77,2670,100,45
|
||||
1791536354,275.83,2670,100,45
|
||||
1791536355,275.69,2670,100,45
|
||||
1791536356,275.42,2670,100,45
|
||||
1791536357,275.40,2670,100,45
|
||||
1791536358,275.39,2670,100,45
|
||||
1791536360,275.35,2670,100,45
|
||||
1791536361,275.18,2670,100,45
|
||||
1791536362,275.49,2670,100,45
|
||||
1791536363,275.30,2670,100,45
|
||||
1791536364,275.49,2670,100,45
|
||||
1791536365,275.52,2670,100,45
|
||||
1791536366,275.42,2670,100,45
|
||||
1791536367,275.55,2670,100,45
|
||||
1791536368,275.41,2670,100,45
|
||||
1791536369,275.51,2670,100,45
|
||||
1791536370,275.74,2670,100,45
|
||||
1791536371,275.93,2670,100,45
|
||||
1791536372,275.71,2670,100,45
|
||||
1791536373,275.59,2670,100,45
|
||||
1791536374,275.64,2670,100,45
|
||||
1791536375,275.63,2670,100,45
|
||||
1791536376,275.64,2670,100,45
|
||||
1791536377,275.20,2670,100,45
|
||||
1791536379,275.46,2670,100,46
|
||||
1791536380,275.75,2670,100,46
|
||||
1791536381,275.81,2670,100,46
|
||||
1791536382,275.48,2670,100,46
|
||||
1791536383,275.74,2670,100,46
|
||||
1791536384,275.67,2670,100,46
|
||||
1791536385,275.55,2670,100,46
|
||||
|
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-07-x4-direct.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-07-x4-direct.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791536406,81.86,2520,0,34
|
||||
1791536407,82.61,2520,0,34
|
||||
1791536408,81.17,2520,0,34
|
||||
1791536409,84.94,2520,0,34
|
||||
1791536410,161.93,2685,0,37
|
||||
1791536411,255.04,2685,100,39
|
||||
1791536412,271.83,2685,100,40
|
||||
1791536414,272.05,2685,100,40
|
||||
1791536415,272.34,2685,100,40
|
||||
1791536416,272.39,2685,100,40
|
||||
1791536417,272.58,2685,100,41
|
||||
1791536418,272.46,2685,100,41
|
||||
1791536419,272.73,2685,100,41
|
||||
1791536420,272.76,2685,100,41
|
||||
1791536421,273.18,2685,100,41
|
||||
1791536422,273.53,2685,100,41
|
||||
1791536423,273.18,2685,100,41
|
||||
1791536424,273.10,2685,100,42
|
||||
1791536425,273.57,2685,100,42
|
||||
1791536426,273.57,2685,100,42
|
||||
1791536427,273.70,2685,100,42
|
||||
1791536428,273.65,2685,100,42
|
||||
1791536429,273.97,2685,100,42
|
||||
1791536430,273.85,2685,100,42
|
||||
1791536431,273.86,2685,100,42
|
||||
1791536433,273.15,2685,100,42
|
||||
1791536434,273.28,2685,100,43
|
||||
1791536435,273.96,2685,100,43
|
||||
1791536436,273.66,2685,100,43
|
||||
1791536437,273.58,2685,100,43
|
||||
1791536438,273.76,2685,100,43
|
||||
1791536439,273.79,2685,100,43
|
||||
1791536440,274.06,2685,100,43
|
||||
1791536441,273.95,2685,100,43
|
||||
1791536442,273.91,2685,100,43
|
||||
1791536443,273.31,2685,100,43
|
||||
1791536444,274.12,2685,100,43
|
||||
1791536445,274.60,2685,100,43
|
||||
1791536446,274.74,2685,100,43
|
||||
1791536447,275.15,2685,100,43
|
||||
1791536448,275.27,2685,100,43
|
||||
1791536449,275.23,2685,100,44
|
||||
1791536450,275.21,2685,100,44
|
||||
1791536451,275.15,2685,100,44
|
||||
1791536452,274.94,2685,100,44
|
||||
1791536454,274.99,2685,100,44
|
||||
1791536455,274.55,2685,100,44
|
||||
1791536456,274.55,2685,100,44
|
||||
1791536457,274.17,2685,100,44
|
||||
1791536458,274.52,2685,100,44
|
||||
1791536459,274.63,2685,100,44
|
||||
1791536460,274.92,2685,100,44
|
||||
1791536461,274.98,2685,100,44
|
||||
1791536462,274.93,2685,100,44
|
||||
1791536463,274.99,2685,100,44
|
||||
1791536464,274.79,2685,100,44
|
||||
1791536465,274.97,2685,100,44
|
||||
1791536466,275.01,2685,100,44
|
||||
1791536467,275.02,2685,100,44
|
||||
1791536468,275.00,2685,100,44
|
||||
1791536469,274.83,2685,100,44
|
||||
1791536470,274.89,2670,100,44
|
||||
1791536471,274.91,2670,100,45
|
||||
1791536472,275.43,2670,100,45
|
||||
1791536474,275.52,2670,100,45
|
||||
1791536475,275.33,2670,100,45
|
||||
1791536476,275.53,2670,100,45
|
||||
1791536477,275.92,2670,100,45
|
||||
1791536478,275.80,2670,100,45
|
||||
1791536479,275.93,2670,100,45
|
||||
1791536480,275.83,2670,100,45
|
||||
1791536481,275.52,2670,100,45
|
||||
1791536482,275.53,2670,100,45
|
||||
1791536483,275.63,2670,100,45
|
||||
1791536484,275.48,2670,100,45
|
||||
1791536485,275.54,2670,100,45
|
||||
1791536486,275.52,2670,100,45
|
||||
1791536487,275.50,2670,100,45
|
||||
1791536488,275.49,2670,100,45
|
||||
1791536489,275.57,2670,100,45
|
||||
1791536490,275.48,2670,100,45
|
||||
1791536491,275.97,2670,100,45
|
||||
1791536493,276.09,2670,100,45
|
||||
1791536494,275.72,2670,100,45
|
||||
1791536495,275.89,2670,100,45
|
||||
1791536496,275.75,2670,100,45
|
||||
1791536497,275.57,2670,100,45
|
||||
1791536498,275.65,2670,100,45
|
||||
1791536499,275.46,2670,100,45
|
||||
1791536500,275.24,2670,100,45
|
||||
1791536501,275.60,2670,100,45
|
||||
1791536502,275.50,2670,100,45
|
||||
1791536503,275.70,2670,100,45
|
||||
1791536504,275.83,2670,100,45
|
||||
1791536505,275.92,2670,100,45
|
||||
1791536506,276.33,2670,100,45
|
||||
1791536507,276.05,2670,100,45
|
||||
1791536508,275.96,2670,100,45
|
||||
1791536510,276.06,2670,100,45
|
||||
1791536511,276.02,2670,100,45
|
||||
1791536512,275.94,2670,100,45
|
||||
1791536513,275.80,2670,100,45
|
||||
1791536514,275.54,2670,100,45
|
||||
1791536515,275.71,2670,100,45
|
||||
1791536516,275.78,2670,100,45
|
||||
1791536517,276.05,2670,100,45
|
||||
1791536518,275.77,2670,100,45
|
||||
1791536519,275.95,2670,100,45
|
||||
1791536520,275.71,2670,100,45
|
||||
1791536521,276.18,2670,100,45
|
||||
1791536522,276.31,2670,100,45
|
||||
1791536523,276.28,2670,100,45
|
||||
1791536524,275.84,2670,100,45
|
||||
1791536525,275.84,2670,100,45
|
||||
1791536526,276.17,2670,100,45
|
||||
1791536528,276.52,2670,100,45
|
||||
1791536529,276.46,2670,100,45
|
||||
1791536530,276.26,2670,100,45
|
||||
|
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-08-hl-v6-all.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s1/smi-08-hl-v6-all.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791536550,27.22,210,0,33
|
||||
1791536551,70.72,2520,0,33
|
||||
1791536552,80.23,2520,0,33
|
||||
1791536553,83.13,2520,0,33
|
||||
1791536554,121.69,2685,100,38
|
||||
1791536555,246.83,2685,100,39
|
||||
1791536556,284.11,2685,100,40
|
||||
1791536557,284.58,2685,100,40
|
||||
1791536558,285.01,2685,100,40
|
||||
1791536559,284.97,2685,100,41
|
||||
1791536561,285.17,2685,100,41
|
||||
1791536562,285.15,2685,100,41
|
||||
1791536563,285.45,2685,100,41
|
||||
1791536564,285.45,2685,100,41
|
||||
1791536565,285.62,2685,100,42
|
||||
1791536566,285.60,2685,100,42
|
||||
1791536567,285.28,2685,100,42
|
||||
1791536568,285.67,2685,100,42
|
||||
1791536569,285.45,2685,100,42
|
||||
1791536570,286.00,2685,100,42
|
||||
1791536571,286.44,2685,100,42
|
||||
1791536572,286.33,2685,100,43
|
||||
1791536573,285.72,2685,100,43
|
||||
1791536574,270.98,2685,100,43
|
||||
1791536575,286.06,2685,100,43
|
||||
1791536576,286.34,2685,100,43
|
||||
1791536577,286.22,2685,100,43
|
||||
1791536578,286.79,2685,100,43
|
||||
1791536580,286.43,2685,100,43
|
||||
1791536581,286.62,2685,100,43
|
||||
1791536582,286.93,2685,100,43
|
||||
1791536583,286.74,2685,100,44
|
||||
1791536584,286.87,2685,100,44
|
||||
1791536585,287.43,2685,100,44
|
||||
1791536586,287.43,2685,100,44
|
||||
1791536587,287.36,2685,100,44
|
||||
1791536588,287.42,2685,100,44
|
||||
1791536589,287.30,2685,99,44
|
||||
1791536590,286.99,2685,100,44
|
||||
1791536591,287.13,2685,100,44
|
||||
1791536592,287.50,2685,100,44
|
||||
1791536593,287.59,2670,100,44
|
||||
1791536594,287.57,2670,100,44
|
||||
1791536595,287.72,2670,100,44
|
||||
1791536596,287.69,2670,100,45
|
||||
1791536597,287.35,2670,100,45
|
||||
1791536598,287.59,2670,100,45
|
||||
1791536600,287.33,2670,100,45
|
||||
1791536601,287.55,2670,100,45
|
||||
1791536602,287.71,2670,100,45
|
||||
1791536603,288.11,2670,100,45
|
||||
1791536604,287.80,2670,100,45
|
||||
1791536605,288.04,2670,100,45
|
||||
1791536606,287.35,2670,100,45
|
||||
1791536607,287.53,2670,100,45
|
||||
1791536608,287.66,2670,100,45
|
||||
1791536609,287.89,2670,100,45
|
||||
1791536610,287.96,2670,100,45
|
||||
1791536611,288.00,2670,100,45
|
||||
1791536612,288.10,2670,100,45
|
||||
1791536613,287.76,2670,100,45
|
||||
1791536614,287.67,2670,100,45
|
||||
1791536615,287.89,2670,100,45
|
||||
1791536616,287.79,2670,100,45
|
||||
1791536617,287.85,2670,100,45
|
||||
1791536619,287.77,2670,100,46
|
||||
1791536620,288.14,2670,100,46
|
||||
1791536621,287.73,2670,100,46
|
||||
1791536622,287.70,2670,100,46
|
||||
1791536623,286.94,2670,100,46
|
||||
1791536624,288.00,2670,100,46
|
||||
1791536625,287.60,2670,100,46
|
||||
1791536626,288.13,2670,100,46
|
||||
1791536627,287.82,2670,100,46
|
||||
1791536628,288.33,2670,100,46
|
||||
1791536629,287.87,2670,100,46
|
||||
1791536630,288.07,2670,100,46
|
||||
1791536631,287.86,2670,100,46
|
||||
1791536632,287.82,2670,100,46
|
||||
1791536633,287.90,2670,100,46
|
||||
1791536634,287.91,2670,100,46
|
||||
1791536635,288.30,2670,100,46
|
||||
1791536636,288.10,2670,100,46
|
||||
1791536638,287.83,2670,100,46
|
||||
1791536639,287.74,2670,100,46
|
||||
1791536640,287.73,2670,100,46
|
||||
1791536641,287.73,2670,100,46
|
||||
1791536642,288.01,2670,100,46
|
||||
1791536643,288.17,2670,100,46
|
||||
1791536644,288.14,2670,100,46
|
||||
1791536645,288.11,2670,100,46
|
||||
1791536646,288.37,2670,100,46
|
||||
1791536647,288.34,2670,100,46
|
||||
1791536648,288.06,2670,100,46
|
||||
1791536649,288.03,2670,100,46
|
||||
1791536650,288.05,2670,100,46
|
||||
1791536651,288.24,2670,100,46
|
||||
1791536652,287.95,2670,100,46
|
||||
1791536653,288.25,2670,100,46
|
||||
1791536654,288.16,2670,100,46
|
||||
1791536656,288.24,2670,100,46
|
||||
1791536657,288.70,2670,100,46
|
||||
1791536658,289.14,2670,100,46
|
||||
1791536659,289.04,2670,100,46
|
||||
1791536660,289.00,2670,100,46
|
||||
1791536661,288.88,2670,100,46
|
||||
1791536662,288.70,2670,100,46
|
||||
1791536663,288.77,2670,100,47
|
||||
1791536664,288.74,2670,100,47
|
||||
1791536665,289.04,2670,100,47
|
||||
1791536666,288.94,2670,100,47
|
||||
1791536667,288.78,2670,100,47
|
||||
1791536668,288.69,2670,100,47
|
||||
1791536669,288.47,2670,100,47
|
||||
1791536670,289.04,2670,100,47
|
||||
1791536672,289.11,2670,100,47
|
||||
1791536673,289.05,2670,100,47
|
||||
1791536674,288.86,2670,100,47
|
||||
|
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2347 cache 2 dataset 29 hot 0 check 1092 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 477.97 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
|
||||
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1626 cache 3 dataset 28 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 479.01 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
|
||||
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1479 cache 2 dataset 29 hot 0 check 1190 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.44 ms; 250 timed dispatches of 16777216 nonces: mean 478.59 ms
|
||||
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.055 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1676 cache 3 dataset 28 hot 0 check 1158 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.39 ms; 250 timed dispatches of 16777216 nonces: mean 479.74 ms
|
||||
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=34.971 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1552 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.53 ms; 250 timed dispatches of 16777216 nonces: mean 478.66 ms
|
||||
RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.050 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1566 cache 2 dataset 29 hot 0 check 1652 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.47 ms; 250 timed dispatches of 16777216 nonces: mean 478.63 ms
|
||||
RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1454 cache 2 dataset 29 hot 0 check 1187 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 479.02 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
|
||||
RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.2 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2538 cache 2 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
warm-up dispatch (base 0): 478.21 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
|
||||
RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
35
docs/analysis/class-v6/1p5x/x4/pod-s2/out-run.log
Normal file
35
docs/analysis/class-v6/1p5x/x4/pod-s2/out-run.log
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
RESULT start 2026-10-09T09:05:41Z NVIDIA GeForce RTX 4090, 595.91.07, 450.00 W, 3105 MHz
|
||||
RESULT worker sha256 804a6f7fea10a62e
|
||||
RESULT run 01-hl-v6-all rc=0 secs=124 t0=1791536741 t1=1791536865
|
||||
BENCH 01-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2347 cache 2 dataset 29 hot 0 check 1092 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 01-hl-v6-all | warm-up dispatch (base 0): 477.97 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
|
||||
BENCH 01-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 02-x4-direct rc=0 secs=124 t0=1791536885 t1=1791537009
|
||||
BENCH 02-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1626 cache 3 dataset 28 hot 0 check 1163 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 02-x4-direct | warm-up dispatch (base 0): 479.01 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
|
||||
BENCH 02-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 03-x4-generated rc=0 secs=123 t0=1791537029 t1=1791537152
|
||||
BENCH 03-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1479 cache 2 dataset 29 hot 0 check 1190 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 03-x4-generated | warm-up dispatch (base 0): 478.44 ms; 250 timed dispatches of 16777216 nonces: mean 478.59 ms
|
||||
BENCH 03-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.055 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 04-x4-prefix rc=0 secs=124 t0=1791537172 t1=1791537296
|
||||
BENCH 04-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1676 cache 3 dataset 28 hot 0 check 1158 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 04-x4-prefix | warm-up dispatch (base 0): 478.39 ms; 250 timed dispatches of 16777216 nonces: mean 479.74 ms
|
||||
BENCH 04-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=34.971 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 05-x4-prefix rc=0 secs=124 t0=1791537316 t1=1791537440
|
||||
BENCH 05-x4-prefix | pack packs/x4-prefix on NVIDIA_GeForce_RTX_4090: nvrtc 1552 cache 2 dataset 29 hot 0 check 1183 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 05-x4-prefix | warm-up dispatch (base 0): 478.53 ms; 250 timed dispatches of 16777216 nonces: mean 478.66 ms
|
||||
BENCH 05-x4-prefix | RESULT pack=packs/x4-prefix class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=154 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.050 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 06-x4-generated rc=0 secs=124 t0=1791537460 t1=1791537584
|
||||
BENCH 06-x4-generated | pack packs/x4-generated on NVIDIA_GeForce_RTX_4090: nvrtc 1566 cache 2 dataset 29 hot 0 check 1652 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 06-x4-generated | warm-up dispatch (base 0): 478.47 ms; 250 timed dispatches of 16777216 nonces: mean 478.63 ms
|
||||
BENCH 06-x4-generated | RESULT pack=packs/x4-generated class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=142 blocks_per_sm=12 warps=0 resident=1536 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.053 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 07-x4-direct rc=0 secs=123 t0=1791537604 t1=1791537727
|
||||
BENCH 07-x4-direct | pack packs/x4-direct on NVIDIA_GeForce_RTX_4090: nvrtc 1454 cache 2 dataset 29 hot 0 check 1187 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 07-x4-direct | warm-up dispatch (base 0): 479.02 ms; 250 timed dispatches of 16777216 nonces: mean 479.05 ms
|
||||
BENCH 07-x4-direct | RESULT pack=packs/x4-direct class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=182 blocks_per_sm=8 warps=0 resident=1024 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.022 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT run 08-hl-v6-all rc=0 secs=125 t0=1791537747 t1=1791537872
|
||||
BENCH 08-hl-v6-all | pack packs/hl-v6-all on NVIDIA_GeForce_RTX_4090: nvrtc 2538 cache 2 dataset 29 hot 0 check 1105 race 0 ms variant base class v6 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 448274a57f508cbc; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
BENCH 08-hl-v6-all | warm-up dispatch (base 0): 478.21 ms; 250 timed dispatches of 16777216 nonces: mean 478.24 ms
|
||||
BENCH 08-hl-v6-all | RESULT pack=packs/hl-v6-all class=mx8-erad810f22d+sh256x27+state+reg64c+fold+rw device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=93 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=e8f4f3289c6ee1fc mhs=35.081 loads=256 bytes=1024 scratch_ops=0 time=wall
|
||||
RESULT end 2026-10-09T09:24:52Z
|
||||
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-01-hl-v6-all.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-01-hl-v6-all.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791536741,27.54,210,0,26
|
||||
1791536742,56.07,2520,0,27
|
||||
1791536743,82.60,2520,0,27
|
||||
1791536744,85.62,2520,11,28
|
||||
1791536745,90.67,2520,57,27
|
||||
1791536746,251.28,2655,100,34
|
||||
1791536747,281.96,2685,100,35
|
||||
1791536748,282.36,2685,100,35
|
||||
1791536749,282.45,2685,100,35
|
||||
1791536750,282.71,2685,100,36
|
||||
1791536751,282.52,2685,100,36
|
||||
1791536752,282.61,2685,100,36
|
||||
1791536753,282.40,2685,100,37
|
||||
1791536754,282.54,2685,100,37
|
||||
1791536756,282.72,2685,100,37
|
||||
1791536757,283.36,2685,100,38
|
||||
1791536758,283.44,2685,100,38
|
||||
1791536759,283.25,2685,100,38
|
||||
1791536760,283.73,2685,100,38
|
||||
1791536761,284.11,2685,100,38
|
||||
1791536762,284.14,2685,100,39
|
||||
1791536763,284.19,2685,100,39
|
||||
1791536764,284.22,2685,100,39
|
||||
1791536765,284.22,2685,100,39
|
||||
1791536766,284.55,2685,100,40
|
||||
1791536767,284.48,2685,100,40
|
||||
1791536768,284.77,2685,100,40
|
||||
1791536769,284.98,2685,100,40
|
||||
1791536770,284.96,2685,100,40
|
||||
1791536771,284.94,2685,100,40
|
||||
1791536772,285.17,2685,100,41
|
||||
1791536773,285.14,2685,100,41
|
||||
1791536775,284.91,2685,100,41
|
||||
1791536776,285.24,2685,100,41
|
||||
1791536777,285.16,2685,100,41
|
||||
1791536778,285.23,2685,100,41
|
||||
1791536779,285.40,2685,100,41
|
||||
1791536780,285.35,2685,100,42
|
||||
1791536781,285.25,2685,100,42
|
||||
1791536782,285.20,2685,100,42
|
||||
1791536783,285.48,2685,100,42
|
||||
1791536784,285.70,2685,100,42
|
||||
1791536785,286.04,2685,100,42
|
||||
1791536786,286.20,2685,100,42
|
||||
1791536787,286.10,2685,100,42
|
||||
1791536788,286.15,2685,100,43
|
||||
1791536789,285.95,2685,100,43
|
||||
1791536790,286.59,2685,100,43
|
||||
1791536791,286.56,2685,100,43
|
||||
1791536793,286.33,2685,100,43
|
||||
1791536794,286.56,2685,100,43
|
||||
1791536795,286.70,2685,100,43
|
||||
1791536796,286.51,2685,100,43
|
||||
1791536797,286.30,2685,100,43
|
||||
1791536798,286.80,2685,100,43
|
||||
1791536799,286.39,2685,100,43
|
||||
1791536800,286.27,2685,100,44
|
||||
1791536801,286.57,2685,100,44
|
||||
1791536802,286.67,2685,100,44
|
||||
1791536803,286.65,2685,100,44
|
||||
1791536804,286.59,2685,100,44
|
||||
1791536805,286.91,2685,100,44
|
||||
1791536806,286.94,2685,100,44
|
||||
1791536807,286.84,2685,100,44
|
||||
1791536808,286.92,2685,100,44
|
||||
1791536810,287.06,2670,100,44
|
||||
1791536811,287.07,2670,100,44
|
||||
1791536812,287.24,2670,100,44
|
||||
1791536813,287.26,2670,100,44
|
||||
1791536814,287.13,2670,100,44
|
||||
1791536815,287.39,2670,100,45
|
||||
1791536816,287.57,2670,100,45
|
||||
1791536817,287.45,2670,100,45
|
||||
1791536818,287.37,2670,100,45
|
||||
1791536819,287.87,2670,100,45
|
||||
1791536820,287.90,2670,100,45
|
||||
1791536821,287.97,2670,100,45
|
||||
1791536822,287.47,2670,100,45
|
||||
1791536823,287.40,2670,100,45
|
||||
1791536824,287.09,2670,100,45
|
||||
1791536825,287.00,2670,100,45
|
||||
1791536827,287.51,2670,100,45
|
||||
1791536828,288.05,2670,100,45
|
||||
1791536829,288.44,2670,100,45
|
||||
1791536830,288.36,2670,100,45
|
||||
1791536831,288.67,2670,100,45
|
||||
1791536832,288.64,2670,100,45
|
||||
1791536833,288.62,2670,100,45
|
||||
1791536834,288.22,2670,100,45
|
||||
1791536835,288.23,2670,100,46
|
||||
1791536836,288.16,2670,100,46
|
||||
1791536837,288.39,2670,100,46
|
||||
1791536838,288.55,2670,100,46
|
||||
1791536839,288.68,2670,100,46
|
||||
1791536840,288.95,2670,100,46
|
||||
1791536841,289.35,2670,100,46
|
||||
1791536842,288.96,2670,100,46
|
||||
1791536843,288.62,2670,100,46
|
||||
1791536845,288.23,2670,100,46
|
||||
1791536846,288.88,2670,100,46
|
||||
1791536847,289.12,2670,100,46
|
||||
1791536848,289.02,2670,100,46
|
||||
1791536849,289.05,2670,100,46
|
||||
1791536850,289.06,2670,100,46
|
||||
1791536851,288.89,2670,100,46
|
||||
1791536852,288.90,2670,100,46
|
||||
1791536853,288.96,2670,100,46
|
||||
1791536854,288.76,2670,100,46
|
||||
1791536855,288.70,2670,100,46
|
||||
1791536856,288.69,2670,100,46
|
||||
1791536857,288.75,2670,100,46
|
||||
1791536858,288.92,2670,100,46
|
||||
1791536859,288.92,2670,100,46
|
||||
1791536860,288.77,2670,100,46
|
||||
1791536862,289.04,2670,100,46
|
||||
1791536863,289.11,2670,100,46
|
||||
1791536864,289.12,2670,100,46
|
||||
1791536865,288.96,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-02-x4-direct.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-02-x4-direct.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791536885,28.32,210,0,33
|
||||
1791536886,45.95,2520,0,33
|
||||
1791536887,81.58,2520,0,33
|
||||
1791536888,92.40,2520,1,35
|
||||
1791536889,236.97,2685,100,39
|
||||
1791536890,271.90,2685,100,39
|
||||
1791536891,272.15,2685,100,39
|
||||
1791536892,272.65,2685,100,40
|
||||
1791536893,272.92,2685,100,40
|
||||
1791536894,272.83,2685,100,40
|
||||
1791536895,273.21,2685,100,40
|
||||
1791536897,273.50,2685,100,41
|
||||
1791536898,273.73,2685,100,41
|
||||
1791536899,274.07,2685,100,41
|
||||
1791536900,274.05,2685,100,41
|
||||
1791536902,274.03,2685,100,41
|
||||
1791536903,273.95,2685,100,41
|
||||
1791536904,273.79,2685,100,41
|
||||
1791536905,273.93,2685,100,42
|
||||
1791536906,273.85,2685,100,42
|
||||
1791536907,273.32,2685,100,42
|
||||
1791536908,273.64,2685,100,42
|
||||
1791536909,273.77,2685,100,42
|
||||
1791536910,274.04,2685,100,42
|
||||
1791536911,273.89,2685,100,42
|
||||
1791536912,273.93,2685,100,42
|
||||
1791536913,273.90,2685,100,42
|
||||
1791536914,274.49,2685,100,42
|
||||
1791536915,274.20,2685,100,42
|
||||
1791536916,274.49,2685,100,43
|
||||
1791536918,274.60,2685,100,43
|
||||
1791536919,274.71,2685,100,43
|
||||
1791536920,274.73,2685,100,43
|
||||
1791536921,274.92,2685,100,43
|
||||
1791536922,274.90,2685,100,43
|
||||
1791536923,274.51,2685,100,43
|
||||
1791536924,274.92,2685,100,43
|
||||
1791536925,275.17,2685,100,43
|
||||
1791536926,275.02,2685,100,43
|
||||
1791536927,274.99,2685,100,43
|
||||
1791536928,274.83,2685,100,43
|
||||
1791536929,275.14,2685,100,43
|
||||
1791536930,275.21,2685,100,44
|
||||
1791536931,274.90,2685,100,44
|
||||
1791536932,275.20,2685,100,44
|
||||
1791536933,274.90,2685,100,44
|
||||
1791536934,275.14,2685,100,44
|
||||
1791536935,275.32,2685,100,44
|
||||
1791536937,275.12,2685,100,44
|
||||
1791536938,275.21,2685,100,44
|
||||
1791536939,275.60,2685,100,44
|
||||
1791536940,275.48,2685,100,44
|
||||
1791536941,275.73,2685,100,44
|
||||
1791536942,275.49,2685,100,44
|
||||
1791536943,275.42,2685,100,44
|
||||
1791536944,275.24,2670,100,44
|
||||
1791536945,275.29,2670,100,44
|
||||
1791536946,274.87,2670,100,44
|
||||
1791536947,275.12,2670,100,44
|
||||
1791536948,275.17,2670,100,44
|
||||
1791536949,275.04,2670,100,44
|
||||
1791536950,275.22,2670,100,44
|
||||
1791536951,275.48,2670,100,44
|
||||
1791536952,275.39,2670,100,44
|
||||
1791536953,275.36,2670,100,45
|
||||
1791536954,275.43,2670,100,45
|
||||
1791536956,275.14,2670,100,45
|
||||
1791536957,275.07,2670,100,45
|
||||
1791536958,275.15,2670,100,45
|
||||
1791536959,274.97,2670,100,45
|
||||
1791536960,274.90,2670,100,45
|
||||
1791536961,275.13,2670,100,45
|
||||
1791536962,275.48,2670,100,45
|
||||
1791536963,275.73,2670,100,45
|
||||
1791536964,275.68,2670,100,45
|
||||
1791536965,275.81,2670,100,45
|
||||
1791536966,275.70,2670,100,45
|
||||
1791536967,276.07,2670,100,45
|
||||
1791536968,276.11,2670,100,45
|
||||
1791536969,275.77,2670,100,45
|
||||
1791536970,275.46,2670,100,45
|
||||
1791536971,276.10,2670,100,45
|
||||
1791536972,275.91,2670,100,45
|
||||
1791536974,275.78,2670,100,45
|
||||
1791536975,275.83,2670,100,45
|
||||
1791536976,276.08,2670,100,45
|
||||
1791536977,275.75,2670,100,45
|
||||
1791536978,275.88,2670,100,45
|
||||
1791536979,276.15,2670,100,45
|
||||
1791536980,276.06,2670,100,45
|
||||
1791536981,276.06,2670,100,45
|
||||
1791536982,276.08,2670,100,45
|
||||
1791536983,275.98,2670,100,45
|
||||
1791536984,275.48,2670,99,45
|
||||
1791536985,275.74,2670,100,45
|
||||
1791536986,276.10,2670,100,45
|
||||
1791536987,275.86,2670,100,45
|
||||
1791536988,275.90,2670,100,45
|
||||
1791536989,275.91,2670,100,45
|
||||
1791536990,275.75,2670,100,45
|
||||
1791536991,275.67,2670,100,45
|
||||
1791536993,275.41,2670,100,45
|
||||
1791536994,275.77,2670,100,45
|
||||
1791536995,275.87,2670,100,45
|
||||
1791536996,275.66,2670,100,45
|
||||
1791536997,275.86,2670,100,45
|
||||
1791536998,275.86,2670,100,45
|
||||
1791536999,275.53,2670,100,46
|
||||
1791537000,275.66,2670,100,46
|
||||
1791537001,276.23,2670,100,46
|
||||
1791537002,276.32,2670,100,46
|
||||
1791537003,276.15,2670,100,46
|
||||
1791537004,276.25,2670,100,46
|
||||
1791537005,276.30,2670,100,46
|
||||
1791537006,276.02,2670,100,46
|
||||
1791537007,276.08,2670,100,46
|
||||
1791537008,276.01,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-03-x4-generated.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-03-x4-generated.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791537029,27.66,210,0,33
|
||||
1791537030,49.07,2520,0,33
|
||||
1791537031,85.97,2520,5,34
|
||||
1791537032,81.32,2520,0,33
|
||||
1791537033,203.31,2685,100,39
|
||||
1791537034,272.00,2685,100,39
|
||||
1791537035,272.31,2685,100,40
|
||||
1791537036,272.09,2685,100,40
|
||||
1791537037,272.53,2685,100,40
|
||||
1791537038,272.13,2685,100,40
|
||||
1791537039,272.68,2685,100,41
|
||||
1791537040,272.79,2685,100,41
|
||||
1791537041,272.94,2685,100,41
|
||||
1791537042,273.07,2685,100,41
|
||||
1791537043,273.10,2685,100,41
|
||||
1791537045,273.07,2685,100,41
|
||||
1791537046,273.30,2685,100,42
|
||||
1791537047,273.49,2685,100,42
|
||||
1791537048,273.49,2685,100,42
|
||||
1791537049,273.74,2685,100,42
|
||||
1791537050,273.77,2685,99,42
|
||||
1791537051,273.86,2685,100,42
|
||||
1791537052,273.77,2685,100,42
|
||||
1791537053,273.90,2685,100,42
|
||||
1791537054,274.03,2685,100,42
|
||||
1791537055,273.97,2685,100,43
|
||||
1791537056,274.10,2685,100,43
|
||||
1791537057,273.77,2685,100,43
|
||||
1791537058,273.93,2685,100,43
|
||||
1791537059,274.38,2685,100,43
|
||||
1791537060,274.26,2685,100,43
|
||||
1791537061,274.35,2685,100,43
|
||||
1791537062,274.69,2685,100,43
|
||||
1791537064,274.33,2685,100,43
|
||||
1791537065,274.71,2685,100,43
|
||||
1791537066,275.16,2685,100,43
|
||||
1791537067,275.14,2685,100,43
|
||||
1791537068,275.09,2685,100,43
|
||||
1791537069,274.91,2685,100,44
|
||||
1791537070,275.14,2685,100,44
|
||||
1791537071,274.98,2685,100,44
|
||||
1791537072,275.21,2685,100,44
|
||||
1791537073,275.32,2685,100,44
|
||||
1791537074,275.83,2685,100,44
|
||||
1791537075,275.63,2685,100,44
|
||||
1791537076,275.89,2685,100,44
|
||||
1791537077,275.54,2685,100,44
|
||||
1791537078,275.65,2670,100,44
|
||||
1791537079,275.15,2670,100,44
|
||||
1791537081,275.23,2670,100,44
|
||||
1791537082,275.42,2670,100,44
|
||||
1791537083,275.24,2670,100,44
|
||||
1791537084,274.85,2670,100,44
|
||||
1791537085,274.88,2670,100,44
|
||||
1791537086,274.88,2670,100,44
|
||||
1791537087,275.05,2670,100,44
|
||||
1791537088,275.16,2670,100,44
|
||||
1791537089,275.00,2670,100,44
|
||||
1791537090,275.00,2670,100,45
|
||||
1791537091,275.17,2670,100,45
|
||||
1791537092,274.95,2670,100,45
|
||||
1791537093,274.98,2670,100,45
|
||||
1791537094,275.10,2670,100,45
|
||||
1791537095,274.61,2670,100,45
|
||||
1791537096,274.99,2670,100,45
|
||||
1791537097,275.37,2670,100,45
|
||||
1791537099,275.49,2670,100,45
|
||||
1791537100,275.48,2670,100,45
|
||||
1791537101,275.46,2670,100,45
|
||||
1791537102,275.20,2670,100,45
|
||||
1791537103,275.04,2670,100,45
|
||||
1791537104,275.05,2670,100,45
|
||||
1791537105,274.96,2670,100,45
|
||||
1791537106,275.33,2670,100,45
|
||||
1791537107,275.64,2670,100,45
|
||||
1791537108,275.24,2670,100,45
|
||||
1791537109,275.51,2670,100,45
|
||||
1791537110,275.32,2670,100,45
|
||||
1791537111,275.23,2670,100,45
|
||||
1791537112,275.09,2670,100,45
|
||||
1791537113,274.94,2670,100,45
|
||||
1791537114,275.56,2670,100,45
|
||||
1791537116,275.22,2670,100,45
|
||||
1791537117,275.43,2670,100,45
|
||||
1791537118,275.17,2670,100,45
|
||||
1791537119,275.43,2670,100,45
|
||||
1791537120,275.65,2670,100,45
|
||||
1791537121,275.96,2670,100,45
|
||||
1791537122,276.02,2670,100,45
|
||||
1791537123,276.05,2670,100,45
|
||||
1791537124,276.19,2670,100,45
|
||||
1791537125,276.01,2670,100,45
|
||||
1791537126,275.80,2670,100,45
|
||||
1791537127,276.15,2670,100,45
|
||||
1791537128,275.88,2670,100,45
|
||||
1791537129,275.86,2670,100,46
|
||||
1791537130,275.82,2670,100,46
|
||||
1791537131,276.18,2670,100,46
|
||||
1791537133,276.09,2670,100,46
|
||||
1791537134,276.21,2670,100,46
|
||||
1791537135,276.31,2670,100,46
|
||||
1791537136,275.97,2670,100,46
|
||||
1791537137,276.20,2670,100,46
|
||||
1791537138,276.17,2670,100,46
|
||||
1791537139,276.55,2670,100,46
|
||||
1791537140,276.47,2670,100,46
|
||||
1791537141,276.25,2670,100,46
|
||||
1791537142,276.45,2670,100,46
|
||||
1791537143,276.54,2670,100,46
|
||||
1791537144,276.25,2670,100,46
|
||||
1791537145,276.14,2670,100,46
|
||||
1791537146,275.65,2670,100,46
|
||||
1791537147,275.82,2670,100,46
|
||||
1791537148,275.87,2670,100,46
|
||||
1791537150,275.84,2670,99,46
|
||||
1791537151,275.64,2670,100,46
|
||||
1791537152,275.50,2670,100,46
|
||||
|
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-04-x4-prefix.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-04-x4-prefix.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791537172,27.55,210,0,33
|
||||
1791537173,49.83,2520,0,34
|
||||
1791537174,85.09,2520,71,34
|
||||
1791537175,86.21,2520,0,33
|
||||
1791537176,176.96,2685,100,38
|
||||
1791537177,273.90,2685,100,40
|
||||
1791537178,274.80,2685,100,40
|
||||
1791537180,275.31,2685,100,40
|
||||
1791537181,251.76,2685,100,40
|
||||
1791537182,275.78,2685,100,41
|
||||
1791537183,275.75,2685,100,41
|
||||
1791537184,275.88,2685,100,41
|
||||
1791537185,276.04,2685,100,41
|
||||
1791537186,276.14,2685,100,41
|
||||
1791537187,276.04,2685,100,41
|
||||
1791537188,276.39,2685,100,42
|
||||
1791537189,276.51,2685,100,42
|
||||
1791537190,276.10,2685,100,42
|
||||
1791537191,276.01,2685,100,42
|
||||
1791537192,276.19,2685,100,42
|
||||
1791537193,276.18,2685,100,42
|
||||
1791537194,276.23,2685,100,42
|
||||
1791537195,275.99,2685,100,42
|
||||
1791537196,275.65,2685,100,43
|
||||
1791537197,276.30,2685,100,43
|
||||
1791537199,276.45,2685,100,43
|
||||
1791537200,276.75,2685,100,43
|
||||
1791537201,276.50,2685,100,43
|
||||
1791537202,276.57,2685,100,43
|
||||
1791537203,276.60,2685,100,43
|
||||
1791537204,276.50,2685,100,43
|
||||
1791537205,276.72,2685,100,43
|
||||
1791537206,276.79,2685,100,43
|
||||
1791537207,276.95,2685,100,43
|
||||
1791537208,276.75,2685,100,43
|
||||
1791537209,276.63,2685,100,44
|
||||
1791537210,276.71,2685,100,44
|
||||
1791537211,276.93,2685,100,44
|
||||
1791537212,276.96,2685,100,44
|
||||
1791537213,277.20,2685,100,44
|
||||
1791537214,277.07,2685,100,44
|
||||
1791537215,277.02,2670,100,44
|
||||
1791537216,277.23,2670,100,44
|
||||
1791537217,276.90,2670,100,44
|
||||
1791537218,277.42,2670,100,44
|
||||
1791537220,277.38,2670,100,44
|
||||
1791537221,277.29,2670,100,44
|
||||
1791537222,277.39,2670,100,44
|
||||
1791537223,277.32,2670,100,44
|
||||
1791537224,277.05,2670,100,44
|
||||
1791537225,276.94,2670,100,44
|
||||
1791537226,277.20,2670,100,45
|
||||
1791537227,277.11,2670,100,45
|
||||
1791537228,277.12,2670,100,45
|
||||
1791537229,277.30,2670,100,45
|
||||
1791537230,277.46,2670,100,45
|
||||
1791537231,277.33,2670,100,45
|
||||
1791537232,277.62,2670,100,45
|
||||
1791537233,277.38,2670,100,45
|
||||
1791537234,277.40,2670,100,45
|
||||
1791537235,277.39,2670,100,45
|
||||
1791537236,277.69,2670,100,45
|
||||
1791537238,277.74,2670,100,45
|
||||
1791537239,277.82,2670,100,45
|
||||
1791537240,277.68,2670,100,45
|
||||
1791537241,277.54,2670,100,45
|
||||
1791537242,277.77,2670,100,45
|
||||
1791537243,277.42,2670,100,45
|
||||
1791537244,277.49,2670,100,45
|
||||
1791537245,277.50,2670,100,45
|
||||
1791537246,277.93,2670,100,45
|
||||
1791537247,277.96,2670,100,45
|
||||
1791537248,277.77,2670,100,45
|
||||
1791537249,277.73,2670,100,45
|
||||
1791537250,278.01,2670,100,45
|
||||
1791537251,278.07,2670,100,45
|
||||
1791537252,277.63,2670,100,45
|
||||
1791537253,277.54,2670,100,45
|
||||
1791537254,277.78,2670,100,45
|
||||
1791537255,277.58,2670,100,45
|
||||
1791537257,277.66,2670,100,45
|
||||
1791537258,277.74,2670,100,46
|
||||
1791537259,277.60,2670,100,46
|
||||
1791537260,277.61,2670,100,46
|
||||
1791537261,277.58,2670,100,46
|
||||
1791537262,277.83,2670,100,46
|
||||
1791537263,277.81,2670,100,46
|
||||
1791537264,277.81,2670,100,46
|
||||
1791537265,277.90,2670,100,46
|
||||
1791537266,278.02,2670,100,46
|
||||
1791537267,278.03,2670,100,46
|
||||
1791537268,277.99,2670,100,46
|
||||
1791537269,277.90,2670,100,46
|
||||
1791537270,277.93,2670,100,46
|
||||
1791537271,278.03,2670,100,46
|
||||
1791537272,278.14,2670,100,46
|
||||
1791537273,278.04,2670,100,46
|
||||
1791537275,278.23,2670,100,46
|
||||
1791537276,278.15,2670,100,46
|
||||
1791537277,278.39,2670,100,46
|
||||
1791537278,278.79,2670,100,46
|
||||
1791537279,278.81,2670,100,46
|
||||
1791537280,279.02,2670,100,46
|
||||
1791537281,278.82,2670,100,46
|
||||
1791537282,278.50,2670,100,46
|
||||
1791537283,278.51,2670,100,46
|
||||
1791537284,278.43,2670,100,46
|
||||
1791537285,278.59,2670,100,46
|
||||
1791537286,278.35,2670,100,46
|
||||
1791537287,278.38,2670,100,46
|
||||
1791537288,278.77,2670,100,46
|
||||
1791537289,278.72,2670,100,46
|
||||
1791537290,278.69,2670,100,46
|
||||
1791537292,278.47,2670,100,46
|
||||
1791537293,278.36,2670,100,46
|
||||
1791537294,278.64,2670,100,46
|
||||
1791537295,278.44,2670,100,46
|
||||
1791537296,278.32,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-05-x4-prefix.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-05-x4-prefix.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791537316,27.58,210,0,33
|
||||
1791537317,39.70,2520,0,34
|
||||
1791537318,86.60,2520,17,34
|
||||
1791537319,80.95,2520,1,34
|
||||
1791537320,205.81,2685,100,39
|
||||
1791537321,274.61,2685,100,40
|
||||
1791537322,274.92,2685,100,40
|
||||
1791537324,275.11,2685,100,40
|
||||
1791537325,275.49,2685,100,41
|
||||
1791537326,275.89,2685,100,41
|
||||
1791537327,275.90,2685,100,41
|
||||
1791537328,275.99,2685,100,41
|
||||
1791537329,276.30,2685,100,41
|
||||
1791537330,276.09,2685,100,41
|
||||
1791537331,276.41,2685,100,42
|
||||
1791537332,276.95,2685,100,42
|
||||
1791537333,276.94,2685,100,42
|
||||
1791537334,276.71,2685,100,42
|
||||
1791537335,276.70,2685,100,42
|
||||
1791537336,276.50,2685,100,42
|
||||
1791537337,276.80,2685,100,42
|
||||
1791537338,276.93,2685,100,42
|
||||
1791537339,276.93,2685,100,43
|
||||
1791537340,276.72,2685,100,43
|
||||
1791537341,276.92,2685,100,43
|
||||
1791537343,277.05,2685,100,43
|
||||
1791537344,277.20,2685,100,43
|
||||
1791537345,277.20,2685,100,43
|
||||
1791537346,277.04,2685,100,43
|
||||
1791537347,276.66,2685,100,43
|
||||
1791537348,277.09,2685,100,43
|
||||
1791537349,277.14,2685,100,43
|
||||
1791537350,276.90,2685,100,43
|
||||
1791537351,277.09,2685,100,43
|
||||
1791537352,277.24,2685,100,44
|
||||
1791537353,277.51,2685,100,44
|
||||
1791537354,277.56,2685,100,44
|
||||
1791537355,277.63,2685,100,44
|
||||
1791537356,277.40,2685,100,44
|
||||
1791537357,277.61,2685,100,44
|
||||
1791537358,277.57,2670,100,44
|
||||
1791537359,277.49,2670,100,44
|
||||
1791537361,277.69,2670,100,44
|
||||
1791537362,277.84,2670,100,44
|
||||
1791537363,277.68,2670,100,44
|
||||
1791537364,277.75,2670,100,44
|
||||
1791537365,277.51,2670,100,44
|
||||
1791537366,277.55,2670,100,44
|
||||
1791537367,278.13,2670,100,44
|
||||
1791537368,278.24,2670,100,44
|
||||
1791537369,278.02,2670,100,44
|
||||
1791537370,277.86,2670,100,44
|
||||
1791537371,277.76,2670,100,45
|
||||
1791537372,277.91,2670,100,45
|
||||
1791537373,277.75,2670,100,45
|
||||
1791537374,277.59,2670,100,45
|
||||
1791537375,277.47,2670,100,45
|
||||
1791537376,277.33,2670,100,45
|
||||
1791537377,277.59,2670,100,45
|
||||
1791537378,277.71,2670,100,45
|
||||
1791537380,277.94,2670,100,45
|
||||
1791537381,277.90,2670,100,45
|
||||
1791537382,278.12,2670,100,45
|
||||
1791537383,277.92,2670,100,45
|
||||
1791537384,277.86,2670,100,45
|
||||
1791537385,278.00,2670,100,45
|
||||
1791537386,278.04,2670,100,45
|
||||
1791537387,277.95,2670,100,45
|
||||
1791537388,277.85,2670,100,45
|
||||
1791537389,277.88,2670,100,45
|
||||
1791537390,277.84,2670,100,45
|
||||
1791537391,278.05,2670,100,45
|
||||
1791537392,278.12,2670,100,45
|
||||
1791537393,277.99,2670,100,45
|
||||
1791537394,277.53,2670,100,45
|
||||
1791537395,277.46,2670,100,45
|
||||
1791537396,277.26,2670,100,45
|
||||
1791537397,278.12,2670,100,45
|
||||
1791537399,277.80,2670,100,45
|
||||
1791537400,278.03,2670,100,45
|
||||
1791537401,278.02,2670,100,45
|
||||
1791537402,278.27,2670,100,45
|
||||
1791537403,278.34,2670,100,45
|
||||
1791537404,278.03,2670,100,45
|
||||
1791537405,277.64,2670,96,45
|
||||
1791537406,277.62,2670,100,45
|
||||
1791537407,278.54,2670,100,45
|
||||
1791537408,277.84,2670,100,45
|
||||
1791537409,278.21,2670,100,46
|
||||
1791537410,277.92,2670,100,46
|
||||
1791537411,277.84,2670,100,46
|
||||
1791537412,278.15,2670,100,46
|
||||
1791537413,278.53,2670,100,46
|
||||
1791537414,278.28,2670,100,46
|
||||
1791537415,278.30,2670,100,46
|
||||
1791537416,278.34,2670,100,46
|
||||
1791537417,278.46,2670,100,46
|
||||
1791537419,278.55,2670,100,46
|
||||
1791537420,278.02,2670,100,46
|
||||
1791537421,278.13,2670,100,46
|
||||
1791537422,278.29,2670,100,46
|
||||
1791537423,278.64,2670,100,46
|
||||
1791537424,278.41,2670,100,46
|
||||
1791537425,278.55,2670,100,46
|
||||
1791537426,278.51,2670,100,46
|
||||
1791537427,278.23,2670,100,46
|
||||
1791537428,278.15,2670,100,46
|
||||
1791537429,278.11,2670,100,46
|
||||
1791537430,277.91,2670,100,46
|
||||
1791537431,278.18,2670,100,46
|
||||
1791537432,278.55,2670,100,46
|
||||
1791537433,278.61,2670,100,46
|
||||
1791537434,278.94,2670,100,46
|
||||
1791537436,278.91,2670,100,46
|
||||
1791537437,278.68,2670,100,46
|
||||
1791537438,278.70,2670,100,46
|
||||
1791537439,278.99,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-06-x4-generated.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-06-x4-generated.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791537460,27.78,210,0,33
|
||||
1791537461,49.56,2520,0,34
|
||||
1791537462,86.83,2520,43,34
|
||||
1791537463,86.76,2520,0,33
|
||||
1791537464,128.93,2685,100,38
|
||||
1791537465,271.06,2685,100,39
|
||||
1791537466,272.26,2685,100,40
|
||||
1791537467,272.39,2685,100,40
|
||||
1791537468,272.47,2685,100,40
|
||||
1791537469,272.55,2685,100,40
|
||||
1791537470,273.35,2685,100,40
|
||||
1791537472,273.18,2685,100,41
|
||||
1791537473,272.39,2685,100,41
|
||||
1791537474,273.84,2685,100,41
|
||||
1791537475,273.62,2685,99,41
|
||||
1791537476,273.85,2685,100,41
|
||||
1791537477,273.70,2685,100,41
|
||||
1791537478,273.80,2685,100,41
|
||||
1791537479,273.46,2685,100,42
|
||||
1791537480,273.37,2685,100,42
|
||||
1791537481,273.42,2685,100,42
|
||||
1791537482,273.84,2685,100,42
|
||||
1791537483,274.07,2685,100,42
|
||||
1791537484,274.21,2685,100,42
|
||||
1791537485,274.43,2685,100,42
|
||||
1791537486,274.73,2685,100,42
|
||||
1791537487,274.43,2685,100,42
|
||||
1791537488,274.43,2685,100,43
|
||||
1791537489,274.33,2685,100,43
|
||||
1791537490,273.98,2685,100,43
|
||||
1791537492,274.48,2685,100,43
|
||||
1791537493,274.78,2685,100,43
|
||||
1791537494,274.71,2685,100,43
|
||||
1791537495,274.56,2685,100,43
|
||||
1791537496,274.80,2685,100,43
|
||||
1791537497,274.70,2685,100,43
|
||||
1791537498,274.75,2685,100,43
|
||||
1791537499,274.66,2685,100,43
|
||||
1791537500,274.46,2685,100,43
|
||||
1791537501,274.53,2685,100,43
|
||||
1791537502,274.48,2685,100,43
|
||||
1791537503,274.67,2685,100,44
|
||||
1791537504,274.49,2685,100,44
|
||||
1791537505,274.22,2685,100,44
|
||||
1791537506,274.42,2685,100,44
|
||||
1791537507,274.69,2685,100,44
|
||||
1791537509,274.79,2685,100,44
|
||||
1791537510,274.49,2685,100,44
|
||||
1791537511,274.48,2670,100,44
|
||||
1791537512,274.73,2670,100,44
|
||||
1791537513,274.59,2670,100,44
|
||||
1791537514,274.79,2670,100,44
|
||||
1791537515,274.33,2670,100,44
|
||||
1791537516,274.62,2670,100,44
|
||||
1791537517,274.60,2670,100,44
|
||||
1791537518,274.78,2670,100,44
|
||||
1791537519,274.37,2670,97,44
|
||||
1791537520,274.47,2670,100,44
|
||||
1791537521,274.94,2670,100,44
|
||||
1791537522,275.42,2670,100,44
|
||||
1791537523,275.34,2670,100,44
|
||||
1791537524,275.12,2670,100,44
|
||||
1791537525,275.26,2670,100,44
|
||||
1791537526,275.38,2670,100,45
|
||||
1791537528,275.47,2670,100,45
|
||||
1791537529,275.05,2670,100,44
|
||||
1791537530,275.18,2670,100,45
|
||||
1791537531,275.41,2670,100,45
|
||||
1791537532,275.73,2670,100,45
|
||||
1791537533,275.77,2670,100,45
|
||||
1791537534,275.38,2670,100,45
|
||||
1791537535,275.20,2670,100,45
|
||||
1791537536,275.27,2670,100,45
|
||||
1791537537,275.29,2670,100,45
|
||||
1791537538,275.40,2670,100,45
|
||||
1791537539,274.98,2670,100,45
|
||||
1791537540,275.19,2670,100,45
|
||||
1791537541,275.27,2670,100,45
|
||||
1791537542,275.15,2670,100,45
|
||||
1791537543,275.28,2670,100,45
|
||||
1791537545,275.53,2670,100,45
|
||||
1791537546,275.58,2670,100,45
|
||||
1791537547,275.81,2670,100,45
|
||||
1791537548,275.49,2670,100,45
|
||||
1791537549,275.24,2670,100,45
|
||||
1791537550,275.24,2670,100,45
|
||||
1791537551,275.51,2670,100,45
|
||||
1791537552,275.41,2670,100,45
|
||||
1791537553,275.43,2670,100,45
|
||||
1791537554,275.48,2670,100,45
|
||||
1791537555,275.57,2670,100,45
|
||||
1791537556,275.73,2670,100,45
|
||||
1791537557,276.05,2670,100,45
|
||||
1791537558,275.66,2670,100,45
|
||||
1791537559,275.39,2670,100,45
|
||||
1791537560,275.60,2670,100,45
|
||||
1791537562,275.39,2670,100,45
|
||||
1791537563,275.62,2670,100,45
|
||||
1791537564,275.68,2670,100,45
|
||||
1791537565,275.84,2670,100,45
|
||||
1791537566,275.54,2670,100,45
|
||||
1791537567,275.51,2670,100,45
|
||||
1791537568,275.70,2670,100,45
|
||||
1791537569,275.59,2670,100,45
|
||||
1791537570,274.98,2670,100,45
|
||||
1791537571,275.85,2670,100,45
|
||||
1791537572,276.00,2670,100,45
|
||||
1791537573,275.61,2670,100,45
|
||||
1791537574,275.47,2670,100,45
|
||||
1791537575,275.48,2670,100,45
|
||||
1791537576,275.54,2670,100,45
|
||||
1791537577,275.87,2670,100,45
|
||||
1791537579,275.84,2670,100,45
|
||||
1791537580,275.49,2670,100,45
|
||||
1791537581,275.34,2670,100,46
|
||||
1791537582,275.41,2670,100,46
|
||||
1791537583,275.46,2670,100,46
|
||||
|
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-07-x4-direct.csv
Normal file
117
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-07-x4-direct.csv
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
1791537604,27.51,210,0,33
|
||||
1791537605,47.95,2520,0,33
|
||||
1791537606,86.03,2520,0,34
|
||||
1791537607,81.64,2520,0,33
|
||||
1791537608,192.44,2685,100,38
|
||||
1791537609,271.61,2685,100,39
|
||||
1791537610,271.80,2685,100,40
|
||||
1791537611,271.72,2685,100,40
|
||||
1791537612,272.13,2685,100,40
|
||||
1791537613,272.34,2685,100,40
|
||||
1791537615,272.41,2685,100,40
|
||||
1791537616,272.02,2685,100,41
|
||||
1791537617,271.95,2685,100,41
|
||||
1791537618,272.37,2685,100,41
|
||||
1791537619,272.10,2685,100,41
|
||||
1791537620,272.14,2685,100,41
|
||||
1791537621,272.49,2685,100,41
|
||||
1791537622,272.52,2685,100,41
|
||||
1791537623,272.54,2685,100,42
|
||||
1791537624,272.59,2685,100,42
|
||||
1791537625,273.15,2685,100,42
|
||||
1791537626,273.42,2685,100,42
|
||||
1791537627,273.12,2685,100,42
|
||||
1791537628,273.47,2685,100,42
|
||||
1791537629,273.56,2685,100,42
|
||||
1791537630,273.83,2685,100,42
|
||||
1791537632,273.72,2685,100,42
|
||||
1791537633,274.03,2685,100,43
|
||||
1791537634,274.26,2685,100,43
|
||||
1791537635,273.67,2685,100,43
|
||||
1791537636,273.82,2685,100,43
|
||||
1791537637,273.91,2685,100,43
|
||||
1791537638,274.09,2685,100,43
|
||||
1791537639,274.06,2685,100,43
|
||||
1791537640,274.09,2685,100,43
|
||||
1791537641,274.11,2685,100,43
|
||||
1791537642,273.97,2685,100,43
|
||||
1791537643,274.58,2685,100,43
|
||||
1791537644,274.49,2685,100,43
|
||||
1791537645,274.88,2685,100,43
|
||||
1791537646,275.07,2685,100,43
|
||||
1791537647,275.20,2685,100,44
|
||||
1791537649,275.51,2685,100,44
|
||||
1791537650,275.23,2685,100,44
|
||||
1791537651,275.10,2685,100,44
|
||||
1791537652,275.18,2685,100,44
|
||||
1791537653,275.02,2685,100,44
|
||||
1791537654,275.15,2670,100,44
|
||||
1791537655,274.88,2670,100,44
|
||||
1791537656,275.16,2670,100,44
|
||||
1791537657,275.14,2670,100,44
|
||||
1791537658,275.09,2670,100,44
|
||||
1791537659,274.88,2670,100,44
|
||||
1791537660,274.87,2670,100,44
|
||||
1791537661,275.16,2670,100,44
|
||||
1791537662,275.24,2670,100,44
|
||||
1791537663,274.98,2670,100,44
|
||||
1791537664,274.68,2670,100,44
|
||||
1791537666,274.64,2670,100,44
|
||||
1791537667,275.03,2670,100,44
|
||||
1791537668,275.03,2670,100,44
|
||||
1791537669,274.77,2670,100,44
|
||||
1791537670,274.99,2670,100,45
|
||||
1791537671,275.12,2670,100,45
|
||||
1791537672,275.27,2670,100,45
|
||||
1791537673,275.44,2670,100,45
|
||||
1791537674,275.14,2670,100,45
|
||||
1791537675,275.09,2670,100,45
|
||||
1791537676,275.39,2670,100,45
|
||||
1791537677,275.51,2670,100,45
|
||||
1791537678,275.53,2670,100,45
|
||||
1791537679,275.66,2670,100,45
|
||||
1791537680,275.76,2670,100,45
|
||||
1791537681,275.70,2670,100,45
|
||||
1791537682,276.13,2670,100,45
|
||||
1791537684,275.75,2670,100,45
|
||||
1791537685,275.75,2670,100,45
|
||||
1791537686,275.86,2670,100,45
|
||||
1791537687,275.65,2670,100,45
|
||||
1791537688,275.73,2670,100,45
|
||||
1791537689,275.67,2670,100,45
|
||||
1791537690,275.65,2670,100,45
|
||||
1791537691,275.67,2670,100,45
|
||||
1791537692,275.95,2670,100,45
|
||||
1791537693,276.16,2670,100,45
|
||||
1791537694,275.87,2670,100,45
|
||||
1791537695,276.40,2670,100,45
|
||||
1791537696,275.88,2670,100,45
|
||||
1791537697,275.58,2670,100,45
|
||||
1791537698,275.83,2670,100,45
|
||||
1791537699,275.79,2670,100,45
|
||||
1791537701,275.62,2670,100,45
|
||||
1791537702,275.62,2670,100,45
|
||||
1791537703,275.67,2670,100,45
|
||||
1791537704,275.69,2670,100,45
|
||||
1791537705,275.80,2670,100,45
|
||||
1791537706,275.79,2670,100,45
|
||||
1791537707,275.96,2670,100,45
|
||||
1791537708,275.91,2670,100,45
|
||||
1791537709,276.00,2670,100,45
|
||||
1791537710,276.33,2670,100,45
|
||||
1791537711,276.05,2670,100,45
|
||||
1791537712,275.82,2670,100,45
|
||||
1791537713,275.83,2670,100,45
|
||||
1791537714,275.79,2670,100,45
|
||||
1791537715,275.68,2670,100,45
|
||||
1791537716,276.52,2670,100,45
|
||||
1791537717,276.24,2670,100,45
|
||||
1791537719,275.78,2670,100,45
|
||||
1791537720,276.03,2670,100,46
|
||||
1791537721,276.27,2670,100,46
|
||||
1791537722,276.12,2670,100,46
|
||||
1791537723,276.33,2670,100,46
|
||||
1791537724,276.52,2670,100,46
|
||||
1791537725,276.54,2670,100,46
|
||||
1791537726,276.20,2670,100,46
|
||||
1791537727,276.32,2670,100,46
|
||||
|
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-08-hl-v6-all.csv
Normal file
118
docs/analysis/class-v6/1p5x/x4/pod-s2/smi-08-hl-v6-all.csv
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
1791537747,27.40,210,0,33
|
||||
1791537749,46.65,2520,0,33
|
||||
1791537750,81.12,2520,0,33
|
||||
1791537751,81.00,2520,0,33
|
||||
1791537752,130.12,2685,100,38
|
||||
1791537753,253.26,2685,100,39
|
||||
1791537754,284.53,2685,100,40
|
||||
1791537755,284.60,2685,100,40
|
||||
1791537756,284.13,2685,100,40
|
||||
1791537757,284.60,2685,100,41
|
||||
1791537758,285.18,2685,100,41
|
||||
1791537759,285.54,2685,100,41
|
||||
1791537760,285.55,2685,100,41
|
||||
1791537761,285.42,2685,100,42
|
||||
1791537762,285.53,2685,100,42
|
||||
1791537763,285.24,2685,100,42
|
||||
1791537764,285.26,2685,100,42
|
||||
1791537765,285.26,2685,100,42
|
||||
1791537767,285.40,2685,100,42
|
||||
1791537768,285.45,2685,100,42
|
||||
1791537769,285.73,2685,100,43
|
||||
1791537770,286.00,2685,100,43
|
||||
1791537771,285.87,2685,100,43
|
||||
1791537772,286.22,2685,100,43
|
||||
1791537773,285.95,2685,100,43
|
||||
1791537774,285.96,2685,100,43
|
||||
1791537775,285.92,2685,100,43
|
||||
1791537776,286.01,2685,100,43
|
||||
1791537777,285.96,2685,100,44
|
||||
1791537778,286.32,2685,100,44
|
||||
1791537779,286.23,2685,100,44
|
||||
1791537780,286.25,2685,100,44
|
||||
1791537781,286.63,2670,100,44
|
||||
1791537782,286.44,2670,100,44
|
||||
1791537783,286.19,2670,100,44
|
||||
1791537785,286.31,2670,100,44
|
||||
1791537786,286.45,2670,100,44
|
||||
1791537787,286.55,2670,100,44
|
||||
1791537788,286.82,2670,100,44
|
||||
1791537789,286.51,2670,100,44
|
||||
1791537790,286.82,2670,100,44
|
||||
1791537791,286.42,2670,100,45
|
||||
1791537792,286.90,2670,100,45
|
||||
1791537793,286.84,2670,100,45
|
||||
1791537794,286.63,2670,100,45
|
||||
1791537795,286.54,2670,100,45
|
||||
1791537796,286.65,2670,100,45
|
||||
1791537797,286.94,2670,100,45
|
||||
1791537798,287.28,2670,100,45
|
||||
1791537799,287.34,2670,100,45
|
||||
1791537800,287.54,2670,100,45
|
||||
1791537801,287.22,2670,100,45
|
||||
1791537802,287.30,2670,100,45
|
||||
1791537804,287.25,2670,100,45
|
||||
1791537805,287.18,2670,100,45
|
||||
1791537806,287.52,2670,100,45
|
||||
1791537807,287.50,2670,100,45
|
||||
1791537808,287.69,2670,100,45
|
||||
1791537809,287.54,2670,100,45
|
||||
1791537810,287.32,2670,100,46
|
||||
1791537811,287.32,2670,100,46
|
||||
1791537812,287.42,2670,100,46
|
||||
1791537813,287.60,2670,100,46
|
||||
1791537814,287.20,2670,100,46
|
||||
1791537815,287.45,2670,100,46
|
||||
1791537816,287.47,2670,100,46
|
||||
1791537817,287.26,2670,100,46
|
||||
1791537818,287.34,2670,100,46
|
||||
1791537819,287.37,2670,100,46
|
||||
1791537820,287.47,2670,100,46
|
||||
1791537822,287.50,2670,100,46
|
||||
1791537823,287.43,2670,100,46
|
||||
1791537824,287.26,2670,100,46
|
||||
1791537825,287.65,2670,100,46
|
||||
1791537826,287.80,2670,100,46
|
||||
1791537827,287.65,2670,100,46
|
||||
1791537828,287.52,2670,100,46
|
||||
1791537829,287.68,2670,100,46
|
||||
1791537830,287.58,2670,100,46
|
||||
1791537831,287.68,2670,100,46
|
||||
1791537832,287.86,2670,100,46
|
||||
1791537833,287.38,2670,100,46
|
||||
1791537834,287.53,2670,100,46
|
||||
1791537835,287.71,2670,100,46
|
||||
1791537836,287.42,2670,100,46
|
||||
1791537837,287.53,2670,100,46
|
||||
1791537838,287.72,2670,100,46
|
||||
1791537840,287.56,2670,100,46
|
||||
1791537841,287.89,2670,100,46
|
||||
1791537842,287.81,2670,100,46
|
||||
1791537843,287.87,2670,100,46
|
||||
1791537844,287.82,2670,100,46
|
||||
1791537845,287.81,2670,100,46
|
||||
1791537846,287.95,2670,100,46
|
||||
1791537847,288.20,2670,100,46
|
||||
1791537848,288.24,2670,100,46
|
||||
1791537849,288.27,2670,100,46
|
||||
1791537850,288.44,2670,100,46
|
||||
1791537851,288.34,2670,100,46
|
||||
1791537852,288.13,2670,100,47
|
||||
1791537853,288.21,2670,100,47
|
||||
1791537854,288.27,2670,100,47
|
||||
1791537855,287.92,2670,100,47
|
||||
1791537856,288.00,2670,100,47
|
||||
1791537857,287.95,2670,100,47
|
||||
1791537859,287.98,2670,100,47
|
||||
1791537860,287.47,2670,100,46
|
||||
1791537861,287.57,2670,100,47
|
||||
1791537862,288.09,2670,100,47
|
||||
1791537863,288.23,2670,100,47
|
||||
1791537864,288.52,2670,100,47
|
||||
1791537865,288.55,2670,100,47
|
||||
1791537866,288.64,2670,100,47
|
||||
1791537867,288.74,2670,100,47
|
||||
1791537868,288.98,2670,100,47
|
||||
1791537869,288.61,2670,100,47
|
||||
1791537870,288.70,2670,100,47
|
||||
1791537871,288.71,2670,100,47
|
||||
|
|
|
@ -0,0 +1,24 @@
|
|||
{
|
||||
"run_id": "1p5x-x4-20261009",
|
||||
"manifest_sha": "1a938abe4 (the frozen control); the forms on 1p5x-x4 b51d8c04b",
|
||||
"evidence_dir": "docs/analysis/class-v6/1p5x/x4/README.md",
|
||||
"boxes": [
|
||||
"build-9",
|
||||
"runpod:fk-x4-4090"
|
||||
],
|
||||
"cells": [
|
||||
{
|
||||
"cell": "rows:1p5x-x4",
|
||||
"status": "NOT RUN",
|
||||
"evidence": "docs/analysis/class-v6/1p5x/x4/README.md",
|
||||
"note": "X4 of the 1.5x programme: three byte-identical reg64c address-mix forms (direct, generated, prefix). Equivalence measured: CPU differential EQUIVALENT (rows/VERDICT; the known-failed form refused first) and GPU self-test plus fingerprint e8f4f3289c6ee1fc on all forms. GPU pairs: RTX 4090 at stock only, g 0.959 to 0.969 at equal rate, with an occupancy confound. Chip rows modelled: 10 to 52 nJ per hash for the cheapest form. Arithmetic from 2.0x: r_new 1.86 to 1.99. No pass claimed. NOT RUN by the brief's rule (rows stay NOT RUN until the steward's X6). The knee, the 5090 and the occupancy control are BLOCKED or NOT RUN (README section 6). Island: the 4090 rows are on an island, not a network."
|
||||
}
|
||||
],
|
||||
"method": "GPU",
|
||||
"release_identity": {
|
||||
"commit": "b51d8c04b (branch 1p5x-x4 off master a7f81d9a9)",
|
||||
"binary": "igneum-pow ccb1bf0efebce4bb (build-9 release build of b51d8c04b); igneum-worker-cuda-gen6 804a6f7fea10a62e",
|
||||
"network_object": "none (packs exported from the frozen object, program id 0x4de7b836cc40a4ea; no network)",
|
||||
"activation": "none"
|
||||
}
|
||||
}
|
||||
3
docs/analysis/class-v6/1p5x/x4/rows/VERDICT
Normal file
3
docs/analysis/class-v6/1p5x/x4/rows/VERDICT
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
tally {('direct', 'AGREE'): 44, ('fold', 'AGREE'): 12, ('generated', 'AGREE'): 44, ('prefix', 'AGREE'): 44, ('wrong', 'DISAGREE'): 40, ('wrong', 'AGREE'): 4}
|
||||
known-failed refused on every reg64c window and seed: True
|
||||
VERDICT EQUIVALENT mismatches 0
|
||||
12
docs/analysis/class-v6/1p5x/x4/rows/arith.txt
Normal file
12
docs/analysis/class-v6/1p5x/x4/rows/arith.txt
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
form g a vs fold (slot, datapath) a vs model (slot, datapath) r_new at r0 2.0, same form both sides (vs fold slot, dp; vs model slot, dp)
|
||||
direct 0.9606 0.9990, 0.9998 1.0726, 1.0150 1.923, 1.922, 1.791, 1.893
|
||||
generated 0.9590 0.9668, 0.9925 1.0381, 1.0075 1.984, 1.933, 1.848, 1.904
|
||||
prefix 0.9693 1.4508, 1.1004 1.5578, 1.1171 1.336, 1.762, 1.244, 1.735
|
||||
grouped incremental 1.0000 (no GPU text) 0.9629, 0.9914 1.0339, 1.0065 2.077, 2.017, 1.934, 1.987
|
||||
|
||||
best pair: the card on 'generated' (g 0.9590), the specialist on 'grouped incremental'
|
||||
r0 2.0: vs fold slot: a 0.9629 r_new 1.992; vs fold datapath: a 0.9914 r_new 1.935; vs model slot: a 1.0339 r_new 1.855; vs model datapath: a 1.0065 r_new 1.906
|
||||
r0 1.9: vs fold slot: a 0.9629 r_new 1.892; vs fold datapath: a 0.9914 r_new 1.838; vs model slot: a 1.0339 r_new 1.762; vs model datapath: a 1.0065 r_new 1.810
|
||||
r0 2.1: vs fold slot: a 0.9629 r_new 2.092; vs fold datapath: a 0.9914 r_new 2.031; vs model slot: a 1.0339 r_new 1.948; vs model datapath: a 1.0065 r_new 2.001
|
||||
|
||||
the yardstick: from 2.0, 1.5 needs g / a = 0.75
|
||||
19
docs/analysis/class-v6/1p5x/x4/rows/chip-rows.txt
Normal file
19
docs/analysis/class-v6/1p5x/x4/rows/chip-rows.txt
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
# loads per hash executed 256 (32 per iteration x 8); base writes per iteration 128 (112 to r8..r63); shadow writes per pass 256, all in r0..r7
|
||||
form mix ops X extra reads A flop bits F state bits per lane slot nJ (lo c hi) datapath nJ (lo c hi) state ports
|
||||
fold (frozen) 16128 16128 0 0 101.0 112.7 139.4 20.2 23.2 30.2 the 64 x 32-bit window only 63 window reads per load
|
||||
direct 15872 16128 0 0 99.4 111.0 137.4 19.9 22.9 30.0 the window only 63 window reads per load (a tree: depth 6, same reads)
|
||||
generated (GPU text: recompute at load) 8400 5792 20224 256 52.5 58.2 70.9 10.5 11.5 14.1 +8 x 32-bit group sums per lane (32 B, flops) group recomputes read 8 registers each; the in-group partial reads up to 7
|
||||
prefix (F05 text: running S on every write) 121320 8160 1802240 32 785.2 852.3 1003.9 177.4 179.0 182.5 +1 x 32-bit running total per lane (flops) the old value of every written register (main and shadow) rotated into S
|
||||
grouped incremental (chip only, by the same identity) 7560 2784 36864 256 47.2 51.8 62.3 9.4 9.9 11.1 +8 x 32-bit group sums per lane (32 B) groups 1..7 move on base writes to r8..r63; group 0 recomputed at each load (8 reads)
|
||||
|
||||
# a = (machine + form) / machine, machine 1.528 microjoules (N5, GDDR7 board, no mix term); per-lane-op delta over the 102,612 shadow+base lane-ops
|
||||
fold (frozen) slot +112.7 nJ a 1.0738 per lane-op +1.098 pJ of the shadow +16.8 percent
|
||||
fold (frozen) dp +23.2 nJ a 1.0152 per lane-op +0.226 pJ of the shadow +3.5 percent
|
||||
direct slot +111.0 nJ a 1.0727 per lane-op +1.082 pJ of the shadow +16.5 percent
|
||||
direct dp +22.9 nJ a 1.0150 per lane-op +0.223 pJ of the shadow +3.4 percent
|
||||
generated (GPU text: recompute at load) slot +58.2 nJ a 1.0381 per lane-op +0.567 pJ of the shadow +8.7 percent
|
||||
generated (GPU text: recompute at load) dp +11.5 nJ a 1.0076 per lane-op +0.112 pJ of the shadow +1.7 percent
|
||||
prefix (F05 text: running S on every write) slot +852.3 nJ a 1.5578 per lane-op +8.306 pJ of the shadow +126.8 percent
|
||||
prefix (F05 text: running S on every write) dp +179.0 nJ a 1.1171 per lane-op +1.744 pJ of the shadow +26.6 percent
|
||||
grouped incremental (chip only, by the same identity) slot +51.8 nJ a 1.0339 per lane-op +0.505 pJ of the shadow +7.7 percent
|
||||
grouped incremental (chip only, by the same identity) dp +9.9 nJ a 1.0065 per lane-op +0.096 pJ of the shadow +1.5 percent
|
||||
15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows-s2.txt
Normal file
15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows-s2.txt
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
run pack MH/s W nJ per hash sm MHz util samples regs blocks/SM fingerprint check
|
||||
01-hl-v6-all hl-v6-all 35.081 286.7 8172 2678 100 110 93 20 e8f4f3289c6ee1fc PASS
|
||||
02-x4-direct x4-direct 35.022 275.2 7857 2676 100 109 182 8 e8f4f3289c6ee1fc PASS
|
||||
03-x4-generated x4-generated 35.055 275.1 7847 2675 100 109 142 12 e8f4f3289c6ee1fc PASS
|
||||
04-x4-prefix x4-prefix 34.971 277.2 7926 2675 100 111 154 12 e8f4f3289c6ee1fc PASS
|
||||
05-x4-prefix x4-prefix 35.050 277.7 7922 2674 100 110 154 12 e8f4f3289c6ee1fc PASS
|
||||
06-x4-generated x4-generated 35.053 274.9 7842 2676 100 109 142 12 e8f4f3289c6ee1fc PASS
|
||||
07-x4-direct x4-direct 35.022 274.9 7850 2675 100 109 182 8 e8f4f3289c6ee1fc PASS
|
||||
08-hl-v6-all hl-v6-all 35.081 287.1 8184 2673 100 111 93 20 e8f4f3289c6ee1fc PASS
|
||||
|
||||
pair form pass 1 rate % pass 1 J/hash % pass 2 rate % pass 2 J/hash % mean rate % mean J/hash % g (J/hash ratio)
|
||||
A/A hl-v6-all run 8 vs run 1 +0.00 +0.15
|
||||
pair x4-direct -0.17 -3.85 -0.17 -4.08 -0.17 -3.97 0.9603
|
||||
pair x4-generated -0.07 -3.98 -0.08 -4.18 -0.08 -4.08 0.9592
|
||||
pair x4-prefix -0.31 -3.01 -0.09 -3.21 -0.20 -3.11 0.9689
|
||||
15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows.txt
Normal file
15
docs/analysis/class-v6/1p5x/x4/rows/gpu-rows.txt
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
run pack MH/s W nJ per hash sm MHz util samples regs blocks/SM fingerprint check
|
||||
01-hl-v6-all hl-v6-all 35.080 285.4 8134 2679 100 111 93 20 e8f4f3289c6ee1fc PASS
|
||||
02-x4-direct x4-direct 35.021 274.5 7839 2681 100 109 182 8 e8f4f3289c6ee1fc PASS
|
||||
03-x4-generated x4-generated 35.053 274.2 7824 2680 100 110 142 12 e8f4f3289c6ee1fc PASS
|
||||
04-x4-prefix x4-prefix 35.056 277.1 7905 2680 100 109 154 12 e8f4f3289c6ee1fc PASS
|
||||
05-x4-prefix x4-prefix 35.053 277.8 7926 2679 100 110 154 12 e8f4f3289c6ee1fc PASS
|
||||
06-x4-generated x4-generated 35.056 274.8 7840 2678 100 109 142 12 e8f4f3289c6ee1fc PASS
|
||||
07-x4-direct x4-direct 35.020 274.9 7851 2677 100 111 182 8 e8f4f3289c6ee1fc PASS
|
||||
08-hl-v6-all hl-v6-all 35.054 287.4 8199 2674 100 110 93 20 e8f4f3289c6ee1fc PASS
|
||||
|
||||
pair form pass 1 rate % pass 1 J/hash % pass 2 rate % pass 2 J/hash % mean rate % mean J/hash % g (J/hash ratio)
|
||||
A/A hl-v6-all run 8 vs run 1 -0.07 +0.80
|
||||
pair x4-direct -0.17 -3.63 -0.10 -4.25 -0.13 -3.94 0.9606
|
||||
pair x4-generated -0.08 -3.82 +0.01 -4.38 -0.04 -4.10 0.9590
|
||||
pair x4-prefix -0.07 -2.82 -0.00 -3.33 -0.04 -3.07 0.9693
|
||||
15
docs/analysis/class-v6/1p5x/x4/rows/suite-b51d8c04b.txt
Normal file
15
docs/analysis/class-v6/1p5x/x4/rows/suite-b51d8c04b.txt
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
test reg64form::tests::x4_forms_equal_the_fold_and_the_wrong_form_is_refused ... ok
|
||||
test result: ok. 76 passed; 0 failed; 6 ignored; 0 measured; 0 filtered out; finished in 140.72s
|
||||
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
|
||||
test result: ok. 2 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 0.01s
|
||||
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 1.42s
|
||||
test result: ok. 5 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.99s
|
||||
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.01s
|
||||
test result: ok. 4 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 9.80s
|
||||
test result: ok. 27 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 8.37s
|
||||
test result: ok. 2 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 6.03s
|
||||
test result: ok. 7 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 4.85s
|
||||
test result: ok. 3 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 7.01s
|
||||
test result: ok. 12 passed; 0 failed; 1 ignored; 0 measured; 0 filtered out; finished in 20.99s
|
||||
test result: ok. 0 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 0.00s
|
||||
EXIT 0
|
||||
188
docs/analysis/class-v6/1p5x/x4/rows/verdicts.txt
Normal file
188
docs/analysis/class-v6/1p5x/x4/rows/verdicts.txt
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
ctx01 direct D@0 AGREE
|
||||
ctx01 direct D1@1572864 AGREE
|
||||
ctx01 direct D1@3141632 AGREE
|
||||
ctx01 direct D@1568768 AGREE
|
||||
ctx01 fold D@0 AGREE
|
||||
ctx01 fold D1@1572864 AGREE
|
||||
ctx01 fold D1@3141632 AGREE
|
||||
ctx01 fold D@1568768 AGREE
|
||||
ctx01 generated D@0 AGREE
|
||||
ctx01 generated D1@1572864 AGREE
|
||||
ctx01 generated D1@3141632 AGREE
|
||||
ctx01 generated D@1568768 AGREE
|
||||
ctx01 prefix D@0 AGREE
|
||||
ctx01 prefix D1@1572864 AGREE
|
||||
ctx01 prefix D1@3141632 AGREE
|
||||
ctx01 prefix D@1568768 AGREE
|
||||
ctx01 wrong D@0 DISAGREE
|
||||
ctx01 wrong D1@1572864 DISAGREE
|
||||
ctx01 wrong D1@3141632 DISAGREE
|
||||
ctx01 wrong D@1568768 DISAGREE
|
||||
ctx02 direct D@0 AGREE
|
||||
ctx02 direct D1@1572864 AGREE
|
||||
ctx02 direct D1@3141632 AGREE
|
||||
ctx02 direct D@1568768 AGREE
|
||||
ctx02 fold D@0 AGREE
|
||||
ctx02 fold D1@1572864 AGREE
|
||||
ctx02 fold D1@3141632 AGREE
|
||||
ctx02 fold D@1568768 AGREE
|
||||
ctx02 generated D@0 AGREE
|
||||
ctx02 generated D1@1572864 AGREE
|
||||
ctx02 generated D1@3141632 AGREE
|
||||
ctx02 generated D@1568768 AGREE
|
||||
ctx02 prefix D@0 AGREE
|
||||
ctx02 prefix D1@1572864 AGREE
|
||||
ctx02 prefix D1@3141632 AGREE
|
||||
ctx02 prefix D@1568768 AGREE
|
||||
ctx02 wrong D@0 DISAGREE
|
||||
ctx02 wrong D1@1572864 DISAGREE
|
||||
ctx02 wrong D1@3141632 DISAGREE
|
||||
ctx02 wrong D@1568768 DISAGREE
|
||||
ctx03 direct D@0 AGREE
|
||||
ctx03 direct D1@1572864 AGREE
|
||||
ctx03 direct D1@3141632 AGREE
|
||||
ctx03 direct D@1568768 AGREE
|
||||
ctx03 fold D@0 AGREE
|
||||
ctx03 fold D1@1572864 AGREE
|
||||
ctx03 fold D1@3141632 AGREE
|
||||
ctx03 fold D@1568768 AGREE
|
||||
ctx03 generated D@0 AGREE
|
||||
ctx03 generated D1@1572864 AGREE
|
||||
ctx03 generated D1@3141632 AGREE
|
||||
ctx03 generated D@1568768 AGREE
|
||||
ctx03 prefix D@0 AGREE
|
||||
ctx03 prefix D1@1572864 AGREE
|
||||
ctx03 prefix D1@3141632 AGREE
|
||||
ctx03 prefix D@1568768 AGREE
|
||||
ctx03 wrong D@0 AGREE
|
||||
ctx03 wrong D1@1572864 AGREE
|
||||
ctx03 wrong D1@3141632 AGREE
|
||||
ctx03 wrong D@1568768 AGREE
|
||||
fuzz0 direct AGREE
|
||||
fuzz0 generated AGREE
|
||||
fuzz0 prefix AGREE
|
||||
fuzz0 wrong DISAGREE
|
||||
fuzz10 direct AGREE
|
||||
fuzz10 generated AGREE
|
||||
fuzz10 prefix AGREE
|
||||
fuzz10 wrong DISAGREE
|
||||
fuzz11 direct AGREE
|
||||
fuzz11 generated AGREE
|
||||
fuzz11 prefix AGREE
|
||||
fuzz11 wrong DISAGREE
|
||||
fuzz12 direct AGREE
|
||||
fuzz12 generated AGREE
|
||||
fuzz12 prefix AGREE
|
||||
fuzz12 wrong DISAGREE
|
||||
fuzz13 direct AGREE
|
||||
fuzz13 generated AGREE
|
||||
fuzz13 prefix AGREE
|
||||
fuzz13 wrong DISAGREE
|
||||
fuzz14 direct AGREE
|
||||
fuzz14 generated AGREE
|
||||
fuzz14 prefix AGREE
|
||||
fuzz14 wrong DISAGREE
|
||||
fuzz15 direct AGREE
|
||||
fuzz15 generated AGREE
|
||||
fuzz15 prefix AGREE
|
||||
fuzz15 wrong DISAGREE
|
||||
fuzz16 direct AGREE
|
||||
fuzz16 generated AGREE
|
||||
fuzz16 prefix AGREE
|
||||
fuzz16 wrong DISAGREE
|
||||
fuzz17 direct AGREE
|
||||
fuzz17 generated AGREE
|
||||
fuzz17 prefix AGREE
|
||||
fuzz17 wrong DISAGREE
|
||||
fuzz18 direct AGREE
|
||||
fuzz18 generated AGREE
|
||||
fuzz18 prefix AGREE
|
||||
fuzz18 wrong DISAGREE
|
||||
fuzz19 direct AGREE
|
||||
fuzz19 generated AGREE
|
||||
fuzz19 prefix AGREE
|
||||
fuzz19 wrong DISAGREE
|
||||
fuzz1 direct AGREE
|
||||
fuzz1 generated AGREE
|
||||
fuzz1 prefix AGREE
|
||||
fuzz1 wrong DISAGREE
|
||||
fuzz20 direct AGREE
|
||||
fuzz20 generated AGREE
|
||||
fuzz20 prefix AGREE
|
||||
fuzz20 wrong DISAGREE
|
||||
fuzz21 direct AGREE
|
||||
fuzz21 generated AGREE
|
||||
fuzz21 prefix AGREE
|
||||
fuzz21 wrong DISAGREE
|
||||
fuzz22 direct AGREE
|
||||
fuzz22 generated AGREE
|
||||
fuzz22 prefix AGREE
|
||||
fuzz22 wrong DISAGREE
|
||||
fuzz23 direct AGREE
|
||||
fuzz23 generated AGREE
|
||||
fuzz23 prefix AGREE
|
||||
fuzz23 wrong DISAGREE
|
||||
fuzz24 direct AGREE
|
||||
fuzz24 generated AGREE
|
||||
fuzz24 prefix AGREE
|
||||
fuzz24 wrong DISAGREE
|
||||
fuzz25 direct AGREE
|
||||
fuzz25 generated AGREE
|
||||
fuzz25 prefix AGREE
|
||||
fuzz25 wrong DISAGREE
|
||||
fuzz26 direct AGREE
|
||||
fuzz26 generated AGREE
|
||||
fuzz26 prefix AGREE
|
||||
fuzz26 wrong DISAGREE
|
||||
fuzz27 direct AGREE
|
||||
fuzz27 generated AGREE
|
||||
fuzz27 prefix AGREE
|
||||
fuzz27 wrong DISAGREE
|
||||
fuzz28 direct AGREE
|
||||
fuzz28 generated AGREE
|
||||
fuzz28 prefix AGREE
|
||||
fuzz28 wrong DISAGREE
|
||||
fuzz29 direct AGREE
|
||||
fuzz29 generated AGREE
|
||||
fuzz29 prefix AGREE
|
||||
fuzz29 wrong DISAGREE
|
||||
fuzz2 direct AGREE
|
||||
fuzz2 generated AGREE
|
||||
fuzz2 prefix AGREE
|
||||
fuzz2 wrong DISAGREE
|
||||
fuzz30 direct AGREE
|
||||
fuzz30 generated AGREE
|
||||
fuzz30 prefix AGREE
|
||||
fuzz30 wrong DISAGREE
|
||||
fuzz31 direct AGREE
|
||||
fuzz31 generated AGREE
|
||||
fuzz31 prefix AGREE
|
||||
fuzz31 wrong DISAGREE
|
||||
fuzz3 direct AGREE
|
||||
fuzz3 generated AGREE
|
||||
fuzz3 prefix AGREE
|
||||
fuzz3 wrong DISAGREE
|
||||
fuzz4 direct AGREE
|
||||
fuzz4 generated AGREE
|
||||
fuzz4 prefix AGREE
|
||||
fuzz4 wrong DISAGREE
|
||||
fuzz5 direct AGREE
|
||||
fuzz5 generated AGREE
|
||||
fuzz5 prefix AGREE
|
||||
fuzz5 wrong DISAGREE
|
||||
fuzz6 direct AGREE
|
||||
fuzz6 generated AGREE
|
||||
fuzz6 prefix AGREE
|
||||
fuzz6 wrong DISAGREE
|
||||
fuzz7 direct AGREE
|
||||
fuzz7 generated AGREE
|
||||
fuzz7 prefix AGREE
|
||||
fuzz7 wrong DISAGREE
|
||||
fuzz8 direct AGREE
|
||||
fuzz8 generated AGREE
|
||||
fuzz8 prefix AGREE
|
||||
fuzz8 wrong DISAGREE
|
||||
fuzz9 direct AGREE
|
||||
fuzz9 generated AGREE
|
||||
fuzz9 prefix AGREE
|
||||
fuzz9 wrong DISAGREE
|
||||
|
|
@ -15,7 +15,8 @@ registry until the panel reads it; this lane writes no PASS. The status words in
|
|||
| The spec | `docs/spec/01-lottery-hash.md` on master bc6bfa75e: 1.0 (the frozen object), 1.6, 1.10, 1.12, 1.13.3 | the dataset policy digest in full, the epoch, day and era clocks |
|
||||
| The signing pair | `igneum-pow/tests/composition.rs` at class-v6 755c2dbcf | epoch seed af89be5d..., era edc4fa84..., day 20730, program id 0x2a1d6caab4c24564 |
|
||||
| The B1 lane's encoding pins (R15-05, a4490b2dfe9114a55, 10:2x UK) | unkeyed BLAKE2b-256, `lambda = 256`, one ASCII role byte per query kind, u64 LE integers, raw-label leaves, path bit `j` = bit `j - 1` of the leaf index (LSB at the root), no path sharing, the graph from `'G' || graph_seed || u64 v || u64 ctr` by rejection sampling (DRSample from ABH17 Algorithm 1) | adopted here whole; B1 owns the primitive and its fixtures |
|
||||
| Figures | `tools/mhpow/b2/b2_figures.py` (sha256 7b8664ea44b770c9f6af246898aa576f3f0a63e65e7bf50a0b278c5727a1ee8b) | output `figures.txt` (sha256 27bb414c8534a438fdeae98cba2d4b9ece9c21d0487aa872673b0da465d9702a), run on build-9 under `/srv/builds/b2/b2-run.pid`: `python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt` |
|
||||
| The B4 theory lane's answers (a46974623d72b032c) | `docs/analysis/mhpow/b4/requirements.md` (branch mhpow-b4 6d9c14596) and `docs/analysis/mhpow/b4/README.md` section 5b (build/master 80b127484) | the B-T rows of section 4 and the lottery rule of O-17 |
|
||||
| Figures | `tools/mhpow/b2/b2_figures.py` (sha256 742b64d9c2f3f8bad0524c9cdf38ac3aeff0c33bb14e000eb17b278053d79103) | output `figures.txt` (sha256 90e0f3932e2d915b7b1bcc958d5a2a74ccba55c2a3a37e71f53390b42bb7a022), run on build-9 under `/srv/builds/b2/b2-run.pid`: `python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt` |
|
||||
|
||||
## 1. What the paper proves, and what it does not
|
||||
|
||||
|
|
@ -96,7 +97,7 @@ The oracle and the domain separation:
|
|||
| Merkle node | `tau_x = H('M', chi || tau_x0 || tau_x1)`; leaves are the raw labels, node `w` at leaf index `w - 1`; root `tau = tau_empty`; a reveal is the label and `n` siblings | section 4.1, Appendix C, salt `chi` |
|
||||
| Challenge | `c_i = int_le(H('C', chi || u64 i || tau)) mod N`, `i = 1 .. k`; open node `c_i + 1` and each parent, each with its own path | `c_i = H(chi, i, tau) mod N` |
|
||||
| Graph | DRSample, indeg 2, its draws from `H('G', graph_seed || u64 v || u64 ctr)` by rejection sampling; `graph_seed` a 32-byte public consensus constant, never `chi` | Fact 8; section 1.2 (the graph fixed a priori) |
|
||||
| Lottery value | NONE in this draft (O-07) | the paper has none |
|
||||
| Lottery value | `W = int_le(H('W', chi || tau)) <= target`, the winner verified IN FULL (O-17, B4's rule; the naive spot-check-only forms FAIL, O-07) | the paper has none |
|
||||
|
||||
Every query is fixed width once the role and the node are known, which keeps Theorem 5's parse unique (the extractor reads the
|
||||
`h`-th parent at a fixed offset after `chi` and `v`). The role byte keeps the query families disjoint (B1's note: without it the challenge query `H(chi, i, tau)` has the shape of
|
||||
|
|
@ -127,30 +128,33 @@ parameter choice (B3, B4) fill them. They are not conformance vectors; the B1 la
|
|||
| O-14 | Rejected trials and cancellation: a trial in flight when the template changes | the instance binds the parent set, so a new block on the network stales every trial in flight; the honest trial takes `O(N)` sequential rounds (Definition 5, item 1) | not a soundness matter; it is a feasibility bound: `N x t_seq <= rho x T_block`, with `T_block` 1 s on the devnet (spec 1.12) and `rho` the stale fraction the chain accepts. The bound caps `N`, and a small `N` fits one instance in SRAM, which is the B5 question | BLOCKED B-N2 (the node lane: `T_block` and `rho` on devnet-4) and B3 (`t_seq` measured, never assumed) |
|
||||
| O-15 | The frozen class stays the chain's binding: the dataset policy 70a6c703 and the signing id 2a1d6caab4c24564 | the instance carries `dataset_policy` (all 32 bytes), `program_id`, `epoch_seed`, `epoch_start_daa`, `era_seed`, `day_index` and `state_root`; the verifier recomputes each from the chain and the header and rejects a mismatch, so no certificate carries across a class object, a policy or an epoch | by construction plus O-01, O-03. Two facts for the node lane: the policy digest sits outside the consensus digest until the class v6 floor is set (f0 manifest), so the instance is the only place a certificate binds it today; and the day rule differs between `bind.rs` (the interim `timestamp_ms / 86,400,000`) and spec 1.12 (DAA seconds) | ANSWERED by construction, conditional on B-N1 and B-N3 |
|
||||
| O-16 | The epoch-seed lead and the day-pack: no precomputation across trials | the labelling needs `chi`, which needs the template's parents; the 600 DAA-second epoch-seed lead and the day key (known before the day) give no label in advance. Static per-day work (the v6 dataset) stays amortisable by design; the instance removes it from the MHPoW part only | O-03 | ANSWERED |
|
||||
| O-17 | The lottery rule (B4-OB-LOT-1, this lane's row): B4's replacement for O-07, and the cost of a fake winner that passes the spot checks | trial id in `chi`; `W = H('W', chi || tau) <= target`; a winner is verified IN FULL (the verifier recomputes all `N` labels and the root, so `tau` is unique per `chi` and one draw costs one labelling); the `k` spot checks stay as the header pre-filter. The pre-filter does NOT price a fake: the prover keeps one honest labelling and re-rolls the red sink until `W` passes, about `(log2 N + 1) / p` calls a fake against `2N / p` for a real winner, and the fake passes the spot checks with `(1 - 1/N)^k`. Every validator it reaches then pays one full labelling (`2N` calls, `N` sequential steps) to reject it. An attacker with share `s` of the honest network's oracle calls makes `s x 2N / (log2 N + 1)` fakes per real block: 1.34 at `s = 10^-6`, 134 at `10^-4`, 13,400 at `10^-2` (`N = 2^24`, figures section 6 (a)). Per fake the attacker pays `(log2 N + 1) D / (2N)` of one validator's rejection cost (`D` labellings per block interval network-wide): 0.745 at `D = 10^6`, 74.5 at `10^8` (section 6 (b)), and every node the fake reaches pays it again | B4 README 5b says R1's theorem prices a spot-check-passing fake at the cmc bound. It does not: Theorem 7 is paid once per trace, and one trace yields fakes at the re-roll price (O-07, B1's fixture A6). The rule's soundness per draw is B4 Lemma C (NOT RUN) with AS15 per fully verified labelling | the rule ADOPTED as the draft binding (work version 1); the fake-winner budget is the open part: BLOCKED B-N4 and B4-OB-LOT-4 (B6) |
|
||||
|
||||
## 4. The BLOCKED questions, with their owners
|
||||
|
||||
| Id | Owner | The exact question |
|
||||
|---|---|---|
|
||||
| B-T1 | B4 theory lane (to be named) | For DRSample sampled from a fixed public seed at `N = 2^20` to `2^24`, what is the probability that the sampled graph is not `(c3 N / log N, c4 N)`-depth-robust, with the constants written out? Is a per-era re-seed from the era seed admissible, given that a party able to bias the era seed could search for a weak graph? |
|
||||
| B-T2 | B4 | The values of `c3` and `c4` (Fact 8, from ABH17 or ABP17) for the sampled DRSample at the chosen `N`, proved, so that Corollary 3's bound and `k = 2 lambda log N / c3` become numbers. Without them every certificate size and every lower bound in this README is a sensitivity row. |
|
||||
| B-T3 | B4 | The lottery. Give a lottery value `W` (or prove none exists) such that the expected number of distinct accepted pairs (`chi`, certificate) with `W` under the target, output by an adversary of cumulative memory `C`, is at most `C` divided by a constant fraction of Corollary 3's bound, with sampled verification of polylog cost. Known: any `W` that depends on labels the verifier samples can be re-rolled through an unchallenged node at the cost of that node's descendants (O-07 (a)); any `W` of `chi` alone is screened for free (O-07 (b)). Candidates for the panel: a succinct proof of the full labelling (a unique output, so Alwen and Serbinenko's bound per trial applies, at a prover cost the paper's own section 1 calls non-egalitarian); or a construction that is not MTP. |
|
||||
| B-T4 | B4 | The adaptive-input version of Corollary 3: the adversary chooses `chi` among at most `q` candidates after querying `H`. State the loss in the bad-event sum. |
|
||||
| B-T5 | B4 | The multi-instance version: producing accepted certificates for `m` distinct inputs costs at least `m (lambda/4)(c3 c4 / 2) N^2 / log N` except with what probability, and how the `q` and `t` terms scale with `m`. |
|
||||
| B-T6 | B4 | The label width `lambda` for an adversary of `q = 2^64` to `2^96` queries: either `lambda >= 8 log2 q + 4` under Lemma 3 as stated (516 to 772 bits, so an XOF in place of BLAKE2b's 512-bit maximum), or a tighter statement of Theorem 6 with the charge `lambda - 2 log2 q - log2 indeg` per pebble at `lambda = 256`. |
|
||||
| B-T7 | B4 | Confirm that no step in Theorems 4 to 7 or Lemmas 2 to 4 uses a coincidence between a label query and a Merkle or challenge query that the role byte would remove (the role byte only splits the domain; the check is that the extractor's hint and parse still hold). |
|
||||
| B-T8 | B4 with the adversary lane | The translation from cumulative memory to energy and bandwidth (the plan's R2, R3), including the full-SRAM design at the `N` that O-14 allows. |
|
||||
| B-T1 | B4 theory lane a46974623d72b032c | STILL BLOCKED (B4-B01: ABH17 not fetched by B4; B1 holds the archived ABH17, eprint 2017/443, sha256 f8e08d36...). For DRSample sampled from a fixed public seed at `N = 2^20` to `2^24`, what is the probability that the sampled graph is not `(c3 N / log N, c4 N)`-depth-robust, with the constants written out? Is a per-era re-seed from the era seed admissible, given that a party able to bias the era seed could search for a weak graph? |
|
||||
| B-T2 | B4 | STILL BLOCKED (B4-B03). The values of `c3` and `c4` (Fact 8, from ABH17 or ABP17) for the sampled DRSample at the chosen `N`, proved, so that Corollary 3's bound and `k = 2 lambda log N / c3` become numbers. Without them every certificate size and every lower bound in this README is a sensitivity row. |
|
||||
| B-T3 | B4 | ANSWERED IN SHAPE by B4 Lemma C (NOT RUN): no `W` with polylog sampled verification meets the bound inside MTP; the replacement is full verification of winners, adopted here as O-17, whose fake-winner budget stays open. The lottery. Give a lottery value `W` (or prove none exists) such that the expected number of distinct accepted pairs (`chi`, certificate) with `W` under the target, output by an adversary of cumulative memory `C`, is at most `C` divided by a constant fraction of Corollary 3's bound, with sampled verification of polylog cost. Known: any `W` that depends on labels the verifier samples can be re-rolled through an unchallenged node at the cost of that node's descendants (O-07 (a)); any `W` of `chi` alone is screened for free (O-07 (b)). Candidates for the panel: a succinct proof of the full labelling (a unique output, so Alwen and Serbinenko's bound per trial applies, at a prover cost the paper's own section 1 calls non-egalitarian); or a construction that is not MTP. |
|
||||
| B-T4 | B4 | ANSWERED AS A LOSS by B4 (NOT RUN): MISCOLOR becomes `q N 2^-lambda`; the other bad events are already unions over the trace. The adaptive-input version of Corollary 3: the adversary chooses `chi` among at most `q` candidates after querying `H`. State the loss in the bad-event sum. |
|
||||
| B-T5 | B4 | STILL BLOCKED (B4-OB-LOT-3; the union-graph route, MISCOLOR `J N 2^-lambda`, proof not written). The multi-instance version: producing accepted certificates for `m` distinct inputs costs at least `m (lambda/4)(c3 c4 / 2) N^2 / log N` except with what probability, and how the `q` and `t` terms scale with `m`. |
|
||||
| B-T6 | B4 | ANSWERED AS A CONSTRAINT by B4: `w >= 8 log2 q + 4`, or R2 Theorem 3.3's `w > 20 log2 q` (1,280 bits at `q = 2^64`); labels of 1 KiB or more meet both, through an XOF or R16's permutation. The instance's `label_bytes` field carries it; `chi` and every fixture move with it. The label width `lambda` for an adversary of `q = 2^64` to `2^96` queries: either `lambda >= 8 log2 q + 4` under Lemma 3 as stated (516 to 772 bits, so an XOF in place of BLAKE2b's 512-bit maximum), or a tighter statement of Theorem 6 with the charge `lambda - 2 log2 q - log2 indeg` per pebble at `lambda = 256`. |
|
||||
| B-T7 | B4 | ANSWERED BY READING by B4 (not a proof audit): the role byte only shifts offsets, and Theorem 4's Merkle trace needs exactly that form separation. Confirm that no step in Theorems 4 to 7 or Lemmas 2 to 4 uses a coincidence between a label query and a Merkle or challenge query that the role byte would remove (the role byte only splits the domain; the check is that the extractor's hint and parse still hold). |
|
||||
| B-T8 | B4 with the adversary lane | ANSWERED by B4 README sections 5, 7, 8 and its Q5: the window `log2 N x M_SRAM / C <= N b <= b rho / t_seq` may be empty for DRSample. The translation from cumulative memory to energy and bandwidth (the plan's R2, R3), including the full-SRAM design at the `N` that O-14 allows. |
|
||||
| B-N1 | node lane a283f5f0d364ceef0 | Which day rule is live on devnet-4 (`bind.rs`'s timestamp day or spec 1.12's DAA day), and the rule the verifier uses to recompute `epoch_seed`, `epoch_start_daa`, `era_seed`, `program_id` and the policy digest from a header and the chain. |
|
||||
| B-N2 | node lane | The block interval on devnet-4, the timestamp acceptance window (past median and future bound), and the stale fraction the chain accepts, so O-14's bound on `N x t_seq` is a number. |
|
||||
| B-N4 | node lane with B6 | O-17's fake-winner budget at the network's scale: does a block that fails full verification cost its sender (peer score, ban, a relay rule of full verification before forwarding), and what full verifications per second per node can the chain absorb before the 1.34-fakes-per-block attacker at `s = 10^-6` (`N = 2^24`) stalls validation? |
|
||||
| B-N3 | node lane | The 32 bytes of the state stream root the class v6 dataset is keyed on for the signing pair (epoch af89be5d, era edc4fa84, day 20730), and whether that root is in the header's past by the epoch boundary. |
|
||||
|
||||
## 5. What this means for Track B
|
||||
|
||||
1. The input binding is complete for reuse: no certificate carries across a template, a trial, an epoch, a day, an era, a network
|
||||
or a class object (O-01 to O-04, O-15, O-16).
|
||||
2. The economic binding is not: the reference construction has no lottery, and the two direct ways to add one either buy about a
|
||||
million draws per labelling at `N = 2^24` or screen trials for free (O-07). Until B-T3 is answered, an MTP certificate per
|
||||
block adds memory work per block, never per lottery trial, and cannot move the 1.5x ratio.
|
||||
2. The economic binding is not in the paper: the reference construction has no lottery, and the two direct ways to add one either
|
||||
buy about a million draws per labelling at `N = 2^24` or screen trials for free (O-07). B4's rule (O-17: full verification of
|
||||
winners) restores one labelling per draw, at a price: a fake winner costs about a millionth of a real one and costs every
|
||||
validator a full labelling, so the rule is adopted as the draft and its denial-of-service budget is the open row (B-N4).
|
||||
3. Binding the template forces each trial to finish inside a fraction of the block interval (O-14), which caps `N` and pushes the
|
||||
instance toward a size that fits in SRAM. B3 and B5 own that collision; it is recorded here because the binding causes it.
|
||||
4. Even granted a lottery, the proved bound sits a factor `4 log N / (c3 c4)` under the honest prover's cumulative memory with
|
||||
|
|
|
|||
|
|
@ -94,3 +94,25 @@ log2_N k honest_calls_per_trial reroll_calls_per_draw amortisation pass_probabil
|
|||
20 9000 2097152 21 9.99e+04 0.991454
|
||||
24 2000 33554432 25 1.34e+06 0.999881
|
||||
24 9000 33554432 25 1.34e+06 0.999464
|
||||
|
||||
== 6. O-17: the fake-winner budget under B4's rule (trial id in chi, W = H(lot, chi, tau), winners verified in full,
|
||||
the k spot checks as the header pre-filter). A fake winner keeps ONE honest labelling and re-rolls the red sink until
|
||||
W <= target: about (log2 N + 1) / p calls per fake once the labelling exists; it passes the spot checks with (1 - 1/N)^k;
|
||||
every validator it reaches recomputes the labelling in full (2N calls, N sequential label steps) before rejecting it.
|
||||
A real winner costs 2N / p calls. p = 1 / D, D = labellings per block interval network-wide.
|
||||
(a) fakes per real block for an attacker holding share s of the honest network's oracle calls: s * 2N / (log2 N + 1)
|
||||
log2_N share fakes_per_real_block
|
||||
20 1e-06 0.0999
|
||||
20 0.0001 9.99
|
||||
20 0.01 999
|
||||
24 1e-06 1.34
|
||||
24 0.0001 134
|
||||
24 0.01 1.34e+04
|
||||
(b) attacker calls per fake / one validator's calls to reject it: (log2 N + 1) D / (2N)
|
||||
log2_N D attacker_over_validator
|
||||
20 10000 0.1
|
||||
20 1e+06 10
|
||||
20 1e+08 1e+03
|
||||
24 10000 0.00745
|
||||
24 1e+06 0.745
|
||||
24 1e+08 74.5
|
||||
|
|
|
|||
|
|
@ -14,14 +14,14 @@
|
|||
"status": "NOT RUN",
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules and B-T3 the open question. POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's.",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules (B1's fixture A6 executes the first); O-17 adopts B4's full-verification rule with its fake-winner budget open (B-N4). POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's.",
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"in_progress": true
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"model:mhpow-b2-binding": {
|
||||
"command": "python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt (a build box under a pid file; byte-identical output, sha256 27bb414c...)",
|
||||
"command": "python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt (a build box under a pid file; byte-identical output, sha256 90e0f393...)",
|
||||
"box_class": "build box, CPU only (build-9)",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@ the certificate root re-rolls for log2 N + 1 hashes per draw after one labelling
|
|||
must cost a fresh labelling: trial id in chi, v = H(tag_lot, chi, tau), winners verified in full, spot checks kept as the
|
||||
pre-filter. Owners by row: B4-OB-LOT (B4), -1 (B2), -2 (B1), -3 (B4), -4 (B2 with B6).
|
||||
|
||||
**THE PIVOT (10:4x UK).** Track B now builds its own construction; the one-page requirements it must meet (Q1 lottery, Q2 bandwidth-bound honest path, Q3 instance above SRAM, Q4 losses under 2x, Q5 the template cap) and the answers to B2's B-T1 to B-T8 are in requirements.md beside this README.
|
||||
|
||||
**The result in four lines.**
|
||||
|
||||
1. The 2025 theorem (Blocki and Smearsoll) proves, in the parallel random oracle model, that any prover whose MTP/DRSample
|
||||
|
|
|
|||
53
docs/analysis/mhpow/b4/requirements.md
Normal file
53
docs/analysis/mhpow/b4/requirements.md
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
# B4: what a Track B construction must meet to be worth a proof (one page)
|
||||
|
||||
9 October 2026, 11:xx UK, for the B1 (a4490b2dfe9114a55) and B3 (a8e608abf1567ff87) candidates due 11:45. NOT RUN: requirements,
|
||||
not results. The reproduction of R1 (Blocki and Smearsoll, eprint 2025/1456) stays the control; its numbers are BOUND (L) rows in
|
||||
README.md beside this page. Inputs by row: B2's O-07 and B-T1 to B-T8 (docs/analysis/mhpow/b2/README.md), X7's s rows
|
||||
(docs/analysis/class-v6/1p5x/x7/README.md), and B3's and B5's findings as the coordinator relayed them at 10:4x UK (not yet landed).
|
||||
|
||||
## The four requirements
|
||||
|
||||
| # | requirement | the number to meet | why (source) | what fails it |
|
||||
|---|---|---|---|---|
|
||||
| Q1 | Every lottery draw costs a fresh labelling (phi = 1), or a per-draw work bound is stated and proved | draws per labelling = 1. Today: 2N / (log2 N + 1), about 1.3 million at N = 2^24 (B2 O-07) | B4 Lemma C (README 5b): any value over an MTP certificate re-rolls through the sink for log2 N + 1 calls, accepted with (1 - 1/N)^k | a lottery over tau with spot-check verification only; a lottery over chi alone (screened for one hash) |
|
||||
| Q2 | The honest path is bandwidth-bound on GDDR7 and fills the GPU by memory traffic, not by instance count | (a) GPU wall joules per byte moved, hashing included: at most 1.5 x the opponent's per byte: 99 pJ/B against a GDDR7 board (66), 57 against HBM3 (38), 33 against near-memory (22) (X7 s rows, 32 B sectors). (b) Access unit at least one DRAM row: X7 shows the 32 B random read at 8.7 nJ knee on the 5090 (272 pJ/B, s = 4.1 to 12.5), so 32 B dependent reads are excluded. (c) Hash input bytes per byte moved rho <= 1, and the hash's GPU energy per byte well under its memory energy per byte | R3 section 4: advantage >= (c_b,GPU + rho c_r,GPU) / (c_b,ASIC + rho c_r,ASIC), with c_r,ASIC near 0; B3: one sequential chain per instance leaves the 5090 equal to 27 to 44 CPU cores at 32 MiB | narrow labels (32 B); one chain per instance with no intra-label parallelism; a label hash costing more per byte than the memory |
|
||||
| Q3 | Instance state exceeds the largest SRAM in the declared technology set, for the graph's best low-space schedule | DRSample: S_instance >= log2 N x M_SRAM / C (it has a pebbling in C N / log2 N labels and time N: README sec. 8; 186 MiB x C for a 4 GiB state). A graph with no o(N)-space, O(N)-time schedule: S_instance >= M_SRAM x a stated constant | R2 section 5.4 (no transfer bound above m = C N / log N); B5: the full-SRAM opponent at 32 MiB pays 7.4 to 7.6 mJ per instance, 92 percent label-hash core ops, i.e. it is hash-bound and an ASIC wins hashing | DRSample at any instance size below log2 N x M_SRAM; M_SRAM undeclared (the panel declares it: row R-Q3) |
|
||||
| Q4 | The certificate's composed losses stay under 2x | bound >= E_honest / 2 in joules, with the full-SRAM and near-memory opponents inside it | today: the generic route certifies at most 0.151 of honest (0.213 for a fully verified winner); the red-blue route loses at least 341x at rho = 0.25 (README 7) | any route through R2 Theorem 4.5 (the square root is inherent); R2's published constants |
|
||||
|
||||
## Q4 in detail: the lemma that has to change for each loss
|
||||
|
||||
| loss (README 7) | published factor | what must change | candidate |
|
||||
|---|---|---|---|
|
||||
| L1 extraction hint | 4x | label width w >= 1 KiB: theta / w = 0.976 at q = 2^64 (B4 restatement of R1 Lemma 3, params.txt sec. 2) | wide labels (Q2 wants them anyway); the RO for wide labels from a permutation per R16 (eps/40, cache 20 delta m: a new loss to tighten) |
|
||||
| L2 red nodes | 2x | beta = 0 for winners | full verification of winning blocks (Q1's fix does this) |
|
||||
| L3 depth-robustness | c1 c2 / log2 N (4 log N / (c3 c4) in B2's form) | a graph with e + d <= (1 - eps) N (eps-extreme depth-robust, R1 sec. 6 citing ABP18, in-degree O(log N)): cc >= e d up to (1 - eps)^2 N^2 / 4 against the honest N^2 / 2 | ABP18's graphs; their in-degree O(log N) raises bytes per label hashed (Q2 (c)) |
|
||||
| L5 generic cmc to joules | sqrt(c_b c_r) / (c_b + c_r) and a square root | do not use it; prove energy directly | none: inherent to R2 Theorem 4.5 |
|
||||
| L6 energy to red-blue | eps/16, cache 9m | R2 Theorem 3.3's interval partition (3m and 4m QueryFirst sets, Lemma 3.9's 2^(-2mw/5)) re-proved with constant >= 1/2 and cache inflation <= 2m | new lemma (B4) |
|
||||
| L7 the graph's red-blue cost | (1 - rho)/16 of N c_b, nothing above C N / log N | a graph whose red-blue cost is >= (1/2) N c_b for every cache up to M_SRAM | the bit-reversal shape of R3 Theorem 2 is near-tight in the pebbling model ((c_b + c_r) n (1 - ...) for n > 2 m c_b / c_r) but has low cc; a graph with both is the design target |
|
||||
| L11 amortisation | open | the union-graph form of R1 and R2 for J distinct chi (B-T5) | B4 |
|
||||
|
||||
**Q5 (a cap, from B2's B-T8).** One labelling per draw must finish inside the template's life: N t_seq <= rho x 1 s, so the instance is at most b rho / t_seq bytes (b = bytes per label, t_seq = one dependent label step). Q3 sets the floor; the construction must show the window between them is not empty at the declared M_SRAM. Wide labels (Q2) widen it: the cap grows with b, the floor does not.
|
||||
|
||||
## B2's B-T rows, answered or BLOCKED
|
||||
|
||||
| row | answer |
|
||||
|---|---|
|
||||
| B-T1 graph sampling failure | BLOCKED: needs ABH17's tail bound (eprint 2017/443 not fetched, README B4-B01). Q3 and L3 point away from sampled DRSample in any case. Question: the probability a seed-sampled DRSample at N = 2^20 to 2^24 is not (c3 N/log N, c4 N)-depth-robust, and whether an era re-seed lets a seed-biasing party search for a weak graph. |
|
||||
| B-T2 c3, c4 | BLOCKED (README B4-B03): R1 Fact 8 is existential; ABH17 not fetched. Every DRSample number stays a sensitivity row. |
|
||||
| B-T3 the lottery | ANSWERED in shape (README 5b, B4 Lemma C, NOT RUN): no W with polylog sampled verification meets the requested bound inside MTP; the replacement is full verification of winners (unique output, AS15 per trial) with spot checks as the DoS pre-filter. That is Q1. B1 executed the re-roll as fixture A6 (attacks-n10-k16.json 805035eb on mhpow-b1 e9f94df6a: 193 to 200 of 200 re-rolls accepted per labelling), a witness for Lemma C. |
|
||||
| B-T4 adaptive chi | ANSWERED as a loss (B4 restatement, NOT RUN): Collision, BadOrder, IE and LuckyQuery are already unions over the whole trace; MisColor becomes q N 2^-lambda (a union over at most q candidate chi). |
|
||||
| B-T5 multi-instance | BLOCKED (README B4-OB-LOT-3): the union graph of J copies, cc additive over components, the extractor on the union; the terms that scale with J are MisColor (J N 2^-lambda) and the per-copy LuckyQuery. Proof not written. |
|
||||
| B-T6 lambda | ANSWERED as a constraint: w >= 8 log2 q + 4 under R1 Lemma 3 as stated (516 to 772 bits for q = 2^64 to 2^96), or the general charge w - 2 log2 q - 1 - s per pebble; R2 Theorem 3.3 needs w > 20 log2 q (1,280 bits at q = 2^64). Q2's labels of 1 KiB or more meet both; BLAKE2b's 512-bit cap means an XOF or a permutation (R16). |
|
||||
| B-T7 role bytes | ANSWERED by reading (not a proof audit): the extractor locates labels by query index and offset (R1 Theorem 5's hint), so a fixed role prefix only shifts offsets; Lemmas 7, 8, 10 hold for any query form; the Merkle trace of Theorem 4 needs the Merkle query form to be distinct from the label form, which the role byte guarantees. No step uses a cross-role coincidence. |
|
||||
| B-T8 memory-time to energy | ANSWERED: README sections 5, 7, 8 (generic 0.151, red-blue >= 341x, the transfer term void above C N / log N). B2's template cap N t_seq <= rho x 1 s bounds the instance from above (Q5); with Q3's floor the window is log2 N x M_SRAM / C <= N b <= b rho / t_seq, and for DRSample it may be empty. |
|
||||
|
||||
## Rows this page opens
|
||||
|
||||
| row | owner | question |
|
||||
|---|---|---|
|
||||
| R-Q2 | B3 with X7 | The 5090's wall pJ per byte moved at row-sized sequential access with the label hash folded in, at stock and at the knee. If it exceeds 33 pJ/B, no construction certifies 1.5x against near-memory by R3 section 4's limit, before any proof loss. This is the kill test and the first row to take. |
|
||||
| R-Q3 | the panel | M_SRAM: the largest on-die or stacked SRAM in the declared technology set (plan section 8). Q3's instance size follows from it. |
|
||||
| R-Q4 | B4 | The two lemmas of Q4 (L6 at constant >= 1/2, L7 for a graph with both high cc and near-tight red-blue cost), or a proof that 2x is out of reach for them. |
|
||||
|
||||
The quantum claim stays classical: every bound here is in the classical parallel random oracle model and no quantum speedup is
|
||||
claimed or estimated.
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -483,6 +483,65 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover
|
|||
- Cases:
|
||||
- TV-02 Reproduce complete supply accounting: partial: scheduled issuance on a straight chain and its reorg, two independent implementations EQUAL to the integer on devnet-4, mainnet and the TV-01 spec; paid, burned, locked, outstanding, DAG reds, the EVM ledger and duplicate records open; the independent panel has not read it
|
||||
|
||||
### model:mhpow-b1-reference
|
||||
|
||||
- Command: `tools/mhpow/b1/run-b1.sh <out_dir> all (a build box under its pid file; kat, attack and k-table files byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS)`
|
||||
- Box class: build box, CPU only (build-6)
|
||||
- Fixtures: tools/mhpow/b1/fixtures/
|
||||
- Cases:
|
||||
- POW-05 Prevent amortised cheap winning attempts: partial: the published primitive's attack fixtures only; the lottery binding and the composed accepted-proof theorem are B2/B4's
|
||||
- POW-06 Bound verifier work and malformed-input cost: partial: verifier refusals and op counts in CPython; no compiled verifier, no admitted-rate timing
|
||||
|
||||
### theory:r15-05-track-b
|
||||
|
||||
- Command: `the Track B cryptography read: docs/analysis/mhpow/b1 (the exact CPU reference of the MTP framework over DRSample, its verifier and the six malicious provers) by tools/mhpow/b1/run-b1.sh <out> all on a build box under a pid file, outputs byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS`
|
||||
- Box class: build box, CPU only
|
||||
- Fixtures: tools/mhpow/b1/fixtures/
|
||||
- Cases:
|
||||
- R15-05 R15-05: Cryptography: partial: the published primitive's reference, attacks and verifier refusals; the lottery binding (B2), the composed theorem (B4) and the panel's reading open
|
||||
|
||||
### class:int8
|
||||
|
||||
- Command: `the int8-dominated research class: cut behind the research flag by the research lane at int8-50, int8-75, int8-90 and arx-16, arx-32 (igneum-pow export with the class string, on a build box); the hash lane's card rows in the P04 form (tools/1p5x/x1/gpu-pairs.sh, gpu-rows.py); the adversary lane's chip rows (tools/1p5x/x5/sweep.py, tools/1p5x/x8/mac.py); the census instruments (igneum-pow addrsite, x1cache)`
|
||||
- Box class: build box for the cut and the census; rented pods for the card rows; a build box for the chip model
|
||||
- Fixtures: F0
|
||||
- Cases:
|
||||
- R15-03 R15-03: GPU + memory analysis: partial: the held-out cache curves of each weight against the frozen control; the layer-8-off control is X1's row
|
||||
- R15-04 R15-04: GPU systems: partial: byte agreement and accepted-work savings of each weight's fold; X2 to X4's rows carry the rest
|
||||
|
||||
### model:x7-memory-route
|
||||
|
||||
- Command: `the X7 memory-route read: docs/analysis/class-v6/1p5x/x7 (the chip model's s on GDDR7, HBM3 and near-memory by tools/1p5x/x5/sweep.py on a build box under a pid file) against the hash lane's read-only twin row on a rented card at stock (the frozen object and its read-only twin, nvidia-smi beside it)`
|
||||
- Box class: a build box for the model; a rented card for the twin row
|
||||
- Fixtures: F0
|
||||
- Cases:
|
||||
- R15-02 R15-02: GPU + hardware: partial: the memory route's f and s only; the component power and traffic model and its sensitivity are X0's and X5's rows
|
||||
|
||||
### model:mhpow-b2-binding
|
||||
|
||||
- Command: `python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt (a build box under a pid file; byte-identical output, sha256 27bb414c...)`
|
||||
- Box class: build box, CPU only (build-9)
|
||||
- Fixtures: none
|
||||
- Cases:
|
||||
- POW-05 Prevent amortised cheap winning attempts: partial: the binding obligations for the Track B work unit only; the lottery binding is BLOCKED (B-T3) and the multi-instance bound BLOCKED (B-T5)
|
||||
- POW-06 Bound verifier work and malformed-input cost: partial: certificate size as a formula; no verifier timing, no malformed-input cost
|
||||
|
||||
### theory:mhpow-b4
|
||||
|
||||
- Command: `python3 tools/mhpow/b4/params.py > docs/analysis/mhpow/b4/params.txt (a build box under a pid file; the composed accepted-certificate energy statement's constants from the published papers R1 to R4 and R16; byte-identical output)`
|
||||
- Box class: build box, CPU only
|
||||
- Fixtures: none
|
||||
- Cases:
|
||||
- R15-07 R15-07: Cryptography + hardware: partial: the composed theorem's statement and the losses on the published constants; terms 2 and 3's amortisation open theorems; L BLOCKED; the panel has not read it
|
||||
|
||||
### theory:r15-07-track-b
|
||||
|
||||
- Command: `the Track B composition read: docs/analysis/mhpow/b2 (the binding obligations O-01 to O-16, figures by tools/mhpow/b2/b2_figures.py) and docs/analysis/mhpow/b4 (the composed theorem and its constants by tools/mhpow/b4/params.py), on a build box under a pid file`
|
||||
- Box class: build box, CPU only
|
||||
- Fixtures: none
|
||||
- Cases:
|
||||
- R15-07 R15-07: Cryptography + hardware: partial: the statement, the obligations and the losses on published constants; the proof of terms 2 and 3, the amortisation and the panel's reading open
|
||||
|
||||
## Automated cases with no harness in the matrix (NOT RUN, the reason)
|
||||
|
||||
- GOV-02 Approve thresholds before results: the approval is recorded in the registry's approval field; the automated half (thresholds frozen before any run_status) is the gate rule landing by 21:00
|
||||
|
|
@ -491,7 +550,6 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover
|
|||
- GPU-04 Find the memory-clock operating ladder: the memory-clock ladder has no harness tonight: the project's own rig mines nothing under the the earlier devnet off order
|
||||
- GPU-06 Measure accepted work under ordinary connectivity: accepted work under ordinary connectivity needs the fault network F4
|
||||
- GPU-07 Survive sustained thermal and power operation: the sustained thermal and power soak has no harness tonight: the project's own rig mines nothing under the the earlier devnet off order
|
||||
- POW-05 Prevent amortised cheap winning attempts: amortised cheap winning attempts are the attack lanes' grind and era harnesses (tools/attack/f7-era, f9-grind), not in the release matrix; their rows come from those lanes
|
||||
- ROT-03 Test miner-voted bring-forward governance: miner-voted bring-forward needs a vote harness on the fault network F4
|
||||
- ROT-04 Resist seed selection and faster evaluators: seed-selection resistance is the census harness (the class v6 invention lane), not yet in the matrix
|
||||
- EVM-01 Match the selected EVM semantics: no EVM conformance-vector harness is mapped tonight; the exec suite does not run the reference test vectors
|
||||
|
|
@ -655,16 +713,11 @@ Rule: a case maps to a cell only where the cell's tests visibly answer it; cover
|
|||
- TV-31 Public-claim and activity review: TV-31 (token value gate, scope CORE): no gate executed; the harness is the owner role's (Qualified counsel); a supplemental layer, never counted as independent evidence; not yet named in the map
|
||||
- TV-32 Observed leadership, not a roadmap certificate: TV-32 (token value gate, scope LEADERSHIP CLAIM): no gate executed; the harness is the owner role's (Independent acceptance panel); a supplemental layer, never counted as independent evidence; not yet named in the map
|
||||
- R15-01 R15-01: Release + measurement: R15-01 (1.5x programme package): no package executed; the harness is the lane's (X0); its batch names the case when it lands; not yet named in the map
|
||||
- R15-02 R15-02: GPU + hardware: R15-02 (1.5x programme package): no package executed; the harness is the lane's (X0, X5); its batch names the case when it lands; not yet named in the map
|
||||
- R15-03 R15-03: GPU + memory analysis: R15-03 (1.5x programme package): no package executed; the harness is the lane's (X1); its batch names the case when it lands; not yet named in the map
|
||||
- R15-04 R15-04: GPU systems: R15-04 (1.5x programme package): no package executed; the harness is the lane's (X2, X3, X4); its batch names the case when it lands; not yet named in the map
|
||||
- R15-05 R15-05: Cryptography: R15-05 (1.5x programme package): no package executed; the harness is the lane's (B1); its batch names the case when it lands; not yet named in the map
|
||||
- R15-06 R15-06: GPU + cryptography: R15-06 (1.5x programme package): no package executed; the harness is the lane's (B3); its batch names the case when it lands; not yet named in the map
|
||||
- R15-07 R15-07: Cryptography + hardware: R15-07 (1.5x programme package): no package executed; the harness is the lane's (B2, B4); its batch names the case when it lands; not yet named in the map
|
||||
- R15-08 R15-08: Independent ASIC team: R15-08 (1.5x programme package): no package executed; the harness is the lane's (X5, B5); its batch names the case when it lands; not yet named in the map
|
||||
- R15-09 R15-09: Measurement + economics: R15-09 (1.5x programme package): no package executed; the harness is the lane's (X6); its batch names the case when it lands; not yet named in the map
|
||||
- R15-10 R15-10: Protocol/security: R15-10 (1.5x programme package): no package executed; the harness is the lane's (B6); its batch names the case when it lands; not yet named in the map
|
||||
|
||||
## Count
|
||||
|
||||
213 automated cases: 92 mapped to a cell, 179 NOT RUN with a reason.
|
||||
213 automated cases: 98 mapped to a cell, 173 NOT RUN with a reason.
|
||||
|
|
|
|||
|
|
@ -1420,32 +1420,31 @@
|
|||
"manual_page": 24,
|
||||
"owner_lane": "hash lane (a690540514aa453d7)",
|
||||
"run_status": "NOT RUN",
|
||||
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|
||||
"run_id": "same-work-20261008-01",
|
||||
"updated": "2026-10-09T08:57:42.332Z",
|
||||
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|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"updated": "2026-10-09T10:12:03.744Z",
|
||||
"evidence_record": {
|
||||
"requirement_id": "POW-01",
|
||||
"decision": "NOT RUN",
|
||||
"method": "GPU",
|
||||
"cell": "harness:p01-vectors",
|
||||
"manifest_sha": "c30ab32c",
|
||||
"run_id": "same-work-20261008-01",
|
||||
"evidence": "build-1:/srv/artefacts/tas/same-work-20261008-01/job-context.json; build-1:/srv/artefacts/tas/same-work-20261008-01/references/ref-D.txt; build-1:/srv/artefacts/tas/same-work-20261008-01/references/ref-D1.txt; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-5090-1.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-5090-2.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-5090-3.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-4090-1.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-4090-2.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-4090-3.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-3090-1.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-3090-2.json; build-1:/srv/artefacts/tas/same-work-20261008-01/cuda-3090-3.json; build-1:/srv/artefacts/tas/same-work-20261008-01/opencl-rx7600-take1.report.txt; build-1:/srv/artefacts/tas/same-work-20261008-01/opencl-rx7600.report.txt; build-1:/srv/artefacts/tas/same-work-20261008-01/metal-1.json; build-1:/srv/artefacts/tas/same-work-20261008-01/metal-2.json; build-1:/srv/artefacts/tas/same-work-20261008-01/metal-3.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-5090-hl-v5-win.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-4090-hl-v5-win.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-3090-hl-v5-win.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-5090-hl-v6-all.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-4090-hl-v6-all.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-3090-hl-v6-all.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-5090-hl-v6-foldrw.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-4090-hl-v6-foldrw.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-3090-hl-v6-foldrw.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-5090-hl-v6-all-nowin.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-4090-hl-v6-all-nowin.json; build-1:/srv/artefacts/p01/p01-20261008-01/cuda-3090-hl-v6-all-nowin.json",
|
||||
"in_progress": false,
|
||||
"coverage": "the million-vector campaign per backend per pack, bit-for-bit; PASS only when every supported backend reads a million vectors with zero disagreement; the malformed-input half is harness:parser-malformed",
|
||||
"cell": "rows:mhpow-b3-gpu-feasibility",
|
||||
"manifest_sha": "bc6bfa75e",
|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b3/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the Track B research candidate's CUDA backend against an independent CPU reference (B1) only; nothing about the shipped v6 evaluator",
|
||||
"release_identity": {
|
||||
"commit": "c30ab32c; the CPU reference class-v6 1a938abe4; the CUDA reader the kit's gen 6 worker 804a6f7f",
|
||||
"commit": "bc6bfa75e",
|
||||
"lockfile": "",
|
||||
"binary": "igneum-pow sha256 0d3f3fca...; igneum-worker-cuda sha256 804a6f7f...",
|
||||
"network_object": "the frozen class v6 object: pack hl-v6-all (tgz sha256 9131431015e102f4..., re-exported byte for byte from class-v6 1a938abe4 on build-4 at 21:44 UK, every file's sha256 equal), id 0x4de7b836cc40a4ea, epoch seed edc4fa84... (the genesis seeds) over the node1 state stream",
|
||||
"activation": "none (a re-check of hashes against one job context, no chain state changes)",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "POW-01's CUDA half across a dataset-day switch on the frozen object: CUDA against the CPU reference bit for bit on three ranges with the day switch at nonce 1572864. NOT same-work evidence: the node engine refuses this seed/stream pair (IgneumEngine::epoch_for's class v5 check wants the stream's block af89be5d... to equal the epoch seed edc4fa84...), so the node and pool readers cannot read it; the coordinator's ruling 22:0x UK keeps it as the CUDA and CPU-only row",
|
||||
"claim_impact": "none: no public figure moves; the Track B candidate is not proposed for activation",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T08:57:42.332Z",
|
||||
"note": "the same-work row on the frozen object is complete: CPU reference, CUDA 5090/4090/3090 x3, OpenCL x3, Metal x3, every nonce equal across the day switch; POW-01 itself is decided by the hash lane's P01 corpus and review, not by this row; the P01 CUDA campaign's evidence is carried here so it stays on the case | Context 01 at build-1:/srv/artefacts/tas/same-work-20261008-01/job-context.json (sha256 d2540e02...). CPU reference: igneum-pow hash-bound (class-v6 1a938abe4, binary 0d3f3fca...) on build-4, 21:46 to 21:55 UK, ref-D c49fed11... over [0, 1572864), ref-D1 5ae1220d... over [1572864, 3145728); ref-D's first million lines equal the hash lane's P01 reference /srv/artefacts/packs/p01-vectors/hl-v6-all.txt byte for byte. The node1 state stream (block af89be5d...) was written on build-4 at 15:34 UK, before the 20:00 UK split; the cell carries the island label by main's 22:2x UK rule. CUDA: the 5090 PASS on all three phases (the gen 6 worker 804a6f7f, the driver at c8b65a26 or later; 23:16 to 23:20 UK: cuda-5090-1.json 1b36fb8a..., cuda-5090-2.json 70200bff... with the day switch at 1572864 driven through the worker's prepare and both boundary hashes equal to the reference (69abfadf816e767e before, 5b3fb17ad84744fd after), cuda-5090-3.json f2ecf5c7...; 1,048,576 agree each, 0 disagree, 0 missing); the 4090 PASS on all three phases (23:22 to 23:25 UK: cuda-4090-1.json cd0f5aee..., cuda-4090-2.json f864f950... with the day switch at 1572864, cuda-4090-3.json 126bd552...; 1,048,576 agree each, 0 disagree, 0 missing); The 3090 PASS on all three phases (05:07 to 05:10 UK; cuda-3090-{1,2,3}.json afa3d4a4..., 167875f9..., cc956dee...; 1,048,576 agree each, 0 disagree, 0 missing; the day switch at 1572864 with the same boundary hashes as every other reader): the fleet lane's first run on that pod at 00:35 UK never ran a phase (its verify rule demanded two reference files where a context carries one, then its put failed on the pod's flapping ssh; a runner fault, reported once), the rerun from 04:57 UK ran detached on the pod under a pid file with a collector pulling each JSON. So the CUDA cell reads three cards on this context. Metal and OpenCL are the morning's reads (08:30 UK). The case stays NOT RUN in progress until every reader has read (the coordinator's ruling 23:1x UK: a PASS by inference is forbidden). OPENCL on the first rig's RX 7600: take 1 (05:54 UK, opencl-rx7600-take1.report.txt 7fb1ee95...) was a job fault on the rig, not a reader result (the script matched an older gen-5-stamped pack of the same name in the rig's jobs tree; the worker refused it as class v5 against a class v6 job); take 2 (run-ca3-pc1-samework01-opencl-7600-20261009-b, the packs by exact path, 06:03 to 06:05 UK) reads PASS on all three phases: p1 digest 1517d572..., p2 91d63d8b... across the day switch 20730 to 20731 at 1572864 (the D+1 pack prepared in 486 ms, the boundary block 8,192 of 8,192 lines), p3 e483e82a..., each 1,048,576 of 1,048,576 equal to ref-D's and ref-D1's slices, both pack ids 0x4de7b836cc40a4ea generator 6 in the RESULT lines; 'RESULT verdict all PASS context=same-work-20261008-01 reader=opencl card=rx7600'; the report opencl-rx7600.report.txt (sha256 84683b16..., read back on build-1 at 06:09 UK). So the OpenCL reader on the RX 7600 reads all three contexts equal to the CPU reference across their day switches; Metal is the sixth reader on every context, 08:30 UK. METAL, the project's macOS machine (Apple M6) on the serve worker igneum-worker-metal 5aeddcba... (built from class-v6 755c2dbcf by the hash lane), the driver on master with --prepare-first, 08:30 to 08:31 UK: PASS on all three phases, metal-{1,2,3}.json a7ab9fac..., 9be3101a..., b3df42ef... (read back on build-1 at 09:41 UK), 1,048,576 agree each, 0 disagree, 0 missing, the day switch at 1572864 with the boundary hashes 69abfadf816e767e before and 5b3fb17ad84744fd after, equal to every other reader's. So the frozen object reads equal on the CPU reference, CUDA (three cards), OpenCL and Metal across the day switch. This row does not decide POW-01 (its accept covers the full P01 corpus across families, boundary seeds and backends with an independent review: the hash lane's); the record stays NOT RUN for POW-01 and carries the hash lane's P01 campaign evidence (p01-20261008-01) beside this row's, because the recorder keeps one record per cell and this run's record had displaced that batch's on harness:p01-vectors since 22:27 UK.",
|
||||
"network_label": "on an island, not a network"
|
||||
"at": "2026-10-09T10:12:03.744Z",
|
||||
"note": "POW-01 (Track B candidate only, not the shipped v6): an independently written CPU reference (B1, Python) and its C port agree with the CUDA backend byte for byte on every checked instance at n = 8 to 24 on two cards. POW-06 (Track B candidate only): the C-port verifier's time per GPU proof at k = 64 is recorded per row; the proof is about 129 to 180 KB at k = 64 and k is not yet fixed by the theorem's constants (BLOCKED row in the README). The GPU feasibility verdict itself (the README's trap rows) is a research finding for the panel, not a registry case. | Track B B3 (R15-06, the GPU feasibility lane, 9 October 2026): GPU adaptation of the Blocki-Smearsoll TCC 2025 MTP/DRSample MHPoW (eprint 2025/1456, full PDF sha256 13c3646e...) without changing the function: CUDA labelling, Merkle commitment and proof creation, batched at 32, 128 and 512 MiB per instance with the card filled, on a rented RTX 5090 and RTX 4090 at stock clocks (no clock lock on rented pods), board power from nvidia-smi at 1 Hz with idle not subtracted. Correctness oracle: the B1 lane's reference encoding (tools/mhpow/b1 working copy on build-6 09:26Z, not landed) through a C port that reproduces B1's five known-answer fixtures byte for byte, then the GPU byte for byte on labels, every Merkle node, root and proof container, instance 0 equal to B1's own fixture, every GPU proof accepted; the known-failed test (DRSample's long edges deleted on the GPU) fires. A research candidate only: nothing activates, no comparison with the v6 work unit is made (the comparison contract is a BLOCKED row), no PASS is claimed. NOT RUN until the panel reads it."
|
||||
},
|
||||
"in_progress_since": "2026-10-08T20:07:26.255Z",
|
||||
"approvals": {
|
||||
|
|
@ -1549,6 +1548,29 @@
|
|||
"reviewer": "",
|
||||
"at": "2026-10-09T08:55:05.275Z",
|
||||
"note": "P01 part A, the CUDA half, complete at 20:41 UK: four packs (hl-v5-win e3da3669 id 0x6554474f410f36f3 gen 5; hl-v6-all 6df3d430 id 0x4de7b836cc40a4ea gen 6; hl-v6-foldrw f0dc3428 id 0xd7eba30115d26dd4; hl-v6-all-nowin 67ceec05 id 0xbe1d6f48928cef4a) on three CUDA cards (RTX 5090 sm_120, 4090 sm_89, 3090 sm_86), twelve runs, every one driver exit 0, answered 1,000,000, agree 1,000,000, disagree 0, missing 0, 41 to 50 s per million; the kit worker 9bfcf728 for gen 5, the generator-6 worker 804a6f7f for gen 6; the twelve JSONs parsed on build-1 with their sha256s. Remaining for PASS: OpenCL (the project's first rig's RX 7600, the hash lane; no rented AMD card exists tonight) and Metal (the mini, the morning); the case stays NOT RUN in progress until then. (rig names scrubbed for the served registry at 22:2x UK, the steward's identity landing.) Re-recorded at 09:5x UK once the recorder kept records per run: the twelve CUDA evidence files return to POW-01's evidence_path beside the same-work run's record."
|
||||
},
|
||||
"rows:mhpow-b3-gpu-feasibility": {
|
||||
"requirement_id": "POW-01",
|
||||
"decision": "NOT RUN",
|
||||
"method": "GPU",
|
||||
"cell": "rows:mhpow-b3-gpu-feasibility",
|
||||
"manifest_sha": "bc6bfa75e",
|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b3/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the Track B research candidate's CUDA backend against an independent CPU reference (B1) only; nothing about the shipped v6 evaluator",
|
||||
"release_identity": {
|
||||
"commit": "bc6bfa75e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; the Track B candidate is not proposed for activation",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:12:03.744Z",
|
||||
"note": "POW-01 (Track B candidate only, not the shipped v6): an independently written CPU reference (B1, Python) and its C port agree with the CUDA backend byte for byte on every checked instance at n = 8 to 24 on two cards. POW-06 (Track B candidate only): the C-port verifier's time per GPU proof at k = 64 is recorded per row; the proof is about 129 to 180 KB at k = 64 and k is not yet fixed by the theorem's constants (BLOCKED row in the README). The GPU feasibility verdict itself (the README's trap rows) is a research finding for the panel, not a registry case. | Track B B3 (R15-06, the GPU feasibility lane, 9 October 2026): GPU adaptation of the Blocki-Smearsoll TCC 2025 MTP/DRSample MHPoW (eprint 2025/1456, full PDF sha256 13c3646e...) without changing the function: CUDA labelling, Merkle commitment and proof creation, batched at 32, 128 and 512 MiB per instance with the card filled, on a rented RTX 5090 and RTX 4090 at stock clocks (no clock lock on rented pods), board power from nvidia-smi at 1 Hz with idle not subtracted. Correctness oracle: the B1 lane's reference encoding (tools/mhpow/b1 working copy on build-6 09:26Z, not landed) through a C port that reproduces B1's five known-answer fixtures byte for byte, then the GPU byte for byte on labels, every Merkle node, root and proof container, instance 0 equal to B1's own fixture, every GPU proof accepted; the known-failed test (DRSample's long edges deleted on the GPU) fires. A research candidate only: nothing activates, no comparison with the v6 work unit is made (the comparison contract is a BLOCKED row), no PASS is claimed. NOT RUN until the panel reads it."
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
@ -2016,25 +2038,31 @@
|
|||
"manual_page": 25,
|
||||
"owner_lane": "pool design seat (a3832b1c3b274b310)",
|
||||
"run_status": "NOT RUN",
|
||||
"evidence_path": "docs/analysis/binding-review-2026-10.md (sections 1 to 5a; master ad5a54c5)",
|
||||
"run_id": "binding-review-2026-10-08-a05",
|
||||
"updated": "2026-10-08T20:10:24.556Z",
|
||||
"evidence_path": "docs/analysis/binding-review-2026-10.md (sections 1 to 5a; master ad5a54c5); docs/analysis/mhpow/b1/README.md; docs/analysis/mhpow/b2/README.md",
|
||||
"run_id": "mhpow-b2-20261009-01",
|
||||
"updated": "2026-10-09T10:10:43.564Z",
|
||||
"evidence_record": {
|
||||
"reason": "amortised cheap winning attempts are the attack lanes' grind and era harnesses (tools/attack/f7-era, f9-grind), not in the release matrix; their rows come from those lanes",
|
||||
"at": "2026-10-08T20:10:24.556Z",
|
||||
"method": "static",
|
||||
"requirement_id": "POW-05",
|
||||
"decision": "NOT RUN",
|
||||
"reviewer": "",
|
||||
"claim_impact": "",
|
||||
"method": "model",
|
||||
"cell": "model:mhpow-b2-binding",
|
||||
"manifest_sha": "13c3646e",
|
||||
"run_id": "mhpow-b2-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the binding obligations for the Track B work unit only; the lottery binding is BLOCKED (B-T3) and the multi-instance bound BLOCKED (B-T5)",
|
||||
"release_identity": {
|
||||
"commit": "",
|
||||
"commit": "13c3646e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
}
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.564Z",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules and B-T3 the open question. POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's. | B2, the binding spec lane of the 1.5x programme's Track B (9 October 2026): the canonical instance input for an MTP/DRSample memory-hard proof of work in Igneum's setting (328 bytes, work version 1, draft) and the obligations table O-01 to O-16 read against Blocki and Smearsoll, eprint 2025/1456 (the full PDF, sha256 13c3646e...). Reuse across template, trial, epoch, day, era, network and class object: answered by the paper's per-input soundness plus the layout. The lottery: two candidate rules FAIL with written counter-examples (re-roll through a red sink, about 1.3 x 10^6 draws per labelling at N = 2^24; free screening on chi alone); the replacement and the multi-instance, adaptive-input, constants and energy questions BLOCKED to the B4 theory lane and the node lane. Figures by tools/mhpow/b2/b2_figures.py on build-9. NOT RUN until the panel reads it; this lane writes no PASS."
|
||||
},
|
||||
"status_note": "REVIEWED: fixed by construction (binding), not applicable (final digest); native tests ok on build-2; no change for 2.0",
|
||||
"approvals": {
|
||||
|
|
@ -2065,8 +2093,55 @@
|
|||
"run_id": "binding-review-2026-10-08-a05",
|
||||
"evidence": "docs/analysis/binding-review-2026-10.md (sections 1 to 5a; master ad5a54c5)",
|
||||
"in_progress": false
|
||||
},
|
||||
"model:mhpow-b1-reference": {
|
||||
"requirement_id": "POW-05",
|
||||
"decision": "NOT RUN",
|
||||
"method": "model",
|
||||
"cell": "model:mhpow-b1-reference",
|
||||
"manifest_sha": "13c3646e",
|
||||
"run_id": "mhpow-b1-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b1/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the published primitive's attack fixtures only; the lottery binding and the composed accepted-proof theorem are B2/B4's",
|
||||
"release_identity": {
|
||||
"commit": "13c3646e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:06:27.563Z",
|
||||
"note": "POW-05: attack fixtures A1 to A6 (tools/mhpow/b1/fixtures/attacks-n10-k16.json): A1 replay and A2 unopened block REFUSED, A3 control-block steering gain 0 with the red-node fallback accepted at (1-1/t)^k, A4 self-similarity saving refused, A5 Attack 1 accepted at (1-|S|/N)^k, A6 many accepted roots per labelling (the lottery binding BLOCKED to B2/B4, rows O-1 and O-8). POW-06: the verifier's named checks refuse malformed containers, wrong positions, skipped parents and wrong tags (test_b1.py); proof bytes and verifier oracle calls per N are exact formulas with measured rows; cold verification at rate BLOCKED to B6 (O-11). | B1 (R15-05), the cryptography lane of the 1.5x programme's Track B (9 October 2026): the exact CPU reference of Blocki and Smearsoll's MTP framework (eprint 2025/1456 as archived, sha256 13c3646e..., Sec 2.2, 3.2, App. C) over DRSample (ABH17 Alg. 1, eprint 2017/443 as archived, sha256 f8e08d36...), its complete verifier (named checks in the paper's order, each with a known-failed test, 17 of 17 OK on build-6), five deterministic known-answer fixtures (n 4 to 20), honest-prover rows n 12 to 24 (CPython, wall time only, no power) and six malicious provers (Dinur-Nadler eprint 2017/497 Sec 4.1, 4.3/5, 8; the paper's Attack 1 and LuckyQuery regrind). Dinur-Nadler's steering and unopened-block attacks are refused; red-node cheats are accepted with the (1-|S|/N)^k probability the paper prices; one labelling yields many accepted roots (F-4). The proven k with ABH17's constant exceeds N to about n 25 (F-3). NOT RUN until the panel reads it; this lane writes no PASS."
|
||||
},
|
||||
"model:mhpow-b2-binding": {
|
||||
"requirement_id": "POW-05",
|
||||
"decision": "NOT RUN",
|
||||
"method": "model",
|
||||
"cell": "model:mhpow-b2-binding",
|
||||
"manifest_sha": "13c3646e",
|
||||
"run_id": "mhpow-b2-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the binding obligations for the Track B work unit only; the lottery binding is BLOCKED (B-T3) and the multi-instance bound BLOCKED (B-T5)",
|
||||
"release_identity": {
|
||||
"commit": "13c3646e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.564Z",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules and B-T3 the open question. POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's. | B2, the binding spec lane of the 1.5x programme's Track B (9 October 2026): the canonical instance input for an MTP/DRSample memory-hard proof of work in Igneum's setting (328 bytes, work version 1, draft) and the obligations table O-01 to O-16 read against Blocki and Smearsoll, eprint 2025/1456 (the full PDF, sha256 13c3646e...). Reuse across template, trial, epoch, day, era, network and class object: answered by the paper's per-input soundness plus the layout. The lottery: two candidate rules FAIL with written counter-examples (re-roll through a red sink, about 1.3 x 10^6 draws per labelling at N = 2^24; free screening on chi alone); the replacement and the multi-instance, adaptive-input, constants and energy questions BLOCKED to the B4 theory lane and the node lane. Figures by tools/mhpow/b2/b2_figures.py on build-9. NOT RUN until the panel reads it; this lane writes no PASS."
|
||||
}
|
||||
}
|
||||
},
|
||||
"in_progress_since": "2026-10-09T10:06:27.563Z"
|
||||
},
|
||||
{
|
||||
"id": "POW-06",
|
||||
|
|
@ -2095,29 +2170,31 @@
|
|||
"manual_page": 25,
|
||||
"owner_lane": "hash lane (a690540514aa453d7)",
|
||||
"run_status": "NOT RUN",
|
||||
"evidence_path": "build-1:/srv/artefacts/tas/p01-partb-20261008-01/summary.jsonl",
|
||||
"run_id": "p01-partb-20261008-01",
|
||||
"updated": "2026-10-08T18:28:32.463Z",
|
||||
"evidence_path": "build-1:/srv/artefacts/tas/p01-partb-20261008-01/summary.jsonl; docs/analysis/mhpow/b1/README.md; docs/analysis/mhpow/b2/README.md; docs/analysis/mhpow/b3/README.md",
|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"updated": "2026-10-09T10:12:03.744Z",
|
||||
"evidence_record": {
|
||||
"cell": "harness:parser-malformed",
|
||||
"manifest_sha": "417c4a57",
|
||||
"coverage": {
|
||||
"POW-06": "partial: three parsers of external bytes (the state stream, the igneum_ RPC params, the pool job line), ten thousand seeded malformed cases each, zero panics, every case under 500 ms (the slowest 152 microseconds); 'accepted' counts mutations that left a valid input, not a parser fault; the verifier work bound (the other half of the accept text) is the proving lane's measurement"
|
||||
},
|
||||
"at": "2026-10-08T18:28:32.463Z",
|
||||
"method": "static",
|
||||
"requirement_id": "POW-06",
|
||||
"decision": "NOT RUN",
|
||||
"reviewer": "",
|
||||
"claim_impact": "",
|
||||
"method": "GPU",
|
||||
"cell": "rows:mhpow-b3-gpu-feasibility",
|
||||
"manifest_sha": "bc6bfa75e",
|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b3/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: verifier time per proof for the Track B candidate at k = 64 on one CPU; no malformed-input or rate budget",
|
||||
"release_identity": {
|
||||
"commit": "417c4a57",
|
||||
"commit": "bc6bfa75e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
}
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; the Track B candidate is not proposed for activation",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:12:03.744Z",
|
||||
"note": "POW-01 (Track B candidate only, not the shipped v6): an independently written CPU reference (B1, Python) and its C port agree with the CUDA backend byte for byte on every checked instance at n = 8 to 24 on two cards. POW-06 (Track B candidate only): the C-port verifier's time per GPU proof at k = 64 is recorded per row; the proof is about 129 to 180 KB at k = 64 and k is not yet fixed by the theorem's constants (BLOCKED row in the README). The GPU feasibility verdict itself (the README's trap rows) is a research finding for the panel, not a registry case. | Track B B3 (R15-06, the GPU feasibility lane, 9 October 2026): GPU adaptation of the Blocki-Smearsoll TCC 2025 MTP/DRSample MHPoW (eprint 2025/1456, full PDF sha256 13c3646e...) without changing the function: CUDA labelling, Merkle commitment and proof creation, batched at 32, 128 and 512 MiB per instance with the card filled, on a rented RTX 5090 and RTX 4090 at stock clocks (no clock lock on rented pods), board power from nvidia-smi at 1 Hz with idle not subtracted. Correctness oracle: the B1 lane's reference encoding (tools/mhpow/b1 working copy on build-6 09:26Z, not landed) through a C port that reproduces B1's five known-answer fixtures byte for byte, then the GPU byte for byte on labels, every Merkle node, root and proof container, instance 0 equal to B1's own fixture, every GPU proof accepted; the known-failed test (DRSample's long edges deleted on the GPU) fires. A research candidate only: nothing activates, no comparison with the v6 work unit is made (the comparison contract is a BLOCKED row), no PASS is claimed. NOT RUN until the panel reads it."
|
||||
},
|
||||
"in_progress_since": "2026-10-08T18:28:32.463Z",
|
||||
"approvals": {
|
||||
|
|
@ -2150,6 +2227,75 @@
|
|||
"run_id": "p01-partb-20261008-01",
|
||||
"evidence": "build-1:/srv/artefacts/tas/p01-partb-20261008-01/summary.jsonl",
|
||||
"in_progress": true
|
||||
},
|
||||
"model:mhpow-b1-reference": {
|
||||
"requirement_id": "POW-06",
|
||||
"decision": "NOT RUN",
|
||||
"method": "model",
|
||||
"cell": "model:mhpow-b1-reference",
|
||||
"manifest_sha": "13c3646e",
|
||||
"run_id": "mhpow-b1-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b1/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: verifier refusals and op counts in CPython; no compiled verifier, no admitted-rate timing",
|
||||
"release_identity": {
|
||||
"commit": "13c3646e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:06:27.563Z",
|
||||
"note": "POW-05: attack fixtures A1 to A6 (tools/mhpow/b1/fixtures/attacks-n10-k16.json): A1 replay and A2 unopened block REFUSED, A3 control-block steering gain 0 with the red-node fallback accepted at (1-1/t)^k, A4 self-similarity saving refused, A5 Attack 1 accepted at (1-|S|/N)^k, A6 many accepted roots per labelling (the lottery binding BLOCKED to B2/B4, rows O-1 and O-8). POW-06: the verifier's named checks refuse malformed containers, wrong positions, skipped parents and wrong tags (test_b1.py); proof bytes and verifier oracle calls per N are exact formulas with measured rows; cold verification at rate BLOCKED to B6 (O-11). | B1 (R15-05), the cryptography lane of the 1.5x programme's Track B (9 October 2026): the exact CPU reference of Blocki and Smearsoll's MTP framework (eprint 2025/1456 as archived, sha256 13c3646e..., Sec 2.2, 3.2, App. C) over DRSample (ABH17 Alg. 1, eprint 2017/443 as archived, sha256 f8e08d36...), its complete verifier (named checks in the paper's order, each with a known-failed test, 17 of 17 OK on build-6), five deterministic known-answer fixtures (n 4 to 20), honest-prover rows n 12 to 24 (CPython, wall time only, no power) and six malicious provers (Dinur-Nadler eprint 2017/497 Sec 4.1, 4.3/5, 8; the paper's Attack 1 and LuckyQuery regrind). Dinur-Nadler's steering and unopened-block attacks are refused; red-node cheats are accepted with the (1-|S|/N)^k probability the paper prices; one labelling yields many accepted roots (F-4). The proven k with ABH17's constant exceeds N to about n 25 (F-3). NOT RUN until the panel reads it; this lane writes no PASS."
|
||||
},
|
||||
"model:mhpow-b2-binding": {
|
||||
"requirement_id": "POW-06",
|
||||
"decision": "NOT RUN",
|
||||
"method": "model",
|
||||
"cell": "model:mhpow-b2-binding",
|
||||
"manifest_sha": "13c3646e",
|
||||
"run_id": "mhpow-b2-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: certificate size as a formula; no verifier timing, no malformed-input cost",
|
||||
"release_identity": {
|
||||
"commit": "13c3646e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.564Z",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules and B-T3 the open question. POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's. | B2, the binding spec lane of the 1.5x programme's Track B (9 October 2026): the canonical instance input for an MTP/DRSample memory-hard proof of work in Igneum's setting (328 bytes, work version 1, draft) and the obligations table O-01 to O-16 read against Blocki and Smearsoll, eprint 2025/1456 (the full PDF, sha256 13c3646e...). Reuse across template, trial, epoch, day, era, network and class object: answered by the paper's per-input soundness plus the layout. The lottery: two candidate rules FAIL with written counter-examples (re-roll through a red sink, about 1.3 x 10^6 draws per labelling at N = 2^24; free screening on chi alone); the replacement and the multi-instance, adaptive-input, constants and energy questions BLOCKED to the B4 theory lane and the node lane. Figures by tools/mhpow/b2/b2_figures.py on build-9. NOT RUN until the panel reads it; this lane writes no PASS."
|
||||
},
|
||||
"rows:mhpow-b3-gpu-feasibility": {
|
||||
"requirement_id": "POW-06",
|
||||
"decision": "NOT RUN",
|
||||
"method": "GPU",
|
||||
"cell": "rows:mhpow-b3-gpu-feasibility",
|
||||
"manifest_sha": "bc6bfa75e",
|
||||
"run_id": "mhpow-b3-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b3/README.md",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: verifier time per proof for the Track B candidate at k = 64 on one CPU; no malformed-input or rate budget",
|
||||
"release_identity": {
|
||||
"commit": "bc6bfa75e",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no public figure moves; the Track B candidate is not proposed for activation",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:12:03.744Z",
|
||||
"note": "POW-01 (Track B candidate only, not the shipped v6): an independently written CPU reference (B1, Python) and its C port agree with the CUDA backend byte for byte on every checked instance at n = 8 to 24 on two cards. POW-06 (Track B candidate only): the C-port verifier's time per GPU proof at k = 64 is recorded per row; the proof is about 129 to 180 KB at k = 64 and k is not yet fixed by the theorem's constants (BLOCKED row in the README). The GPU feasibility verdict itself (the README's trap rows) is a research finding for the panel, not a registry case. | Track B B3 (R15-06, the GPU feasibility lane, 9 October 2026): GPU adaptation of the Blocki-Smearsoll TCC 2025 MTP/DRSample MHPoW (eprint 2025/1456, full PDF sha256 13c3646e...) without changing the function: CUDA labelling, Merkle commitment and proof creation, batched at 32, 128 and 512 MiB per instance with the card filled, on a rented RTX 5090 and RTX 4090 at stock clocks (no clock lock on rented pods), board power from nvidia-smi at 1 Hz with idle not subtracted. Correctness oracle: the B1 lane's reference encoding (tools/mhpow/b1 working copy on build-6 09:26Z, not landed) through a C port that reproduces B1's five known-answer fixtures byte for byte, then the GPU byte for byte on labels, every Merkle node, root and proof container, instance 0 equal to B1's own fixture, every GPU proof accepted; the known-failed test (DRSample's long edges deleted on the GPU) fires. A research candidate only: nothing activates, no comparison with the v6 work unit is made (the comparison contract is a BLOCKED row), no PASS is claimed. NOT RUN until the panel reads it."
|
||||
}
|
||||
}
|
||||
},
|
||||
|
|
@ -20321,44 +20467,58 @@
|
|||
"manual_page": null,
|
||||
"run_status": "NOT RUN",
|
||||
"plan_status": "NOT RUN",
|
||||
"updated": "2026-10-09T09:19:24.923Z",
|
||||
"run_id": "r15-02-x7-20261009-01",
|
||||
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|
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||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
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||||
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|
||||
"note": "BOUND (B1, F-3): with ABH17's proven constant the paper's challenge count k exceeds N at lambda 256 and N 2^20 (to about n 25): no practical parameter in the proven regime. FINDING (B1, F-4): one labelling yields 193 to 200 accepted roots in 200 tries at 26 oracle calls per try, so a lottery over tau is not bound to the labelling cost (fixture A6, attacks-n10-k16.json, run on build-6). The package R15-05 (no improvised sampled-memory soundness) stays NOT RUN until the independent panel reads the reference and its verifier (17 of 17 named checks with known-failed tests) | the coordinator's order (10:4x UK, 9 October 2026): Track B's reproduction findings as BOUND rows, NOT RUN, no pass or fail claimed for the package"
|
||||
}
|
||||
},
|
||||
"in_progress_since": "2026-10-09T10:06:27.821Z",
|
||||
"approvals": {
|
||||
"scope_approved": null,
|
||||
"implementation_complete": null,
|
||||
|
|
@ -20716,44 +20918,81 @@
|
|||
"manual_page": null,
|
||||
"run_status": "NOT RUN",
|
||||
"plan_status": "NOT RUN",
|
||||
"updated": "2026-10-09T09:19:24.923Z",
|
||||
"run_id": "r15-track-b-20261009-01",
|
||||
"evidence_path": "docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py; docs/analysis/mhpow/b2/README.md; docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"updated": "2026-10-09T10:10:43.747Z",
|
||||
"evidence_record": {
|
||||
"reason": "R15-07 (1.5x programme package): no package executed; the harness is the lane's (B2, B4); its batch names the case when it lands; not yet named in the map",
|
||||
"at": "2026-10-09T09:19:24.923Z",
|
||||
"method": "static",
|
||||
"requirement_id": "R15-07",
|
||||
"decision": "NOT RUN",
|
||||
"reviewer": "",
|
||||
"claim_impact": "",
|
||||
"method": "model",
|
||||
"cell": "theory:r15-07-track-b",
|
||||
"manifest_sha": "067dca70",
|
||||
"run_id": "r15-track-b-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md; docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the statement, the obligations and the losses on published constants; the proof of terms 2 and 3, the amortisation and the panel's reading open",
|
||||
"release_identity": {
|
||||
"commit": "",
|
||||
"commit": "master 067dca70 (B2 eb999f0e, B4 12822bf5, B6 1ab735be landed); B1 e9f94df6 and B3 land by 11:45 UK and are recorded then under R15-05 and R15-06",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
}
|
||||
"network_object": "none: documents and tests only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": "R1 2025/1456 13c3646e...; params.py 7ac7fd48...; params.txt a98ac460..."
|
||||
},
|
||||
"claim_impact": "none",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.747Z",
|
||||
"note": "BOUND (B4): no 1.5x certificate is reachable from the published constants; the generic route at most 0.151 of the honest prover's energy at log2 N = 22, the red-blue route losing at least 341x at rho 0.25 (docs/analysis/mhpow/b4/README.md, params.txt). FINDING (B2, obligation O-07): the two naive lottery rules FAIL with written counter-examples (the sink re-roll at log2 N + 1 calls, about 1.3 million draws per labelling at N = 2^24; free screening on chi alone), the replacement BLOCKED to B4 (B-T3) (docs/analysis/mhpow/b2/README.md). The package R15-07 (no invalid theorem composition) stays NOT RUN until the independent panel reads the composed statement; terms 2 and 3's amortisation are open theorems; L BLOCKED | the coordinator's order (10:4x UK, 9 October 2026): Track B's reproduction findings recorded as BOUND rows, NOT RUN, no pass or fail claimed for any package; every chip figure WITNESS or BOUND by the R15 suite rule"
|
||||
},
|
||||
"evidence_records": {
|
||||
"record": {
|
||||
"reason": "R15-07 (1.5x programme package): no package executed; the harness is the lane's (B2, B4); its batch names the case when it lands; not yet named in the map",
|
||||
"at": "2026-10-09T09:19:24.923Z",
|
||||
"method": "static",
|
||||
"theory:mhpow-b4": {
|
||||
"requirement_id": "R15-07",
|
||||
"decision": "NOT RUN",
|
||||
"reviewer": "",
|
||||
"claim_impact": "",
|
||||
"method": "model",
|
||||
"cell": "theory:mhpow-b4",
|
||||
"manifest_sha": "12822bf5",
|
||||
"run_id": "mhpow-b4-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the composed theorem's statement and the losses on the published constants; terms 2 and 3's amortisation open theorems; L BLOCKED; the panel has not read it",
|
||||
"release_identity": {
|
||||
"commit": "",
|
||||
"commit": "branch mhpow-b4 12822bf5, landed on master at 067dca70 (the typeset docs: docs/analysis/mhpow/b4)",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "",
|
||||
"activation": "",
|
||||
"profile_hashes": ""
|
||||
"network_object": "none: a theorem statement and an audit of published papers, no chain state read or written",
|
||||
"activation": "none (Track B lands documents and tests only)",
|
||||
"profile_hashes": "R1 2025/1456 13c3646e...; R2 2018/221 2a466b97...; R3 2017/225 29c5a9c0...; R4 2026/1024 aa6caa39...; R16 arXiv 2207.11519 ac273393...; params.py 7ac7fd48..., params.txt a98ac460..."
|
||||
},
|
||||
"in_progress": false
|
||||
"claim_impact": "none: the composed accepted-proof energy statement is a draft with named proof obligations; the published constants cannot carry a 1.5x certificate (loss at least 6.6x on the generic route, at least 341x on the red-blue route); every row NOT RUN until the panel reads it",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.656Z",
|
||||
"note": "NOT RUN: statement and losses written; terms 2 (transfers) and the amortisation of terms 2 and 3 are open theorems; L is BLOCKED (no lower-bound certificate for any technology coefficient); X5 rows stay WITNESS (E_D) | recorded by the CI steward on the coordinator's order (10:4x UK, 9 October 2026): Track B's findings as BOUND and NOT RUN rows; the cell theory:mhpow-b4 carried in map_cell_requested. NOT RUN by this lane: the steward records it only if the coordinator asks, with the cell added to the map. BLOCKED rows B4-B01 to B4-B10 in README section 12."
|
||||
},
|
||||
"theory:r15-07-track-b": {
|
||||
"requirement_id": "R15-07",
|
||||
"decision": "NOT RUN",
|
||||
"method": "model",
|
||||
"cell": "theory:r15-07-track-b",
|
||||
"manifest_sha": "067dca70",
|
||||
"run_id": "r15-track-b-20261009-01",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md; docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"in_progress": true,
|
||||
"coverage": "partial: the statement, the obligations and the losses on published constants; the proof of terms 2 and 3, the amortisation and the panel's reading open",
|
||||
"release_identity": {
|
||||
"commit": "master 067dca70 (B2 eb999f0e, B4 12822bf5, B6 1ab735be landed); B1 e9f94df6 and B3 land by 11:45 UK and are recorded then under R15-05 and R15-06",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: documents and tests only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": "R1 2025/1456 13c3646e...; params.py 7ac7fd48...; params.txt a98ac460..."
|
||||
},
|
||||
"claim_impact": "none",
|
||||
"reviewer": "",
|
||||
"at": "2026-10-09T10:10:43.747Z",
|
||||
"note": "BOUND (B4): no 1.5x certificate is reachable from the published constants; the generic route at most 0.151 of the honest prover's energy at log2 N = 22, the red-blue route losing at least 341x at rho 0.25 (docs/analysis/mhpow/b4/README.md, params.txt). FINDING (B2, obligation O-07): the two naive lottery rules FAIL with written counter-examples (the sink re-roll at log2 N + 1 calls, about 1.3 million draws per labelling at N = 2^24; free screening on chi alone), the replacement BLOCKED to B4 (B-T3) (docs/analysis/mhpow/b2/README.md). The package R15-07 (no invalid theorem composition) stays NOT RUN until the independent panel reads the composed statement; terms 2 and 3's amortisation are open theorems; L BLOCKED | the coordinator's order (10:4x UK, 9 October 2026): Track B's reproduction findings recorded as BOUND rows, NOT RUN, no pass or fail claimed for any package; every chip figure WITNESS or BOUND by the R15 suite rule"
|
||||
}
|
||||
},
|
||||
"in_progress_since": "2026-10-09T10:10:43.656Z",
|
||||
"approvals": {
|
||||
"scope_approved": null,
|
||||
"implementation_complete": null,
|
||||
|
|
|
|||
|
|
@ -1174,7 +1174,9 @@ fn reg_decl(p: &Program, ty: &str) -> String {
|
|||
}
|
||||
let names: Vec<String> = (0..p.registers()).map(|k| format!("r{k}")).collect();
|
||||
let m = if p.address_mix() {
|
||||
if ty == "uint32_t" && reg64_prefix() {
|
||||
if ty == "uint32_t" && reg64_form() == crate::reg64form::Reg64Form::Generated {
|
||||
format!("\n {ty} m, S, p_, g0, g1, g2, g3, g4, g5, g6, g7; // reg64 full chain in the X4 generated form: the eight group sums, recomputed where the schedule wrote")
|
||||
} else if ty == "uint32_t" && reg64_prefix() {
|
||||
format!("\n {ty} m, S, p_, t_; // reg64 full chain in the F05 prefix form: S the running xor of the rotated registers, p_ the prefix, t_ the old term")
|
||||
} else {
|
||||
format!("\n {ty} m; // reg64 full chain: the address mix of all 64 registers before every load")
|
||||
|
|
@ -1194,14 +1196,65 @@ fn reg_decl(p: &Program, ty: &str) -> String {
|
|||
/// `r[s] ^ ror(P_s, 1) ^ (S ^ P_s ^ a[s])` with `P_s` the xor of the first `s` terms. The same hash, the same vectors
|
||||
/// (`verify::reg64_address_source`); a measurement text for the fleet, never the definition. OpenCL and Metal keep
|
||||
/// the fold.
|
||||
static REG64_PREFIX: std::sync::atomic::AtomicBool = std::sync::atomic::AtomicBool::new(false);
|
||||
|
||||
/// X4 of the 1.5x programme (9 October 2026): the switch is one value of the CUDA text's form
|
||||
/// (`crate::reg64form`, `igneum-pow export --reg64-form fold|direct|generated|prefix`); `--reg64-prefix` is `prefix`.
|
||||
pub fn set_reg64_prefix(on: bool) {
|
||||
REG64_PREFIX.store(on, std::sync::atomic::Ordering::Relaxed);
|
||||
crate::reg64form::set_gpu_form(if on { crate::reg64form::Reg64Form::Prefix } else { crate::reg64form::Reg64Form::Fold });
|
||||
}
|
||||
|
||||
pub fn reg64_prefix() -> bool {
|
||||
REG64_PREFIX.load(std::sync::atomic::Ordering::Relaxed)
|
||||
crate::reg64form::gpu_form() == crate::reg64form::Reg64Form::Prefix
|
||||
}
|
||||
|
||||
/// The CUDA text's form of the reg64 address mix (the fold unless `--reg64-form` names another).
|
||||
fn reg64_form() -> crate::reg64form::Reg64Form {
|
||||
crate::reg64form::gpu_form()
|
||||
}
|
||||
|
||||
/// X4 direct form: the mix statement before a load of source `src` as the definition's closed sum, one rotation
|
||||
/// per term (`rotl(rK, (62 - k) mod 32)` before the source, `(63 - k) mod 32` after it), xored as a balanced tree.
|
||||
fn reg64_direct_mix_line(src: u8) -> String {
|
||||
let s = src as usize;
|
||||
let terms: Vec<String> = (0..64)
|
||||
.filter(|&k| k != s)
|
||||
.map(|k| {
|
||||
let n = crate::reg64form::direct_rot(k, s);
|
||||
if n == 0 { format!("r{k}") } else { format!("rotl_imm(r{k}, {n}u)") }
|
||||
})
|
||||
.collect();
|
||||
format!("m = {};", xor_tree(&terms))
|
||||
}
|
||||
|
||||
/// A balanced xor tree of `terms` as text (parenthesised so the compiler is handed the tree, not a chain).
|
||||
fn xor_tree(terms: &[String]) -> String {
|
||||
match terms.len() {
|
||||
0 => "0u".to_string(),
|
||||
1 => terms[0].clone(),
|
||||
n => format!("({} ^ {})", xor_tree(&terms[..n / 2]), xor_tree(&terms[n / 2..])),
|
||||
}
|
||||
}
|
||||
|
||||
/// X4 generated form: one group sum `gJ = a[8J] ^ ... ^ a[8J + 7]` as a statement.
|
||||
fn reg64_group_line(j: usize) -> String {
|
||||
let terms: Vec<String> = (j * 8..j * 8 + 8).map(reg64_term).collect();
|
||||
format!("g{j} = {};", xor_tree(&terms))
|
||||
}
|
||||
|
||||
/// X4 generated form: the statements before a load of source `src` (the plan's stale groups recomputed, then
|
||||
/// `m = ror(P, 1) ^ S ^ P ^ a[src]` with `S` the eight groups and `P` the groups before src's plus the partial).
|
||||
fn reg64_generated_mix_line(recompute: &[usize], src: u8) -> String {
|
||||
let s = src as usize;
|
||||
let mut out = String::new();
|
||||
for &j in recompute {
|
||||
out.push_str(®64_group_line(j));
|
||||
out.push(' ');
|
||||
}
|
||||
let groups: Vec<String> = (0..8).map(|j| format!("g{j}")).collect();
|
||||
let jj = s / 8;
|
||||
let mut prefix: Vec<String> = (0..jj).map(|j| format!("g{j}")).collect();
|
||||
prefix.extend((jj * 8..s).map(reg64_term));
|
||||
out.push_str(&format!("S = {}; p_ = {}; m = rotr_var(p_, 1u) ^ S ^ p_ ^ {};", xor_tree(&groups), xor_tree(&prefix), reg64_term(s)));
|
||||
out
|
||||
}
|
||||
|
||||
/// `rotl(rK, (63 - k) mod 32)` as text; a rotation of 0 is the register itself (`rotl_imm` takes 1..31).
|
||||
|
|
@ -1220,6 +1273,13 @@ fn reg64_prefix_mix_line(src: u8) -> String {
|
|||
|
||||
/// The prefix form's running total after the register init: `S = a[0] ^ ... ^ a[63]`.
|
||||
fn reg64_prefix_init(p: &Program) -> String {
|
||||
if p.class.reg64 && p.address_mix() && reg64_form() == crate::reg64form::Reg64Form::Generated {
|
||||
let mut s = String::from(" // X4 generated form: the eight group sums of the rotated registers\n");
|
||||
for j in 0..8 {
|
||||
s.push_str(&format!(" {}\n", reg64_group_line(j)));
|
||||
}
|
||||
return s;
|
||||
}
|
||||
if !p.class.reg64 || !p.address_mix() || !reg64_prefix() {
|
||||
return String::new();
|
||||
}
|
||||
|
|
@ -1278,13 +1338,22 @@ fn cuda_instr_lines(p: &Program, geom: DatasetGeom) -> String {
|
|||
// just before the load (the verifier's addr_src, the same chain)
|
||||
let address_mix = p.address_mix();
|
||||
let addr_src = |a: &str| -> String { if address_mix { format!("({a} ^ m)") } else { a.to_string() } };
|
||||
for (k, ins) in p.scheduled().iter().enumerate() {
|
||||
let scheduled = p.scheduled();
|
||||
let form = reg64_form();
|
||||
let plan = if address_mix && form == crate::reg64form::Reg64Form::Generated { crate::reg64form::generated_plan(&scheduled, &p.shadow) } else { Vec::new() };
|
||||
for (k, ins) in scheduled.iter().enumerate() {
|
||||
let d = format!("r{}", ins.dst);
|
||||
let a = format!("r{}", ins.src);
|
||||
let b = format!("r{}", ins.src2);
|
||||
let prefix = address_mix && reg64_prefix();
|
||||
if address_mix && ins.op == Op::Load {
|
||||
s.push_str(&format!(" {}\n", if prefix { reg64_prefix_mix_line(ins.src) } else { reg64_mix_line(p, ins.src) }));
|
||||
let line = match form {
|
||||
crate::reg64form::Reg64Form::Prefix => reg64_prefix_mix_line(ins.src),
|
||||
crate::reg64form::Reg64Form::Direct => reg64_direct_mix_line(ins.src),
|
||||
crate::reg64form::Reg64Form::Generated => reg64_generated_mix_line(&plan[k], ins.src),
|
||||
_ => reg64_mix_line(p, ins.src),
|
||||
};
|
||||
s.push_str(&format!(" {line}\n"));
|
||||
}
|
||||
if prefix {
|
||||
// the old term of the destination, so S can drop it after the write
|
||||
|
|
|
|||
|
|
@ -30,6 +30,7 @@ pub mod emit;
|
|||
pub mod generator;
|
||||
pub mod memhard;
|
||||
pub mod packcheck;
|
||||
pub mod reg64form;
|
||||
pub mod seed;
|
||||
pub mod state;
|
||||
pub mod verify;
|
||||
|
|
|
|||
|
|
@ -123,7 +123,9 @@ fn usage() -> ! {
|
|||
\x20 --dataset-words N research class ds55: the dataset at N words (a multiple of 65,536 in 2^28 ..= 2^31; 1476395008 = 5.5 GiB); a non-power-of-two uses idx = (src * N) >> 32 in every load (spec 01 section 1.13.3), a power of two is --dataset-log2\n\\
|
||||
\x20 --reg64 the 64-register window per lane over the class (research; the same as --class <class>+reg64; CUDA, OpenCL and Metal texts)\n\
|
||||
\x20 --reg64-chain reg64 with the full-chain address mix: every load's address consumes all 64 registers (the same as --class <class>+reg64c)\n\
|
||||
\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)"
|
||||
\x20 --reg64-prefix export: the CUDA texts carry the reg64 chain in its closed prefix form (review B's F05; the same hash and vectors, a measurement text)\n\
|
||||
\x20 --reg64-form <f> export: the CUDA texts' reg64 address-mix form, fold (the default), direct, generated or prefix (X4, 1.5x programme; the same hash)\n\
|
||||
\x20 --reg64-cpu-form <f> the CPU interpreter computes the reg64 address mix in form f (fold, direct, generated, prefix, or wrong: the known-failed form), the X4 differential only"
|
||||
);
|
||||
std::process::exit(2)
|
||||
}
|
||||
|
|
@ -191,6 +193,11 @@ fn parse() -> Args {
|
|||
a.reg64_chain = true;
|
||||
}
|
||||
"--reg64-prefix" => igneum_pow::emit::set_reg64_prefix(true),
|
||||
"--reg64-form" => match igneum_pow::reg64form::Reg64Form::parse(&val()) {
|
||||
Some(igneum_pow::reg64form::Reg64Form::Wrong) | None => usage(),
|
||||
Some(f) => igneum_pow::reg64form::set_gpu_form(f),
|
||||
},
|
||||
"--reg64-cpu-form" => igneum_pow::reg64form::set_cpu_form(igneum_pow::reg64form::Reg64Form::parse(&val()).unwrap_or_else(|| usage())),
|
||||
_ => usage(),
|
||||
}
|
||||
}
|
||||
|
|
|
|||
322
igneum-pow/src/reg64form.rs
Normal file
322
igneum-pow/src/reg64form.rs
Normal file
|
|
@ -0,0 +1,322 @@
|
|||
//! X4 of the 1.5x programme (9 October 2026, the k lane): byte-identical implementation forms of the class v6
|
||||
//! reg64c address mix (`docs/analysis/class-v6/1p5x/x4/README.md`). The DEFINITION stays the verifier's fold
|
||||
//! (`verify::step`'s `addr_src`: `m = r[k0]; m = rotl(m, 1) ^ r[k1]; ...` over the 63 registers other than the load's
|
||||
//! source `s`, in index order, the address source `r[s] ^ m`). Every form here computes the same 32-bit word on every
|
||||
//! register state and every source; none of them is a consensus change, and the default everywhere is the fold.
|
||||
//!
|
||||
//! * `Fold`: the frozen text (the 63-term dependent chain per load).
|
||||
//! * `Direct`: the definition's closed sum written directly, `m = XOR_{k<s} rotl(r[k], (62 - k) mod 32) ^
|
||||
//! XOR_{k>s} rotl(r[k], (63 - k) mod 32)`, a balanced XOR tree with no carried chain and no state.
|
||||
//! * `Generated`: a code-generated form over eight group sums `g_j = XOR_{k in 8j..8j+7} a[k]`, `a[k] = rotl(r[k],
|
||||
//! (63 - k) mod 32)`. The generator reads the static schedule and recomputes, before each load, only the groups
|
||||
//! written since the previous load ([`generated_plan`]); the shadow block draws its registers from r0..r7
|
||||
//! (`generator.rs`, `dst = rng.below(8)`), so the 55,296 shadow writes dirty group 0 only. A load's source is
|
||||
//! `r[s] ^ ror(P_s, 1) ^ S ^ P_s ^ a[s]` with `S = XOR g_j` and `P_s` the whole groups before `s`'s group plus the
|
||||
//! in-group partial (review B's F05 identity, `verify::reg64_address_source`).
|
||||
//! * `Prefix`: review B's F05 text as landed (`--reg64-prefix`): a running `S` updated after every write (main and
|
||||
//! shadow), `P_s` recomputed per load.
|
||||
//! * `Wrong`: the known-failed variant for the differential test only (`r[s] ^ S ^ a[s]`, every term rotated as if it
|
||||
//! sat after the source); the differential must refuse it. Never emitted.
|
||||
|
||||
use std::sync::atomic::{AtomicU8, Ordering};
|
||||
|
||||
use crate::generator::{Instr, Op, LANES};
|
||||
|
||||
/// Registers per group of the generated form.
|
||||
pub const GROUP: usize = 8;
|
||||
/// Groups of the generated form (64 registers).
|
||||
pub const GROUPS: usize = 8;
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
pub enum Reg64Form {
|
||||
Fold,
|
||||
Direct,
|
||||
Generated,
|
||||
Prefix,
|
||||
Wrong,
|
||||
}
|
||||
|
||||
impl Reg64Form {
|
||||
pub fn parse(s: &str) -> Option<Reg64Form> {
|
||||
Some(match s {
|
||||
"fold" => Reg64Form::Fold,
|
||||
"direct" => Reg64Form::Direct,
|
||||
"generated" => Reg64Form::Generated,
|
||||
"prefix" => Reg64Form::Prefix,
|
||||
"wrong" => Reg64Form::Wrong,
|
||||
_ => return None,
|
||||
})
|
||||
}
|
||||
pub fn name(self) -> &'static str {
|
||||
match self {
|
||||
Reg64Form::Fold => "fold",
|
||||
Reg64Form::Direct => "direct",
|
||||
Reg64Form::Generated => "generated",
|
||||
Reg64Form::Prefix => "prefix",
|
||||
Reg64Form::Wrong => "wrong",
|
||||
}
|
||||
}
|
||||
fn code(self) -> u8 {
|
||||
self as u8
|
||||
}
|
||||
fn from_code(c: u8) -> Reg64Form {
|
||||
[Reg64Form::Fold, Reg64Form::Direct, Reg64Form::Generated, Reg64Form::Prefix, Reg64Form::Wrong][c as usize]
|
||||
}
|
||||
}
|
||||
|
||||
static GPU_FORM: AtomicU8 = AtomicU8::new(0);
|
||||
static CPU_FORM: AtomicU8 = AtomicU8::new(0);
|
||||
|
||||
/// The CUDA text's form (`igneum-pow export --reg64-form <form>`; `--reg64-prefix` is `prefix`). `Wrong` is refused.
|
||||
pub fn set_gpu_form(f: Reg64Form) {
|
||||
assert!(f != Reg64Form::Wrong, "the known-failed form is never emitted");
|
||||
GPU_FORM.store(f.code(), Ordering::Relaxed);
|
||||
}
|
||||
pub fn gpu_form() -> Reg64Form {
|
||||
Reg64Form::from_code(GPU_FORM.load(Ordering::Relaxed))
|
||||
}
|
||||
/// The CPU interpreter's form (`--reg64-cpu-form <form>`, the differential test's switch). The fold is the
|
||||
/// definition and the default; every other form runs beside it only in the X4 differential.
|
||||
pub fn set_cpu_form(f: Reg64Form) {
|
||||
CPU_FORM.store(f.code(), Ordering::Relaxed);
|
||||
}
|
||||
pub fn cpu_form() -> Reg64Form {
|
||||
Reg64Form::from_code(CPU_FORM.load(Ordering::Relaxed))
|
||||
}
|
||||
|
||||
/// `a[k] = rotl(r[k], (63 - k) mod 32)`: register k's rotation in the full 64-register chain.
|
||||
#[inline(always)]
|
||||
pub fn term(r: &[u32; 64], k: usize) -> u32 {
|
||||
r[k].rotate_left(((63 - k) % 32) as u32)
|
||||
}
|
||||
|
||||
/// The rotation register `k` carries in the chain of a load whose source is `s` (k != s).
|
||||
#[inline(always)]
|
||||
pub fn direct_rot(k: usize, s: usize) -> u32 {
|
||||
if k < s { ((62 - k) % 32) as u32 } else { ((63 - k) % 32) as u32 }
|
||||
}
|
||||
|
||||
/// The definition, one lane: `r[s] ^ m` with the 63-term chain (the same loop as `verify::step`).
|
||||
pub fn fold(r: &[u32; 64], s: usize) -> u32 {
|
||||
let mut m = 0u32;
|
||||
let mut started = false;
|
||||
for (k, &v) in r.iter().enumerate() {
|
||||
if k == s {
|
||||
continue;
|
||||
}
|
||||
m = if started { m.rotate_left(1) ^ v } else { v };
|
||||
started = true;
|
||||
}
|
||||
r[s] ^ m
|
||||
}
|
||||
|
||||
/// The direct form: the closed sum, one rotation per term.
|
||||
pub fn direct(r: &[u32; 64], s: usize) -> u32 {
|
||||
let mut m = 0u32;
|
||||
for k in 0..64 {
|
||||
if k != s {
|
||||
m ^= r[k].rotate_left(direct_rot(k, s));
|
||||
}
|
||||
}
|
||||
r[s] ^ m
|
||||
}
|
||||
|
||||
/// One group sum of the generated form.
|
||||
#[inline(always)]
|
||||
pub fn group(r: &[u32; 64], j: usize) -> u32 {
|
||||
let mut g = 0u32;
|
||||
for k in j * GROUP..(j + 1) * GROUP {
|
||||
g ^= term(r, k);
|
||||
}
|
||||
g
|
||||
}
|
||||
|
||||
/// The generated form's query from the cached group sums `g` (stale groups give a wrong word: the plan's job).
|
||||
pub fn grouped(g: &[u32; GROUPS], r: &[u32; 64], s: usize) -> u32 {
|
||||
let total = g.iter().fold(0u32, |x, y| x ^ y);
|
||||
let j = s / GROUP;
|
||||
let mut p = g[..j].iter().fold(0u32, |x, y| x ^ y);
|
||||
for k in j * GROUP..s {
|
||||
p ^= term(r, k);
|
||||
}
|
||||
r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
|
||||
}
|
||||
|
||||
/// The prefix form's query from a running total `total` (= XOR of every `a[k]` when kept fresh).
|
||||
pub fn prefixed(total: u32, r: &[u32; 64], s: usize) -> u32 {
|
||||
let mut p = 0u32;
|
||||
for k in 0..s {
|
||||
p ^= term(r, k);
|
||||
}
|
||||
r[s] ^ p.rotate_right(1) ^ total ^ p ^ term(r, s)
|
||||
}
|
||||
|
||||
/// The known-failed form (the F05 test's wrong variant).
|
||||
pub fn wrong(r: &[u32; 64], s: usize) -> u32 {
|
||||
let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
|
||||
r[s] ^ total ^ term(r, s)
|
||||
}
|
||||
|
||||
/// The generated form's static plan: for each statement of the scheduled list, the groups to recompute just before
|
||||
/// it (non-empty only at loads). The groups entering an iteration are those written after the last load of the
|
||||
/// previous iteration's list plus every group the shadow block writes (group 0 on the shipped class); the kernel
|
||||
/// computes all eight after the register init, so iteration 0 recomputes a superset (idempotent).
|
||||
pub fn generated_plan(scheduled: &[Instr], shadow: &[Instr]) -> Vec<Vec<usize>> {
|
||||
let all: u8 = 0xff;
|
||||
let bit = |ins: &Instr| 1u8 << (ins.dst as usize / GROUP);
|
||||
let mut dirty = all;
|
||||
for ins in scheduled {
|
||||
if ins.op == Op::Load {
|
||||
dirty = 0;
|
||||
}
|
||||
dirty |= bit(ins);
|
||||
}
|
||||
let shadow_groups = shadow.iter().fold(0u8, |m, ins| m | bit(ins));
|
||||
let mut dirty = dirty | shadow_groups;
|
||||
let mut plan = Vec::with_capacity(scheduled.len());
|
||||
for ins in scheduled {
|
||||
if ins.op == Op::Load {
|
||||
plan.push((0..GROUPS).filter(|j| dirty & (1 << j) != 0).collect());
|
||||
dirty = 0;
|
||||
} else {
|
||||
plan.push(Vec::new());
|
||||
}
|
||||
dirty |= bit(ins);
|
||||
}
|
||||
plan
|
||||
}
|
||||
|
||||
/// The groups the shadow block writes (a bit per group).
|
||||
pub fn shadow_group_mask(shadow: &[Instr]) -> u8 {
|
||||
shadow.iter().fold(0u8, |m, ins| m | (1u8 << (ins.dst as usize / GROUP)))
|
||||
}
|
||||
|
||||
/// Counts of the generated plan per iteration: (loads, group recomputes) — the op count's input.
|
||||
pub fn plan_counts(plan: &[Vec<usize>], scheduled: &[Instr]) -> (usize, usize) {
|
||||
let loads = scheduled.iter().filter(|i| i.op == Op::Load).count();
|
||||
let recomputes = plan.iter().map(|v| v.len()).sum();
|
||||
(loads, recomputes)
|
||||
}
|
||||
|
||||
/// The CPU interpreter's state for a form (the differential's emulation of each kernel text): the generated
|
||||
/// form's eight cached group sums per lane, recomputed only where [`generated_plan`] says; the prefix form's running
|
||||
/// total per lane, updated after every write (main list and shadow), as the F05 text does.
|
||||
pub struct FormState {
|
||||
form: Reg64Form,
|
||||
plan: Vec<Vec<usize>>,
|
||||
groups: [[u32; LANES]; GROUPS],
|
||||
total: [u32; LANES],
|
||||
}
|
||||
|
||||
fn lane_regs(r: &[[u32; LANES]], lane: usize) -> [u32; 64] {
|
||||
std::array::from_fn(|k| r[k][lane])
|
||||
}
|
||||
|
||||
impl FormState {
|
||||
pub fn new(form: Reg64Form, plan: Vec<Vec<usize>>) -> FormState {
|
||||
FormState { form, plan, groups: [[0; LANES]; GROUPS], total: [0; LANES] }
|
||||
}
|
||||
/// After the register init (and the probe's flip): every group and the running total from the live registers.
|
||||
pub fn init(&mut self, r: &[[u32; LANES]]) {
|
||||
for lane in 0..LANES {
|
||||
let regs = lane_regs(r, lane);
|
||||
for j in 0..GROUPS {
|
||||
self.groups[j][lane] = group(®s, j);
|
||||
}
|
||||
self.total[lane] = (0..64).map(|k| term(®s, k)).fold(0, |x, y| x ^ y);
|
||||
}
|
||||
}
|
||||
/// After a write of register `d` whose value before the write was `old`: the prefix form's running total moves
|
||||
/// by the term's change; the generated form keeps its groups stale until the plan recomputes them.
|
||||
pub fn after_write(&mut self, r: &[[u32; LANES]], d: usize, old: &[u32; LANES]) {
|
||||
if self.form == Reg64Form::Prefix {
|
||||
let rot = ((63 - d) % 32) as u32;
|
||||
for lane in 0..LANES {
|
||||
self.total[lane] ^= old[lane].rotate_left(rot) ^ r[d][lane].rotate_left(rot);
|
||||
}
|
||||
}
|
||||
}
|
||||
/// The address source of the load at scheduled position `k` with source `s`, per lane, in this form.
|
||||
pub fn source(&mut self, r: &[[u32; LANES]], k: usize, s: usize) -> [u32; LANES] {
|
||||
if self.form == Reg64Form::Generated {
|
||||
for &j in &self.plan[k] {
|
||||
for lane in 0..LANES {
|
||||
let regs = lane_regs(r, lane);
|
||||
self.groups[j][lane] = group(®s, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
std::array::from_fn(|lane| {
|
||||
let regs = lane_regs(r, lane);
|
||||
match self.form {
|
||||
Reg64Form::Fold => fold(®s, s),
|
||||
Reg64Form::Direct => direct(®s, s),
|
||||
Reg64Form::Generated => grouped(&std::array::from_fn(|j| self.groups[j][lane]), ®s, s),
|
||||
Reg64Form::Prefix => prefixed(self.total[lane], ®s, s),
|
||||
Reg64Form::Wrong => wrong(®s, s),
|
||||
}
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
|
||||
fn stream(seed: u64) -> impl FnMut() -> u32 {
|
||||
let mut x = seed;
|
||||
move || {
|
||||
x = x.wrapping_add(0x9e37_79b9_7f4a_7c15);
|
||||
let mut z = x;
|
||||
z = (z ^ (z >> 30)).wrapping_mul(0xbf58_476d_1ce4_e5b9);
|
||||
z = (z ^ (z >> 27)).wrapping_mul(0x94d0_49bb_1331_11eb);
|
||||
(z ^ (z >> 31)) as u32
|
||||
}
|
||||
}
|
||||
|
||||
/// Known-failed first: the wrong form must disagree with the fold somewhere; then the three forms agree with the
|
||||
/// fold on every source over 4,096 random states and on the structured states (all zero, all ones, one bit,
|
||||
/// the init rule's registers).
|
||||
#[test]
|
||||
fn x4_forms_equal_the_fold_and_the_wrong_form_is_refused() {
|
||||
let mut next = stream(0x1505_0004);
|
||||
let mut wrong_differs = 0usize;
|
||||
let mut states: Vec<[u32; 64]> = Vec::new();
|
||||
for _ in 0..4096 {
|
||||
let mut r = [0u32; 64];
|
||||
for v in r.iter_mut() {
|
||||
*v = next();
|
||||
}
|
||||
states.push(r);
|
||||
}
|
||||
states.push([0u32; 64]);
|
||||
states.push([u32::MAX; 64]);
|
||||
for b in 0..64 * 32 {
|
||||
let mut r = [0u32; 64];
|
||||
r[b / 32] = 1 << (b % 32);
|
||||
states.push(r);
|
||||
}
|
||||
let mut r = [0u32; 64];
|
||||
for k in 0..8 {
|
||||
r[k] = next();
|
||||
}
|
||||
for k in 8..64 {
|
||||
r[k] = r[k & 7].wrapping_mul(0x9e37_79b9).wrapping_add(k as u32);
|
||||
}
|
||||
states.push(r);
|
||||
for r in &states {
|
||||
let g: [u32; GROUPS] = std::array::from_fn(|j| group(r, j));
|
||||
let total = (0..64).map(|k| term(r, k)).fold(0, |x, y| x ^ y);
|
||||
for s in 0..64 {
|
||||
let want = fold(r, s);
|
||||
if wrong(r, s) != want {
|
||||
wrong_differs += 1;
|
||||
}
|
||||
assert_eq!(direct(r, s), want, "direct, source r{s}");
|
||||
assert_eq!(grouped(&g, r, s), want, "generated, source r{s}");
|
||||
assert_eq!(prefixed(total, r, s), want, "prefix, source r{s}");
|
||||
}
|
||||
}
|
||||
assert!(wrong_differs > 0, "the known-failed form must be refused");
|
||||
}
|
||||
}
|
||||
|
|
@ -581,6 +581,10 @@ fn interpret_warp_core(
|
|||
// the iteration's statements: the drawn program, or its interleaved two-window form under reg64
|
||||
let scheduled = program.scheduled();
|
||||
let address_mix = program.address_mix();
|
||||
// X4: a byte-identical form of the address mix beside the definition (crate::reg64form), off by default
|
||||
let cpu_form = crate::reg64form::cpu_form();
|
||||
let form_on = address_mix && cpu_form != crate::reg64form::Reg64Form::Fold;
|
||||
let mut fs = crate::reg64form::FormState::new(cpu_form, if form_on { crate::reg64form::generated_plan(&scheduled, &program.shadow) } else { Vec::new() });
|
||||
let mut items_derived = 0usize;
|
||||
let mut idx = [0u32; LANES];
|
||||
let mut val = [0u32; LANES];
|
||||
|
|
@ -606,9 +610,15 @@ fn interpret_warp_core(
|
|||
}
|
||||
}
|
||||
}
|
||||
if it == 0 && form_on {
|
||||
// X4: the form's state from the registers as iteration 0 sees them (after the init and any probe flip)
|
||||
fs.init(&r);
|
||||
}
|
||||
let sel = r[0];
|
||||
for ins in &scheduled {
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
|
||||
for (k, ins) in scheduled.iter().enumerate() {
|
||||
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
|
||||
let ovr = if form_on && ins.op == Op::Load { Some(fs.source(&r, k, ins.src as usize)) } else { None };
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, ovr.as_ref());
|
||||
if it == 0 && ins.op == Op::Load {
|
||||
if let Some(pr) = probe.as_deref_mut() {
|
||||
if !pr.seen_first_load {
|
||||
|
|
@ -625,12 +635,19 @@ fn interpret_warp_core(
|
|||
r[d][lane] = m.rmw(&program.seed, base_nonce, lane, slot, r[d][lane]);
|
||||
}
|
||||
}
|
||||
if form_on {
|
||||
fs.after_write(&r, ins.dst as usize, &old);
|
||||
}
|
||||
}
|
||||
// Latency-shadow block (Counter ASIC 3.0 item 8): the block runs `reps` times after instruction 63 with the
|
||||
// iteration's `sel`; it is empty on every class without a shadow, so version 2 and class v3 run nothing here.
|
||||
for _ in 0..program.shadow_reps() {
|
||||
for ins in &program.shadow {
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix);
|
||||
let old = if form_on { r[ins.dst as usize] } else { [0u32; LANES] };
|
||||
step(ins, &mut r, &sel, geom, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived, address_mix, None);
|
||||
if form_on {
|
||||
fs.after_write(&r, ins.dst as usize, &old);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -668,6 +685,7 @@ fn step(
|
|||
val: &mut [u32; LANES],
|
||||
items_derived: &mut usize,
|
||||
address_mix: bool,
|
||||
src_override: Option<&[u32; LANES]>,
|
||||
) {
|
||||
let d = ins.dst as usize;
|
||||
let a = ins.src as usize;
|
||||
|
|
@ -679,6 +697,11 @@ fn step(
|
|||
if !address_mix {
|
||||
return r[a][lane];
|
||||
}
|
||||
// X4 (1.5x programme): a byte-identical form computed by the caller; never set unless the differential's
|
||||
// `--reg64-cpu-form` names a form other than the fold (crate::reg64form)
|
||||
if let Some(o) = src_override {
|
||||
return o[lane];
|
||||
}
|
||||
let mut m = 0u32;
|
||||
let mut started = false;
|
||||
for k in 0..r.len() {
|
||||
|
|
|
|||
33
tools/1p5x/x4/arith.py
Normal file
33
tools/1p5x/x4/arith.py
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
#!/usr/bin/env python3
|
||||
"""X4 (1.5x programme): r_new = r0 * g / a from the GPU pairs (gpu_rows.py output) and the chip rows (chip_rows.py
|
||||
output). g: the card's joules per hash with the form over the frozen text's, the mean of the two same-session passes.
|
||||
a: the specialist's machine energy with a form over the reference, at the adversary lane's 1.528 microjoules (N5, GDDR7
|
||||
board), two references: (fold) a specialist that implements the frozen literal fold, (model) the served machine, which
|
||||
carries no address-mix term. Each side picks its cheapest form on its own; the per-form rows (both sides on one form) are
|
||||
printed for the record. Usage: arith.py <gpu-rows.txt> <chip-rows.txt> [r0 ...] (default r0 2.0, 1.9, 2.1)."""
|
||||
import re, sys
|
||||
gtxt, ctxt = open(sys.argv[1]).read(), open(sys.argv[2]).read()
|
||||
r0s = [float(x) for x in sys.argv[3:]] or [2.0, 1.9, 2.1]
|
||||
M = 1528.0
|
||||
g = {m.group(1).replace("x4-", ""): float(m.group(2)) for m in re.finditer(r"^pair\t(x4-\S+)\t.*\t([0-9.]+)$", gtxt, re.M)}
|
||||
chip = {}
|
||||
for line in ctxt.splitlines():
|
||||
p = line.split("\t")
|
||||
if len(p) >= 7 and re.match(r"[\d.]+ [\d.]+ [\d.]+$", p[5]):
|
||||
chip[p[0].split(" (")[0]] = (float(p[5].split()[1]), float(p[6].split()[1]))
|
||||
fold_s, fold_d = chip["fold"]
|
||||
print("form\tg\ta vs fold (slot, datapath)\ta vs model (slot, datapath)\tr_new at r0 2.0, same form both sides (vs fold slot, dp; vs model slot, dp)")
|
||||
for k in ("direct", "generated", "prefix", "grouped incremental"):
|
||||
s, d = chip[k]
|
||||
gg = g.get(k, 1.0)
|
||||
af = ((M + s) / (M + fold_s), (M + d) / (M + fold_d)); am = ((M + s) / M, (M + d) / M)
|
||||
print(f"{k}\t{gg:.4f}{'' if k in g else ' (no GPU text)'}\t{af[0]:.4f}, {af[1]:.4f}\t{am[0]:.4f}, {am[1]:.4f}\t" + ", ".join(f"{2.0*gg/a:.3f}" for a in (*af, *am)))
|
||||
gk = min(g, key=g.get); ck = min((k for k in chip if k != "fold"), key=lambda k: chip[k][0])
|
||||
s, d = chip[ck]
|
||||
print(f"\nbest pair: the card on '{gk}' (g {g[gk]:.4f}), the specialist on '{ck}'")
|
||||
for r0 in r0s:
|
||||
out = []
|
||||
for lab, a in (("vs fold slot", (M + s) / (M + fold_s)), ("vs fold datapath", (M + d) / (M + fold_d)), ("vs model slot", (M + s) / M), ("vs model datapath", (M + d) / M)):
|
||||
out.append(f"{lab}: a {a:.4f} r_new {r0 * g[gk] / a:.3f}")
|
||||
print(f"r0 {r0}: " + "; ".join(out))
|
||||
print("\nthe yardstick: from 2.0, 1.5 needs g / a = 0.75")
|
||||
102
tools/1p5x/x4/chip_rows.py
Normal file
102
tools/1p5x/x4/chip_rows.py
Normal file
|
|
@ -0,0 +1,102 @@
|
|||
#!/usr/bin/env python3
|
||||
"""X4 (1.5x programme): the chip-side cost of each byte-identical reg64c address-mix form, counted from the exported
|
||||
kernel texts of the frozen object and priced with the adversary lane's calibrated constants (its message of 09:4x UK,
|
||||
9 October 2026, on class-v6-adversary 43c9f7cd8 tools/chip-model/mf/: e_op 6.55 pJ per lane-op at N5, band 6.01 to
|
||||
7.77; an xor-rotate that does not pass the slot's macro read about 1.0 pJ; e_rf 3.5 pJ per 256-bit macro access shared by
|
||||
8 lanes, band 2.0 to 7.0; flop state 0.03 pJ per bit written; the slot reads 3 and writes 1 window register per
|
||||
instruction already; the chip's shadow 0.672 microjoules and the GDDR7 machine 1.528 microjoules per hash at N5).
|
||||
Counts per hash per lane: X = xor or rotate-xor ops of the mix, A = window reads beyond the slot's own, F = flop bits
|
||||
written for the form's state. Two pricings: 'slot' (each mix op a full lane-op, the adversary's literal-fold row) and
|
||||
'datapath' (each mix op an xor at 1.0 pJ, the running-total row). Usage: chip_rows.py <ex dir with fold/ generated/
|
||||
prefix/ direct/> [--tsv out.tsv]. Modelled, no chip measured."""
|
||||
import re, sys
|
||||
|
||||
EX = sys.argv[1]
|
||||
ITS, REPS = 8, 27
|
||||
E_OP = {"lo": 6.01, "c": 6.55, "hi": 7.77}
|
||||
E_X_DP = 1.0
|
||||
E_RF = {"lo": 2.0, "c": 3.5, "hi": 7.0}
|
||||
E_FLOP_BIT = 0.03
|
||||
SHADOW_UJ, MACHINE_UJ = 0.672, 1.528
|
||||
|
||||
def loop_body(path):
|
||||
t = open(path).read()
|
||||
k = t.index("__global__ void igneum_hash(")
|
||||
t = t[k:]
|
||||
a = t.index("for (uint32_t it = 0u;")
|
||||
b = t.index("latency-shadow block", a)
|
||||
c = t.index("for (uint32_t sh = 0u;", b)
|
||||
d = t.index("\n }\n", c)
|
||||
return t[a:b], t[c:d], t[:a]
|
||||
|
||||
def terms(expr):
|
||||
return len(re.findall(r"rotl_imm\(r\d+, \d+u\)|\br\d+\b|\bg\d\b", expr))
|
||||
|
||||
def writes(body):
|
||||
return [int(m.group(1)) for m in re.finditer(r"^\s+r(\d+) = .*//\s*s?\d+ \w+$", body, re.M)]
|
||||
|
||||
rows = []
|
||||
main_f, shadow_f, _ = loop_body(f"{EX}/fold/kernel.cu")
|
||||
loads_per_it = len(re.findall(r"// \d+ load", main_f))
|
||||
main_w = writes(main_f)
|
||||
shadow_w = writes(shadow_f)
|
||||
assert all(d < 8 for d in shadow_w), "a shadow write outside r0..r7"
|
||||
L = loads_per_it * ITS
|
||||
# fold and direct: 63 terms, 63 reads, 63 (fold: rotl(m,1)^r) or 62 (tree) ops per load
|
||||
rows.append(("fold (frozen)", 63 * L, 63 * L, 0, 0, "the 64 x 32-bit window only", "63 window reads per load"))
|
||||
rows.append(("direct", 62 * L, 63 * L, 0, 0, "the window only", "63 window reads per load (a tree: depth 6, same reads)"))
|
||||
# generated: parse each load's statement line
|
||||
gm, _, ginit = loop_body(f"{EX}/generated/kernel.cu")
|
||||
X = A = F = 0
|
||||
for line in gm.splitlines():
|
||||
if "S = " not in line:
|
||||
continue
|
||||
n_groups = len(re.findall(r"\bg\d = \(", line))
|
||||
X += n_groups * 7; A += n_groups * 8; F += n_groups * 32
|
||||
p = re.search(r"p_ = (.*?); m =", line).group(1)
|
||||
pt = terms(p); pr = len(re.findall(r"\br\d+\b", p))
|
||||
X += 7 + max(pt - 1, 0) + 3
|
||||
A += pr
|
||||
X *= ITS; A *= ITS; F *= ITS
|
||||
rows.append(("generated (GPU text: recompute at load)", X, A, F, 8 * 32, "+8 x 32-bit group sums per lane (32 B, flops)", "group recomputes read 8 registers each; the in-group partial reads up to 7"))
|
||||
# prefix (F05 text): every write moves S; per load p_ over the first s terms
|
||||
pm, ps, _ = loop_body(f"{EX}/prefix/kernel.cu")
|
||||
nw = len(writes(pm)) * ITS + len(writes(ps)) * REPS * ITS
|
||||
X = 2 * nw; F = 32 * nw; A = 0
|
||||
for line in pm.splitlines():
|
||||
m = re.search(r"p_ = (.*?); m =", line)
|
||||
if m:
|
||||
pt = terms(m.group(1)); X += (max(pt - 1, 0) + 3) * ITS; A += len(re.findall(r"\br\d+\b", m.group(1))) * ITS
|
||||
rows.append(("prefix (F05 text: running S on every write)", X, A, F, 32, "+1 x 32-bit running total per lane (flops)", "the old value of every written register (main and shadow) rotated into S"))
|
||||
# the chip's best: group sums 1..7 kept on main-program writes (dst >= 8), group 0 recomputed at each load
|
||||
# (the shadow's 55,296 writes land in r0..r7 only, so they move nothing kept)
|
||||
upd = sum(1 for d in main_w if d >= 8) * ITS
|
||||
X = 2 * upd; F = 32 * upd; A = 0
|
||||
for line in gm.splitlines():
|
||||
m = re.search(r"p_ = (.*?); m =", line)
|
||||
if m:
|
||||
p = m.group(1)
|
||||
X += (7 + 7 + max(terms(p) - 1, 0) + 3) * ITS
|
||||
A += (8 + len(re.findall(r"\br\d+\b", p))) * ITS
|
||||
F += 32 * ITS
|
||||
rows.append(("grouped incremental (chip only, by the same identity)", X, A, F, 8 * 32, "+8 x 32-bit group sums per lane (32 B)", "groups 1..7 move on base writes to r8..r63; group 0 recomputed at each load (8 reads)"))
|
||||
|
||||
def price(X, A, F, pr, b):
|
||||
e_x = E_OP[b] if pr == "slot" else E_X_DP
|
||||
return (X * e_x + A * E_RF[b] / 8 + F * E_FLOP_BIT) / 1000.0 # nJ
|
||||
|
||||
out = []
|
||||
hdr = "form\tmix ops X\textra reads A\tflop bits F\tstate bits per lane\tslot nJ (lo c hi)\tdatapath nJ (lo c hi)\tstate\tports"
|
||||
out.append(hdr)
|
||||
for name, X, A, F, sb, state, ports in rows:
|
||||
s = [price(X, A, F, "slot", b) for b in ("lo", "c", "hi")]
|
||||
d = [price(X, A, F, "dp", b) for b in ("lo", "c", "hi")]
|
||||
out.append(f"{name}\t{X}\t{A}\t{F}\t{sb}\t{s[0]:.1f} {s[1]:.1f} {s[2]:.1f}\t{d[0]:.1f} {d[1]:.1f} {d[2]:.1f}\t{state}\t{ports}")
|
||||
print(f"# loads per hash executed {L} ({loads_per_it} per iteration x {ITS}); base writes per iteration {len(main_w)} ({sum(1 for d in main_w if d >= 8)} to r8..r63); shadow writes per pass {len(shadow_w)}, all in r0..r7")
|
||||
print("\n".join(out))
|
||||
# per-lane-op delta and a: machine energy with the form against the model's machine (which carries no mix cost)
|
||||
print("\n# a = (machine + form) / machine, machine 1.528 microjoules (N5, GDDR7 board, no mix term); per-lane-op delta over the 102,612 shadow+base lane-ops")
|
||||
for name, X, A, F, sb, *_ in rows:
|
||||
for pr in ("slot", "dp"):
|
||||
e = price(X, A, F, pr, "c")
|
||||
print(f"{name}\t{pr}\t+{e:.1f} nJ\ta {(MACHINE_UJ*1000 + e)/(MACHINE_UJ*1000):.4f}\tper lane-op +{e*1000/102612:.3f} pJ\tof the shadow +{100*e/(SHADOW_UJ*1000):.1f} percent")
|
||||
84
tools/1p5x/x4/differential.sh
Executable file
84
tools/1p5x/x4/differential.sh
Executable file
|
|
@ -0,0 +1,84 @@
|
|||
#!/usr/bin/env bash
|
||||
# X4 (1.5x programme): the CPU differential of the reg64c address-mix forms against the frozen definition.
|
||||
# Runs on a build box (never the Mac), from the box worktree root holding igneum-pow/ (built --release) and in/:
|
||||
# in/node1-state.igsd1 (sha256 abb58003...), in/state-epoch2.igsd1 (f36e6bba...),
|
||||
# in/ref0{1,2,3}/{ref-D.txt,ref-D1.txt,job-context.json} (build-1:/srv/artefacts/tas/same-work-20261008-0N/).
|
||||
# Order: the known-failed form first (it must disagree on every reg64c context, or the test is void), then the
|
||||
# forms fold, direct, generated and prefix must equal the same-work references on every sampled nonce, then the
|
||||
# fuzz set (random epoch, era and prehash on the class v6 string) where each form must equal the fold.
|
||||
# Usage: tools/1p5x/x4/differential.sh <out dir> [count per window, default 4096] [fuzz seeds, default 32]
|
||||
set -u
|
||||
OUT=${1:?out dir}; N=${2:-4096}; FZ=${3:-32}
|
||||
B=igneum-pow/target/release/igneum-pow
|
||||
mkdir -p "$OUT"
|
||||
PRE=0000000000000000000000000000000000000000000000000000000000000001
|
||||
G=edc4fa844da9dc98d37e965176f6558a31560e40502ab3ae5491b21aaaabfb07
|
||||
CS=af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3
|
||||
V5E=3c3fab434f7fd894ce6db0b09f298c3865726253e4fc68fd77acd163ccea8221
|
||||
V5ERA=7c36b83374a673e990213be462509dcb08bcfc85144306aa9517cf3ad66faf6e
|
||||
day() { printf '69676e65756d2d6461792f%s' "$(python3 -c "import struct,sys; print(struct.pack('<Q', int(sys.argv[1])).hex())" "$1")"; }
|
||||
args_for() { # context day-index
|
||||
case $1 in
|
||||
01) echo "--epoch-hex $G --day-hex $(day $2) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$G --era-widths 4 --state in/node1-state.igsd1" ;;
|
||||
02) echo "--epoch-hex $CS --day-hex $(day $2) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$G --era-widths 4 --state in/node1-state.igsd1" ;;
|
||||
03) echo "--epoch-hex $V5E --day-hex $(day $2) --program-class v5 --era-hex $V5ERA --state in/state-epoch2.igsd1" ;;
|
||||
esac
|
||||
}
|
||||
# windows: (context, day index offset, ref file, start nonce)
|
||||
JOBS=$OUT/jobs.txt; : > "$JOBS"
|
||||
for c in 01 02 03; do
|
||||
d0=$( [ $c = 03 ] && echo 20734 || echo 20730 )
|
||||
for form in wrong fold direct generated prefix; do
|
||||
for w in "D 0" "D $((1572864 - N))" "D1 1572864" "D1 $((3145728 - N))"; do
|
||||
set -- $w; dd=$([ $1 = D ] && echo $d0 || echo $((d0 + 1)))
|
||||
echo "ctx $c $form $1 $2 $dd" >> "$JOBS"
|
||||
done
|
||||
done
|
||||
done
|
||||
for i in $(seq 0 $((FZ - 1))); do
|
||||
for form in wrong fold direct generated prefix; do echo "fuzz $i $form" >> "$JOBS"; done
|
||||
done
|
||||
run_job() {
|
||||
set -- $1
|
||||
if [ "$1" = ctx ]; then
|
||||
local c=$2 form=$3 ref=$4 start=$5 dd=$6
|
||||
local f=$OUT/ctx$c-$form-$ref-$start.txt
|
||||
$B hash-bound $(args_for $c $dd) --prehash $PRE --nonce $start --count $N --reg64-cpu-form $form > $f 2>$f.err
|
||||
local lineno
|
||||
[ "$ref" = D ] && lineno=$((start + 1)) || lineno=$((start - 1572864 + 1))
|
||||
if tail -n +$lineno in/ref$c/ref-$ref.txt | head -n $N | cmp -s - $f; then echo "ctx$c $form $ref@$start AGREE"; else echo "ctx$c $form $ref@$start DISAGREE"; fi
|
||||
else
|
||||
local i=$2 form=$3
|
||||
local h=$(printf 'x4-fuzz-%d' $i | sha256sum | cut -c1-64)
|
||||
local era=$(printf 'x4-era-%d' $i | sha256sum | cut -c1-64)
|
||||
local pre=$(printf 'x4-pre-%d' $i | sha256sum | cut -c1-64)
|
||||
local nonce=$(( 0x$(printf 'x4-nonce-%d' $i | sha256sum | cut -c1-6) * 32 ))
|
||||
$B hash-bound --epoch-hex $h --day-hex $(day 20730) --class mx8+sh256x27+state+reg64c+fold+rw --era 0:$era --era-widths 4 --state in/node1-state.igsd1 --prehash $pre --nonce $nonce --count 1024 --reg64-cpu-form $form > $OUT/fuzz$i-$form.txt 2>$OUT/fuzz$i-$form.txt.err
|
||||
echo "fuzz$i $form DONE"
|
||||
fi
|
||||
}
|
||||
export -f run_job args_for day; export B OUT N PRE G CS V5E V5ERA
|
||||
xargs -P ${PAR:-24} -I{} bash -c 'run_job "{}"' < "$JOBS" > "$OUT/runs.txt"
|
||||
# fuzz verdicts against the fold
|
||||
for i in $(seq 0 $((FZ - 1))); do
|
||||
for form in wrong direct generated prefix; do
|
||||
if cmp -s $OUT/fuzz$i-fold.txt $OUT/fuzz$i-$form.txt; then echo "fuzz$i $form AGREE"; else echo "fuzz$i $form DISAGREE"; fi
|
||||
done
|
||||
done >> "$OUT/runs.txt"
|
||||
grep -v DONE "$OUT/runs.txt" | sort > "$OUT/verdicts.txt"
|
||||
# the verdict: known-failed refused on every reg64c window and fuzz seed; every other form agrees everywhere;
|
||||
# context 03 (class v5, no reg64) is the no-op control: every form, the wrong one too, agrees with the reference
|
||||
python3 - "$OUT/verdicts.txt" <<'PY' | tee "$OUT/VERDICT"
|
||||
import sys, collections
|
||||
rows=[l.split() for l in open(sys.argv[1])]
|
||||
bad=[]; t=collections.Counter()
|
||||
for key, form, *rest in rows:
|
||||
v=rest[-1]; t[(form,v)]+=1
|
||||
reg64 = not key.startswith("ctx03")
|
||||
want = "DISAGREE" if (form=="wrong" and reg64) else "AGREE"
|
||||
if v!=want: bad.append(" ".join([key,form]+rest))
|
||||
print("tally", dict(t))
|
||||
print("known-failed refused on every reg64c window and seed:", all(r[-1]=="DISAGREE" for r in rows if r[1]=="wrong" and not r[0].startswith("ctx03")))
|
||||
print("VERDICT", "EQUIVALENT" if not bad else "FAIL", "mismatches", len(bad))
|
||||
for b in bad[:20]: print(" ", b)
|
||||
PY
|
||||
43
tools/1p5x/x4/gpu_rows.py
Normal file
43
tools/1p5x/x4/gpu_rows.py
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
#!/usr/bin/env python3
|
||||
"""X4 (1.5x programme): the GPU rows of a pod-x4.sh run (the hash lane's recipe, build-1:/srv/artefacts/1p5x/
|
||||
gpu-row-recipe.md sha cbab453c: rate = the worker's own mhs=, watts = mean power.draw from 8 s in to the end of the
|
||||
timed dispatches, nJ per hash = W / MH/s x 1,000, check=PASS and the fingerprint gate the row; pairs inside one
|
||||
session). Usage: gpu_rows.py <pod out dir> <out-run.log>. Prints the per-run rows, then each form against the frozen
|
||||
pack: pass 1 against run 1, pass 2 against run 8 (the order A B C D D C B A), and the mean of the two."""
|
||||
import re, sys, glob, os, statistics as st
|
||||
|
||||
d, runlog = sys.argv[1], sys.argv[2]
|
||||
times = {m.group(1): (int(m.group(2)), int(m.group(3))) for m in re.finditer(r"RESULT run (\S+) rc=0 secs=\d+ t0=(\d+) t1=(\d+)", open(runlog).read())}
|
||||
rows = {}
|
||||
for name, (t0, t1) in sorted(times.items()):
|
||||
log = open(f"{d}/bench-{name}.log").read()
|
||||
r = re.search(r"^RESULT (.*)$", log, re.M).group(1)
|
||||
f = dict(kv.split("=", 1) for kv in r.split() if "=" in kv)
|
||||
w, clk, util = [], [], []
|
||||
for line in open(f"{d}/smi-{name}.csv"):
|
||||
p = line.strip().split(",")
|
||||
if len(p) < 5 or not p[1].replace(".", "").isdigit():
|
||||
continue
|
||||
t = int(p[0])
|
||||
if t0 + 8 <= t <= t1:
|
||||
w.append(float(p[1])); clk.append(float(p[2])); util.append(float(p[3]))
|
||||
mhs = float(f["mhs"]); W = st.mean(w)
|
||||
rows[name] = dict(pack=name.split("-", 1)[1], mhs=mhs, W=W, nj=W / mhs * 1000, fp=f["fingerprint"], check=f["check"], regs=f["regs"], bps=f["blocks_per_sm"], sm=st.mean(clk), util=st.mean(util), n=len(w))
|
||||
print("run\tpack\tMH/s\tW\tnJ per hash\tsm MHz\tutil\tsamples\tregs\tblocks/SM\tfingerprint\tcheck")
|
||||
for k, r in rows.items():
|
||||
print(f"{k}\t{r['pack']}\t{r['mhs']:.3f}\t{r['W']:.1f}\t{r['nj']:.0f}\t{r['sm']:.0f}\t{r['util']:.0f}\t{r['n']}\t{r['regs']}\t{r['bps']}\t{r['fp']}\t{r['check']}")
|
||||
ks = list(rows)
|
||||
frozen = [k for k in ks if k.endswith("hl-v6-all")]
|
||||
print("\npair\tform\tpass 1 rate %\tpass 1 J/hash %\tpass 2 rate %\tpass 2 J/hash %\tmean rate %\tmean J/hash %\tg (J/hash ratio)")
|
||||
f1, f2 = rows[frozen[0]], rows[frozen[-1]]
|
||||
aa_r = 100 * (f2["mhs"] / f1["mhs"] - 1); aa_e = 100 * (f2["nj"] / f1["nj"] - 1)
|
||||
print(f"A/A\thl-v6-all run 8 vs run 1\t{aa_r:+.2f}\t{aa_e:+.2f}\t\t\t\t\t")
|
||||
for form in ("x4-direct", "x4-generated", "x4-prefix"):
|
||||
rs = [k for k in ks if k.endswith(form)]
|
||||
if len(rs) < 2:
|
||||
continue
|
||||
a, b = rows[rs[0]], rows[rs[1]]
|
||||
p1r, p1e = 100 * (a["mhs"] / f1["mhs"] - 1), 100 * (a["nj"] / f1["nj"] - 1)
|
||||
p2r, p2e = 100 * (b["mhs"] / f2["mhs"] - 1), 100 * (b["nj"] / f2["nj"] - 1)
|
||||
g = ((a["nj"] / f1["nj"]) + (b["nj"] / f2["nj"])) / 2
|
||||
print(f"pair\t{form}\t{p1r:+.2f}\t{p1e:+.2f}\t{p2r:+.2f}\t{p2e:+.2f}\t{(p1r+p2r)/2:+.2f}\t{(p1e+p2e)/2:+.2f}\t{g:.4f}")
|
||||
28
tools/1p5x/x4/pod-x4.sh
Executable file
28
tools/1p5x/x4/pod-x4.sh
Executable file
|
|
@ -0,0 +1,28 @@
|
|||
#!/usr/bin/env bash
|
||||
# X4 (1.5x programme) on one rented card: same-session pairs of the frozen pack against the three alternative
|
||||
# packs, stock clocks, the gen-6 worker --bench (250 x 2^24, block-warps 1, the pack self-test first: check=PASS and
|
||||
# the 2^24 fingerprint), nvidia-smi power.draw at 1 Hz for each run. Order A B C D D C B A (the second pass reversed,
|
||||
# so drift and heat land on both sides of every pair). Logs under /root/x4/out. Started under /root/x4/pids/bench.pid.
|
||||
set -u
|
||||
cd /root/x4
|
||||
W=${W:-/root/x4/igneum-worker-cuda-gen6}
|
||||
mkdir -p out pids
|
||||
echo $$ > pids/bench.pid
|
||||
echo "RESULT start $(date -u +%FT%TZ) $(nvidia-smi --query-gpu=name,driver_version,power.limit,clocks.max.sm --format=csv,noheader -i 0)"
|
||||
echo "RESULT worker sha256 $(sha256sum $W | cut -c1-16)"
|
||||
ORDER=${ORDER:-"hl-v6-all x4-direct x4-generated x4-prefix x4-prefix x4-generated x4-direct hl-v6-all"}
|
||||
i=0
|
||||
for P in $ORDER; do
|
||||
i=$((i + 1)); N=$(printf '%02d-%s' $i $P)
|
||||
( while :; do echo "$(date -u +%s),$(nvidia-smi --query-gpu=power.draw,clocks.sm,utilization.gpu,temperature.gpu --format=csv,noheader,nounits -i 0 | tr -d ' ')"; sleep 1; done ) > out/smi-$N.csv 2>/dev/null &
|
||||
SMI=$!; echo $SMI > pids/smi.pid
|
||||
T0=$(date +%s)
|
||||
timeout 900 $W --bench --pack packs/$P --batches ${BATCHES:-250} --batch-log2 24 --block-warps 1 --device 0 > out/bench-$N.log 2>&1; RC=$?
|
||||
T1=$(date +%s)
|
||||
kill $SMI 2>/dev/null; rm -f pids/smi.pid
|
||||
echo "RESULT run $N rc=$RC secs=$((T1 - T0)) t0=$T0 t1=$T1"
|
||||
grep -E "^RESULT|self-test|timed dispatches" out/bench-$N.log | sed "s/^/BENCH $N | /"
|
||||
sleep ${GAP:-20}
|
||||
done
|
||||
echo "RESULT end $(date -u +%FT%TZ)"
|
||||
rm -f pids/bench.pid
|
||||
42
tools/ci/batches/mhpow-b1-20261009-01.json
Normal file
42
tools/ci/batches/mhpow-b1-20261009-01.json
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
{
|
||||
"run_id": "mhpow-b1-20261009-01",
|
||||
"manifest_sha": "13c3646e",
|
||||
"evidence_dir": "docs/analysis/mhpow/b1",
|
||||
"method": "model",
|
||||
"boxes": [
|
||||
"build-6"
|
||||
],
|
||||
"note": "B1 (R15-05), the cryptography lane of the 1.5x programme's Track B (9 October 2026): the exact CPU reference of Blocki and Smearsoll's MTP framework (eprint 2025/1456 as archived, sha256 13c3646e..., Sec 2.2, 3.2, App. C) over DRSample (ABH17 Alg. 1, eprint 2017/443 as archived, sha256 f8e08d36...), its complete verifier (named checks in the paper's order, each with a known-failed test, 17 of 17 OK on build-6), five deterministic known-answer fixtures (n 4 to 20), honest-prover rows n 12 to 24 (CPython, wall time only, no power) and six malicious provers (Dinur-Nadler eprint 2017/497 Sec 4.1, 4.3/5, 8; the paper's Attack 1 and LuckyQuery regrind). Dinur-Nadler's steering and unopened-block attacks are refused; red-node cheats are accepted with the (1-|S|/N)^k probability the paper prices; one labelling yields many accepted roots (F-4). The proven k with ABH17's constant exceeds N to about n 25 (F-3). NOT RUN until the panel reads it; this lane writes no PASS.",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "model:mhpow-b1-reference",
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b1/README.md",
|
||||
"note": "POW-05: attack fixtures A1 to A6 (tools/mhpow/b1/fixtures/attacks-n10-k16.json): A1 replay and A2 unopened block REFUSED, A3 control-block steering gain 0 with the red-node fallback accepted at (1-1/t)^k, A4 self-similarity saving refused, A5 Attack 1 accepted at (1-|S|/N)^k, A6 many accepted roots per labelling (the lottery binding BLOCKED to B2/B4, rows O-1 and O-8). POW-06: the verifier's named checks refuse malformed containers, wrong positions, skipped parents and wrong tags (test_b1.py); proof bytes and verifier oracle calls per N are exact formulas with measured rows; cold verification at rate BLOCKED to B6 (O-11).",
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"in_progress": true
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"model:mhpow-b1-reference": {
|
||||
"command": "tools/mhpow/b1/run-b1.sh <out_dir> all (a build box under its pid file; kat, attack and k-table files byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS)",
|
||||
"box_class": "build box, CPU only (build-6)",
|
||||
"fixtures": [
|
||||
"tools/mhpow/b1/fixtures/"
|
||||
],
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"coverage": {
|
||||
"POW-05": "partial: the published primitive's attack fixtures only; the lottery binding and the composed accepted-proof theorem are B2/B4's",
|
||||
"POW-06": "partial: verifier refusals and op counts in CPython; no compiled verifier, no admitted-rate timing"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
37
tools/ci/batches/mhpow-b2-20261009-01.json
Normal file
37
tools/ci/batches/mhpow-b2-20261009-01.json
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
{
|
||||
"run_id": "mhpow-b2-20261009-01",
|
||||
"manifest_sha": "13c3646e",
|
||||
"evidence_dir": "docs/analysis/mhpow/b2",
|
||||
"method": "model",
|
||||
"note": "B2, the binding spec lane of the 1.5x programme's Track B (9 October 2026): the canonical instance input for an MTP/DRSample memory-hard proof of work in Igneum's setting (328 bytes, work version 1, draft) and the obligations table O-01 to O-16 read against Blocki and Smearsoll, eprint 2025/1456 (the full PDF, sha256 13c3646e...). Reuse across template, trial, epoch, day, era, network and class object: answered by the paper's per-input soundness plus the layout. The lottery: two candidate rules FAIL with written counter-examples (re-roll through a red sink, about 1.3 x 10^6 draws per labelling at N = 2^24; free screening on chi alone); the replacement and the multi-instance, adaptive-input, constants and energy questions BLOCKED to the B4 theory lane and the node lane. Figures by tools/mhpow/b2/b2_figures.py on build-9. NOT RUN until the panel reads it; this lane writes no PASS.",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "model:mhpow-b2-binding",
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md",
|
||||
"note": "POW-05: obligations O-06 to O-11 and O-16 (grinding, chosen instance, amortisation, partial evaluation, precomputation); O-07 records two FAIL rules and B-T3 the open question. POW-06: O-11's certificate sizes as functions of DRSample's unproved constant c3 (13.6 to 194.9 MiB at lambda 256), a sensitivity table only; the verifier budget is B6's.",
|
||||
"claim_impact": "none: no public figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"in_progress": true
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"model:mhpow-b2-binding": {
|
||||
"command": "python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt (a build box under a pid file; byte-identical output, sha256 27bb414c...)",
|
||||
"box_class": "build box, CPU only (build-9)",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"coverage": {
|
||||
"POW-05": "partial: the binding obligations for the Track B work unit only; the lottery binding is BLOCKED (B-T3) and the multi-instance bound BLOCKED (B-T5)",
|
||||
"POW-06": "partial: certificate size as a formula; no verifier timing, no malformed-input cost"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
43
tools/ci/batches/mhpow-b4-20261009-01.json
Normal file
43
tools/ci/batches/mhpow-b4-20261009-01.json
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
{
|
||||
"run_id": "mhpow-b4-20261009-01",
|
||||
"manifest_sha": "12822bf5",
|
||||
"method": "model",
|
||||
"evidence_dir": "docs/analysis/mhpow/b4",
|
||||
"release_identity": {
|
||||
"commit": "branch mhpow-b4 12822bf5, landed on master at 067dca70 (the typeset docs: docs/analysis/mhpow/b4)",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: a theorem statement and an audit of published papers, no chain state read or written",
|
||||
"activation": "none (Track B lands documents and tests only)",
|
||||
"profile_hashes": "R1 2025/1456 13c3646e...; R2 2018/221 2a466b97...; R3 2017/225 29c5a9c0...; R4 2026/1024 aa6caa39...; R16 arXiv 2207.11519 ac273393...; params.py 7ac7fd48..., params.txt a98ac460..."
|
||||
},
|
||||
"claim_impact": "none: the composed accepted-proof energy statement is a draft with named proof obligations; the published constants cannot carry a 1.5x certificate (loss at least 6.6x on the generic route, at least 341x on the red-blue route); every row NOT RUN until the panel reads it",
|
||||
"reviewer": "",
|
||||
"note": "recorded by the CI steward on the coordinator's order (10:4x UK, 9 October 2026): Track B's findings as BOUND and NOT RUN rows; the cell theory:mhpow-b4 carried in map_cell_requested. NOT RUN by this lane: the steward records it only if the coordinator asks, with the cell added to the map. BLOCKED rows B4-B01 to B4-B10 in README section 12.",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "theory:mhpow-b4",
|
||||
"status": "NOT RUN",
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"note": "NOT RUN: statement and losses written; terms 2 (transfers) and the amortisation of terms 2 and 3 are open theorems; L is BLOCKED (no lower-bound certificate for any technology coefficient); X5 rows stay WITNESS (E_D)",
|
||||
"in_progress": true,
|
||||
"cases": [
|
||||
"R15-07"
|
||||
]
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"theory:mhpow-b4": {
|
||||
"command": "python3 tools/mhpow/b4/params.py > docs/analysis/mhpow/b4/params.txt (a build box under a pid file; the composed accepted-certificate energy statement's constants from the published papers R1 to R4 and R16; byte-identical output)",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"R15-07"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-07": "partial: the composed theorem's statement and the losses on the published constants; terms 2 and 3's amortisation open theorems; L BLOCKED; the panel has not read it"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
48
tools/ci/batches/r15-02-x7-20261009-01.json
Normal file
48
tools/ci/batches/r15-02-x7-20261009-01.json
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
{
|
||||
"run_id": "r15-02-x7-20261009-01",
|
||||
"manifest_sha": "6ba3f01b",
|
||||
"method": "model",
|
||||
"evidence_dir": "docs/analysis/class-v6/1p5x/x7",
|
||||
"boxes": [
|
||||
"build-9"
|
||||
],
|
||||
"release_identity": {
|
||||
"commit": "master 6ba3f01b (the X7 README; the verdict commit ca2fb6b2 and X8's rows e64eb265 cited when the landing hand lands them)",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: documents and models only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: a negative control on the memory route; no served figure moves",
|
||||
"note": "main's order through the coordinator (11:0x UK, 9 October 2026): X7's memory-route verdict recorded as a BOUND-side negative control under R15-02, NOT RUN; X8's tensor-route chip rows join when they land and the hash lane's measured card rows arrive",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "model:x7-memory-route",
|
||||
"cases": [
|
||||
"R15-02"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"in_progress": true,
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/class-v6/1p5x/x7/README.md; tools/ci/batches/adversary-20261009-x7.json",
|
||||
"note": "BOUND-side negative control (X7): f = 0.854 on the 4090 at stock, the frozen object at 8,077 nJ per hash against its read-only twin at 6,899 at the same rate (the hash lane's row, fk-x7-4090, 10:44 UK); s = 13 to 39 on the chip's GDDR7, HBM3 and near-memory (the adversary lane's X7 rows): no read-dominated design reaches 1.5x or 1.25x at any f, because the card's random-read path is its least efficient part against a chip. The chip figures are modelled (BOUND); the card figure is a WITNESS on a named rented card. X8's chip side (every int8 mix raising the ratio against a systolic array; the dp4a-only cells stopping at 1.54x) is the tensor route's first witness row set, pending the hash lane's measured card rows; recorded here when e64eb265 lands. R15-02 (no device or whole-machine boundary mismatch) stays NOT RUN until read",
|
||||
"claim_impact": "none"
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"model:x7-memory-route": {
|
||||
"command": "the X7 memory-route read: docs/analysis/class-v6/1p5x/x7 (the chip model's s on GDDR7, HBM3 and near-memory by tools/1p5x/x5/sweep.py on a build box under a pid file) against the hash lane's read-only twin row on a rented card at stock (the frozen object and its read-only twin, nvidia-smi beside it)",
|
||||
"box_class": "a build box for the model; a rented card for the twin row",
|
||||
"fixtures": [
|
||||
"F0"
|
||||
],
|
||||
"cases": [
|
||||
"R15-02"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-02": "partial: the memory route's f and s only; the component power and traffic model and its sensitivity are X0's and X5's rows"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
49
tools/ci/batches/r15-int8-20261009-01.json
Normal file
49
tools/ci/batches/r15-int8-20261009-01.json
Normal file
|
|
@ -0,0 +1,49 @@
|
|||
{
|
||||
"run_id": "r15-int8-20261009-01",
|
||||
"manifest_sha": "d799c086",
|
||||
"method": "model",
|
||||
"evidence_dir": "docs/plans/igneum-2.0-master/1p5x/research-plan",
|
||||
"boxes": [],
|
||||
"release_identity": {
|
||||
"commit": "master d799c086; the class is cut by the research lane behind a research flag, not in any release",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: documents and models only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: a research class behind a flag; no served figure moves and nothing activates",
|
||||
"note": "main's order through the coordinator (11:0x UK, 9 October 2026): the cells for the int8-dominated class opened, every row NOT RUN until read; the lanes land their own batches on these cells with map_cell_requested",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "class:int8",
|
||||
"cases": [
|
||||
"R15-03",
|
||||
"R15-04"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"in_progress": true,
|
||||
"method": "model",
|
||||
"evidence": "docs/plans/igneum-2.0-master/1p5x/research-plan/packages.json; docs/analysis/class-v6/1p5x/x1/README.md",
|
||||
"note": "opened, nothing measured yet: the int8-dominated class behind a research flag at three weights (int8-50, int8-75, int8-90) and the ARX-only points (arx-16, arx-32); the research lane cuts the class, the hash lane measures the card rows, the adversary lane the chip rows, the census instruments read it; R15-03 (layer-8-off control and held-out cache curves) and R15-04 (compaction, exact-fold alternatives, tuning) take their rows from those batches",
|
||||
"claim_impact": "none"
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"class:int8": {
|
||||
"command": "the int8-dominated research class: cut behind the research flag by the research lane at int8-50, int8-75, int8-90 and arx-16, arx-32 (igneum-pow export with the class string, on a build box); the hash lane's card rows in the P04 form (tools/1p5x/x1/gpu-pairs.sh, gpu-rows.py); the adversary lane's chip rows (tools/1p5x/x5/sweep.py, tools/1p5x/x8/mac.py); the census instruments (igneum-pow addrsite, x1cache)",
|
||||
"box_class": "build box for the cut and the census; rented pods for the card rows; a build box for the chip model",
|
||||
"fixtures": [
|
||||
"F0"
|
||||
],
|
||||
"cases": [
|
||||
"R15-03",
|
||||
"R15-04"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-03": "partial: the held-out cache curves of each weight against the frozen control; the layer-8-off control is X1's row",
|
||||
"R15-04": "partial: byte agreement and accepted-work savings of each weight's fold; X2 to X4's rows carry the rest"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
46
tools/ci/batches/r15-track-b-20261009-01.json
Normal file
46
tools/ci/batches/r15-track-b-20261009-01.json
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
{
|
||||
"run_id": "r15-track-b-20261009-01",
|
||||
"manifest_sha": "067dca70",
|
||||
"method": "model",
|
||||
"evidence_dir": "docs/analysis/mhpow",
|
||||
"boxes": [
|
||||
"build-9"
|
||||
],
|
||||
"release_identity": {
|
||||
"commit": "master 067dca70 (B2 eb999f0e, B4 12822bf5, B6 1ab735be landed); B1 e9f94df6 and B3 land by 11:45 UK and are recorded then under R15-05 and R15-06",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: documents and tests only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": "R1 2025/1456 13c3646e...; params.py 7ac7fd48...; params.txt a98ac460..."
|
||||
},
|
||||
"claim_impact": "none: no served figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"note": "the coordinator's order (10:4x UK, 9 October 2026): Track B's reproduction findings recorded as BOUND rows, NOT RUN, no pass or fail claimed for any package; every chip figure WITNESS or BOUND by the R15 suite rule",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "theory:r15-07-track-b",
|
||||
"cases": [
|
||||
"R15-07"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"in_progress": true,
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b2/README.md; docs/analysis/mhpow/b4/README.md; docs/analysis/mhpow/b4/params.txt; docs/analysis/mhpow/b4/RUNS.md; tools/mhpow/b4/params.py",
|
||||
"note": "BOUND (B4): no 1.5x certificate is reachable from the published constants; the generic route at most 0.151 of the honest prover's energy at log2 N = 22, the red-blue route losing at least 341x at rho 0.25 (docs/analysis/mhpow/b4/README.md, params.txt). FINDING (B2, obligation O-07): the two naive lottery rules FAIL with written counter-examples (the sink re-roll at log2 N + 1 calls, about 1.3 million draws per labelling at N = 2^24; free screening on chi alone), the replacement BLOCKED to B4 (B-T3) (docs/analysis/mhpow/b2/README.md). The package R15-07 (no invalid theorem composition) stays NOT RUN until the independent panel reads the composed statement; terms 2 and 3's amortisation are open theorems; L BLOCKED",
|
||||
"claim_impact": "none"
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"theory:r15-07-track-b": {
|
||||
"command": "the Track B composition read: docs/analysis/mhpow/b2 (the binding obligations O-01 to O-16, figures by tools/mhpow/b2/b2_figures.py) and docs/analysis/mhpow/b4 (the composed theorem and its constants by tools/mhpow/b4/params.py), on a build box under a pid file",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"R15-07"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-07": "partial: the statement, the obligations and the losses on published constants; the proof of terms 2 and 3, the amortisation and the panel's reading open"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
48
tools/ci/batches/r15-track-b-20261009-02.json
Normal file
48
tools/ci/batches/r15-track-b-20261009-02.json
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
{
|
||||
"run_id": "r15-track-b-20261009-02",
|
||||
"manifest_sha": "0f370527",
|
||||
"method": "model",
|
||||
"evidence_dir": "docs/analysis/mhpow/b1",
|
||||
"boxes": [
|
||||
"build-6"
|
||||
],
|
||||
"release_identity": {
|
||||
"commit": "master 0f370527 (B1 e9f94df6 landed)",
|
||||
"lockfile": "",
|
||||
"binary": "",
|
||||
"network_object": "none: documents and models only, no chain state read or written",
|
||||
"activation": "none",
|
||||
"profile_hashes": ""
|
||||
},
|
||||
"claim_impact": "none: no served figure moves; Track B's construction is not adopted and nothing activates",
|
||||
"note": "the coordinator's order (10:4x UK, 9 October 2026): Track B's reproduction findings as BOUND rows, NOT RUN, no pass or fail claimed for the package",
|
||||
"cells": [
|
||||
{
|
||||
"cell": "theory:r15-05-track-b",
|
||||
"cases": [
|
||||
"R15-05"
|
||||
],
|
||||
"status": "NOT RUN",
|
||||
"in_progress": true,
|
||||
"method": "model",
|
||||
"evidence": "docs/analysis/mhpow/b1/README.md; tools/mhpow/b1/fixtures/attacks-n10-k16.json; tools/mhpow/b1/fixtures/SHA256SUMS",
|
||||
"note": "BOUND (B1, F-3): with ABH17's proven constant the paper's challenge count k exceeds N at lambda 256 and N 2^20 (to about n 25): no practical parameter in the proven regime. FINDING (B1, F-4): one labelling yields 193 to 200 accepted roots in 200 tries at 26 oracle calls per try, so a lottery over tau is not bound to the labelling cost (fixture A6, attacks-n10-k16.json, run on build-6). The package R15-05 (no improvised sampled-memory soundness) stays NOT RUN until the independent panel reads the reference and its verifier (17 of 17 named checks with known-failed tests)",
|
||||
"claim_impact": "none"
|
||||
}
|
||||
],
|
||||
"map_cell_requested": {
|
||||
"theory:r15-05-track-b": {
|
||||
"command": "the Track B cryptography read: docs/analysis/mhpow/b1 (the exact CPU reference of the MTP framework over DRSample, its verifier and the six malicious provers) by tools/mhpow/b1/run-b1.sh <out> all on a build box under a pid file, outputs byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [
|
||||
"tools/mhpow/b1/fixtures/"
|
||||
],
|
||||
"cases": [
|
||||
"R15-05"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-05": "partial: the published primitive's reference, attacks and verifier refusals; the lottery binding (B2), the composed theorem (B4) and the panel's reading open"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -36,6 +36,9 @@ docs/analysis/class-v6/history.md
|
|||
docs/analysis/class-v6/invention.md
|
||||
docs/analysis/class-v6/mixed-fp32.md
|
||||
docs/analysis/class-v6/multi-family-adversary.md
|
||||
# 9 October 2026: the 1.5x programme X4, the reg64c implementation forms (research documents and their generators)
|
||||
docs/analysis/class-v6/1p5x/x4
|
||||
tools/1p5x/x4
|
||||
# 8 October 2026: the miner window audit (an internal design record: the founder's order, lane ids, the build plan)
|
||||
docs/design/app-audit-2026-10-08.md
|
||||
# 8 October 2026: the public shape of the pre-2.0 ledger, kept as history at the Igneum 2.0 reset (not served, not linked;
|
||||
|
|
|
|||
|
|
@ -822,6 +822,112 @@
|
|||
"coverage": {
|
||||
"TV-02": "partial: scheduled issuance on a straight chain and its reorg, two independent implementations EQUAL to the integer on devnet-4, mainnet and the TV-01 spec; paid, burned, locked, outstanding, DAG reds, the EVM ledger and duplicate records open; the independent panel has not read it"
|
||||
}
|
||||
},
|
||||
"model:mhpow-b1-reference": {
|
||||
"command": "tools/mhpow/b1/run-b1.sh <out_dir> all (a build box under its pid file; kat, attack and k-table files byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS)",
|
||||
"box_class": "build box, CPU only (build-6)",
|
||||
"fixtures": [
|
||||
"tools/mhpow/b1/fixtures/"
|
||||
],
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"coverage": {
|
||||
"POW-05": "partial: the published primitive's attack fixtures only; the lottery binding and the composed accepted-proof theorem are B2/B4's",
|
||||
"POW-06": "partial: verifier refusals and op counts in CPython; no compiled verifier, no admitted-rate timing"
|
||||
}
|
||||
},
|
||||
"theory:r15-05-track-b": {
|
||||
"command": "the Track B cryptography read: docs/analysis/mhpow/b1 (the exact CPU reference of the MTP framework over DRSample, its verifier and the six malicious provers) by tools/mhpow/b1/run-b1.sh <out> all on a build box under a pid file, outputs byte-identical to tools/mhpow/b1/fixtures/SHA256SUMS",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [
|
||||
"tools/mhpow/b1/fixtures/"
|
||||
],
|
||||
"cases": [
|
||||
"R15-05"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-05": "partial: the published primitive's reference, attacks and verifier refusals; the lottery binding (B2), the composed theorem (B4) and the panel's reading open"
|
||||
}
|
||||
},
|
||||
"class:int8": {
|
||||
"command": "the int8-dominated research class: cut behind the research flag by the research lane at int8-50, int8-75, int8-90 and arx-16, arx-32 (igneum-pow export with the class string, on a build box); the hash lane's card rows in the P04 form (tools/1p5x/x1/gpu-pairs.sh, gpu-rows.py); the adversary lane's chip rows (tools/1p5x/x5/sweep.py, tools/1p5x/x8/mac.py); the census instruments (igneum-pow addrsite, x1cache)",
|
||||
"box_class": "build box for the cut and the census; rented pods for the card rows; a build box for the chip model",
|
||||
"fixtures": [
|
||||
"F0"
|
||||
],
|
||||
"cases": [
|
||||
"R15-03",
|
||||
"R15-04"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-03": "partial: the held-out cache curves of each weight against the frozen control; the layer-8-off control is X1's row",
|
||||
"R15-04": "partial: byte agreement and accepted-work savings of each weight's fold; X2 to X4's rows carry the rest"
|
||||
}
|
||||
},
|
||||
"model:x7-memory-route": {
|
||||
"command": "the X7 memory-route read: docs/analysis/class-v6/1p5x/x7 (the chip model's s on GDDR7, HBM3 and near-memory by tools/1p5x/x5/sweep.py on a build box under a pid file) against the hash lane's read-only twin row on a rented card at stock (the frozen object and its read-only twin, nvidia-smi beside it)",
|
||||
"box_class": "a build box for the model; a rented card for the twin row",
|
||||
"fixtures": [
|
||||
"F0"
|
||||
],
|
||||
"cases": [
|
||||
"R15-02"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-02": "partial: the memory route's f and s only; the component power and traffic model and its sensitivity are X0's and X5's rows"
|
||||
}
|
||||
},
|
||||
"model:mhpow-b2-binding": {
|
||||
"command": "python3 tools/mhpow/b2/b2_figures.py > docs/analysis/mhpow/b2/figures.txt (a build box under a pid file; byte-identical output, sha256 27bb414c...)",
|
||||
"box_class": "build box, CPU only (build-9)",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"POW-05",
|
||||
"POW-06"
|
||||
],
|
||||
"coverage": {
|
||||
"POW-05": "partial: the binding obligations for the Track B work unit only; the lottery binding is BLOCKED (B-T3) and the multi-instance bound BLOCKED (B-T5)",
|
||||
"POW-06": "partial: certificate size as a formula; no verifier timing, no malformed-input cost"
|
||||
}
|
||||
},
|
||||
"theory:mhpow-b4": {
|
||||
"command": "python3 tools/mhpow/b4/params.py > docs/analysis/mhpow/b4/params.txt (a build box under a pid file; the composed accepted-certificate energy statement's constants from the published papers R1 to R4 and R16; byte-identical output)",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"R15-07"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-07": "partial: the composed theorem's statement and the losses on the published constants; terms 2 and 3's amortisation open theorems; L BLOCKED; the panel has not read it"
|
||||
}
|
||||
},
|
||||
"theory:r15-07-track-b": {
|
||||
"command": "the Track B composition read: docs/analysis/mhpow/b2 (the binding obligations O-01 to O-16, figures by tools/mhpow/b2/b2_figures.py) and docs/analysis/mhpow/b4 (the composed theorem and its constants by tools/mhpow/b4/params.py), on a build box under a pid file",
|
||||
"box_class": "build box, CPU only",
|
||||
"fixtures": [],
|
||||
"cases": [
|
||||
"R15-07"
|
||||
],
|
||||
"coverage": {
|
||||
"R15-07": "partial: the statement, the obligations and the losses on published constants; the proof of terms 2 and 3, the amortisation and the panel's reading open"
|
||||
}
|
||||
},
|
||||
"rows:mhpow-b3-gpu-feasibility": {
|
||||
"command": "tools/mhpow/b3/build.sh && tools/mhpow/b3/test_known_failed_b1.sh <b1-kat-dir> && tools/mhpow/b3/run_rows_b1.sh <card-label> <b1-kat-dir> (on a rented GPU pod; never the Mac); python3 tools/mhpow/b3/parse_rows.py <out-dirs>",
|
||||
"box_class": "rented GPU pod (RTX 5090, RTX 4090), stock clocks",
|
||||
"fixtures": [
|
||||
"F0"
|
||||
],
|
||||
"cases": [
|
||||
"POW-01",
|
||||
"POW-06"
|
||||
],
|
||||
"coverage": {
|
||||
"POW-01": "partial: the Track B research candidate's CUDA backend against an independent CPU reference (B1) only; nothing about the shipped v6 evaluator",
|
||||
"POW-06": "partial: verifier time per proof for the Track B candidate at k = 64 on one CPU; no malformed-input or rate budget"
|
||||
}
|
||||
}
|
||||
},
|
||||
"not_run": {
|
||||
|
|
@ -831,7 +937,6 @@
|
|||
"GPU-04": "the memory-clock ladder has no harness tonight: the project's own rig mines nothing under the the earlier devnet off order",
|
||||
"GPU-06": "accepted work under ordinary connectivity needs the fault network F4",
|
||||
"GPU-07": "the sustained thermal and power soak has no harness tonight: the project's own rig mines nothing under the the earlier devnet off order",
|
||||
"POW-05": "amortised cheap winning attempts are the attack lanes' grind and era harnesses (tools/attack/f7-era, f9-grind), not in the release matrix; their rows come from those lanes",
|
||||
"ROT-03": "miner-voted bring-forward needs a vote harness on the fault network F4",
|
||||
"ROT-04": "seed-selection resistance is the census harness (the class v6 invention lane), not yet in the matrix",
|
||||
"EVM-01": "no EVM conformance-vector harness is mapped tonight; the exec suite does not run the reference test vectors",
|
||||
|
|
@ -995,12 +1100,7 @@
|
|||
"TV-31": "TV-31 (token value gate, scope CORE): no gate executed; the harness is the owner role's (Qualified counsel); a supplemental layer, never counted as independent evidence; not yet named in the map",
|
||||
"TV-32": "TV-32 (token value gate, scope LEADERSHIP CLAIM): no gate executed; the harness is the owner role's (Independent acceptance panel); a supplemental layer, never counted as independent evidence; not yet named in the map",
|
||||
"R15-01": "R15-01 (1.5x programme package): no package executed; the harness is the lane's (X0); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-02": "R15-02 (1.5x programme package): no package executed; the harness is the lane's (X0, X5); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-03": "R15-03 (1.5x programme package): no package executed; the harness is the lane's (X1); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-04": "R15-04 (1.5x programme package): no package executed; the harness is the lane's (X2, X3, X4); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-05": "R15-05 (1.5x programme package): no package executed; the harness is the lane's (B1); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-06": "R15-06 (1.5x programme package): no package executed; the harness is the lane's (B3); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-07": "R15-07 (1.5x programme package): no package executed; the harness is the lane's (B2, B4); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-08": "R15-08 (1.5x programme package): no package executed; the harness is the lane's (X5, B5); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-09": "R15-09 (1.5x programme package): no package executed; the harness is the lane's (X6); its batch names the case when it lands; not yet named in the map",
|
||||
"R15-10": "R15-10 (1.5x programme package): no package executed; the harness is the lane's (B6); its batch names the case when it lands; not yet named in the map"
|
||||
|
|
|
|||
|
|
@ -12,7 +12,8 @@ Sections:
|
|||
3. Lemma 3's precondition lambda/4 >= 2 log2 q + log2 indeg and the per-pebble charge lambda - 2 log2 q - log2 indeg
|
||||
(the extractor's bound before the paper rounds it to lambda/4);
|
||||
4. Corollary 2's challenge count and the certificate size, as functions of DRSample's unproved constant c3;
|
||||
5. the lottery re-roll counter-example (obligation O-07): honest oracle calls per trial against the re-roll's.
|
||||
5. the lottery re-roll counter-example (obligation O-07): honest oracle calls per trial against the re-roll's;
|
||||
6. O-17, the fake-winner budget under B4's full-verification rule (B4-OB-LOT-1).
|
||||
|
||||
Nothing here is a measurement. Every row is arithmetic on the paper's statements (eprint 2025/1456, the copy with
|
||||
sha256 13c3646e7d85c1aa58a92914582caab5798d90cf2a3cad33e58d81d49c1d31db) and on the draft layout.
|
||||
|
|
@ -213,12 +214,34 @@ def section5():
|
|||
print(f"{ln}\t{k}\t{honest}\t{reroll}\t{honest / reroll:.3g}\t{p:.6f}")
|
||||
|
||||
|
||||
def section6():
|
||||
print()
|
||||
print("== 6. O-17: the fake-winner budget under B4's rule (trial id in chi, W = H(lot, chi, tau), winners verified in full,")
|
||||
print(" the k spot checks as the header pre-filter). A fake winner keeps ONE honest labelling and re-rolls the red sink until")
|
||||
print(" W <= target: about (log2 N + 1) / p calls per fake once the labelling exists; it passes the spot checks with (1 - 1/N)^k;")
|
||||
print(" every validator it reaches recomputes the labelling in full (2N calls, N sequential label steps) before rejecting it.")
|
||||
print(" A real winner costs 2N / p calls. p = 1 / D, D = labellings per block interval network-wide.")
|
||||
print(" (a) fakes per real block for an attacker holding share s of the honest network's oracle calls: s * 2N / (log2 N + 1)")
|
||||
print("log2_N\tshare\tfakes_per_real_block")
|
||||
for ln in (20, 24):
|
||||
n = 2 ** ln
|
||||
for share in (1e-6, 1e-4, 1e-2):
|
||||
print(f"{ln}\t{share:g}\t{share * 2 * n / (ln + 1):.3g}")
|
||||
print(" (b) attacker calls per fake / one validator's calls to reject it: (log2 N + 1) D / (2N)")
|
||||
print("log2_N\tD\tattacker_over_validator")
|
||||
for ln in (20, 24):
|
||||
n = 2 ** ln
|
||||
for d in (1e4, 1e6, 1e8):
|
||||
print(f"{ln}\t{d:g}\t{(ln + 1) * d / (2 * n):.3g}")
|
||||
|
||||
|
||||
def main():
|
||||
total = section1()
|
||||
section2(total)
|
||||
section3()
|
||||
section4()
|
||||
section5()
|
||||
section6()
|
||||
return 0
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue