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igneum-labs
dda5dedf44 Site reset to Igneum 2.0, first pass: /bench and /journey gone, no testnet, no 0.x history, the Igneum 2.0 devnet, the positioning line 
- build.mjs no longer writes bench.html, journey.html or journey.json; the three files are deleted; /bench -> /evidence and
  /journey -> /live redirects (permanent: false); nav, footer, sitemap, capture routes and the site-nav-check groups drop them;
  link-check resolves literal vercel.json redirects and lists every link that leans on one (evidence.html: /bench, another hand)
- every testnet card, column, row, notice and link removed from the pages this lane owns; release manifest: the testnet entry
  gone, network igneum-devnet-4 "Igneum 2.0 devnet", the Devnet 3 genesis, digest, vote domain and floor lines dropped
- "Devnet 3" leaves every owned page; the devnet state is one constant in build.mjs (DEVNET_STATE, 'starting' now: the nav
  pill and the homepage badge read "Igneum 2.0 devnet starting"; 'live' flips both and re-enables the nav's live read)
- no 0.x release history: screenshot alt texts say the current build, the miner page's "Current build:" keeps the data-rm
  spans without the node version; miner-bench.json keeps the current-program rows only, no Counter ASIC names, no versions;
  /miners drops the earlier-classes table, the history note and the miner-version column
- /income keeps the calculator; the testnet-era tier tables (docs/analysis/income-tiers.md) are not served
- the positioning line is the first line of the footer partial (every page), the homepage meta description's first sentence
  and the hero's sub-line; share metas (site/og/pages.mjs) carry no Devnet 3 or zkEVM
- ledger-text-check is red on two index.html pins (X2, X31: the testnet sentences), owned by the ledger hand

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:40:33 +00:00
igneum-labs
d5ba3c3a90 Merge the box master 31496f4e into release-manifest-8 (the evidence page rebuilt) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:25:22 +00:00
igneum-labs
d94c69e460 Chip text: the third review's claim statement served verbatim above the sentence on every copy; rotation named an optional improvement, not the mechanism; no threshold as the economic headline (the coexistence model owed); X35 pin added 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:18:17 +00:00
igneum-labs
31496f4ef9 Merge counter-asic-4 7e5897dc into master (gate: green on 7e5897dc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:12:06 +00:00
igneum-labs
ffd6751e7c Release manifest and the proving economics: site/release-manifest.json served at /release.json (network and chain id, source commits and fingerprints, mining class and dataset, finality rule v3, proof program ids, verifier off per P21, fees, versions per platform, the proving view, generated date); /build, /economics, /miner, /evidence and the litepaper read it at build through data-rm spans and a gate check holds the pages to it; /light, /receipt and the light client say two thirds of total weight; 4463 marked historical in older docs; dated log entries labelled historical; the evidence page's sixth label (activated) and the reference-repository wording; /economics gains "Who pays for proving": three incomes apart, the burned base fee stated, the measured 24-hour payout, the halving walk computed from emission.mjs at build, per card per hour, the two routes priced, no price 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:11:33 +00:00
igneum-labs
b0411162c0 Merge class-v6-floor-denominator-docs-3 03b7bf05 into master (gate: green on 03b7bf05, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:11:19 +00:00
igneum-labs
abf5a5a606 Chip text: the bracket serves (about 2.3x to 3.3x a node ahead, 2.0x to 2.9x node for node, approximate and provisional) in place of the provisional 2.2x to 2.4x figures, on main's order; the placed gated core row replaces it when it lands; labels, evidence row 17, X35 and the pin follow 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:10:34 +00:00
igneum-labs
c1f082c87b Merge ca3-coord-record e8f017e7 into master (gate: green on e8f017e7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:07:38 +00:00
igneum-labs
7e5897dc32 Class v6 10.0i: the adversary's re-optimised core (the gated base k 0.37 at N3, the gated window 0.50, +0.13 of k the window's honest defence; the placed ungated core +64 percent over synthesis) and the bracket the served figures sit in until the placed gated rows at 17:30 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:04:41 +00:00
igneum-labs
03b7bf05a1 Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 394da98a9 (394da98a91) for the box mirror master
 2026-10-08 15:04:38 +00:00
igneum-labs
999fec1519 Merge class-v6-floor-denominator-docs-2 8384bfc7 into master (gate: green on 8384bfc7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:03:47 +00:00
igneum-labs
e1d397e8b0 Merge the mirror's master da5e1e8a into counter-asic-4 (the coord record lane's earlier copy of class-v6-rotating-family.md superseded by this branch's) 
# Conflicts:
#	docs/design/class-v6-rotating-family.md
 2026-10-08 15:03:33 +00:00
igneum-labs
7fab675a02 Chip text: the served sentence opens "adopts the 64-register window and retains it across every rotation" (the close's 10.0h after the site audit read); the card's cost of the window labelled measured (rented 5090 and 4090 at stock, 8 October 2026); the X35 pin follows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:03:10 +00:00
igneum-labs
e8f017e766 Counter ASIC 3.0 status: the public 0.3.26 cut 5054d0ee with the 16:00 minute, the first two class v6 packs (hl-v6-fold 482dc0da, hl-v6-rw 30628f8a) an hour early, the census lane's dry PASS and its per-pack pass line, the RX 7600 read (13.88 MH/s at 113 W), lane 5's manifest order, the floor-sm amendment 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:00:15 +00:00
igneum-labs
da5e1e8a69 Merge ca3-coord-record 7fdd094a into master (gate: green on 7fdd094a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:58:07 +00:00
igneum-labs
01d2848791 Class v6: the window's card cost MEASURED (within 5 percent per load with the liveness chain, no spill); the served sentence's one word made honest (adopts, retains across every rotation); lane D's report (x16 over the verifier gate; the genesis table's 75-point spelling under test); lane C's drawn-era F8 read (the per-load class must take (c''')); lane 1's memory-clock ladder (the memory side bought one for one with the rate) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:56:22 +00:00
igneum-labs
8384bfc795 Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6ef2a4ba8 (6ef2a4ba86) for the box mirror master
 2026-10-08 14:51:28 +00:00
igneum-labs
7fdd094ab8 Counter ASIC 3.0 status: the register window's measured set on the 5090 and 4090 (at most 5 percent per load, no spill, no rate per unit of work), all five floor documents on master, lane C's drawn-era F8 row (layer 5 takes the floor), lane D's full report 3958f0d29, lane 5's served text read, the build order's amendments relayed; the 7 October public-text file marked superseded 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:50:51 +00:00
igneum-labs
308aa4a7da Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6d666ce9d (6d666ce9d6) for the box mirror master
 2026-10-08 14:49:41 +00:00
igneum-labs
3958f0d29c Merge class-v6-family-gate 4eca18c3 into master (gate: green on 4eca18c3, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:46:07 +00:00
igneum-labs
025785b217 Site: the served chip text is the class v6 close's sentence (10.0h), verbatim, on the home line, the litepaper (abstract, chip section, limits) and the miner page; three statements separate, every number labelled, the harness and scoring-rule links beside it; the 2.1x/3.4x line, the 5x to 9x baseline, the 2.8x rung and the USD 100 M row struck; evidence row 17 and ledger X35/X36 restated; pins moved 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:43:12 +00:00
igneum-labs
698837d70a Class v6: the liveness rule on the window in change (4) (main, 15:56 UK); the three v7 research lanes named 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:42:27 +00:00
igneum-labs
513bca993b Merge class-v6-invention f812e800 into master (gate: green on f812e800, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:40:15 +00:00
igneum-labs
4eca18c34e Class v6 family gate, the full report: point B's row (0 hot sets at the 64 shape, 5 over 1.2x, the floor refusing 1 of 64) and the 18:00 amendment line (the best-mix genesis table under test) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:40:03 +00:00
igneum-labs
bcdce0f120 Merge class-v6-floor-k-docs e0a81517 into master (gate: green on e0a81517, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 14:39:16 +00:00
igneum-labs
781fc1b549 Merge class-v6-family-gate 72b58cec into master (gate: green on 72b58cec, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:38:28 +00:00
igneum-labs
4db034da80 Merge ca3-coord-record bf394283 into master (gate: green on bf394283, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:37:26 +00:00
igneum-labs
b6a45ced76 Class v6 10.0f: lane 3's profitability surface, first cut (p* scales as C_dev over q times the discounted life and under 5 percent with the per-joule edge; the conditions under which development is attractive; the fixed-lane chip needs 4x the price of the programmable one); the served economic line carries it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:35:20 +00:00
igneum-labs
6211413a74 Class v6 10.0h: the served text (the review's sentence verbatim, each number's label, the lines beside it, what is withdrawn) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:32:53 +00:00
igneum-labs
e0a81517b5 shadow-k: the 32-lane core (5.55 pJ per lane-op, k 0.45 at the lock), the shuffle row (1.24 pJ, k 0.021), the mix optimiser's best corner 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of bfccc26ed (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:45 +00:00
igneum-labs
b039ded194 shadow-k: row (2'), the 32-lane 16-register core (4.2 pJ per lane-op ASAP7, k 0.34 at the lock at N3) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 3e2a202fe (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:45 +00:00
igneum-labs
f5e1045318 shadow-k: the node column (node-for-node the base core is k 0.78 and the GDDR7 board 2.4x at the lock) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 05275ca6a (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:45 +00:00
igneum-labs
44bb0b406d shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 036c1aded (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:45 +00:00
igneum-labs
069d4f032f shadow-k: the ranking and the mixed draw (the census lane's re-weight on the unit floors and the core) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of e92167057 (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:44 +00:00
igneum-labs
a97605d7c0 shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of ed7d2626d (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:44 +00:00
igneum-labs
7784bdc7d1 chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6fab785c5 (bfccc26ed4) for the box mirror master
 2026-10-08 14:32:43 +00:00
igneum-labs
15d1c284fa Class v6 10.0g: the second external review's seven amendments (energy, economic and response statements kept separate; the minimax evaluation rule with the free adversary and the negative controls; the discrete-GPU cohort; the 1.25x same-node gate; no arrival probabilities; the RandomX wording; the next programme named) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:31:49 +00:00
igneum-labs
72b58cec74 Class v6 family gate, the full report (16:30 BST): 38,000 drawn eras, the lossy-share curve per shape (the exhaustion a 256-shape interaction, about 6x the independent estimate), the pre-floor spread per width and the width-4 floor decision (0.995 kept at its measured cost), the two live-dataset censuses (128 band epochs: 2 hot sets at the 256 shape, both refused by the class v5 floor), the seven known-failed seeds through the sigma form (one value-level test, the bucket bound retired into the bit read; p212 and p225 at bit R), the x4, x8 and x16 verifier rows (x16 outside the band on the 10 ms gate), the band stratum's gate records as JSON lines; every row's log under logs/ 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:31:37 +00:00
igneum-labs
f812e800ee Merge remote-tracking branch 'build/master' into class-v6-invention 2026-10-08 14:31:15 +00:00
igneum-labs
c6f999bd6b Class v6 invention: the drawn-era F8-form read of the sound per-load form (not clean: 7 of 64 seeds with a site under the 0.995 floor, min 0.940, one item at 1,938 reads; the per-load class runs no (c'''), so the floor joins G5-draw with the seven seeds as the known-failed case; the uniform-control share column labelled as not F8's number), the harness's era option 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:31:14 +00:00
igneum-labs
ad00108853 Class v6 10.0f: the external review's five corrections (the programmable chip's 3-year life with the per-life table, the lifetime headline withdrawn; the profitability surface in place of the single threshold; the dataset claim narrowed to a stale machine; proving an opportunity not an exclusion; the served sentence as the review words it; Monero an observed comparison; the window k not a lower bound); the 32-lane window core as the chip assessed (about 2.6x a node ahead, 2.2x node-for-node) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:30:45 +00:00
igneum-labs
bf39428306 Counter ASIC 3.0 status: the class v6 floor closed at 15:28 (the table, the capex wall, the served line in two units, the four changes, amendment 1's best-mix table), the 5.5 GiB row measured on a rented 5090, the attack pass's 15:30 reading (F9 max attempt 32, F1's one letter miss at parity pending), preview 1 on the founder's Mac, main's class v6 build order fanned to five lanes with clocks (packs 21:00, census 22:30, object 23:30, 0.3.27 tomorrow, the chip page 17:30) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:30:20 +00:00
igneum-labs
4f409e7ce9 Merge app-audit-26 612764d8 into master (gate: green on 612764d8, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 14:29:58 +00:00
igneum-labs
44eacd733d Class v6 amendment 15:3x UK: the chip's shuffle is k 0.011 to 0.021 (the lowest family), the register file linear in its entries (the window is the knob), the core32 row; change (1) amended: the op mix moves to the band's best mix as the genesis table, subject to one acceptance pass 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:28:58 +00:00
igneum-labs
731caa1f18 Class v6 3.3: lane 3's reading of the measured 5.5 GiB step (the mapping safe at the v6 epoch; 4 percent at stock, about 9 at the knee; the 8 GB tier's RX 7600 row owed) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:25:50 +00:00
igneum-labs
a41aa5a0cc Class v6 3.3: the 5.5 GiB genesis floor measured on a rented 5090 at stock (3.5 percent of rate, about 4 percent of energy; the non-power-of-two mapping no cliff on sm_120; the ds55 pin) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:24:53 +00:00
igneum-labs
612764d819 Miner window audit: the Earnings row is two windows (7 days, all time) under the 24-hour headline; the 24-hour count never falls back to zero before the engine's earned sums land 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:23:33 +00:00
igneum-labs
65ef6d3f4b Counter ASIC 3.0 status: the second minute 15:05:00 on f8da7515 (named on the gates, the fast-time PASS 15:17 behind it), the Intel row closed on the Arc B580 (one fingerprint on six platforms), the k lane's design sweep and node column, kit d's op-mix row, the W = 8 row at stock, lane D's strata complete (38,000 eras), the floor-sm, denominator and invention landings, the preview 1 line, PC 1's 13 percent caveat 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:19:50 +00:00
igneum-labs
07cb5d933a Class v6: W = 8 withdrawn on measurement (the 5090 at stock pays +4.8 percent of energy for 0.2x of the die's shadowed edge; lane 3 083ea1e4); the width is W = 4, 16 never 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:15:53 +00:00
igneum-labs
9ff09ecc9f Class v6: W = 16 closed from the knee side (2.3x the energy per hash at the 5090's lock); nothing on it owed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:05:47 +00:00