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Class v6 10.0f: lane 3's profitability surface, first cut (p* scales as C_dev over q times the discounted life and under 5 percent with the per-joule edge; the conditions under which development is attractive; the fixed-lane chip needs 4x the price of the programmable one); the served economic line carries it

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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docs/design/class-v6-rotating-family.md
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@ -396,6 +396,23 @@ So for the programmable chip the lifetime unit says: above about USD 23 M to 83
**(2) Economics.** The single USD 340 M threshold comes out. In its place a profitability surface (lane 3's model is the base, its 180-day life one row of the surface; asked of lane 3, the row owed): NPV with the development cost, the initial fleet capital, the captured share q, the operating margin, electricity, the pre-production period with zero revenue, discounting and residual value; the operator and the manufacturer modelled separately (self-mining, hardware sales, hybrid; the development cost shared across entrants; a first design against a revision); GPU miners allowed to enter and exit. The result is stated as the set of conditions under which development is attractive, never as "the chain stays below X". Until the surface lands, the honest statement from lane 3's rows is conditional: a USD 20 M DRAM-board project taking the whole chain is attractive above about USD 23 M a year of miner revenue at a 10 percent discount; the same project at a third of the hash above about USD 75 M to 91 M; a USD 75 M project at a third above about USD 280 M to 340 M; a USD 100 M SRAM project at a third above about USD 330 M to 450 M; every figure moves 5x with the project cost and 1.4x with the chip's edge, and a longer productive life than the 180 days assumed there lowers each by the ratio of the lives.
**The profitability surface, first cut (lane 3, `docs/analysis/class-v6/floor/sram-and-floor.md` section 4.4, class-v6-floor-sram 163a6204, 15:34 UK, inside the 16:45 clock; all modelled; the script `scratchpad/surface.py` on build-3).** The model: an entrant pays C_dev at time zero, earns nothing for T0, then holds share q of the hash for a life L and earns q x m x R(y) at the spec's emission (0.77 / 0.80 / 0.40 / 0.40 / 0.20 / 0.20 B IGN to miners, years 1 to 6) at price p; GPU miners enter and exit at their all-in cost (the 5090 at the lock, USD 0.00092 per MH/s-hour, 0.000084 of it power), which sets the revenue per hash while any GPU mines; the chip's margin m = 1 - (0.000084 / e + capex / (L x 8,766)) / 0.00092 (0.96 at 5x, USD 0.5 per MH/s and 3 years; 0.86 at 0.5 years; 0.29 for the GDDR7 board at USD 2.8 and 0.5 years); fleet capital at T0 (under USD 10 M everywhere), a 20 percent residual, a 10 percent discount. p* is the break-even price in USD per IGN; development is attractive where the expected price over the life exceeds it.
Table A, the operator self-mining a first design, the edge 5x, silicon USD 0.5 per MH/s; p* at q 0.1 / 0.3 / 1.0 (the launch-year miner revenue in USD M a year in brackets for the L 3 column):
| C_dev | T0 | L 0.5 y (the fixed-lane chip under rotation) | L 1 y | L 2 y | L 3 y (the programmable chip) |
|---|---|---|---|---|---|
| 20 M | 1 y | 0.77 / 0.26 / 0.08 | 0.33 / 0.11 / 0.03 | 0.22 / 0.07 / 0.02 | 0.17 / 0.055 / 0.017 (128 / 43 / 13) |
| 20 M | 2 y | 1.69 / 0.56 / 0.17 | 0.73 / 0.24 / 0.07 | 0.36 / 0.12 / 0.04 | 0.29 / 0.10 / 0.03 (224 / 75 / 22) |
| 75 M | 2 y | 6.3 / 2.1 / 0.63 | 2.7 / 0.92 / 0.28 | 1.35 / 0.45 / 0.14 | 1.09 / 0.36 / 0.11 (842 / 281 / 84) |
| 150 M (the SRAM die, N2) | 2 y | 12.6 / 4.2 / 1.27 | 5.5 / 1.83 / 0.55 | 2.7 / 0.90 / 0.27 | 2.19 / 0.73 / 0.22 (1,684 / 561 / 168) |
| 500 M | 2 y | 42 / 14 / 4.2 | 18 / 6.1 / 1.83 | 9.0 / 3.0 / 0.90 | 7.3 / 2.4 / 0.73 |
Table B, the manufacturer selling hardware (bears C_dev, keeps half the operators' profit): p* about 2x the operator's at the same C_dev (150 M, T0 2, L 3: 1.50 at q 0.3, 0.45 at q 1). Table C, a revision at 0.3 x C_dev and T0 1 year: 150 M reads 0.25 / 0.16 / 0.12 at L 1 / 2 / 3; shared by three entrants 0.61 / 0.30 / 0.24. Table D, the hybrid (self-mine year one, then sell): 75 M at L 3 0.55, 150 M 1.10. Table E, the NPV at 150 M, T0 2, q 0.3: -144 to -149 M at IGN 0.03 at every life; +16 M (L 2) and +56 M (L 3) at IGN 1.00; +349 and +467 at 3.00.
The conditions, read off the surface, which are the economic-resistance statement: (1) p* scales as C_dev / (q x the discounted life): 5x on the project cost, 3x on the share from a third to the whole chain, 2x to 4x on the life from 1 to 3 years, 2x on T0 from 1 to 2 years, and under 5 percent on the per-joule edge from 2x to 13x (the margin is 0.93 to 0.97 at every edge once the chip's power is a tenth of a GPU's: **the per-joule number is nearly irrelevant to the investment decision**). (2) The fixed-lane chip at L 0.5 needs 4x the price of the programmable chip at L 3 and never pays at the DRAM board's USD 2.8 per MH/s: the rotation is that factor, not a wall. (3) The cheapest attractive project is a USD 20 M DRAM-board design taking the whole chain for three years at about IGN 0.02 to 0.03 (USD 13 to 22 M a year of miner revenue), at a third 0.055 to 0.10 (43 to 75 M); the SRAM die at N2 0.22 taking the chain or 0.73 at a third (168 to 561 M a year), a revision of it 0.12 to 0.16, shared by three 0.24 to 0.30. (4) Selling hardware raises p* about 2x, so the first entrant self-mines and sells once the design is paid. (5) The chain controls L against a fixed lane, the honest cost per MH/s-hour (the operating point, the floor) and the visibility of q (the detector); it does not control C_dev, T0 or p. Unverified, for the second cut: the GPU all-in cost at MSRP (street prices halve every p*), the half-profit split, the residual and the discount; GPU re-entry at a higher price, a per-year q path, the emission beyond year 8.
**(3) Dataset.** The class v5 claim is narrowed: a chain-state dataset makes a STALE machine wrong on every item; it does not exclude a specialised machine with a host and external memory that keeps the dataset current. What layer 2 prices instead is the update bandwidth, the sync and the storage that keeping it current costs: the state delta per block (the touched leaves times 64 bytes; at the devnet's 150 tx/s and a few leaves per transaction, of the order of 100 KB a second, approximate), the lazy derivation of the touched items per epoch on the host (the verifier's own cost, under 10 ms per warp), and a board that holds the schedule's size (5.5 / 8.5 / 11.5 GiB) beside the chip; against that the layer's measured honest-side cost (section 3.3). The chip rows of section 3.2 stand for the stateless chip only; the hosted chip's extra cost is the host, the link and the board, priced in 10.3's ticket terms (owed as a row, approximate).
**(4) Proving.** Useful proving does not bind mining to a GPU: an ASIC-plus-GPU operator is inside the adversary model, and proving is an opportunity for GPU owners, not an exclusion. Thread 5 of the research file (proof of useful work) and 10.5's "proof of latency" kill stand with that reading.
@ -427,7 +444,7 @@ So for the programmable chip the lifetime unit says: above about USD 23 M to 83
The labels on its numbers: "2.2x to 2.4x" is modelled (the GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33, both on class v4, PC 1 and rented pods, 8 October 2026; the chip side the k lane's synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on TSMC's headline factors, claimed; the chip's memory the chip model's GDDR7 board, modelled). "2.0x on the GPU's own node" is modelled (the same core node-for-node, k 1.09). Against the 32-lane window core the adversary would build the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node-for-node (synthesised, pending the re-optimised row by 18:00 UK); the served sentence's range is kept as the review wrote it and the 32-lane rows sit beside it on the page as the pending row. The window's k is synthesis-derived and not a lower bound.
The lines the page carries beside it, each labelled:
- The three statements, separate (10.0g item 1): energy resistance (the figures above); economic resistance (a profitability surface under stated development cost, revenue, share, margin and productive lifetime; the conditions under which development is attractive; lane 3's cut owed, the conditional statement of 10.0f item 2 until then, modelled); response capability (a passed rotation boundary proves the rotation works, not that hardware dies; the schedule of 10.0d: hourly, weekly, 180-day family, emergency vote; measured per boundary).
- The three statements, separate (10.0g item 1): energy resistance (the figures above); economic resistance (the profitability surface of 10.0f item 2, lane 3's first cut, modelled: p* scales as the project cost over the share times the discounted life, and under 5 percent with the per-joule edge; the cheapest attractive project is a USD 20 M DRAM-board design taking the whole chain for three years at about IGN 0.02 to 0.03, at a third 0.055 to 0.10; the SRAM die at N2 0.22 to 0.73; a fixed-lane chip under rotation needs 4x the price of a programmable one; stated as the conditions under which development is attractive); response capability (a passed rotation boundary proves the rotation works, not that hardware dies; the schedule of 10.0d: hourly, weekly, 180-day family, emergency vote; measured per boundary).
- The node column (10.0e, claimed scaling): 2.0x against a chip on the GPU's own node, 2.4x a node ahead, 2.8x two nodes ahead on the 8-lane core; the honest tier moves to the next node with every GPU generation while a chip must re-tape-out.
- The precedents as sourced (10.0b; every figure with its URL and date, nameplate and community tables, about 20 percent either way): RandomX's rules stable since 2019, its programs varying per hash, the Antminer X5 46 months after the fork at 6.37 J per kH at the wall against a stated CPU measurement, an observed comparison, not a ceiling; Ethash 36 months to a first chip worse than a GPU, the iPollo V2H about 14x today; Kaspa 21 months, 167x to 725x.
- The commodity cohort: the discrete-GPU population the network protects; the Apple row reported beside it, never the headline (10.0g item 3).