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Merge the box master 31496f4e into release-manifest-8 (the evidence page rebuilt)

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
This commit is contained in:
igneum-labs 2026-10-08 15:25:22 +00:00
commit d5ba3c3a90
291 changed files with 75941 additions and 551 deletions
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211
app/igneum-app/tiers/class-v5-tiers.json
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@ -1081,9 +1081,9 @@
"memory_gb": 24,
"label": "estimated",
"stock": {
"mhs": 28.0,
"w": 300.0,
"uj": 10.7,
"mhs": 40.0,
"w": 310.0,
"uj": 7.75,
"class": "v4"
},
"tiers": [
@ -1094,13 +1094,13 @@
"mem_mhz": 0,
"core_offset_mhz": -500,
"power_offset_pct": -30,
"limit_w": 355,
"mhs": 28.0,
"w": 224.0,
"mhw": 0.125,
"limit_w": 310.0,
"mhs": 40.0,
"w": 235.6,
"mhw": 0.1698,
"source": "measured",
"label": "estimated",
"uj": 8.0,
"uj": 5.89,
"note": "not rentable, not owned: the 9070 XT's dependent-read rate per channel (150 M per second per 32-bit channel) on 24 channels; the knob by the 9070 XT grid"
},
{
@ -1110,13 +1110,13 @@
"mem_mhz": 0,
"core_offset_mhz": -300,
"power_offset_pct": -15,
"limit_w": 355,
"mhs": 28.0,
"w": 255.0,
"mhw": 0.1098,
"limit_w": 310.0,
"mhs": 40.0,
"w": 266.6,
"mhw": 0.15,
"source": "measured",
"label": "estimated",
"uj": 9.1,
"uj": 6.67,
"note": "half the offsets"
},
{
@ -1126,14 +1126,14 @@
"mem_mhz": 0,
"core_offset_mhz": 0,
"power_offset_pct": 0,
"limit_w": 355,
"mhs": 28.0,
"w": 300.0,
"mhw": 0.0933,
"limit_w": 310.0,
"mhs": 40.0,
"w": 310.0,
"mhw": 0.129,
"source": "stock",
"label": "estimated",
"uj": 10.7,
"note": "modelled"
"uj": 7.75,
"note": "24 channels at the RX 7600's measured per-channel rate: about 40 MH/s at about 310 W (7.8); not rentable, not owned"
}
],
"src": "modelled on the 9070 XT rows"
@ -1149,9 +1149,9 @@
"memory_gb": 16,
"label": "estimated",
"stock": {
"mhs": 18.0,
"mhs": 27.0,
"w": 230.0,
"uj": 12.8,
"uj": 8.52,
"class": "v4"
},
"tiers": [
@ -1162,13 +1162,13 @@
"mem_mhz": 0,
"core_offset_mhz": -500,
"power_offset_pct": -30,
"limit_w": 263,
"mhs": 18.0,
"w": 171.0,
"mhw": 0.1053,
"limit_w": 230.0,
"mhs": 27.0,
"w": 174.8,
"mhw": 0.1545,
"source": "measured",
"label": "estimated",
"uj": 9.5,
"uj": 6.47,
"note": "16 channels of GDDR6 at the 9070 XT's per-channel rate; the knob by the 9070 XT grid"
},
{
@ -1178,13 +1178,13 @@
"mem_mhz": 0,
"core_offset_mhz": -300,
"power_offset_pct": -15,
"limit_w": 263,
"mhs": 18.0,
"w": 195.0,
"mhw": 0.0923,
"limit_w": 230.0,
"mhs": 27.0,
"w": 197.8,
"mhw": 0.1365,
"source": "measured",
"label": "estimated",
"uj": 10.8,
"uj": 7.33,
"note": "half the offsets"
},
{
@ -1194,18 +1194,85 @@
"mem_mhz": 0,
"core_offset_mhz": 0,
"power_offset_pct": 0,
"limit_w": 263,
"mhs": 18.0,
"limit_w": 230.0,
"mhs": 27.0,
"w": 230.0,
"mhw": 0.0783,
"mhw": 0.1174,
"source": "stock",
"label": "estimated",
"uj": 12.8,
"note": "modelled"
"uj": 8.52,
"note": "16 channels at the RX 7600's measured 1.74 MH/s per channel: about 27 MH/s at about 230 W (8.5); not rentable, not owned"
}
],
"src": "modelled on the 9070 XT rows"
},
{
"card": "AMD Radeon RX 7600",
"match": [
"7600"
],
"vendor": "amd",
"arch": "rdna3",
"memory_gb": 8,
"label": "estimated",
"stock": {
"mhs": 13.88,
"w": 113.0,
"uj": 8.14,
"class": "v4"
},
"tiers": [
{
"id": "efficiency",
"clock_mhz": 0,
"power_pct": 70,
"mem_mhz": 0,
"core_offset_mhz": -500,
"power_offset_pct": -30,
"limit_w": 113.0,
"mhs": 13.88,
"w": 85.9,
"mhw": 0.1616,
"source": "measured",
"label": "estimated",
"uj": 6.19,
"note": "the 9070 XT's ADLX grid (24 percent of the draw for no rate) applied; this card's own 24-point grid runs on PC 1 by about 16:50 UK and replaces this row"
},
{
"id": "balanced",
"clock_mhz": 0,
"power_pct": 85,
"mem_mhz": 0,
"core_offset_mhz": -300,
"power_offset_pct": -15,
"limit_w": 113.0,
"mhs": 13.88,
"w": 97.2,
"mhw": 0.1428,
"source": "measured",
"label": "estimated",
"uj": 7.0,
"note": "half the offsets, inside the flat band"
},
{
"id": "max",
"clock_mhz": 0,
"power_pct": 100,
"mem_mhz": 0,
"core_offset_mhz": 0,
"power_offset_pct": 0,
"limit_w": 113.0,
"mhs": 13.88,
"w": 113.0,
"mhw": 0.1228,
"source": "stock",
"label": "measured",
"uj": 8.14,
"note": "the founder's RX 7600 (8 GB) on PC 1, the card-in job 15:46 to 15:50 UK: class v4 sub-version 3 at stock 13.88 MH/s at 113 W (8.14), the v4 and v5 fingerprints equal to the pinned readings, the app's own row 13.4 at 113 W; class v5 within 2 percent; the 1 GiB dataset fits in 8,176 MB (the 2, 4 and 5.5 GiB rows follow)"
}
],
"src": "the card-in lane's PC 1 job, 8 October 2026 15:50 UK"
},
{
"card": "AMD Radeon RX 7600 XT",
"match": [
@ -1217,9 +1284,9 @@
"memory_gb": 16,
"label": "estimated",
"stock": {
"mhs": 9.0,
"w": 160.0,
"uj": 17.8,
"mhs": 13.9,
"w": 120.0,
"uj": 8.63,
"class": "v4"
},
"tiers": [
@ -1230,13 +1297,13 @@
"mem_mhz": 0,
"core_offset_mhz": -500,
"power_offset_pct": -30,
"limit_w": 190,
"mhs": 9.0,
"w": 117.0,
"mhw": 0.0769,
"limit_w": 120.0,
"mhs": 13.9,
"w": 91.2,
"mhw": 0.1524,
"source": "measured",
"label": "estimated",
"uj": 13.0,
"uj": 6.56,
"note": "8 channels; the card-in queue holds one for a PC measurement"
},
{
@ -1246,13 +1313,13 @@
"mem_mhz": 0,
"core_offset_mhz": -300,
"power_offset_pct": -15,
"limit_w": 190,
"mhs": 9.0,
"w": 136.0,
"mhw": 0.0662,
"limit_w": 120.0,
"mhs": 13.9,
"w": 103.2,
"mhw": 0.1347,
"source": "measured",
"label": "estimated",
"uj": 15.1,
"uj": 7.42,
"note": "half the offsets"
},
{
@ -1262,14 +1329,14 @@
"mem_mhz": 0,
"core_offset_mhz": 0,
"power_offset_pct": 0,
"limit_w": 190,
"mhs": 9.0,
"w": 160.0,
"mhw": 0.0563,
"limit_w": 120.0,
"mhs": 13.9,
"w": 120.0,
"mhw": 0.1158,
"source": "stock",
"label": "estimated",
"uj": 17.8,
"note": "modelled"
"uj": 8.63,
"note": "the same Navi 33 die as the measured RX 7600 (13.88 MH/s at 113 W) with 16 GB in clamshell: the same rate, about 120 W (8.6); the card-in queue holds one"
}
],
"src": "modelled on the 9070 XT rows"
@ -1285,9 +1352,9 @@
"memory_gb": 16,
"label": "estimated",
"stock": {
"mhs": 9.5,
"mhs": 12.0,
"w": 130.0,
"uj": 13.7,
"uj": 10.83,
"class": "v4"
},
"tiers": [
@ -1298,13 +1365,13 @@
"mem_mhz": 0,
"core_offset_mhz": -500,
"power_offset_pct": -30,
"limit_w": 160,
"mhs": 9.5,
"w": 95.0,
"mhw": 0.1,
"limit_w": 130.0,
"mhs": 12.0,
"w": 98.8,
"mhw": 0.1215,
"source": "measured",
"label": "estimated",
"uj": 10.0,
"uj": 8.23,
"note": "8 channels of GDDR6 on RDNA 4; the card-in queue holds one"
},
{
@ -1314,13 +1381,13 @@
"mem_mhz": 0,
"core_offset_mhz": -300,
"power_offset_pct": -15,
"limit_w": 160,
"mhs": 9.5,
"w": 110.0,
"mhw": 0.0864,
"limit_w": 130.0,
"mhs": 12.0,
"w": 111.8,
"mhw": 0.1073,
"source": "measured",
"label": "estimated",
"uj": 11.6,
"uj": 9.32,
"note": "half the offsets"
},
{
@ -1330,14 +1397,14 @@
"mem_mhz": 0,
"core_offset_mhz": 0,
"power_offset_pct": 0,
"limit_w": 160,
"mhs": 9.5,
"limit_w": 130.0,
"mhs": 12.0,
"w": 130.0,
"mhw": 0.0731,
"mhw": 0.0923,
"source": "stock",
"label": "estimated",
"uj": 13.7,
"note": "modelled"
"uj": 10.83,
"note": "8 channels on RDNA 4 between the 9070 XT's 1.18 MH/s per channel and the 7600's 1.74: about 12 MH/s at about 130 W (10.8); the card-in queue holds one"
}
],
"src": "modelled on the 9070 XT rows"

3
brand/README.md
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@ -41,7 +41,8 @@ polygons). The Windows `.ico` and the favicons render each size from the vector,
| `brand/profile/github-org-512.png` | organisation avatar | github.com/igneum-network (uploaded by hand from the Igneum Chrome profile) |
| `brand/profile/x-banner-1500x500.png` | X header | the mark centred on obsidian |
| `brand/igneum-icon-512.png`, `igneum-icon-1024.png` | the square at 512 and 1024 | the same as the profile files; kept for links that already point here |
| `site/og-small.png` (256 square), `og-square.png` (1024), `og-coin.png` and `og.png` (1200 x 630 card: mark left, IGNEUM wordmark, tagline) | share images, `?v=2` in every `og:image` and `twitter:image` | index, live, litepaper (`og-small`); bench, evidence, `build.mjs` (`og`) |
| `site/og/<card>.png` (1200 x 630) and `site/og/<card>-square.png` (1200 x 1200), one per row of `CARDS` in `site/og/pages.mjs`: the mark over a soft ember glow, a kicker, one line, a quiet sub line, the route at the foot | share images (WhatsApp, iMessage, Slack, X, LinkedIn); the metas of every page come from `site/og/pages.mjs` through `site/build.mjs`, `?v=` from `OG_VERSION` | every served page; rendered by `node site/og/render.mjs` on a build box from `site/og/card.html` (8 October 2026) |
| `site/og.png`, `og-coin.png`, `og-square.png`, `og-small.png` | the earlier share images, kept only for links already cached by readers; nothing in the site points at them | retired 8 October 2026 |
| `brand/profile/github-social-1280x640.png` | repository social preview | github.com/igneum-network/igneum settings (by hand) |
| `brand/profile/vercel-avatar-512.png` | Vercel team or project avatar | by hand |

115
docs/analysis/class-v6/family-gate.md
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@ -1,6 +1,6 @@
# Class v6, the family gate: how a parameter family is cryptanalysed as a family
Research lane D of the class v6 rotating-family design, under the Counter ASIC coordinator. First cut landed on the mirror's master at 11:40 BST, 8 October 2026 (fbe62a8b); this cut, with the measured coverage, is the 17:00 BST deliverable; the full report by 09:00 BST on 9 October. Branch `class-v6-family-gate` (this document) and the harness branch `family-gate-v5` (the class v5 crate at 8f481459 plus the census harness, never a chain path). Internal research, not an independent review; nothing here touches a served number, the devnet or the testnet object; no consensus code this week. Every figure carries its source: a lane report on the mirror, a log on a box, or an arithmetic step shown in the text. Figures from memory are labelled approximate.
Research lane D of the class v6 rotating-family design, under the Counter ASIC coordinator. First cut landed on the mirror's master at 11:40 BST, 8 October 2026 (fbe62a8b); the 17:00 cut with the measured coverage landed at 238100b0 (13:13 BST); this is the full report, pulled to 16:30 BST on the founder's clock (every row measured, a partial carries its count). Branch `class-v6-family-gate` (this document) and the harness branch `family-gate-v5` (the class v5 crate at 8f481459 plus the census harness, never a chain path). Internal research, not an independent review; nothing here touches a served number, the devnet or the testnet object; no consensus code this week. Every figure carries its source: a lane report on the mirror, a log on a box, or an arithmetic step shown in the text. Figures from memory are labelled approximate.
The question. Class v6 (the founder's word at 11:1x BST, 8 October 2026) draws per era the parameters a release used to fix (layer 1), lets the dataset track the chain state (layer 2), rotates instruction families by height (layer 3) and generalises the acceptance floor and the uniformity test to each era's draw with a redraw on failure (layer 4). A chip is then built against a FAMILY of hashes, not one hash. The in-house pass of 7 October and the attack board F1 to F10 bounded ONE member of the family (class v4 sub-version 3 at 017e7037 and class v5 at 1c420786). This document says how the family is bounded: what the space is, how many eras must be drawn to say anything about the worst era, which tests the chain runs itself on every era and epoch, what the offline board looks like over the testnet period, what a published proof of testing contains, and what the whole apparatus cannot see.
@ -14,7 +14,7 @@ The question. Class v6 (the founder's word at 11:1x BST, 8 October 2026) draws p
| The per-era tests (section 3) | Three rings. Ring A, the chain runs per era at the cut, microseconds: the structural redraw rules (the band membership of every draw, the day-key cost rule, the product-bias rotation class recorded). Ring B, the chain runs per epoch, seconds: the acceptance rule generalised to the family's shape ((a) (b) (a') (c) (c') (c'') (c''') plus the two next-class tests, the per-site largest-256-item-bucket bound and the index-bit bias read, on the same 2^20 pass). Ring C, the gate runs offline per drawn era, box-hours: the F8-form census at 2^24 on 64 seeds, the attempts census, the exhaustion count. Each row carries its known-failed shape and its clean-seed cost so the redraw is priced |
| The board (section 4) | F1 to F10 and the nine lanes classified per-era, per-family or chain-run, with the harness taking the era draw as an input; the proof of testing is one JSON record per drawn era (the draw, the object, the binary, the seeds, every verdict with its statistic, threshold and log sha256, the core-seconds) and one family summary (eras per stratum, the worst era per test, the refuse rate per band, the bound's arithmetic) |
| The honest line (section 5) | The gate sees what its tests see. It does not see the diffuse era-stride class below the bit-bias read's resolution (a bias under 0.3 percent at 2^20), a mechanism that lives in a joint corner no stratum names, a mixer weakness below adv-mixer-3's bands, or an era whose draw sits in the untested 1 in 64. A GPU-like chip loses nothing on any era; what a corner buys it is a per-era hot set bounded at 1.002x (the floor) or 1.0024x (the diffuse class), or, at `m = 4`, a mixer with 2 applications of measured margin instead of 6 |
| Measured (section 6) | 24,000 drawn eras through the ring-B tests in 54 core-hours (1.7 box-hours) on build-1 and build-3, 11:16 to 12:13 BST, the harness as a diff in `logs/`. Four measured rows move the design: the lossy corner of B = 4 exhausts the 256 cap in 1.2 percent of eras (61 of 5,000) against 0 of 19,000 elsewhere, so the band is B = 4 on the injecting families with or/mul/mulhi never raised (0 of 3,000 under it); the (c''') floor at 0.995 costs 4.5 to 6.5 percent of candidates at width 4 against 0.6 to 1.0 at width 1 (a per-width calibration); the shape axis moves the draw from 1.8 attempts (64 x 108) to 3.8 (256 x 27); the era-stride bias sits at over 6 sigma on one address bit (bit R in 73 percent of cases) in about half the eras of every stratum and at over 100 sigma in a third, falling to 7.5 percent under R in 28..31, a structural fact for the research lane's layer 4 rather than a per-epoch refusal |
| Measured (section 6) | 38,000 drawn eras through the ring-B tests on four boxes (about 90 core-hours), the lossy-share curve per shape, two live-dataset censuses at 2^24, the pre-floor spread per width, the seven known-failed seeds through the sigma form; the rows that move the design: the band is B = 4 on the injecting families with or/mul/mulhi never raised (the lossy corner exhausts the 256 cap on the 256 x 27 shape alone, 3.3 to 3.6 percent of its eras at r = 0.98, about 6x the independent-attempt figure; 0 of 5,000 shape-64 eras at any lossy share); the (c''') floor stays at 0.995 at the pinned width 4 at its measured cost (14.6 percent of the candidates reaching the 2^20 pass, +0.3 attempts per epoch) because the floor refused both hot sets of the live point-A census (p38 at 0.9932, p54 at 0.9945) and the width-4 statistic has a real tail no single floor removes at the width-1 cost; the shape axis moves the draw from 1.8 attempts (64 x 108) to 3.8 (256 x 27); the mixer axis is invisible to every per-era statistic and is closed per family; the era-stride bias at bit R (the product's bit 0 at z = -512 exactly) in half the eras of every stratum is one value-level mechanism that the bucket bound sees only at narrow windows above bit 12, so the family carries ONE test, the per-site index-bit read, as a per-era record and the structural lever's known-failed set (p4, p8, p10, p34, p212, p225, p15 all caught at 6 sigma; a refusal band of 300 sigma catches five and redraws 16 percent of epochs; 6 sigma would redraw half) |
## 1. The parameter space
@ -22,9 +22,9 @@ The question. Class v6 (the founder's word at 11:1x BST, 8 October 2026) draws p
| Axis | Band proposed for the draw | What fixed the band (the measured rows) | The tested margin inside the band | Known-failed corner, named |
|---|---|---|---|---|
| Mixer multiplier `m` (applications per round, `LoadClass::mixer_mult`; 72 per item at `m = 8`, 8 between dependent reads) | {4, 8, 16}; the research lane's outline; this lane's reading: {8} plus {4} as a corner, {16} only after the verifier row | x4 and x8 measured (`docs/plans/mixer-x4.md` section 6.4: 1.92 and 2.79 ms per unit on a loaded M5 Max core; the daily build 42 ms at x8 on the 5090, measured); x16 estimated at about 3.7 ms per unit on the M5 Max core and 9 ms on a 2019-class core (chip-model-v3 section 3 item 1), against the 10 ms verifier gate | adv-mixer-3 (`report-mixer-3.md`, "The round margin, stated"): no statistic survives 2 of the 8 keyed applications between reads at bands 0.0015 (Q2, 2^24 states), 0.00026 (2^27), 0.00018 (Q2b, 2^28); SAT solved at k = 1 in 137 s and timed out at k = 2, 3, 4; two real days and eight random days agree. So at `m = 8` 6 of 8 applications are margin; at `m = 4` the same rows leave 2 of 4; at `m = 16` 14 of 16 | None measured. The corner is `m = 4` by margin and `m = 16` by the verifier; the all-ROT-equal day key is the day-level corner (rejected by the AP-F4-1 rule) |
| Mixer multiplier `m` (applications per round, `LoadClass::mixer_mult`; 72 per item at `m = 8`, 8 between dependent reads) | {4, 8} on the measured verifier rows (section 6.7: x16 reads 7.13 ms per warp on one core against x8's 4.12, 1.73x, which puts it over the 10 ms gate on the 2019-class core and the half-core proxy by scaling); the research lane's outline had {4, 8, 16} | x4 and x8 measured (`docs/plans/mixer-x4.md` section 6.4: 1.92 and 2.79 ms per unit on a loaded M5 Max core; the daily build 42 ms at x8 on the 5090, measured); x16 estimated at about 3.7 ms per unit on the M5 Max core and 9 ms on a 2019-class core (chip-model-v3 section 3 item 1), against the 10 ms verifier gate | adv-mixer-3 (`report-mixer-3.md`, "The round margin, stated"): no statistic survives 2 of the 8 keyed applications between reads at bands 0.0015 (Q2, 2^24 states), 0.00026 (2^27), 0.00018 (Q2b, 2^28); SAT solved at k = 1 in 137 s and timed out at k = 2, 3, 4; two real days and eight random days agree. So at `m = 8` 6 of 8 applications are margin; at `m = 4` the same rows leave 2 of 4; at `m = 16` 14 of 16 | None measured. The corner is `m = 4` by margin and `m = 16` by the verifier; the all-ROT-equal day key is the day-level corner (rejected by the AP-F4-1 rule) |
| Op-mix weights (the ten non-load families, sum 75) | Each weight within B points of table 1.4.2 (add 12, xor 10, mul 8, mad 8, shfl 8, rotl 7, sub 6, mulhi 6, rotr 6, or 4), renormalised by largest remainder; shfl and mulhi never raised; B = 2 (spec 1.13.1, proposed) or B = 4 (the research lane) | The microbench (`counter-asic-4-research.md` 15.1a, the 5090 alone, 8 October): pJ per counted op at the stock clock and the 1,300 MHz lock: arx 11.3 / 6.2, mul 13.9 / 8.3, mulhi 39.6 / 21.0, prmt 22.3 / 11.5, lop3 24.1 / 13.0, shfl 55.8 / 29.4; the shuffle is 4.9x the add, so a draw that raises shfl raises the card's premium per instruction with no better `k` for a chip (15.1b). F7's era census: the op-weight corners (15 to 31 of 75) read 1.0x against the GPU, 0 memory effect | The acceptance's rejection rate moves with the lossy share: at the table 0.68 per candidate ((a') 83.5 percent of rejections; adv-accept row 90, 20,000 seeds); the F7 census at B = 2 read every corner clean for the chip. MEASURED today (section 6): at B = 4 with the lossy families free to rise the random stratum reads r = 0.72 and a maximum attempt of 107 (the shipped stream's maximum is 28); at the lossy corner r = 0.956 and 1.2 percent of eras EXHAUST the 256 cap | The lossy corner: or, mul and mulhi all at +B (30 of 75 against the table's 18). It is OUTSIDE the band: 8 of 663 drawn eras reached the last resort, which fails rule (a) in 9 percent of seeds (adv-accept-3 finding 1). The band this lane carries: B = 4 on the seven injecting families, or/mul/mulhi never raised above their base (the `lossybase` stratum of section 6 is its measurement), with ring A's lossy-share rule as the check |
| Read width `W` (words per load) | {1, 4} | `docs/plans/read-width.md` (5 October): w16 within the rules (5090 139.8 against 136.1 MH/s, 9070 XT 17.90 against 18.15, M5 Max within 1 percent); w64 bandwidth-bound (5090 share 0.58, 71.9 MH/s): out; the per-load mixes out on the 5 percent spread rule | The acceptance runs unchanged on aligned addresses (read-width.md section 2), but (c'') and (c''') read a site's distinct ALIGNED indices against `E_s = N - N^2 / 2W_s`: at `W = 4` the index space is `W_s / 4`, so the expectation must follow or every width-4 program reads 0.976 at a quarter window and is refused by the 0.98 floor. The harness divides the window by the width (`site_window_words`); the spec line is owed | `W = 16` (w64): excluded by measurement, never in the band |
| Read width `W` (words per load) | {1, 4} in this census; the research lane's floor reading (13:2x BST, `class-v6-rotating-family.md` section 10.3) pins W = 4 words at genesis (the width is the one wire lever on the SRAM full-store die and the cards pay nothing for 16 bytes), with W = 8 the next value once the crate carries it, so the axis is a one-value band at genesis and the width-4 strata here are its calibration | `docs/plans/read-width.md` (5 October): w16 within the rules (5090 139.8 against 136.1 MH/s, 9070 XT 17.90 against 18.15, M5 Max within 1 percent); w64 bandwidth-bound (5090 share 0.58, 71.9 MH/s): out; the per-load mixes out on the 5 percent spread rule | The acceptance runs unchanged on aligned addresses (read-width.md section 2), but (c'') and (c''') read a site's distinct ALIGNED indices against `E_s = N - N^2 / 2W_s`: at `W = 4` the index space is `W_s / 4`, so the expectation must follow or every width-4 program reads 0.976 at a quarter window and is refused by the 0.98 floor. The harness divides the window by the width (`site_window_words`); the spec line is owed | `W = 16` (w64): excluded by measurement, never in the band |
| Shadow block shape (instructions per block, passes per iteration) | {64 x 108, 128 x 54, 256 x 27}: 6,912 shadow instructions per iteration at rung 0 | 64-instruction blocks ran 2.5 to 3.5 percent faster than 256 on the 5090 and the M5 Max (6 October, measured); 1,024 cost the M5 Max 17 percent (out) | F1's shadow redundancy bound (3.0 percent of peephole-removable instructions, the v5 generator's `SHADOW_REMOVABLE_MAX_PERMILLE`) was set from F1's census at 256 instructions; the removable fraction per block is a property of the block's length, so the fraction must be re-read at 64 and 128 (a per-family row). The acceptance's (a') fixpoint and the shadow's execution in (c) take any length | The per-load placement (16 sub-blocks of 16 after each load): dead as a chain class (`counter-asic-4-research.md` 20.2a-close): 22 of 1,621 candidates accepted, 42 of 64 seeds exhaust 32 attempts, candidate 0 carries index bit 0 set in 40 of 1,024 addresses at site 0 (z 29.5). The placement axis therefore has ONE value in the band |
| Program length `N` (counted ops per hash) | Not drawn: the ladder's signal (rungs 0 to 2); the research lane's outline keeps it so | F6: the worst of 10^5 class v4 programs 8.708 ms on the half-core proxy, so N about 300,000 fits under 10 ms (rung 2 admissible, rung 3 not); the M5 Max loses 3.3 to 10 points across the band (measured ladder) | The verifier's worst case was censused at rung 0 only; a draw inside the ladder needs the 10^5-program worst case at the top rung (per-family row) | Rung 3 (inadmissible by F6) |
| Era stride and interleave (`M` odd, `R` in 1..31, `pos` four ascending bit positions, the fold rotations, the per-site windows `k_off`, `o`) | As spec 1.13.1 draws them today | F7's 2^24 era census (stride bijective, R, pos, M uniform, no class over 1.1x); adv-cache-2 section 2.3: the same 32 base programs read 2 of 32 with a site over 1.04x under `R = 29` and 16 of 32 under drawn eras (8 over 1.2x, worst 1.75x), because `rotl(x * M, R)` places a product's biased low bits (P(bit 0) = 1/4) at address bits R and up, inside the 28-bit index unless R is 29 or 30; at D = 29 only R = 30 and 31 cut bit 0 | The whole 64-seed F8 census is a census over drawn eras (each f8 seed carries its own era), so the per-era uniformity verdicts of sub-version 3 and class v5 (60 of 64 and 61 of 64 under 1.2x) already sample this axis; the devnet's clean reading at R = 29 is the accident, the drawn-era figure the chain's | R in 1..27 with a product as the last writer of a load's source (sub-class A); the warp-uniform mulhi source (sub-class B, 1 in 16,000 warps) |
@ -119,7 +119,7 @@ The three rings. A test's ring says who runs it and what a failure costs.
| (c''') the hot-item floor at 0.995 | the same `E_s`; the floor's clean spread re-read per stratum (section 6): a fixed 0.995 under a spread that moves with the shape or the width is either a liveness cost or a miss | seed 100767 (0.9919) and the nine live hot sets | 2.435 percent of accepted class v4 programs, +0.045 on the mean attempt | in the (c'') pass |
| The per-site largest-256-item-bucket bound (NEW, the F8 tail's catch) | the largest count over a site's 4,096-word buckets in its window against `N / (W_s / 4096)`, in SIGMA of the bucket's expectation (`(max - E) / sqrt(E)`), refused above a band set from the clean spread. The ratio alone cannot carry the bound: a clean full-window site's largest of 65,536 Poisson(16) buckets reads 2.1x at +4.4 sigma, a quarter-window site's largest of 16,384 Poisson(64) buckets 1.5x at +4 sigma (the 16-era smoke run read ratios 2.2 to 2.4 on clean sites); the four tail seeds' 3.1x to 5.6x at narrow windows are +17 to +37 sigma | p4, p8, p10, p34 | measured in section 6 (the columns `bucket_z_max`, `bucket_win`) | one linear pass over the (c'') indices |
| The index-bit bias read (NEW, adv-cache-2's value-level test) | per site, the one-count of each free index bit (bits above the width's alignment and below the window's cut) over the 2^20 evaluations, in sigma (`sigma = sqrt(N) / 2 = 512`); a 6-sigma band is a bias of 0.3 percent at 2^20 (the product law's bit 0 at 25 percent reads z about 512, bit 1 at 3/8 z 256, bit 3 at 3.1 percent z 64, bit 6 at 0.4 percent z 8, bit 7 at 0.2 percent z 4: passes). MEASURED on the first 16 drawn eras (11:21 BST, section 6): 7 of 16 accepted programs carry one site with a bias of 130 to 511 sigma at address bit R or R + 1 (the era's rotation), the era-stride class exactly, on programs (c''') passes at 0.9954 to 1.0000; the 9 others read under 3.8 sigma. So as a REFUSAL the read would redraw about 40 percent of epochs; its right use is as a record per era plus the structural lever (fold the product's low bits in `load_index` before the rotation, a next-class item), and the chip price is stated in section 5 | Devnet 3 site 0, era-drawn-28 site 15, the per-load candidate 0; and now the 7 of 16 | 7 of 16 at 6 sigma (a refusal is not the form); 0 of 16 at a 600-sigma band | one pass over the indices, 28 bit tests each |
| The cap and the last resort | unchanged at 256; class v5 carries the verified construction (`last_resort_v5`: a scan of 256 more candidates past the cap, each rewritten and its stale loads re-sourced, the first that passes the whole rule; the unchecked fallback behind it), so adv-accept-3's finding 1 (sub-version 3's unchecked last resort failing (a) in 9 percent of seeds) is closed on the family's crate. What the family changes: the scan's stated odds (under 1e-300) assume independent attempts, and section 6 measures a per-era exhaustion rate 1,000x the independent estimate at the lossy corner, so the fallback's odds are the corner's, not the arithmetic's; ring A keeps the corner out of the band | the reject-everything mirror; the 61 exhausted eras of section 6 (the scan's verdict on each is the full report's item 5) | 0 reached in 1.02 x 10^6 seeds of the shipped draw; 0 of 19,000 family eras outside the lossy corner | n/a |
| The cap and the last resort | unchanged at 256; class v5 carries the verified construction (`last_resort_v5`: a scan of 256 more candidates past the cap, each rewritten and its stale loads re-sourced, the first that passes the whole rule; the unchecked fallback behind it), so adv-accept-3's finding 1 (sub-version 3's unchecked last resort failing (a) in 9 percent of seeds) is closed on the family's crate. What the family changes: the scan's stated odds (under 1e-300) assume independent attempts, and section 6.4 measures a per-era exhaustion rate about 6x the independent estimate at the lossy corner on the 256-instruction shape (the attempts of one era share its weight table), so the fallback's odds are the corner's, not the arithmetic's; ring A keeps the corner out of the band, and on every exhausted era seen (41) the scan passed at its first to third candidate | the reject-everything mirror; the 61 exhausted eras of section 6 (the scan's verdict on each is the full report's item 5) | 0 reached in 1.02 x 10^6 seeds of the shipped draw; 0 of 19,000 family eras outside the lossy corner | n/a |
### 3.3 Ring C: the offline tests per drawn era
@ -178,18 +178,18 @@ What the family gate cannot see, and how a chip would use it.
| Blind spot | Why the gate misses it | What a chip gets from it | Bound today |
|---|---|---|---|
| The era-stride class, measured today at the bit level on 7 of 16 drawn eras (section 3.2): not diffuse, a 25 percent bias on ONE address bit (bit R, the product's bit 0 through `rotl(x * M, R)`) at one site, on programs every floor passes | the (c''') floor reads distinct counts, which a one-bit bias barely moves (0.9954 to 1.0000 on the seven); the bit read sees it at 130 to 511 sigma but refusing it would redraw about 40 percent of epochs; the class is structural (`load_index`'s form and the weights' products), so the catch is a next-class change to the address form, not a per-era floor | a store holding the favoured half of that site's window (128 MiB at D = 28) serves 75 percent of that site's reads instead of 50: 25 percent of 1/16 of a hash's reads, about 1.6 percent of reads at f = 1/2 from one site in about 40 percent of eras (arithmetic on the measured bias); the honest partial-store curve already costs 1.26x the ops at f = 1/2 (adv-cache-2 Q4), so the f = 1 verdict stands; the top-0.1-percent reading of the ledger (1.0024x) was the same class seen through the coarser instrument | the per-era record (ring A names the rotation class; ring B logs the bit read); the structural fix is the family's first owed item for the research lane |
| The era-stride class, measured at the bit level on half the eras of every stratum (sections 6.2 and 6.8): not diffuse, a 25 percent bias on ONE address bit (bit R, the product's bit 0 through `rotl(x * M, R)`, z = -512 at 2^20 exactly) at one site, on programs every floor passes; the morning's F8 tail and the hash lane's p212 and p225 are the same mechanism | the (c''') floor reads distinct counts, which a one-bit bias barely moves (0.9954 to 1.0000 on the seven); the bit read sees it at 130 to 511 sigma but refusing it would redraw about 40 percent of epochs; the class is structural (`load_index`'s form and the weights' products), so the catch is a next-class change to the address form, not a per-era floor | a store holding the favoured half of that site's window (128 MiB at D = 28) serves 75 percent of that site's reads instead of 50: 25 percent of 1/16 of a hash's reads, about 1.6 percent of reads at f = 1/2 from one site in about 40 percent of eras (arithmetic on the measured bias); the honest partial-store curve already costs 1.26x the ops at f = 1/2 (adv-cache-2 Q4), so the f = 1 verdict stands; the top-0.1-percent reading of the ledger (1.0024x) was the same class seen through the coarser instrument | the per-era record (ring A names the rotation class; ring B logs the bit read); the structural fix is the family's first owed item for the research lane |
| A joint corner no stratum names | the 128 cells pin the axes with a KNOWN mechanism; a mechanism that needs, say, a particular `M` with a particular weight table and a particular shape is reached only by the random stratum, which bounds its fraction at 3/n | one era (180 days) of whatever the corner is worth, at most once per occurrence | 1/64 to 1/256 of eras untested at 95 percent (section 2.1); the chain-run rings catch the known shapes on every era |
| The mixer below adv-mixer-3's bands | biases under 0.00018 (Q2b), correlations under 0.00073 with multi-bit masks, differentials under 2^-19, any structure a SAT model of 2 or more applications would expose; at `m = 4` the measured margin is 2 applications | a shortcut that saves applications against the 9,360 ops per item; none found at any k | the round margin, stated; `m = 4` is the corner that spends 4 of the 6 measured spare applications |
| The verifier at `m = 16` and rung 2 on a 2019-class core | unmeasured (an estimate of 9 ms against the 10 ms gate) | nothing for a chip; a node tier retired if the corner is drawn | the row is owed before 16 enters the band |
| The acceptance's stand-in at D = 28 against a live D = 29 | the windows cap `min(k_off, D - 26)` and the rotation's cut set move with D; the gap is measured at D = 28 only | a per-site concentration the closed form does not reproduce | 0.0004 at D = 28; unmeasured at 29 (ring C row) |
| The union bound's own looseness | the per-test miss rates rest on 3 to 11 known-failed cases each (section 2.2), so the family's false-pass rate is not yet a number under 1 | nothing new; the bound is on what the gate claims, not on the hash | fixed by cases, not eras: 60 fired cases per test for `delta` under 0.05 |
| The last-resort path at a corner | class v5's scan hands out a rule-checked program, and its unchecked fallback is priced at under 1e-300 on INDEPENDENT attempts; the lossy corner measured 1.2 percent of eras exhausting against a 1.3e-5 independent estimate, so at a corner the attempts of one era are correlated through the era's own weights and the fallback's odds are unknown there | a program that re-reads one address in two loads of the same hash, if the fallback were ever reached | ring A keeps the corner out of the band (0 of 19,000 eras exhaust elsewhere); the scan's verdict on the 61 exhausted eras is owed (section 7 item 5) |
| The last-resort path at a corner | class v5's scan hands out a rule-checked program, and its unchecked fallback is priced at under 1e-300 on INDEPENDENT attempts; the lossy corner measured 3.3 percent of 256-shape eras exhausting against a 0.5 percent independent estimate (section 6.4), so at a corner the attempts of one era are correlated through the era's own weights by a factor of several and the fallback's odds there are the measured curve's, not the arithmetic's | a program that re-reads one address in two loads of the same hash, if the fallback were ever reached | ring A keeps the corner out of the band (0 of 19,000 eras exhaust elsewhere); the scan's verdict on the 61 exhausted eras is owed (section 7 item 5) |
| The era redraw's own grindability | a ring-A redraw consumes the stream's next block, so an adversary who could steer `E_n` could steer which block is used; the era VDF of F7 (517 s on the fastest prover, 259x the window) closes the steering of `E_n` itself | nothing beyond F7's bound | F7 (a) PASS with the VDF in the node |
A GPU-like chip (the `f = 1` stored-dataset chip with a programmable core, chip-model-v3 section 5) loses nothing on any era of the family: every drawn parameter is firmware to it, and what the family costs it is the core sized for the band's top (the research lane's USD 30 to 60 per chip, modelled). The family gate's job is therefore not to defeat that chip (the identity of the research file's section 2 says the per-joule edge is the card's own idle, 2.1x at `k = 1`) but to make sure no drawn era hands ANY chip more than the one hash did: a per-era hot set, a per-era mixer shortcut, a per-era verifier miss. Everything in this document is a bound on that increment, and the increments found so far are 1.002x and 1.0024x.
## 6. The coverage measured (24,000 drawn eras, 11:16 to 12:13 BST, 8 October 2026)
## 6. The coverage measured (38,000 drawn eras in 6.1 to 6.5, the lossy curve, the live censuses, the sigma form and the verifier rows; 11:16 to 15:3x BST, 8 October 2026)
The harness: branch `family-gate-v5` at 3dc3117c (the class v5 crate 8f481459 plus `accept::tests::family_gate_era_census`; the diff is `logs/harness-family-gate-v5-3dc3117c.diff` (a plain diff of igneum-pow/src: the gate refuses the patch form's author lines) in this directory, since the branch's push to the mirror was refused by the class v5 tree's own pre-push hook and is held). What it does per era `k` of a label space: the era bytes from `igneum-family-gate[/stratum]/era/k` and the epoch bytes from `.../program/k` (the F8 label space's form); from the era's own stream, in a fixed order and consumed whether pinned or not, the shadow block shape in {64 x 108, 128 x 54, 256 x 27}, the mixer multiplier in {4, 8, 16} (recorded: the acceptance never runs the mixer), the ten non-load weights perturbed by `below(2B + 1) - B` with shfl and mulhi never raised and renormalised to 75 by largest remainder (B = 4), the read width through the era draw over {1, 4} words (the mix one-hot on the drawn width); then the chain draw of that era's epoch through the real rule keyed on the family's shape (`is_family_shape`, the acceptance's `is_class_v4_shape` generalised behind `IGNEUM_FAMILY_GATE`; the draw's source rule reads the same predicate), every candidate's first failing part recorded, the cap 256 and the last resort as shipped; on the accepted program, on the rule's own 2^20 sample (4,096 units), per site: the (c'') and (c''') ratio with the window divided by the width, the largest 4,096-word (256-item) bucket in sigma of its expectation, and the largest index-bit one-count excess in sigma over the free bits. One TSV row per era (`logs/<stratum>-family_gate_era_census-<from>-<n>.tsv`, the run's log beside it with the binary's sha256 and the lease line); every binary a pinned copy under `/srv/builds/_adv-family-gate/bin/<tag>/` (fg2 9b7f764a for the first corners, fg5 e7a50f8d for the width-4 and lossy-base strata). Cost: about 10 core-seconds per era; 54.4 core-hours in all (1.7 box-hours of 32-core slots) on build-1 (random, lossy cap, width 4) and build-3 (shape 64, lossy base, width 4 plus lossy cap), every run under `lease pool` at class measure. The control: `v5_attempts_census` on the shipped class v5 draw over 10,000 seeds of the F8 label space (build-1, 24 cores, 1,534 s, binary 4bec799c, `logs/base-v5_attempts_census-1000-10000.log`): r = 0.6854, mean attempt 2.179, 0 exhaustions, (a') 82.5 percent of rejections, (c''') 0.9 percent, the row-90 reading reproduced.
@ -229,7 +229,7 @@ Readings, each a measured row above:
1. The mixer axis is invisible to every per-era statistic, as section 1.3 said it must be: the three `m` values read the same to the noise (r 0.714 to 0.731, the biased share 51 to 52 percent). `m` is a per-family axis, closed by the mixer rows of section 4, not by drawing eras.
2. The shape axis moves the draw's cost: 256 x 27 costs 3.82 attempts against 1.81 at 64 x 108 (r 0.792 against 0.645), because the freshness fixpoint (a') walks the whole block and a 256-instruction block holds more lossy last writers per iteration than a 64-instruction one. The band's cheapest shape is the fastest card shape too (64, measured 2.5 to 3.5 percent faster on 6 October).
3. The width axis moves the (c''') floor's calibration: at width 4 the floor at 0.995 refuses 4.5 to 6.5 percent of candidates against 0.6 to 1.0 at width 1, with the expectation already divided by the width. The clean spread of the ratio at width 4 is not the width-1 spread the floor was set from (the aligned index space is a quarter the size, so the birthday collisions on the closed form are 4x denser, and the `N - N^2 / 2W` form is 0.0007 low at `N / W = 1/16`). A floor fixed at one number across the family is therefore a per-width liveness cost of 4x the (c''') attempts; the family's floor is set per width from the clean spread (the next measurement, section 7 item 1), or the statistic is re-expressed as a sigma over its own expectation as the bucket statistic now is.
4. The lossy corner breaks the exhaustion bound: r = 0.957 to 0.959 and 1.2 percent of eras at the 256 cap in both lossy strata (61 of 5,000), against 0 of 19,000 in every other stratum and 0 of 10,000 on the shipped draw. The arithmetic agrees: 0.957^256 = 1.3e-5 per seed is the geometric estimate, but the attempts are not independent across one seed's candidates (the lossy weight table is shared by every attempt of the era, so the rejection rate per era is itself drawn from a spread), and the measured per-era rate is 1.2e-2, three orders above the independent-attempt figure. The ring-A rule is the one the data forces: or + mul + mulhi never raised above the table's 18 of 75. Under it (the lossy-base stratum) r = 0.595, the mean attempt 1.47, the maximum 59, 0 exhaustions in 3,000.
4. The lossy corner breaks the exhaustion bound: r = 0.957 to 0.959 and 1.2 percent of eras at the 256 cap in both lossy strata (61 of 5,000), against 0 of 19,000 in every other stratum and 0 of 10,000 on the shipped draw. Read per shape (section 6.4) the exhaustion sits on the 256 x 27 shape alone (3.3 to 3.6 percent of its eras; 0 of 5,000 at 64 x 108), where r = 0.98 and the independent-attempt figure 0.98^256 is 0.5 percent: the attempts of one era are correlated through its weight table by about 6x. The ring-A rule is the one the data forces: or + mul + mulhi never raised above the table's 18 of 75. Under it (the lossy-base stratum) r = 0.595, the mean attempt 1.47, the maximum 59, 0 exhaustions in 3,000.
5. The index-bit bias is the family's standing fact: 48 to 58 percent of accepted programs in every stratum carry one site with a bias over 6 sigma at 2^20, and 73 percent of those are at bit R exactly, 12 percent at R + 1, 5 percent at R + 2 (the product law's bits 0, 1, 2 at P = 1/4, 3/8, 7/16 through `rotl(x * M, R)`); 74 percent read P(bit) under 1/2 (a product's low bit), 26 percent over 1/2 (an or-shaped source, 5/8 and up). Under R in 28..31 (bit 0 cut by the 28-bit mask) the share over 100 sigma falls from 37.7 to 7.5 percent and the bucket excess's p99 from +44 to +6.5 sigma, which is adv-cache-2's R-class reading at 10,000 eras. The shipped devnet's R = 29 is one of the four clean rotations; the chain's eras are drawn from all 31. The bucket statistic and the bit statistic see the same mechanism (the bucket's p99 on the bit-clean eras is +6.8 sigma, on the biased ones +44), so one next-class test covers both: the value-level read, with the structural fix in `load_index` as the remedy rather than a refusal (a 6-sigma refusal redraws half the epochs; a 100-sigma one a third).
6. The (c''') floor holds everywhere by construction (0 accepted programs under 0.995) and its clean spread at width 1 is the shipped one (p1 of the minimum ratio 0.9958 to 0.9961, median 0.9999 across strata); the floor's refuse rate moves from 2.7 percent (random) to 3.9 (the band) and 0.4 (the lossy corner, where (a') refuses first).
@ -237,25 +237,96 @@ Readings, each a measured row above:
| Claim | n | Bound at 95 percent | Bound at 99 percent |
|---|---|---|---|
| An era of the proposed band whose chain draw exhausts the 256 cap | 3,000 of 3,000 passed (lossy base) | under 1.0e-3 of eras (one in 1,000: one per 490 years at 180-day eras) | under 1.5e-3 |
| An era of the proposed band whose chain draw exhausts the 256 cap | 9,000 of 9,000 passed (lossy base 3,000, the width-1 and width-4 band strata 3,000 each; the afternoon's strata) | under 3.3e-4 of eras (one in 3,000: one per 1,500 years at 180-day eras) | under 5.1e-4 |
| The same on the random stratum at B = 4 on every family | 10,000 of 10,000 | under 3.0e-4 | under 4.6e-4 |
| An era of the band whose accepted draw sits under the (c''') floor | 3,000 of 3,000 (and 19,000 of 19,000 outside the lossy corner) | under 1.0e-3 | under 1.5e-3 |
| An era of the band whose accepted draw sits under the (c''') floor | 9,000 of 9,000 (and 33,000 of 33,000 outside the lossy corner, every stratum of the day) | under 3.3e-4 | under 5.1e-4 |
| An era of the lossy corner that exhausts | 61 of 5,000 FAILED | the rate is 1.2 percent, a measurement, not a bound: the corner is out of the band; class v5's last-resort scan then hands each such era a rule-checked program (the scan's own verdicts on the 61 are owed) | |
| The (c''') floor's miss rate on the few-item hot-set class | 9 of 9 fired (unchanged: this census reads the acceptance's sample, not the live dataset) | under 0.33 | under 0.40 |
| The bit-bias read's firing on the product class | 5,172 of the random stratum's eras read over 6 sigma; the three named cases (Devnet 3 site 0, era-drawn-28 site 15, the per-load candidate 0) are of that class | a record, not a refusal: no miss rate is claimed | |
| The (c''') floor's miss rate on the few-item hot-set class | 11 of 11 fired (the in-house pass's nine, plus point A's p38 and p54 under a band era's weights, section 6.6) | under 0.27 | under 0.34 |
| The bit-bias read's firing on the product class | 7 of 7 named seeds at 6 sigma (p4, p8, p10, p34, p212, p225, p15; section 6.8) and the three attributed sites of the pass; 5 of 7 at 300 sigma | under 0.35 at 6 sigma on the named set; the read is a record, not a refusal, so no miss rate is claimed for a chain rule | |
The union bound stays loose where section 2.2 said it would: the two floors' miss rates on the live-dataset classes rest on nine and five cases, and this census adds cases to the exhaustion and bias rows only. The live-dataset census at 2^24 on 64 seeds of two eras of the band (one at width 4, one at R in 1..27 with a 1,000-sigma site) is the next ring-C row (section 7 item 6); it is what turns the bit read's z into a per-era hot-set price on the real item map.
## 7. Owed by 09:00 BST on 9 October (the full report)
### 6.4 The lossy-share curve, per shape (build-1, 12:5x to 13:2x BST; 3,000 eras per point, every other axis drawn)
1. The (c''') floor's clean spread per width (and per shape) from the accepted draws of section 6, with the per-width floor or the sigma form that keeps the clean refuse rate near the shipped 2.4 percent; the spec line for 1.4.6.5's expectation under a drawn width.
2. The bucket bound stated in sigma from the bit-clean spread (p99 +6.8, max +28 over 4,828 eras): a band at +8 sigma refuses under 1 percent of bit-clean programs and every F8 tail seed (+17 to +37); its cost on the biased eras is the bit read's cost, so the two tests are one rule.
3. The lossy-corner reading taken one step further: the exhaustion rate per era against the lossy share in points (18 to 30 of 75), so the band's edge is a measured curve, not one corner; 10^4 seeds at each of three shares.
4. The mixer rows at `m = 4` and 16 (adv-mixer-3's index and sac at k = 2 on two days; the SAT at k = 2) as the per-family corner rows, on build-4 when its pool frees; else the plan with its hours.
5. The class v5 last-resort scan on the 61 exhausted eras (the first passing k past the cap, or the fallback), and the lossy-share curve at +1, +2, +3 and +4 points (3,000 eras each, running on build-1 from 12:5x BST with the fg6 harness).
6. The F8-form census at 2^24 on 64 seeds of two eras of the band (one at width 4, one with a 1,000-sigma site under R in 1..27), the first ring-C rows on the family (about 2 box-hours each): the live-dataset hot-set price of the bit-level bias.
7. The gate-record JSON per era (the format of 4.3) generated from the TSV rows by `fg-records.py` (in `logs/`), and the family summary.
8. The two build-4 strata (shape 64 plus lossy cap, shape 256) when its pool frees; nothing in the cut depends on them.
The band's edge measured as a curve rather than a corner: or, mul and mulhi each raised by the same number of points over the table (the lossy share of the 75 non-load points from 18 to 30), the seven injecting families drawn within B = 4 as before. `r` is the per-candidate rejection, `r^256` the exhaustion figure the independent-attempt arithmetic of spec 1.4.6.6 would give, the measured column what the eras did.
| Lossy points added | Lossy share of 75 | Shape | Eras | r | r^256 (independent attempts) | Exhausted, measured | Mean attempt | Max | Past attempt 31 |
|---|---|---|---|---|---|---|---|---|---|
| +0 (the band) | 18 | 64 x 108 | 980 | 0.550 | 4e-67 | 0 | 1.22 | 14 | 0.0 percent |
| +0 | 18 | 128 x 54 | 963 | 0.562 | 1e-64 | 0 | 1.28 | 12 | 0.0 |
| +0 | 18 | 256 x 27 | 1,057 | 0.651 | 2e-48 | 0 | 1.87 | 59 | 0.2 |
| +1 | 21 | 64 | 1,009 | 0.716 | 7e-38 | 0 | 2.52 | 46 | 0.2 |
| +1 | 21 | 128 | 1,015 | 0.768 | 4e-30 | 0 | 3.31 | 47 | 0.1 |
| +1 | 21 | 256 | 976 | 0.867 | 1e-16 | 0 | 6.50 | 142 | 2.3 |
| +2 | 24 | 64 | 1,010 | 0.772 | 2e-29 | 0 | 3.39 | 52 | 0.4 |
| +2 | 24 | 128 | 991 | 0.841 | 5e-20 | 0 | 5.29 | 55 | 1.4 |
| +2 | 24 | 256 | 999 | 0.928 | 4e-9 | 2 (0.20 percent) | 12.29 | 249 | 8.8 |
| +3 | 27 | 64 | 1,012 | 0.829 | 1e-21 | 0 | 4.85 | 58 | 1.2 |
| +3 | 27 | 128 | 980 | 0.885 | 2e-14 | 0 | 7.66 | 73 | 4.1 |
| +3 | 27 | 256 | 1,008 | 0.958 | 2e-5 | 6 (0.60 percent) | 21.25 | 241 | 19.6 |
| +4 (the corner) | 30 | 64 | 1,004 | 0.872 | 6e-16 | 0 | 6.83 | 56 | 2.5 |
| +4 | 30 | 128 | 998 | 0.924 | 2e-9 | 0 | 12.21 | 117 | 7.7 |
| +4 | 30 | 256 | 998 | 0.979 | 5e-3 | 33 (3.31 percent) | 38.53 | 244 | 36.7 |
Readings. (1) The exhaustion is a shape-256 interaction, not a corner-wide one: no era of shape 64 x 108 exhausted at any lossy share (0 of 5,015 across the five points, plus 0 of 2,000 on build-3's shape-64 lossy-cap stratum and 0 of 646 at width 4), one of 4,947 at 128 x 54 (the first corner stratum), and every other exhaustion at 256 x 27. The 256-instruction block holds three times the lossy last writers of a 64-instruction one, and (a')'s fixpoint walks the whole block. (2) The morning's "1,000x above the independent estimate" was the mixed-shape average read against the mixed-shape `r`; per shape the gap is about 6x (0.979^256 = 0.5 percent against 3.3 percent measured at 256 x 27 and +4; 1.7e-5 against 0.6 percent at +3), so one era's attempts are correlated through its weight table by a factor of several, not thousands. The arithmetic of 1.4.6.6 is therefore an under-estimate by that factor at any lossy share, which the band's rule absorbs by holding the share at 18 (where `r` is 0.55 to 0.65 and `r^256` is under 1e-48). (3) The band's edge: at +2 on the 256 shape 8.8 percent of eras pass attempt 31 and 2 of 999 exhaust; the ring-A rule "lossy families never raised above their base" is the measured line, and the research lane's layer 1 carries it (section 5.1b of `docs/design/class-v6-rotating-family.md`). (4) Every exhausted era of every stratum took class v5's last-resort scan and passed at its first candidate past the cap (k = 256) in 38 of 41 cases, at k = 257 or 258 in the other three: the rewrite plus the stale-load repair hands the chain a rule-checked program at once, and the unchecked fallback was never reached.
### 6.5 The pre-floor spread per width and the width-4 floor (W = 4 words pinned at genesis by the research lane)
Measured on the fg7 harness (the ratio of every candidate the two floors refuse, beside the accepted draw's), 3,000 eras per width under the band (build-2 `logs/w1band-*`, build-3 `logs/w4band-*`):
| Width | Candidates | Reaching the 2^20 pass (every earlier part passed) | (c'') refused at 0.98 | (c''') refused at 0.995 | Pre-floor minimum-site ratio of the reaching candidates: p1 / p2.5 / p5 / p10 / median | A floor at 0.990 / 0.993 / 0.995 / 0.996 refuses (percent of reaching candidates) |
|---|---|---|---|---|---|---|
| 1 word | 6,920 | 3,093 | 38 (1.2 percent) | 55 (1.8 percent) | 0.968 / 0.993 / 0.9961 / 0.9978 / 0.9999 | 1.8 / 2.4 / 3.0 / 3.9 |
| 4 words | 8,270 | 3,646 | 113 (3.1 percent) | 533 (14.6 percent) | 0.912 / 0.971 / 0.985 / 0.991 / 0.9999 | 9.5 / 15.1 / 17.7 / 19.0 |
Reading. At width 4 the statistic itself moves, not just its tail: a tenth of the candidates that reach the 2^20 pass read a minimum-site ratio under 0.991, against 2 percent at width 1, with the expectation already divided by the width. The aligned index drops the two low address bits, so a site whose source carries its entropy in the low bits reads full at width 1 and concentrated at width 4; the shift is in the programs, not in the formula (the `N - N^2 / 2W` form is 0.07 percent low at `N / W = 1/16`, nothing like the 1 to 9 percent seen). So no single number keeps the clean refusal near the shipped 2.4 percent at width 4: a floor at 0.990 still refuses 9.5 percent of reaching candidates (3.8 percent of all candidates), and the sigma-over-expectation form would re-scale the same distribution without moving its tail. The decision this lane ships for the 09:00 report: keep (c''') at 0.995 at width 4, with its measured cost (14.6 percent of reaching candidates, 6.5 percent of all candidates, +0.3 attempts per epoch, about 0.7 s per epoch per node at 2.2 s per candidate), because the floor's job is soundness and the known-failed hot sets of point A sit at 0.9932 and 0.9945 (section 6.6), inside the band a lower floor would admit; and read the 0.990 to 0.995 band at width 4 on the live dataset (a ring-C row, the census at 2^24 on 64 width-4 seeds) before any floor moves, since whether those candidates are hot sets or thin spreads is exactly the question adv-accept answered at width 1 (7 of 12 deep seeds were thin spreads) and nobody has answered at width 4.
### 6.6 Ring C: the live-dataset census at two band points
Point A DONE (build-1, 11:3x to 13:49 BST, 4,783 s on 24 pool cores, about 32 core-hours; `logs/f8-A.log`): attack-f8's 64-seed census (p2 to p65 of the F8 label space, each seed its own era, 2^24 nonces each, the window-model control, the by-site attribution) built against the family crate with the band era 49's weight table (add 17, xor 6, mul 4, mad 13, shfl 9, rotl 9, sub 2, mulhi 2, rotr 9, or 4) at shape 256 x 27 and width 1. The class-v5 tree's copy of attack-f8 predates the `--class v5` path, so the draws are generator 4 under the family's shape predicate: sub-version 3's rule with (c'') at 0.98 and WITHOUT class v5's (c''') floor at 0.995. Result: 45 of 64 PASS with no test fired; 3 beyond 1.2x of the window model at the top 0.1 percent (p38 1.678x, p54 1.589x, p4 1.297x; the shipped class read 4 of 64 over, p4 among them at 1.217x); HOT SETS in 2 (p54: X at 0.1 percent +0.120, X at 1 percent +0.684; p38: +0.102 and +0.576), against 0 of 64 on the shipped class; windowed 64-item buckets beyond 6 sigma in 18 of 64 (the bit-level class of section 6.2 seen on the live item map: p38's largest bucket +106 sigma, p4's +84), against the shipped class's 4. The class v5 floor's read on the same 64 programs (`v5_hot_census` under the same weight table, build-3, queued at 13:5x BST) says whether (c''') refuses p38 and p54 as it refused the nine hot sets of the in-house pass; LANDED 14:3x BST (build-3, 79 s on 8 threads, `logs/floor-read-A.log`): the class v5 floor at 0.995 refuses 3 of the 64 class v4 draws, p38 at 0.9932 (site 0), p54 at 0.9945 (site 12) and p11 at 0.9933, so BOTH hot sets of point A are refused and the class v5 draw moves to the next attempt (min ratio 0.9999 on each); p4 at 0.9963 passes, as it did on the shipped class. The floor does under the family's weights what it did on the shipped class: nine of nine then, two of two now. What a chip gets from p54 as it stands (on the class v4 rule; under class v5 it never runs): the top 1 percent of items (16 MiB) holding 0.68 percent more of the reads than the window model, the 1.002x class of the ledger, no row of the chip model moves; what an auditor sees is two hot sets in 64 epochs where the shipped class had none, which is the per-era weight axis showing on the item map and the reason the floor is a per-epoch rule and not a per-class census.
Point B DONE (build-3, 12:2x to 15:30 BST on 8 then 16 pool cores; `logs/f8-B.log`, `logs/floor-read-B.log`): the same census at shape 64 x 108 with the band era 5's weight table (add 11, xor 15, mul 6, mad 9, shfl 7, rotl 11, sub 4, mulhi 6, rotr 2, or 4). Result: 46 of 64 PASS with no test fired; HOT SETS in 0; 5 beyond 1.2x of the window model at the top 0.1 percent (p10 1.505x, the seed the shipped class reads at 1.504x with the same hottest item; p42 1.472x; p64 1.351x; p18 1.215x; one more at 1.2x to 1.21x), against the shipped class's 4 of 64; windowed buckets beyond 6 sigma in 18 of 64 (p64's largest bucket +150 sigma, p42's +105, p10's +100: the bit-R class again); the class v5 floor refuses 1 of the 64 draws (p15 at 0.9934, the draw moving to attempt 4 at 0.9993), the next lowest 0.9957 to 0.9962 pass. So the 64-instruction shape under a band table reads the shipped class's own profile on the live item map (the same tail seeds over 1.2x, no hot set, the same bucket class), and the shape axis moves the draw's cost (section 6.4) and nothing on the item map. Across the two points: 128 live epochs of the band, 2 hot sets (both at the 256 shape, both refused by the floor), 8 over 1.2x (the shipped class: 4 of 64), 36 with a site over 6 sigma on the windowed buckets (the shipped class: 4 of 64; the bit-R mechanism of section 6.8, which the family's weight tables widen from a 6 percent to a 28 percent share of epochs on the live map); chip price of the worst: the 1.002x class of the ledger. What this ring-C pair bounds: the fraction of band epochs with a hot set under the class v4 rule is under 3/128 = 2.3 percent at 95 percent, and 0 of 2 reached the chain under class v5's floor.
### 6.7 The mixer axis per family: the verifier rows at x4, x8 and x16 (build-3, 15:1x BST, `logs/bench-x{4,8,16}.log`)
`igneum-pow bench --seed igneum-genesis --day 2026-10-03 --class v2m<m>g+sh256x27 --warps 50` (the fg7 CLI; `v2m8g+sh256x27` is the class v4 shape and prints as `mx8+sh256x27`), one leased core of build-3 (AMD Ryzen 9 7950X3D, the box at load from the point-B census and the strata; the cold warp is the ladder's method, one warp per vector base, then the average of 50):
| Mixer `m` | Mixers per item | Cold warp, ms (base 0 / 4,096 / 1,000,000) | Average of 50, ms | Against x8 | Scaled to the 2019-class core (the O-1.14 i7-9700K read x8 at 6.33 cold) | Scaled to the half-core proxy (x8 at 8.23) | The 10 ms gate |
|---|---|---|---|---|---|---|---|
| 4 | 36 | 4.07 / 3.65 / 3.66 | 3.73 | 0.91x | about 5.7 | about 7.5 | passes with margin |
| 8 (the shipped class) | 72 | 4.37 / 4.16 / 4.11 | 4.12 | 1.00x | 6.33 (measured) | 8.23 (measured) | passes |
| 16 | 144 | 7.43 / 7.23 / 7.15 | 7.13 | 1.73x | about 11.0 | about 14.2 | FAILS on both proxies (approximate: a ratio scaling; the x16 row on the proxies themselves is the hash lane's to take) |
Reading. The mixer's cost sits in the item derivation, which the verifier pays in full (4,096 items per warp) and the card hides behind the dataset build: x16 adds 3.0 ms per warp on this core, 73 percent over x8, so on the 2019-class core and the half-core proxy it lands over the 10 ms gate by one to four milliseconds. The band for `m` is therefore {4, 8} on the verifier's measured rows, with 16 outside it until a verifier change (or the ladder's rung 0 budget re-cut) brings it under 10 ms; x4 keeps 2 of 4 applications of measured margin (adv-mixer-3's rows clean from k = 2) against x8's 6 of 8, so the family's safe band on this axis is x8 with x4 as the one corner, and the chip row of chip-model-v3 (the f = 0 recompute chip's rate halving per doubling, the f = 1 chip unmoved) is unchanged by the draw. Per tier: nothing moves for a card (the item derivation is the daily build, 42 ms at x8 on the 5090); a node verifying x4 saves 10 percent of a warp, x16 would cost it 73 percent more and the 2019-class tier its margin.
### 6.8 The two next-class tests on one scale: the known-failed cases through the sigma form (build-2, 14:2x BST, `logs/f8space-*`)
The F8 label space's p2 to p65 and p212 to p225 drawn at the shipped parameters through the family harness (shape 256 x 27, m = 8, width 1, the table weights, B = 0; every attempt equal to the chain's class v5 draw, p2 at 5, p3 at 1, p4 at 0, p8 at 2, p10 at 0, p212 at 4, p225 at 0), read at the rule's own 2^20 sample: the minimum (c'') ratio, the largest 4,096-word bucket in sigma of its window expectation, the largest index-bit one-count excess in sigma.
| Seed | What it is | min ratio, site | Largest bucket: ratio, sigma, site (window) | Bit bias: sigma, site, bit | R | Bucket band at +8 | Bit band at 6 sigma | Bit band at 300 sigma |
|---|---|---|---|---|---|---|---|---|
| p4 | the morning's tail (1.217x live) | 0.9961 at site 1 | 7.17x, +49.4, site 1 (quarter) | -511, site 1, bit 13 | 13 | caught | caught | caught |
| p8 | the tail (1.378x) | 0.9963 at site 14 | 3.72x, +21.8, site 14 (quarter) | -513, site 6, bit 22 | 22 | caught | caught | caught |
| p10 | the tail (1.504x) | 0.9963 at site 8 | 6.27x, +42.1, site 8 (quarter) | -513, site 8, bit 17 | 17 | caught | caught | caught |
| p34 | the tail on sub-version 3 (1.250x; not on class v5's list) | 0.9999 | 2.38x, +5.5 (clean) | +10.8, site 4, bit 7 | 7 | missed | caught | missed |
| p212 | the hash lane's F8-256 attribution: site 9's bucket at 1.75x its window expectation, 0.019 bits short | 0.9958 at site 9 | 1.72x, +5.75, site 9 (quarter): the clean spread's own maximum | -512, site 9, bit 8 | 8 | missed | caught | caught |
| p225 | the hash lane's value-level concentration at a mad-written site, the bucket at expectation | 0.9974 at site 4 | 2.38x, +5.5 (clean) | -567, site 4, bit 2 | 2 | missed | caught | caught |
| p23, p19, p18, p56 | the strong seeds of sub-versions 1 and 2, closed by (a') and (c'') | 0.9999 to 1.0000 | +5.1 to +5.5 (clean) | under 4.4 | | clean | clean | clean |
| p15 | the same | 0.99997 | +6.0 | -58, site 0, bit 0 | 26 | clean | caught | missed |
Reading. (1) Every named case is the SAME mechanism at the bit level: a product's bit 0 (P = 1/4, z = -512 at 2^20 exactly: (0.25 - 0.5) x 2^20 / 512) or bit 1 at address bit R of one site; the bucket statistic sees it only when R lands inside the 4,096-word bucket's bits at a narrow window (p4, p8, p10 at bits 13, 22, 17 on quarter windows) and not when it lands below bit 12 (p212 at bit 8, p225 at bit 2). So the bucket bound at any band catches a subset of what the bit read catches, and p212 and p225 are exactly the cases the research lane asked about: a bucket bound at about 2x (+8 sigma at 2^20) refuses p4, p8 and p10 and neither of the two; a bucket bound at 1.5x would take p212 (1.72x) at a cost the random stratum prices at 7.3 percent of eras over +15 sigma and 14.5 percent over +8 (the biased population, section 6.2), not the 3 to 6 percent of a clean spread. (2) The bit read at 6 sigma catches all seven named cases (p34 and p15 too); its cost is the family's standing fact, 48 to 52 percent of eras over 6 sigma, 34 percent over 100, 16 percent over 300, 11 percent over 500 (random stratum, 10,000 eras; the band 47.7, 31.1, 15.7, 11.1; width 4 under the band 44.9, 26.5, 9.4, 5.6). A band at 300 sigma catches p4, p8, p10, p212, p225 (all at or above 511) and misses p34 (+10.8) and p15 (-58), at a redraw cost of 16 percent of epochs; the clean-era maximum over 26 bits and 16 sites is 5.5 sigma at p99, so nothing clean is refused at any band from 6 up. (3) The bucket excess beyond what the bit read already names is 0.07 to 0.23 percent of eras (bucket over +8 with every bit under 6 sigma: 15 of 10,000 random, 7 of 3,000 band, 2 of 3,000 at width 4), which is the bucket bound's whole independent catch; a chip reads nothing in it that the bit read did not price. The decision this lane ships: ONE value-level test, the per-site index-bit read, as a per-era RECORD at the acceptance's 2^20 sample (its z at bit R names the product writer for the record) and as the structural lever's known-failed set (the seven seeds above), with the bucket bound retired into it; the refusal band, if the research lane wants one before `load_index`'s fold lands, is 300 sigma (five of seven named cases, 16 percent of epochs redrawn) and never 6 (half the epochs).
## 7. The 16:30 BST report (the founder's clock, pulled from 09:00; a partial carries its count)
1. DONE 13:2x BST: the lossy-share curve per shape (section 6.4) and the last-resort scan's verdicts on every exhausted era.
2. DONE 14:4x BST: the pre-floor spread at width 4 against width 1 under the band and the floor decision (section 6.5: 0.995 kept at width 4 at its measured cost; the 0.990 to 0.995 band at width 4 read live before any floor moves).
3. DONE 15:30 BST: the two ring-C live-dataset rows (section 6.6: 128 live epochs of the band, 2 hot sets at the 256 shape both refused by the floor, 0 at the 64 shape).
4. DONE 15:1x BST: the x4, x8 and x16 verifier rows (section 6.7, build-3 one core: 3.73 / 4.12 / 7.13 ms per warp; x16 outside the band on the 10 ms gate by scaling to the proxies).
5. DONE 14:4x BST: the width-4 plus shape-64 crossing (build-4, 3,000 eras: r = 0.654, 0 exhausted, (c''') 5.3 percent of candidates, the width's floor cost again) and section 6.8, the F8 label space's p2 to p65 and p212 to p225 through the sigma form at the shipped parameters (build-2, queued 14:0x BST), so the two F8-256 attributions the hash lane added to layer 4's bucket-bound row (p212, site 9 at 1.75x its window expectation; p225, a value-level concentration at a mad-written site with the bucket at expectation) and the morning's four tail seeds are read as known-failed cases of the bucket-sigma and bit-bias tests on one scale; and the bucket bound in sigma (from the bit-clean spread: p99 +6.8, p99.9 +16.5 to +20.1, max +35 over 9,409 eras; a band at +8 refuses 0.3 to 0.4 percent of bit-clean programs and 11 to 18 percent of all, which is the biased population, so the bucket bound and the bit read are one rule).
6. The gate-record form: `logs/gate-records-lossy-base.jsonl` (3,000 records of the band stratum in the section 4.3 shape, one per line, 3.6 MB) and `logs/fg-records.py`, which derives every other stratum's records from its TSV rows in this directory.
7. Amendment by 18:00 BST (the coordinator's order of 15:45): the research lane's best-mix genesis table (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0, sum 83; renormalised to 75 by largest remainder as 14, 13, 4, 11, 3, 10, 9, 2, 9, 0 in the generator's order) through the acceptance at the shipped parameters: the attempts census with the refused-ratio column at widths 4 and 1 (1,500 eras each, build-3, the fg8 harness), the index-bit read, and attack-f8 at 2^20 on 64 seeds; running from 15:5x BST, the verdict to the coordinator, the hash, census and research lanes with its minute.
8. Not in this report: the mixer ladder re-run at m = 4 and 16 (adv-mixer-3's harness rows; the per-family rows of section 4), the F8 census at D = 29 (the stand-in gap row), the 10^5-program verifier census at the top corner (F6 per family): each a named per-family row with its hours in section 4.1.
## 8. Sources

27
docs/analysis/class-v6/floor/denominator.md
View file

@ -118,10 +118,11 @@ Max; the wall more); the NVIDIA and AMD rows are whole-card.
| NVIDIA GeForce RTX 3070 | 8 GB | 4.8 | estimated | 5.29 (measured) | 8.3x / 6.1x / 4.3x | 11.1x / 7.4x / 5.0x | 19.1x / 10.4x / 6.1x | 1800 MHz at 80 percent. the Ampere cap lever on the measured stock rows (class v3 142.3 W, class v4 196.4 W); the 3070 Ti 38.98 MH/s at 177.1 / 267.6 W Stock: rented pods 8 October; the class v5 sweep's two 3070 hosts closed the connection mid-bench |
| NVIDIA GeForce RTX 3060 | 12 GB | 5.77 | estimated | 6.4 (measured) | 10.0x / 7.3x / 5.2x | 13.3x / 8.9x / 6.0x | 23.0x / 12.4x / 7.3x | 1800 MHz at 80 percent. the Ampere cap lever (10 percent) on the measured class v4 stock row; the 3060 Ti at a 130 W host cap held 33.06 MH/s at 128.7 W under class v4 (3.89): a cap row measured on a sibling Stock: class v5 measured on a Vast 3060 (13:53 UK): 26.53 MH/s at 169.8 W (6.40) at the host's 170 W limit (the limit binding: the class v4 pod read 26.89 at 166.1 W, 6.18); class v3 26.53 at 120.4 W on the same host; stock, lock owed |
| AMD Radeon RX 9070 XT | 16 GB | 7.9 | measured | 10.7 (measured) | 13.7x / 10.0x / 7.1x | 18.3x / 12.3x / 8.2x | 31.4x / 17.0x / 10.0x | ADLX -500 MHz, -30 percent. the ADLX grid (24 rows, PC 1): the rate flat at 18.9 MH/s across the grid, the best point -500 MHz core and -30 percent power, 24 percent under stock; class v5 about 8.1 Stock: the app's own power reading at the stock point, 8 October 07:11 UK |
| AMD Radeon RX 7900 XTX | 24 GB | 8.0 | estimated | 10.7 (estimated) | 13.9x / 10.1x / 7.2x | 18.5x / 12.4x / 8.3x | 31.8x / 17.3x / 10.2x | ADLX -500 MHz, -30 percent. not rentable, not owned: the 9070 XT's dependent-read rate per channel (150 M per second per 32-bit channel) on 24 channels; the knob by the 9070 XT grid Stock: modelled |
| AMD Radeon RX 7800 XT | 16 GB | 9.5 | estimated | 12.8 (estimated) | 16.5x / 12.0x / 8.5x | 22.0x / 14.7x / 9.8x | 37.8x / 20.5x / 12.1x | ADLX -500 MHz, -30 percent. 16 channels of GDDR6 at the 9070 XT's per-channel rate; the knob by the 9070 XT grid Stock: modelled |
| AMD Radeon RX 7600 XT | 16 GB | 13.0 | estimated | 17.8 (estimated) | 22.5x / 16.5x / 11.7x | 30.1x / 20.2x / 13.4x | 51.7x / 28.0x / 16.5x | ADLX -500 MHz, -30 percent. 8 channels; the card-in queue holds one for a PC measurement Stock: modelled |
| AMD Radeon RX 9060 XT | 16 GB | 10.0 | estimated | 13.7 (estimated) | 17.3x / 12.7x / 9.0x | 23.1x / 15.5x / 10.3x | 39.8x / 21.6x / 12.7x | ADLX -500 MHz, -30 percent. 8 channels of GDDR6 on RDNA 4; the card-in queue holds one Stock: modelled |
| AMD Radeon RX 7900 XTX | 24 GB | 5.89 | estimated | 7.75 (estimated) | 10.2x / 7.5x / 5.3x | 13.6x / 9.1x / 6.1x | 23.4x / 12.7x / 7.5x | ADLX -500 MHz, -30 percent. not rentable, not owned: the 9070 XT's dependent-read rate per channel (150 M per second per 32-bit channel) on 24 channels; the knob by the 9070 XT grid Stock: 24 channels at the RX 7600's measured per-channel rate: about 40 MH/s at about 310 W (7.8); not rentable, not owned |
| AMD Radeon RX 7800 XT | 16 GB | 6.47 | estimated | 8.52 (estimated) | 11.2x / 8.2x / 5.8x | 15.0x / 10.0x / 6.7x | 25.7x / 14.0x / 8.2x | ADLX -500 MHz, -30 percent. 16 channels of GDDR6 at the 9070 XT's per-channel rate; the knob by the 9070 XT grid Stock: 16 channels at the RX 7600's measured 1.74 MH/s per channel: about 27 MH/s at about 230 W (8.5); not rentable, not owned |
| AMD Radeon RX 7600 | 8 GB | 6.19 | estimated | 8.14 (measured) | 10.7x / 7.8x / 5.6x | 14.3x / 9.6x / 6.4x | 24.6x / 13.3x / 7.9x | ADLX -500 MHz, -30 percent. the 9070 XT's ADLX grid (24 percent of the draw for no rate) applied; this card's own 24-point grid runs on PC 1 by about 16:50 UK and replaces this row Stock: the founder's RX 7600 (8 GB) on PC 1, the card-in job 15:46 to 15:50 UK: class v4 sub-version 3 at stock 13.88 MH/s at 113 W (8.14), the v4 and v5 fingerprints equal to the pinned readings, the app's own row 13.4 at 113 W; class v5 within 2 percent; the 1 GiB dataset fits in 8,176 MB (the 2, 4 and 5.5 GiB rows follow) |
| AMD Radeon RX 7600 XT | 16 GB | 6.56 | estimated | 8.63 (estimated) | 11.4x / 8.3x / 5.9x | 15.2x / 10.2x / 6.8x | 26.1x / 14.1x / 8.3x | ADLX -500 MHz, -30 percent. 8 channels; the card-in queue holds one for a PC measurement Stock: the same Navi 33 die as the measured RX 7600 (13.88 MH/s at 113 W) with 16 GB in clamshell: the same rate, about 120 W (8.6); the card-in queue holds one |
| AMD Radeon RX 9060 XT | 16 GB | 8.23 | estimated | 10.83 (estimated) | 14.3x / 10.4x / 7.4x | 19.0x / 12.8x / 8.5x | 32.8x / 17.7x / 10.5x | ADLX -500 MHz, -30 percent. 8 channels of GDDR6 on RDNA 4; the card-in queue holds one Stock: 8 channels on RDNA 4 between the 9070 XT's 1.18 MH/s per channel and the 7600's 1.74: about 12 MH/s at about 130 W (10.8); the card-in queue holds one |
| NVIDIA H100 80GB HBM3 | DC | 2.0 | estimated | 2.58 (measured) | 3.5x / 2.5x / 1.8x | 4.6x / 3.1x / 2.1x | 8.0x / 4.3x / 2.5x | 1400 MHz at 80 percent. the premium 240 to 280 W at stock says half of it is the clock; a lock on an owned host (Hopper at 1,980 MHz boost, HBM3-bound): about 500 W (2.0); band 1.9 to 2.4; rented hosts refuse -lgc Stock: the denominator sweep, RunPod, 13:25 UK: class v3 252.96 MH/s at 382.4 W (1.51), class v5 241.34 at 621.6 W (2.58, 7 samples, the SM throttled to 1,590 MHz under the 700 W cap); the 7 and 8 October pods read class v4 250.6 at 695.1 W (2.77); -lmc answered 'use --lock-memory-clocks-deferred' and the memory clock stayed 2,619; stock, lock owed |
| NVIDIA L40S | DC | 3.78 | estimated | 5.29 (measured) | 6.5x / 4.8x / 3.4x | 8.7x / 5.9x / 3.9x | 15.0x / 8.2x / 4.8x | 1860 MHz at 60 percent. the Ada shape on the measured stock rows (class v3 220.7 W, class v4 277.6 W); re-based on the measured class v5 stock row of 13:5x UK (the architecture's shape on the measured v3 draw and the measured premium) Stock: class v5 measured (13:49 UK): 56.49 MH/s at 298.7 W (5.29, 46 samples, SM 2,520); class v3 56.35 at 221.5 W on the same host; the v4watts pod read class v4 56.4 at 277.6 W; stock, lock owed |
| NVIDIA A100-SXM4-80GB | DC | 2.89 | estimated | 2.99 (measured) | 5.0x / 3.7x / 2.6x | 6.7x / 4.5x / 3.0x | 11.5x / 6.2x / 3.7x | 1200 MHz at 80 percent. the card already runs at 1,410 MHz and the 400 W host limit binds under class v5 (SM clock gives); a cap under it costs rate on Ampere, so the floor is within 5 percent of the measured stock row Stock: the denominator sweep, RunPod, 13:24 UK: class v3 138.06 MH/s at 294.9 W (2.14), class v5 133.11 at 398.1 W (2.99, 19 samples, at the host's 400 W limit, memory 1,593 MHz); the v4watts pod on a 500 W host read class v4 138.0 at 489.3 W (3.54); -lmc 'not supported' on this card; stock, lock owed |
@ -178,6 +179,18 @@ win, because on this hash the memory clock is the rate and the core clock is onl
climb may raise the memory clock (5 percent of the range per probe) where the vendor exposes it, and no measured row
yet shows a gain from it (the 5090's memory sits at 13,801 of 14,001 MHz).
Amendment, 15:5x UK (floor lane 1's memory-clock ladder on PC 1, the 5090 alone at the 1,300 MHz core lock, job
run-ca4-pc1-memclk-5090-20261008-b, every row bit-exact; `docs/analysis/class-v6/floor/sm-sparse.md` section 3.1 at
66bc6ca7): the memory clock is not a lever, now measured. The driver holds the 5090's memory in two states only (asks
of 8,001 MHz and above read 13,801; 6,001 and below read 7,001, the PHY's half-rate state). Class v3 at the lock:
13,801 MHz 134.1 to 134.5 MH/s at 222.7 to 223.7 W (1.66); 7,001 MHz 76.0 MH/s at 141 to 142 W (1.86 to 1.87).
Class v4: 134.3 to 134.5 at 308 to 309 W (2.29 to 2.30); 76.1 at 184 to 187 W (2.42 to 2.46). The half-rate state
loses 43 percent of the rate (the activate ceiling scales with the memory clock) for 37 percent of the watts, so the
energy per hash rises 12 percent on class v3 and 5 on class v4; the 82 W between the states at 7.4 G reads per second
lost is 11 nJ per read at the margin, equal to the DRAM chase probe's whole-path figure, so the memory-side term is 80
to 90 W of the 223 W at the lock and is bought one for one with the rate. The table's "never touched" line stands as
a measurement; the tiers table carries `mem_mhz` 0 on every row.
## 4. The LPDDR6 and unified-memory tier, five years out
The method. The M5 Max row is the only measured unified-memory point and it splits three ways at the meter: the DRAM
@ -347,8 +360,10 @@ closed the connection mid-bench). The sweep closed at 14:35 UK: 20 rows landed,
- The 5070 Ti and 5070 floors (1.7 to 2.1) are the strongest claims in this file and both are estimated from stock
rows; a 5070 Ti ladder on PC 1 or PC 2 (the card-in job's queue) would settle whether the honest NVIDIA floor is a 16
GB card.
- The AMD rows other than the 9070 XT are modelled on one card; the 9060 XT and 7600 XT in the card-in queue will
replace two of them.
- The AMD rows other than the 9070 XT and the RX 7600 are modelled on those two measured points (the 7600's stock row
landed 15:50 UK from the card-in job on PC 1: 13.88 MH/s at 113 W, 8.14 microjoules, twice as good as this file's
morning estimate for the Navi 33 die; its own ADLX grid by about 16:50 and the 9060 XT in the card-in queue replace
the estimated rows).
- The Apple M4 Max, M4 Pro and M3 Max rows are modelled on the M5 Max's split; a Metal bench on any of them with the
IOReport meter would replace its row in an hour.
- Section 4's LPDDR6 rows are modelled on JESD209-6's public summary (the bank count and tFAW are behind the

324
docs/analysis/class-v6/floor/shadow-k.md Normal file
View file

@ -0,0 +1,324 @@
# The shadow's k from RTL (floor lane 2, 8 October 2026)
Branch `class-v6-floor-k` from `counter-asic-4` at 7618e729. Every chip-side number in this file comes from
synthesis and place-and-route of RTL written for this lane (Yosys 0.68 plus OpenROAD, the ORFS docker image
`openroad/orfs:latest`, the ASAP7 predictive PDK, run on igneum-build-4), with switching activity from a
random-input gate-level simulation (iverilog on the routed netlist). Every GPU-side number is the record's
measurement (`docs/analysis/counter-asic-4-research.md` 15.1a: PC 1, the RTX 5090, 20 probes at 60 s, 8
October 2026) and is not re-estimated here. The RTL, testbenches, flow configs and a Makefile that reproduces
every row are under `tools/chip-model/rtl/`.
## 0. One page
(filled from the rows below; see section 2 for the table and section 4 for the edge)
## 1. The question and the identity
The chip's energy per hash is `E_chip = E_mem + k x F` (research file section 2): `E_mem` the memory system's
reads, controller and static (0.466 microjoules per hash on the record's GDDR7 board, modelled), `F` the shadow's
premium on the card (measured: 1.10 microjoules unlocked, 0.652 at the 1,300 MHz lock on the 5090 for class
v4's 102,100 counted ops per hash), and `k = e_chip / e_gpu` the chip core's energy per forced op over the
card's. The card's side of `k` is measured; the chip's side has been a claimed band (ALU 0.3 to 0.8, int8 tile
0.03 to 0.3, L2 hit 0.1 to 0.3, shuffle 0.4 to 0.7). This file replaces the claimed side with a synthesised one,
family by family, and reads the mix that maximises the expected `k` under the invention lane's sound-form rules.
## 2. Method
### 2.1 What was built (RTL, `tools/chip-model/rtl/rtl/`)
Each family is a minimal chip-side shadow core: the smallest circuit a chip maker would have to build to run that
family's instructions bit-exactly at one op per cycle per lane. The common lane shape is an instruction register,
an 8 x 32-bit register window in flops (the card's lane holds its working set in a register file too; 8 registers
is the class program's window), two or three read ports through muxes, the functional unit, and one write port.
Nothing is shared across lanes and nothing is pipelined beyond one stage, so the figure is the datapath plus the
minimum operand delivery: a floor for the chip, which makes the `k` it gives a floor too.
| Family | Module | What one op is | Ops per cycle | Clock set (ps) |
|---|---|---|---|---|
| ARX | `lane_arx` | int32 add, sub, xor, or, rotl by immediate, rotr by register (op drawn per cycle; rows per op by fixing the op field) | 1 | 1,000 |
| MUL | `lane_mul` | 32 x 32 to 64: mul (low word), mulhi (high word), mad (src x src2 + dst) | 1 | 1,500 |
| PRMT | `lane_prmt` | byte permute: 4 output bytes from the 8 bytes of two registers by a 16-bit selector, sign-replicate bit as on the card | 1 | 1,000 |
| LOP3 | `lane_lop3` | three-input logic by an 8-bit truth table, bitwise | 1 | 1,000 |
| FOLD | `lane_fold` | the index fold `((rotl(x * M, R) & WM) \| OFF) & MASK` with the era's constants held in registers | 1 | 1,500 |
| SHFL | `shfl32` | the 32-lane xor-mask shuffle `r[dst][lane] ^= r[src][lane ^ m]` over a 1 KB window (32 lanes x 8 x 32 bits): a 5-stage butterfly | 32 lane-ops | 1,000 |
| XBAR | `xbar32` | the general 32-lane crossbar over the same window (any source lane per lane, a 5-bit select each): the upper bound on a shuffle network | 32 lane-ops | 1,000 |
| SCRATCH | `scratch8k` | one random 32-bit read of a 2,048 x 32 (8 KB) flop array, a write on one cycle in eight: the chip's L1 as the pessimistic flop form | 1 read | 1,500 |
| TILE | `tile8` | the int8 8x8x8 tile `C += A x B` with int32 accumulators: 512 MACs per cycle | 512 MACs | 2,000 |
### 2.2 The flow
ORFS on ASAP7 (7.5-track RVT cells, the TC corner: 0.70 V, 0 C, NLDM), the default flow end to end: Yosys
synthesis with ABC, floorplan at 40 percent utilisation, global and detailed placement, CTS, global and detailed
routing, parasitic extraction (OpenRCX, the platform's rules). Power is OpenSTA's `report_power` on the routed
design with its SPEF, under two activities: (a) the VCD of a random-input simulation of the routed netlist
(ASAP7 has no cell Verilog models in the image, so Yosys builds the cell bodies from the liberty functions and
writes the netlist as primitives; iverilog runs 3,000 to 4,000 cycles with every instruction field drawn by
`$random` each cycle and a random 32-bit load into the window every 16th cycle), and (b) a propagated 0.5
activity on every input as the cross-check. The energy per op is the total power (internal, switching and leakage)
times the clock period over the ops per cycle. Leakage is reported beside it; at these clocks it is a few percent.
### 2.3 Node scaling (approximate; every factor claimed from the foundry's own headline)
ASAP7 is a predictive 7 nm-class FinFET PDK (ASU and ARM, Clark et al., Microelectronics Journal 2016), not a
foundry node, so the row is first stated at ASAP7 and then scaled by the foundry's published per-node power
reductions at the same speed: N7 to N5 x0.70 (TSMC: "30 percent lower power"), N5 to N3E x0.72 (TSMC: "25 to 30
percent lower power", the midpoint), N3E to N2 x0.72 (TSMC: "25 to 30 percent lower power", the midpoint). So
N5 = 0.70, N3 = 0.50 and N2 = 0.36 of the ASAP7 figure. These are the foundry's claims for a whole design at a
fixed frequency, and a shadow core at a low clock could run at a lower voltage still; the N2 column is therefore
the chip's best case from this method, not its floor. Sources in section 7.
### 2.4 What the method leaves out, on both sides
On the chip side the figure omits instruction fetch and decode (a chip would run the program from a small SRAM
or a decoded instruction cache shared by many lanes, about 1 to 2 pJ per lane-instruction amortised across 32
lanes, approximate), the clock tree beyond the block's own, and the result's move to a memory address unit. On
the card side the 15.1a figure is the whole card's marginal per counted op (the sleep floor subtracted), which
includes the card's own fetch, decode, operand collection and register file. So the `k` here is the chip's
datapath-and-window cost over the card's whole-lane cost: a FLOOR on the chip's cost and so a floor on `k`.
## 3. The rows: per-unit floors (the minimal lane per family)
Every row: ASAP7 routed, SPEF, OpenSTA `report_power` under the random-input gate-level VCD (every pin annotated,
0 unannotated), the TC corner (0.70 V). "pJ/op" is total power (internal + switching + leakage) times the clock
period over the ops per cycle. The propagated-0.5 cross-check is in `table.csv`; it agrees within 2x on the
logic lanes and overestimates the multiplier lanes 50x (OpenSTA's statistical propagation through a multiplier
is not a measurement), so the VCD row is the row. The GPU side is 15.1a: pJ per counted op on the RTX 5090 at
stock and at the 1,300 MHz lock, and 6.9 pJ per counted op on the Apple M5 Max (the class v4 shadow, measured).
`k` is absolute: the chip's own pJ per op at the node over the card's at its point.
| Family (chip RTL) | Cells (with fill) | pJ/op ASAP7 | pJ/op N5 | pJ/op N3 | pJ/op N2 | 5090 pJ/op stock / lock | k, N3 chip vs 5090 stock / lock | k, N3 vs M5 Max 6.9 | k, ASAP7 unscaled vs lock | Label |
|---|---|---|---|---|---|---|---|---|---|---|
| ARX add | 11,631 | 2.16 | 1.51 | 1.09 | 0.78 | 11.3 / 6.2 | 0.096 / 0.18 | 0.16 | 0.35 | synthesised; N3 and N2 scaled (claimed) |
| ARX sub | | 2.14 | 1.50 | 1.08 | 0.78 | 11.3 / 6.2 | 0.095 / 0.17 | 0.16 | 0.35 | |
| ARX xor | | 2.09 | 1.46 | 1.05 | 0.76 | 11.3 / 6.2 | 0.093 / 0.17 | 0.15 | 0.34 | |
| ARX rotl (immediate) | | 2.15 | 1.50 | 1.08 | 0.78 | 11.3 / 6.2 | 0.095 / 0.17 | 0.16 | 0.35 | |
| ARX rotr (by register) | | 2.13 | 1.49 | 1.07 | 0.77 | 11.3 / 6.2 | 0.095 / 0.17 | 0.16 | 0.34 | |
| or (lossy; the values saturate to ones and the activity falls) | | 1.45 | 1.01 | 0.73 | 0.53 | 11.3 / 6.2 | 0.065 / 0.12 | 0.11 | 0.23 | |
| ARX random mix | | 2.24 | 1.57 | 1.13 | 0.81 | 11.3 / 6.2 | 0.10 / 0.18 | 0.16 | 0.36 | |
| mul (32 x 32, low word) | 19,603 | 1.35 | 0.94 | 0.68 | 0.49 | 13.9 / 8.3 | 0.049 / 0.082 | | 0.16 | |
| mulhi (high word; the same multiplier) | | 1.35 | 0.94 | 0.68 | 0.49 | 39.6 / 21.0 | 0.017 / 0.032 | | 0.064 | |
| mad (src x src2 + dst; three reads) | | 3.29 | 2.30 | 1.66 | 1.19 | 13.9 / 8.3 | 0.12 / 0.20 | | 0.40 | |
| mul random mix | | 1.53 | 1.07 | 0.77 | 0.56 | 13.9 / 8.3 | 0.055 / 0.093 | | 0.18 | |
| index fold (x M, rotl R, masks; era constants in registers) | 14,965 | 2.37 | 1.66 | 1.19 | 0.86 | 13.9 / 8.3 (read against int_mul) | 0.086 / 0.14 | | 0.29 | |
| prmt (byte permute) | 6,744 | 1.27 | 0.89 | 0.64 | 0.46 | 22.3 / 11.5 | 0.029 / 0.056 | | 0.11 | |
| lop3 (8-bit truth table) | 7,274 | 1.42 | 0.99 | 0.72 | 0.52 | 24.1 / 13.0 | 0.030 / 0.055 | | 0.11 | |
| 32-lane xor-mask shuffle (butterfly over the 1 KB window), per lane-op | 181,580 | 1.24 | 0.87 | 0.63 | 0.45 | 55.8 / 29.4 | 0.011 / 0.021 | | 0.042 | routed with SPEF; 15:1x UK |
| 32-lane general crossbar, per lane-op | ROW_XBAR |
| 8 KB scratch, one random read (flop array: the pessimistic form) | ROW_SCRATCH |
| int8 8x8x8 tile, per MAC | ROW_TILE |
Reading the floors: a lane's add costs the chip about 2.2 pJ at ASAP7 and 1.1 at N3, against the 5090's 6.2
at the lock and 11.3 at stock, so even the floor is not a tenth of the card's cost at the knee, and the claimed
"2 to 5 pJ for a SIMD array at N5" (15.1) was the right order for the unscaled lane with nothing around it. The
multiplier is the cheapest unit per op relative to the card (the 5090 pays 8.3 pJ for mul and 21 for mulhi, the
chip 0.68 for either, because the high word falls out of the same array), and mad is the dearest for the chip
(three register reads and two units). The fold costs a chip one multiply and a rotate: 1.2 pJ per address at N3,
or 0.15 nJ per hash over 128 loads, a third of a percent of the GDDR7 board's 0.466 microjoules.
## 4. The headline row: the programmable sequencer core
The per-unit lanes of section 3 are floors for a chip that cannot exist under class v6: layers 1 and 3 (per-era
op-mix, program-length and read-width draws, family epochs) kill any fixed lane, so the chip that competes is a
programmable core. `core_v6` (`tools/chip-model/rtl/rtl/core_v6.v`) is the minimal in-order SIMD sequencer that
executes the drawn class v6 shadow program: a 256 x 32-bit instruction memory (a flop array) sized to the drawn
program, a program counter wrapping at the era's drawn length, fetch into an instruction register, decode, the
era's parameter registers (M, R, WM, OFF, MASK, N), and per lane a 32 x 32-bit register file (flops) with three
read ports and one write port and every class unit: add, sub, xor, or, rotl, rotr, mul, mulhi, mad, prmt, lop3,
the xor-mask shuffle across the lanes (a butterfly), and the load (the index fold on the address path, the returned
word written next cycle). One instruction per cycle for every lane. The program is 256 instructions drawn with the
class v4 weights (`NONLOAD_WEIGHTS`), with a variant at one load per 16 instructions. Two builds: 8 lanes (the fast
row) and 32 lanes (the imem amortised over 32), and a 32-lane build with a 16-register file (the sensitivity).
The activity: the gate-level random-input VCD of the synthesised netlist; two run lengths (150 and 800 cycles)
bracket the 260-cycle program-load phase, and solving the pair gives the steady-state run power (the load phase
draws 13.9 mW, the run phase 36.9 mW for 8 lanes at 1.5 ns).
| Row | Stage | Cells | pJ per lane-op ASAP7 | N5 | N3 | N2 | 5090 stock / lock / M5 Max pJ per op | k absolute at N3 vs stock / lock / M5 Max | k at N2 | k unscaled ASAP7 vs lock | Label |
|---|---|---|---|---|---|---|---|---|---|---|---|
| core, 8 lanes, 32 registers | synthesis only (no wires, no clock tree) | 186,443 | 6.9 | 4.8 | 3.5 | 2.5 | 11.3 / 6.2 / 6.9 | 0.31 / 0.56 / 0.50 | 0.22 / 0.40 / 0.36 | 1.1 | synthesised; 14:0x UK |
| of which the sequential term (register file, imem and IR clock pins, no clock gating) | | | 2.4 | 1.7 | 1.2 | 0.9 | | | | | |
| of which the units, the read muxes and the butterfly | | | 4.5 | 3.1 | 2.3 | 1.6 | | | | | |
| core, 8 lanes, 32 registers | placed and routed, SPEF | ROW_CORE8_PLACED |
| core, 32 lanes, 32 registers | synthesis only (steady state from 150 and 400 run cycles) | 600,381 | 5.55 | 3.9 | 2.8 | 2.0 | 11.3 / 6.2 / 6.9 | 0.25 / 0.45 / 0.41 | 0.18 / 0.32 / 0.29 | 0.90 | synthesised; 15:2x UK |
| core, 32 lanes, 16 registers | synthesis only | 443,258 | 4.2 | 2.9 | 2.1 | 1.5 | 11.3 / 6.2 / 6.9 | 0.18 / 0.34 / 0.30 | 0.13 / 0.24 / 0.22 | 0.68 | synthesised; one run length, about plus or minus 10 percent; 15:0x UK |
| the bare ARX lane (section 3, the floor) | routed | 11,631 | 2.2 | 1.5 | 1.1 | 0.8 | 11.3 / 6.2 / 6.9 | 0.10 / 0.18 / 0.16 | 0.07 / 0.13 / 0.11 | 0.35 | the lower bound |
Reading: fetch, decode, a 32-register file and the full unit set cost a chip 3.1x the bare lane, and the core's
k at the 1,300 lock is 0.56 at N3 (0.40 at N2), inside the record's claimed 0.3 to 0.8 band and at its centre, with
the bare lane's 0.18 as the lower bound. Two corrections pull opposite ways: placement adds wires and a clock tree
(+20 to +40 percent on a design like this, approximate; the placed rows read it) and a chip maker gates the
register-file clock (one of 32 registers is written per cycle; gating removes about 2.0 of the 2.4 pJ sequential
term, approximate), so the net figure for the re-fold is 7.0 / 4.9 / 3.5 / 2.5 pJ per lane-op at ASAP7 / N5 / N3 /
N2 (the synthesis-only figure within the rounding). The imem is amortised over 8 lanes in this row and over 32 in
the core32 row.
### 4a. The design sweep: what a class could add to the core's cost (the coordinator's order, 14:3x UK; rows 14:5x)
Synthesis-only (no wires, no clock tree), 8 lanes unless stated, the same corner and scaling; the steady-state run
power solved from two run lengths (150 and 600 cycles after the program load). The GPU side per knob is the hash
lane's: knob 3 measured on a rented 5090 and 4090 (RunPod, 14:28 to 14:39 UK), knobs 1 and 4 modelled until a
generator line exists (a 64-entry window is a new ISA: an init rule and a fold rule for the extra registers, about
half a day; the select tree is a new instruction kind), knob 2 has no GPU side (the warp's shuffle already spans
32 lanes).
| Variant | Cells | pJ per lane-op ASAP7 | of which clocking (RF, imem, IR; no gating) | N5 | N3 | N2 | k at N3 vs 5090 stock / lock / M5 Max | GPU side |
|---|---|---|---|---|---|---|---|---|
| base: 32 registers, 256-entry imem (the headline row) | 186,443 | 6.9 | 2.4 | 4.8 | 3.5 | 2.5 | 0.31 / 0.56 / 0.50 | measured (class v4) |
| (1) 64-register file (a 40-bit instruction word) | 267,731 | 9.7 | 3.75 | 6.8 | 4.9 | 3.5 | 0.43 / 0.78 / 0.70 | new ISA; 64 live registers takes a 5090 or 4090 thread to about 110 of 255, occupancy to about half; under the latency-bound chain the rate is expected to hold and the energy to move little (the hash lane, modelled); the unmeasured term is the per-lane register traffic |
| (3) 1,024-entry imem, the program drawn at 1,024, as built (a flop array) | 324,543 | 12.0 | 6.0 | 8.4 | 6.1 | 4.4 | 0.53 / 0.97 / 0.87 | measured: the 1,024 block at 27 passes costs the 5090 1.58x the energy per hash (4.96 against 3.14 microjoules at stock, 111 against 141 MH/s at the 575 W cap) and the 4090 1.57x (7.01 against 4.48, the rate held at 62.5 MH/s), for 4x the shadow instructions: 0.40x per instruction |
| (3) the same with the imem as a 4 KB SRAM macro shared by the lanes (2 to 4 pJ per 32-bit read, approximate) | | about 7.2 | about 1.9 | 5.0 | 3.6 | 2.6 | about 0.32 / 0.58 / 0.52 | the same |
| (4) the drawn select tree (the era's 16-entry op permutation ahead of decode; every unit evaluated every cycle, as in the base) | 186,870 | 6.85 | 2.4 | 4.8 | 3.4 | 2.5 | 0.30 / 0.55 / 0.50 | the units' microbench sum (approximate) |
| (2) 32 lanes, 32 registers (the butterfly across 32; the imem amortised over 32) | 600,381 | 5.55 | 1.5 | 3.9 | 2.8 | 2.0 | 0.25 / 0.45 / 0.41 | no GPU knob |
| (2') 32 lanes, 16 registers (the register-file sensitivity the other way; one run length of 150 cycles, the load phase subtracted at the 8-lane ratio, about plus or minus 10 percent) | 443,258 | 4.2 | 2.3 | 2.9 | 2.1 | 1.5 | 0.18 / 0.34 / 0.30 | no GPU knob |
| (5) all four together (32 lanes, 64 registers, 1,024 imem, the select tree) | ROW_CORE32ALL |
Reading, for the founder's "under 2x at the lock" (which needs k near 0.9 on the GDDR7 board): the 64-register
window is the one robust knob, because its cost is per lane and a chip cannot share it (+2.8 pJ per lane-op at
ASAP7, +0.22 of k at the lock). The long block's cost is instruction memory, which a chip shares across its lanes
as SRAM, so most of its 0.97 as built is the flop array's clock and the honest figure is about 0.6; the card
meanwhile pays 1.58x the energy per hash for it (measured), so on the GDDR7 board at stock the chip reads
4.96 / (0.466 + 408,400 x 3.6 pJ) = 2.6x (1.7x on the flop-array row, which is not a chip anyone builds). The
select tree costs the chip nothing because every unit already evaluates every cycle in the base core. (1) + (3)
together reach about 10 pJ per lane-op at ASAP7 with the SRAM imem (5.0 at N3, k about 0.81 at the lock, 0.45 at
stock), 14.8 as built (k about 1.2); so k 0.85 is reached only on the flop-array reading, and the DRAM board
under 2x at the lock needs the window, the long block and the knee together and holds only while the chip's imem
stays unamortised, which it does not. The GPU pays nothing for the window until occupancy binds, 1.58x per hash for
the long block (0.40x per forcing instruction), and nothing for the select tree.
### 4b. The node column: which part of the edge is the node (the coordinator's order, 15:0x UK)
The record compares a chip scaled to N3 or N2 against a TSMC 4N card (N5 class; the M5 Max is N3), so part of
the edge is the node. Factors as in 2.3, every one claimed. Absolute; the GDDR7 board at the lock = 2.33 /
(0.466 + 102,100 x e_chip).
| Core | pJ per lane-op ASAP7 / N5 / N3 / N2 | k at the lock, N5 / N3 / N2 | GDDR7 board at the lock, N5 / N3 / N2 |
|---|---|---|---|
| base (32 registers, 256 imem) | 6.9 / 4.8 / 3.5 / 2.5 | 0.78 / 0.56 / 0.40 | 2.4x / 2.8x / 3.2x |
| 64-register file | 9.7 / 6.8 / 4.9 / 3.5 | 1.09 / 0.78 / 0.56 | 2.0x / 2.4x / 2.8x |
| all four together | ROW_CORE32ALL_NODE |
One line: of the 2.8x at k 0.56, the N5-to-N3 node step is worth 0.4x (2.4x node-for-node, a factor of 1.17,
claimed); the rest is the memory system (3.6x at zero shadow at the lock, modelled) less what the class v4 shadow
takes back on the card's own node (3.6x to 2.4x), which is the design. Node-for-node the base core already sits at
k 0.78 and the 64-register core at 1.09, so "near 0.9" is reached node-for-node by the window alone; what it does
not survive is the node step a chip project would buy (an N3 core gives back 0.4x, an N2 core 0.8x).
## 5. The chip edge at the measured k
`E_chip = E_mem + N_ops x e_chip` (absolute: the chip's shadow cost is 102,100 x 3.5 pJ = 0.36 microjoules per hash
at N3, 0.26 at N2, whatever the card does); the record's convention `E_mem + k x F` beside it with `k` read at the
card's point (it coincides at the lock by construction and is the same at stock here because both are the same
arithmetic on the same ops; it differs when the chip's cost is held fixed while the card's point moves, which is
what the SRAM lane found flattered the die 1.6x). Cards: the 5090 at stock (3.36 microjoules, F 1.10) and at the
lock (2.33, F 0.652), the M5 Max (1.40 on class v4, 0.78 on class v3, 6.9 pJ per op). Chips: the record's GDDR7
board and the hardware-future lane's rows (their `E_mem` at zero shadow). The record's rows that this recomputes
are hardware-future.md section 5: "2.6x to 2.8x at k = 1 and 4.4x to 5.1x at k = 0.5" for the strongest DRAM chips
against the stock 5090 (the GDDR7 board's own row there is 2.1x and 3.3x).
Chip shadow per hash, absolute: N3 0.357 microjoules, N2 0.255.
| Chip (E_mem, microjoules) | Card row | Zero shadow | Absolute, N3 core | Absolute, N2 core | Record convention at the measured k (N3) | at k = 1 | at k = 0.5 |
|---|---|---|---|---|---|---|---|
| GDDR7 board, 28 nm controller (the record) (0.466) | 5090 stock (class v4) | 4.8x | 4.1x | 4.7x | 4.1x (k 0.32) | 2.1x | 3.3x |
| GDDR7 board, 28 nm controller (the record) (0.466) | 5090 at the 1,300 MHz lock | 3.6x | 2.8x | 3.2x | 2.8x (k 0.55) | 2.1x | 2.9x |
| GDDR7 board, 28 nm controller (the record) (0.466) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 1.7x | 1.7x | 1.9x | 1.8x (k 0.51) | 1.3x | 1.8x |
| HBM3E one stack (0.321) | 5090 stock (class v4) | 7.0x | 5.0x | 5.8x | 5.0x (k 0.32) | 2.4x | 3.9x |
| HBM3E one stack (0.321) | 5090 at the 1,300 MHz lock | 5.2x | 3.4x | 4.0x | 3.4x (k 0.55) | 2.4x | 3.6x |
| HBM3E one stack (0.321) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 2.4x | 2.1x | 2.4x | 2.2x (k 0.51) | 1.5x | 2.2x |
| HBM4 one stack, N12 base die (0.22) | 5090 stock (class v4) | 10.3x | 5.8x | 7.1x | 5.8x (k 0.32) | 2.5x | 4.4x |
| HBM4 one stack, N12 base die (0.22) | 5090 at the 1,300 MHz lock | 7.6x | 4.0x | 4.9x | 4.0x (k 0.55) | 2.7x | 4.3x |
| HBM4 one stack, N12 base die (0.22) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 3.5x | 2.4x | 2.9x | 2.6x (k 0.51) | 1.7x | 2.6x |
| custom HBM4E base die, N3P (0.18) | 5090 stock (class v4) | 12.6x | 6.3x | 7.7x | 6.3x (k 0.32) | 2.6x | 4.6x |
| custom HBM4E base die, N3P (0.18) | 5090 at the 1,300 MHz lock | 9.3x | 4.3x | 5.4x | 4.3x (k 0.55) | 2.8x | 4.6x |
| custom HBM4E base die, N3P (0.18) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 4.3x | 2.6x | 3.2x | 2.8x (k 0.51) | 1.7x | 2.9x |
| DRAM on logic, hybrid bonded (2029 to 2031) (0.15) | 5090 stock (class v4) | 15.1x | 6.6x | 8.3x | 6.6x (k 0.32) | 2.7x | 4.8x |
| DRAM on logic, hybrid bonded (2029 to 2031) (0.15) | 5090 at the 1,300 MHz lock | 11.2x | 4.6x | 5.7x | 4.6x (k 0.55) | 2.9x | 4.9x |
| DRAM on logic, hybrid bonded (2029 to 2031) (0.15) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 5.2x | 2.8x | 3.5x | 3.0x (k 0.51) | 1.8x | 3.0x |
| SRAM full store, one N2 reticle (0.14) | 5090 stock (class v4) | 16.1x | 6.8x | 8.5x | 6.8x (k 0.32) | 2.7x | 4.9x |
| SRAM full store, one N2 reticle (0.14) | 5090 at the 1,300 MHz lock | 12.0x | 4.7x | 5.9x | 4.7x (k 0.55) | 2.9x | 5.0x |
| SRAM full store, one N2 reticle (0.14) | M5 Max (class v4 1.40 microjoules, class v3 0.78; 6.9 pJ per op; F 0.62) | 5.6x | 2.8x | 3.5x | 3.1x (k 0.51) | 1.8x | 3.1x |
Floor lane 1 assumption (not in by 18:00 UK): the honest 5090 at 1.0 microjoules per hash at zero shadow.
| Chip | Premium kept at 0.652 (card 1.652): absolute N3 / N2 | Premium scaled with the card, 0.390 (card 1.390): absolute N3 / N2 | zero shadow |
|---|---|---|---|
| GDDR7 board, 28 nm controller (the record) | 2.0x / 2.3x | 1.7x / 1.9x | 2.1x |
| HBM3E one stack | 2.4x / 2.9x | 2.0x / 2.4x | 3.1x |
| HBM4 one stack, N12 base die | 2.9x / 3.5x | 2.4x / 2.9x | 4.5x |
| custom HBM4E base die, N3P | 3.1x / 3.8x | 2.6x / 3.2x | 5.6x |
| DRAM on logic, hybrid bonded (2029 to 2031) | 3.3x / 4.1x | 2.7x / 3.4x | 6.7x |
| SRAM full store, one N2 reticle | 3.3x / 4.2x | 2.8x / 3.5x | 7.1x |
What the rows say. (1) At the knee the GDDR7 board keeps 2.8x with the shadow on (3.2x at an N2 core) against
3.6x at zero shadow: the class v4 shadow buys the honest card 0.8x of edge, not the 1.5x the k = 1 row served and
not the 0.1x the bare-lane floor would give. (2) The strongest DRAM chips read 4.3x to 4.7x at the knee and 6.3x to
6.8x at stock against the 5090 (the record's 2.6x to 2.8x at k = 1 and 4.4x to 5.1x at k = 0.5 bracket the stock
figure and understate the knee one, because the record's k was read at stock). (3) Against the M5 Max the whole
table compresses to 1.7x to 2.8x: the honest SoC's own operating point is most of the resistance. (4) Floor lane
1's honest 5090 at 1.0 microjoules (assumed; its rows were not in by 18:00 UK) would put the GDDR7 board at 1.7x
to 2.3x and the strongest chips at 2.6x to 4.2x.
## 6. The ranking and the mixed draw
### 6.1 Families ranked by k, highest first (the hardest for a chip), absolute at N3 against the 5090's lock
| Rank | Family | Chip pJ/op N3 (unit floor) | 5090 pJ/op at the lock | k (floor) | In the class draw? |
|---|---|---|---|---|---|
| 1 | mad | 1.66 | 8.3 | 0.20 | yes (8 of 75) |
| 2 | add, sub, rotl, rotr, xor | 1.05 to 1.09 | 6.2 | 0.17 to 0.18 | yes (12, 6, 7, 6, 10) |
| 3 | the index fold | 1.19 | 8.3 | 0.14 | every load |
| 4 | or | 0.73 | 6.2 | 0.12 | yes (4) |
| 5 | mul | 0.68 | 8.3 | 0.082 | yes (8) |
| 6 | prmt, lop3 | 0.64, 0.72 | 11.5, 13.0 | 0.056, 0.055 | not drawn (RTL rows only) |
| 7 | mulhi | 0.68 | 21.0 | 0.032 | yes (6) |
| 8 | 32-lane shuffle (butterfly) | 0.63 | 29.4 | 0.021 | yes (8) |
| 9 | L1 scratch read (8 KB flop array) against the card's L2 hit | ROW_SCRATCH_K | 1,400 | pending | not drawn |
| 10 | int8 8x8x8 tile, per MAC | ROW_TILE_K | 2.2 | pending | not drawn (the tensor lever is dead on other grounds) |
The order is set by the card's price, not the chip's: the chip pays 0.6 to 1.7 pJ for everything, and the card
pays 6.2 for an add, 8.3 for a multiply, 21 for a high word and 29 for a shuffle. So the families the card pays
MOST for (mulhi, shuffle) are the ones a chip undercuts most, and the forcing work is the plain ARX and mad the
card does cheapest. This is the measured form of 15.1b's hold on the shuffle-heavy re-weight.
### 6.2 The mixed draw that maximises the expected k
The objective at a FIXED GPU premium: `k_eff(w) = sum w_i e_chip_i / sum w_i e_gpu_i` (the chip's energy for the
drawn program over the card's for the same program; at a fixed `F` the chip pays `k_eff x F`). The band (layer
1, the research lane's 17:00 reading of lane D's cut): B = 4 points on the injecting families only (add, sub,
xor, mad, shfl, rotl, rotr), the lossy families (or, mul, mulhi) at or under their base, `or + mul + mulhi` at most
18 + B, the shuffle capped at its class v4 weight; the index fold on every address and the F8 uniformity floor are
not functions of the weights and do not move. `tools/chip-model/rtl/flow/mix.py` searches the band exhaustively
over the corners (the objective is a ratio of linear forms, so the optimum is at a corner of each family's range).
On the unit floors (N3, the lock; the shuffle row in at 0.63 pJ, its k 0.021 the lowest of the drawn families):
| Mix | add, xor, mul, mad, shfl, rotl, sub, mulhi, rotr, or | k_eff (floors) | The card's pJ per op at the lock | k_eff on the core (floor + the core's 2.4 pJ per op overhead at N3) |
|---|---|---|---|---|
| class v4 (the base) | 12, 10, 8, 8, 8, 7, 6, 6, 6, 4 | 0.097 (with the shuffle row in: 0.130 over the other 67 points) | 10.3 | 0.43 |
| the census lane's re-weight (d20eb04bd, PASS on 256 seeds, no era and eras 0 to 7, W = 4 and W = 16) | 13, 11, 6, 10, 8, 8, 7, 2, 6, 4 | 0.115 (+19 percent; 0.153 over the 67 points) | 9.0 | 0.49 (+14 percent) |
| the band's best corner (mix.py, exhaustive: every injecting family at +4, the shuffle at its floor, the lossy families at base minus 4) | 16, 14, 4, 12, 4, 11, 10, 2, 10, 0 | 0.137 (+42 percent) | 8.2 | about 0.51 (+19 percent) |
| the band's worst corner (shuffle and mulhi heavy) | 8, 6, 4, 4, 8, 3, 2, 6, 2, 0 | 0.074 | 12.3 | about 0.40 |
Reading: the re-weight moves six points off the chip's two easiest families (mulhi, mul) onto the hardest (mad,
the ARX families) and lifts the expected k by about a seventh on the core; its acceptance is the census lane's
(0 exhausted, F8 0.999 to 1.008 of uniform, the verifier within 4 percent); its energy cost on the card is a
premium per instruction 11 percent LOWER (fewer mulhi), so at a fixed premium the program is 12 percent longer.
The shuffle's own row decides whether it goes to its floor: on the card it is the dearest op (29.4 pJ at the lock)
and on the chip a butterfly over the window, so its k is the lowest of the drawn families unless the synthesis says
otherwise. The recommendation: the band's best corner (add 16, xor 14, mad 12, rotl 11, sub 10, rotr 10, shfl 4, mul 4, mulhi 2, or 0) if its census passes (the census lane's harness, about five box-minutes per candidate); the census lane's draw as the passed fallback. Either way the shuffle goes to its floor: the card pays 29.4 pJ for a move the chip does for 0.6.
## 7. Sources
- The GPU side: `docs/analysis/counter-asic-4-research.md` 15.1a (the 5090 microbench, 8 October 2026, measured)
and 20.3 (the packs job: 10.8 / 6.4 pJ per counted op on the class v4 shadow); the M5 Max 6.9 pJ per counted
op from the coordinator's order of 8 October 2026 (the latency-shadow record).
- ASAP7: L. T. Clark et al., "ASAP7: A 7-nm finFET predictive process design kit", Microelectronics Journal 53
(2016); the ORFS platform files (`flow/platforms/asap7`, the 7.5-track RVT library, TC corner 0.70 V / 0 C).
- The flow: OpenROAD-flow-scripts (docker image `openroad/orfs:latest`, Yosys 0.68, OpenROAD and OpenSTA with
`read_vcd`); iverilog 12 for the gate-level simulation.
- Node scaling (claimed): TSMC N5 "30 percent lower power at the same speed" against N7 (TSMC technology page,
https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_5nm); N3E "25 to 30 percent lower power"
against N5 (https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_3nm); N2 "25 to 30 percent lower
power" against N3E (https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm). Read 8 October 2026.
- The chip model's memory rows: `docs/analysis/chip-model-v3.md` 5.5 (the GDDR7 board, 0.466 microjoules) and
`docs/analysis/class-v6/hardware-future.md` section 5 (the strongest DRAM and SRAM rows).
- The band: `docs/design/class-v6-rotating-family.md` section 2 (layer 1) and `igneum-pow/src/generator.rs`
`NONLOAD_WEIGHTS`.

64
docs/analysis/class-v6/floor/sm-sparse.md
View file

@ -40,8 +40,9 @@ M5 Max's 0.78 is measured (6 October). "Edge" is the card's microjoules over the
On the H100 the persistent shape itself loses 4 percent of the class v4 rate and the self-tune installs nothing.
PC 1's class v3 at stock agrees with the rented ladder at every rung (43 SMs 136.5 of 136.7 MH/s at 10 W under
base; 170 SMs x 8 warps 137.1 at 310.8 W, 3.5 percent under base, the best shape on that board).
4. **The residual is the core clock domain and the memory path on the GPU side, and the memory clock is the one
knob left after the core lock.** The decomposition probes (section 3) put the 5090's draw over idle at the hash
4. **The residual is the core clock domain and the memory path on the GPU side, and the memory clock is not a
lever either (section 3.1: the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43
percent of the rate for 37 percent of the watts, so the energy per hash rises 12 percent).** The decomposition probes (section 3) put the 5090's draw over idle at the hash
into: the resident SMs issuing nothing (the SM clock domain awake), the L2 and crossbar path per read, and the DRAM
path per read on top of the memory's own modelled 2.0 nJ; the memory-clock ladder on PC 1 at the 1,300 lock reads
the PHY's share directly. The honest floor per tier is the base row at stock within 2 percent, the core lock
@ -536,7 +537,30 @@ The floorsm ladder
### PC 1, the memory-clock ladder at the 1,300 MHz lock, job `run-ca4-pc1-memclk-5090-20261008`
The memory-clock ladder: not landed.
The memory-clock ladder
| Pack | State | Shape | MH/s | W | Microjoules | SM MHz | Mem MHz | Temp max | Check |
|---|---|---|---|---|---|---|---|---|---|
| v4-devnet-epoch0 | unlocked | base (grid) | 136.552 | 464.3 | 3.400 | 2852.1 | 13801 | 70 | PASS |
| mx8-devnet-epoch0 | unlocked | base (grid) | 136.29 | 328.1 | 2.407 | 2850 | 13801 | 65 | PASS |
| v4-devnet-epoch0 | 1300 | base (grid) | 134.34 | 309 | 2.300 | 1290 | 13801 | 60 | PASS |
| mx8-devnet-epoch0 | 1300 | base (grid) | 134.089 | 222.9 | 1.662 | 1290 | 13801 | 57 | PASS |
| v4-devnet-epoch0 | 1300m14001 | base (grid) | 134.513 | 308.1 | 2.290 | 1290 | 13801 | 59 | PASS |
| mx8-devnet-epoch0 | 1300m14001 | base (grid) | 134.342 | 222.7 | 1.658 | 1290 | 13801 | 56 | PASS |
| v4-devnet-epoch0 | 1300m12001 | base (grid) | 134.528 | 308.6 | 2.294 | 1290 | 13801 | 59 | PASS |
| mx8-devnet-epoch0 | 1300m12001 | base (grid) | 134.252 | 223.1 | 1.662 | 1290 | 13801 | 56 | PASS |
| v4-devnet-epoch0 | 1300m10001 | base (grid) | 134.487 | 308.9 | 2.297 | 1290 | 13801 | 59 | PASS |
| mx8-devnet-epoch0 | 1300m10001 | base (grid) | 134.287 | 223.7 | 1.666 | 1290 | 13801 | 55 | PASS |
| v4-devnet-epoch0 | 1300m8001 | base (grid) | 134.541 | 308.7 | 2.294 | 1290 | 13801 | 60 | PASS |
| mx8-devnet-epoch0 | 1300m8001 | base (grid) | 134.33 | 223 | 1.660 | 1290 | 13801 | 56 | PASS |
| v4-devnet-epoch0 | 1300m6001 | base (grid) | 76.09 | 187 | 2.458 | 1290 | 7001 | 53 | PASS |
| mx8-devnet-epoch0 | 1300m6001 | base (grid) | 76.009 | 142.2 | 1.871 | 1290 | 7001 | 51 | PASS |
| v4-devnet-epoch0 | 1300m5001 | base (grid) | 76.091 | 184.4 | 2.423 | 1290 | 7001 | 50 | PASS |
| mx8-devnet-epoch0 | 1300m5001 | base (grid) | 76.007 | 141.1 | 1.856 | 1290 | 7001 | 48 | PASS |
| v4-devnet-epoch0 | 1300m3001 | base (grid) | 76.082 | 183.8 | 2.416 | 1290 | 7001 | 50 | PASS |
| mx8-devnet-epoch0 | 1300m3001 | base (grid) | 75.96 | 140.9 | 1.855 | 1290 | 7001 | 47 | PASS |
| v4-devnet-epoch0 | unlocked-end | base (grid) | 136.562 | 452.5 | 3.314 | 2866.6 | 13801 | 61 | PASS |
| mx8-devnet-epoch0 | unlocked-end | base (grid) | 136.298 | 318.6 | 2.338 | 2865 | 13801 | 60 | PASS |
### The decomposition probes (the worker's --microbench: sleep = full residency and no issue; the L2 chase; the dependent DRAM chase; the ALU probe; 30 s each with the sampler's watts and both clocks)
@ -626,6 +650,35 @@ clock for the PHY. The core lock takes the first three down with the clock (the
reads per second on PC 1, 20.3); the memory-clock lock is the only knob on the fourth, and no rented host allows it, so
its row is PC 1's (the memory-clock ladder table in section 1, the job `run-ca4-pc1-memclk-5090-20261008`).
### 3.1 The memory-clock ladder (PC 1, the 5090 alone, job `run-ca4-pc1-memclk-5090-20261008-b`, 15:0x to 15:4x UK, the helper's `lmc` verb at the 1,300 MHz core lock; the amendment of 15:50 UK)
The driver holds the 5090's memory clock at two points only: every ask at or above 8,001 MHz reads 13,801 on the row
and every ask at or below 6,001 reads 7,001 (the GDDR7 PHY's half-rate state). The rows, both bit-exact against the
Mac's fingerprints:
| Pack | Core lock, memory ask | Memory MHz on the row | MH/s | Watts | Microjoules per hash | nJ per dependent read, whole card | Label |
|---|---|---|---|---|---|---|---|
| class v3 (mx8) | 1,300, no memory lock | 13,801 | 134.09 | 222.9 | 1.662 | 13.0 | measured |
| class v3 | 1,300, lmc 14001 / 12001 / 10001 / 8001 | 13,801 | 134.3 to 134.5 | 222.7 to 223.7 | 1.658 to 1.666 | 13.0 | measured (no change) |
| class v3 | 1,300, lmc 6001 / 5001 / 3001 | 7,001 | 76.0 | 140.9 to 142.2 | 1.855 to 1.871 | 14.5 | measured |
| class v4 (sh256x27) | 1,300, no memory lock | 13,801 | 134.34 | 309.0 | 2.300 | | measured |
| class v4 | 1,300, lmc 8001 and above | 13,801 | 134.5 | 308.1 to 308.9 | 2.290 to 2.297 | | measured |
| class v4 | 1,300, lmc 6001 and below | 7,001 | 76.1 | 183.8 to 187.0 | 2.416 to 2.458 | | measured |
| both, unlocked (the pass's own base) | none | 13,801 | 136.3 / 136.6 | 318.6 to 328.1 / 452.5 to 464.3 | 2.34 to 2.41 / 3.31 to 3.40 | | measured (the heat drift across the pass) |
The reading: the memory clock is not a lever either. At the half-rate PHY state the rate falls 43 percent (134 to 76
MH/s: the hash is bound by the memory's activate ceiling, which scales with the memory clock) and the watts fall 37
percent (82 W on class v3, 125 W on class v4), so the energy per hash RISES 12 percent on class v3 (1.66 to 1.86) and
5 percent on class v4 (2.30 to 2.42). Read as a decomposition, the 82 W between the two memory states on class v3 is
the memory path's clock-scaled share at 7.4 G reads per second of rate lost: 11 nJ per read at the margin, the same
figure the DRAM chase probes give for the whole memory path on the GPU side (10.9 to 11.8 nJ). So the memory-side term
of the 5090's draw is about 80 to 90 W of its 223 W at the lock (the PHY, controllers and L2 at the memory clock plus
the devices' own 55 W modelled), and it is bought one for one with the rate: the honest floor at the 1,300 lock stays
1.66 microjoules on this board (1.58 on 20.3b's cooler pass), and no clock or occupancy knob on the card takes it lower
without taking the rate with it. The class v4 premium at the half-rate state is 43 W for 76 MH/s x 102,100 ops = 5.5
pJ per counted op (6.3 at the full memory clock on the same pass): the shadow's marginal is the core domain's, not the
memory's, as expected.
## 4. The honest floor per tier, and the fraction a chip cannot strip
The chip of the record pays the memory's own energy per read, its static power and a controller and PHY of its own
@ -702,10 +755,7 @@ AMD or Apple owner gets nothing from this lane (the shapes are CUDA's; Metal and
reading the sparse shapes lower than 20.3b did on the same board at the same lock (85 SMs 111.0 against 129.8 MH/s);
the pass ran across the founder's card swap on PC 1 (14:2x UK), so the class v3 lock row stays 20.3b's (43 SMs
126.3 MH/s at 205.4 W against the full grid's 134.0 at 211.4: 1.63 against 1.58 microjoules, nothing saved) and the
ladder is re-run on a quiet PC 1 before it replaces it. The memory-clock ladder is queued behind the hash lane's two
jobs (run-ca4-pc1-memclk-5090-20261008-b) and lands in section 1 when its upload does.
- The decomposition probes on the 4090 and the 5090 host c: in section 1 when their runs end (queued behind the
sweeps on the same cards so no row shares the card).
ladder is re-run on a quiet PC 1 before it replaces it. The memory-clock ladder landed at 15:4x UK (section 3.1).
- The memory side's own share per tier is modelled (chip-model 5.3); the memory-clock ladder is the one measurement of
its PHY term, and only on PC 1.
- Class v5 on the rented 5090s was not run (the v5-kits worker carries the leaf upload and not the sparse shapes; the

11
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@ -0,0 +1,11 @@
lease: holding 1 pool cores (10, waited 0 s, class measure): family gate: verifier row, bench v2m16g+sh256x27 50 warps one core (build-3)
igneum-pow bench: seed "igneum-genesis", day "2026-10-03", dataset 2^28 words (memory-hard)
cache: fill 323.7 ms on one core (2^26 words, 256 MiB, 65536 chains of 64 ChaCha12 blocks), FNV-1a 64 48c4f5bf24166b2e
program: class v2m16g+sh256x27, 128 loads/hash, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0], 4096 items/warp, mixer x16 (144 mixers/item), cache 2^26 words, op mix load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1; epoch built in 309.8 ms
shadow: 256 instructions x 27 passes per iteration, 55296 shadow instructions per hash, op mix add=47 rotl=30 xor=30 shfl=29 mad=27 mul=22 sub=21 rotr=20 mulhi=18 or=12
warp base 0: single cold run 7.429 ms, 4096 items derived, lane0 11a6ebee3f284225 lane31 d69b6f764b683e9c
warp base 4096: single cold run 7.226 ms, 4096 items derived, lane0 f13cf250640b741e lane31 b77d190ae6454aaf
warp base 1000000: single cold run 7.149 ms, 4096 items derived, lane0 1d0f32760ac86802 lane31 952916a3b036252d
CPU verify: 7.128 ms per 32-lane warp, avg of 50 (checksum 9a88da132b815f31)
Terminated
lease: released 1 pool cores after 1 s, exit 0

11
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@ -0,0 +1,11 @@
lease: holding 1 pool cores (9, waited 0 s, class measure): family gate: verifier row, bench v2m4g+sh256x27 50 warps one core (build-3)
igneum-pow bench: seed "igneum-genesis", day "2026-10-03", dataset 2^28 words (memory-hard)
cache: fill 374.9 ms on one core (2^26 words, 256 MiB, 65536 chains of 64 ChaCha12 blocks), FNV-1a 64 48c4f5bf24166b2e
program: class mx4+sh256x27, 128 loads/hash, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0], 4096 items/warp, mixer x4 (36 mixers/item), cache 2^26 words, op mix load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1; epoch built in 397.6 ms
shadow: 256 instructions x 27 passes per iteration, 55296 shadow instructions per hash, op mix add=47 rotl=30 xor=30 shfl=29 mad=27 mul=22 sub=21 rotr=20 mulhi=18 or=12
warp base 0: single cold run 4.074 ms, 4096 items derived, lane0 7d5c0b3cbd0fcade lane31 2a25e4b6bf48485d
warp base 4096: single cold run 3.650 ms, 4096 items derived, lane0 73a7e6af84f4d3ca lane31 f26081f8ff529a1a
warp base 1000000: single cold run 3.661 ms, 4096 items derived, lane0 2e20e9a0b5cb35da lane31 a8a0e975fa5ae184
CPU verify: 3.725 ms per 32-lane warp, avg of 50 (checksum 164082cfe849fab4)
Terminated
lease: released 1 pool cores after 1 s, exit 0

10
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lease: holding 1 pool cores (8, waited 0 s, class measure): family gate: verifier row, bench v2m8g+sh256x27 50 warps one core (build-3)
igneum-pow bench: seed "igneum-genesis", day "2026-10-03", dataset 2^28 words (memory-hard)
cache: fill 448.8 ms on one core (2^26 words, 256 MiB, 65536 chains of 64 ChaCha12 blocks), FNV-1a 64 48c4f5bf24166b2e
program: class mx8+sh256x27, 128 loads/hash, 512 bytes/hash, widths (1,4,16 words) [16, 0, 0], 4096 items/warp, mixer x8 (72 mixers/item), cache 2^26 words, op mix load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1; epoch built in 2033.0 ms
shadow: 256 instructions x 27 passes per iteration, 55296 shadow instructions per hash, op mix add=47 rotl=30 xor=30 shfl=29 mad=27 mul=22 sub=21 rotr=20 mulhi=18 or=12
warp base 0: single cold run 4.368 ms, 4096 items derived, lane0 dfbc8db1c06dacd8 lane31 b92715f32b721587
warp base 4096: single cold run 4.161 ms, 4096 items derived, lane0 433afad2164a8dda lane31 207c50f288cbb677
warp base 1000000: single cold run 4.113 ms, 4096 items derived, lane0 4ffd090a02db43b4 lane31 60308a0e058e1e29
CPU verify: 4.116 ms per 32-lane warp, avg of 50 (checksum 900cd36a9ead25cf)
lease: released 1 pool cores after 3 s, exit 0

3539
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File diff suppressed because it is too large Load diff

3538
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File diff suppressed because it is too large Load diff

12
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binary bc21542a5b421170 commit fg7 test family_gate_era_census from 2 seeds 64 threads 8 start 2026-10-08T13:05:16Z
lease: 0 of 8 pool cores free (88 leased); waiting
lease: holding 8 pool cores (14,15,16,17,24,25,26,27, waited 1217 s, class measure): family gate: family_gate_era_census f8space-p2-65 seeds 2+64
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 64 eras 2..66 in 49 s on 8 threads -> /srv/builds/_adv-family-gate/logs/f8space-p2-65-family_gate_era_census-2-64.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 49.18s
lease: released 8 pool cores after 1267 s, exit 0
end 2026-10-08T13:26:23Z rc 0

65
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@ -0,0 +1,65 @@
k shape reps mixer width R M pos w_add w_xor w_mul w_mad w_shfl w_rotl w_sub w_mulhi w_rotr w_or attempt candidates a_prime a b c_const c_lane c_sat c_bias c_distinct c1_sat_source c2_low_entropy c3_hot_item min_ratio min_site top_count_max bucket_ratio_max bucket_z_max bucket_site bucket_win bit_z_max bit_site bit_win bit last_resort_k c3_ratios secs
8 256 27 8 1 22 573e71b3 [1, 4, 7, 12] 12 10 8 8 8 7 6 6 6 4 2 3 1 1 0 0 0 0 0 0 0 0 0 0.99628 14 4 3.719 21.75 14 2 -512.76 6 1 22 4.6
2 256 27 8 1 4 bf0fab63 [2, 3, 7, 15] 12 10 8 8 8 7 6 6 6 4 5 6 4 0 1 0 0 0 0 0 0 0 0 0.99994 10 3 1.688 5.50 6 2 -2.83 6 2 16 4.7
4 256 27 8 1 13 2477779f [5, 10, 11, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99613 1 4 7.172 49.38 1 2 -510.71 1 2 13 4.7
6 256 27 8 1 21 05ba4603 [0, 2, 7, 11] 12 10 8 8 8 7 6 6 6 4 6 7 5 0 1 0 0 0 0 0 0 0 0 0.99987 14 4 2.062 6.01 1 1 -3.95 10 2 24 4.8
3 256 27 8 1 1 a80102a7 [0, 5, 8, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99968 8 4 2.375 5.50 0 0 257.84 8 1 1 5.0
5 256 27 8 1 4 435fd6c5 [0, 3, 11, 12] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 1 3 1.938 5.30 4 1 -2.60 2 0 17 5.0
7 256 27 8 1 25 ff347267 [2, 6, 7, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99946 13 4 2.938 7.75 13 0 -511.12 13 0 25 5.1
9 256 27 8 1 18 07114293 [0, 3, 11, 14] 12 10 8 8 8 7 6 6 6 4 8 9 7 1 0 0 0 0 0 0 0 0 0 0.99990 6 3 2.438 5.75 10 0 168.61 12 0 18 8.6
12 256 27 8 1 16 2fda8d19 [0, 4, 6, 10] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99999 14 4 2.375 5.50 0 0 35.93 0 0 17 4.6
11 256 27 8 1 29 b889f389 [3, 5, 9, 12] 12 10 8 8 8 7 6 6 6 4 3 4 2 1 0 0 0 0 0 0 0 0 0 0.99993 12 4 2.312 5.25 3 0 -5.30 1 1 0 4.7
13 256 27 8 1 26 3340424b [1, 7, 14, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99994 3 4 2.562 6.25 8 0 144.94 8 0 26 4.7
10 256 27 8 1 17 5732bb5d [3, 5, 8, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99626 8 3 6.266 42.12 8 2 -512.88 8 2 17 4.9
16 256 27 8 1 1 a6ea3eb1 [1, 4, 7, 10] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99991 8 4 2.375 5.50 9 0 -128.13 4 0 1 4.7
14 256 27 8 1 23 55fb3ce5 [2, 5, 8, 11] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99993 1 4 2.375 5.50 9 0 3.25 8 1 0 4.8
15 256 27 8 1 26 26f35c81 [0, 2, 14, 15] 12 10 8 8 8 7 6 6 6 4 4 5 2 0 1 0 0 0 0 0 0 1 0 0.99997 10 3 2.500 6.00 1 0 -58.21 0 1 0 c2:943 7.3
21 256 27 8 1 22 48825377 [3, 5, 6, 8] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99995 11 4 2.438 5.75 0 0 2.63 0 0 4 4.4
20 256 27 8 1 28 aa378839 [0, 3, 7, 10] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99988 14 4 1.906 5.13 7 1 3.34 12 2 24 4.5
22 256 27 8 1 25 1d32e3af [7, 9, 11, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99991 7 3 1.938 5.30 1 1 -129.05 6 2 25 4.9
23 256 27 8 1 26 d88595c9 [0, 1, 4, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99996 5 4 2.312 5.25 0 0 2.97 5 0 13 5.1
19 256 27 8 1 9 69944467 [6, 9, 11, 12] 12 10 8 8 8 7 6 6 6 4 2 3 0 1 0 0 0 0 0 0 0 1 0 0.99995 13 3 1.906 5.13 6 1 4.40 2 0 25 c2:933 6.9
18 256 27 8 1 22 83e41bc3 [1, 8, 10, 13] 12 10 8 8 8 7 6 6 6 4 9 10 7 1 0 0 0 0 0 0 0 1 0 0.99992 10 4 2.375 5.50 1 0 3.38 6 1 23 c2:927 7.0
17 256 27 8 1 7 fb71a153 [2, 5, 8, 10] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99992 15 4 2.375 5.50 11 0 2.93 14 0 4 8.4
24 256 27 8 1 3 44fd49d7 [0, 4, 7, 9] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99985 14 4 1.906 5.13 3 1 -9.35 15 0 6 4.9
26 256 27 8 1 19 9f5f0bdb [2, 7, 11, 12] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99910 2 3 6.938 23.75 2 0 -511.00 2 0 19 4.7
25 256 27 8 1 14 c619dd6b [2, 6, 8, 15] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99984 2 3 2.250 5.00 11 0 -2.72 13 0 3 4.8
27 256 27 8 1 15 ab4deb19 [4, 5, 11, 13] 12 10 8 8 8 7 6 6 6 4 6 7 6 0 0 0 0 0 0 0 0 0 0 0.99899 1 3 8.562 30.25 1 0 -512.72 1 0 15 4.5
28 256 27 8 1 26 347b218b [0, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99995 0 3 2.312 5.25 3 0 3.66 1 0 10 4.7
29 256 27 8 1 25 e597ba17 [4, 5, 9, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99991 2 4 2.500 6.00 10 0 84.65 12 1 25 4.6
30 256 27 8 1 18 ac8f1c1b [3, 4, 11, 12] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 4 3 2.375 5.50 4 0 -2.95 4 0 13 4.6
32 256 27 8 1 17 dc6791fd [6, 11, 14, 15] 12 10 8 8 8 7 6 6 6 4 6 7 3 1 0 0 0 2 0 0 0 0 0 0.99878 12 4 8.188 28.75 12 0 -513.54 12 0 17 4.7
33 256 27 8 1 6 3e376d09 [0, 3, 4, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99711 0 4 2.312 5.25 10 0 -512.62 7 1 6 4.6
35 256 27 8 1 24 96fc94e3 [0, 7, 12, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99986 11 4 1.656 5.25 14 2 -4.81 1 0 25 4.8
36 256 27 8 1 27 4c7a6647 [9, 10, 12, 15] 12 10 8 8 8 7 6 6 6 4 12 13 11 1 0 0 0 0 0 0 0 0 0 0.99993 11 4 2.375 5.50 14 0 2.74 6 0 3 4.9
34 256 27 8 1 7 2e362f07 [3, 6, 11, 14] 12 10 8 8 8 7 6 6 6 4 1 2 0 0 0 0 0 0 0 0 0 0 1 0.99992 3 4 2.375 5.50 14 0 10.78 4 1 7 c3:992 6.7
38 256 27 8 1 19 06d774fb [3, 4, 12, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99993 6 4 2.312 5.25 1 0 -63.05 5 2 19 4.5
31 256 27 8 1 14 d4aea2c7 [2, 5, 12, 14] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99994 15 3 2.375 5.50 1 0 7.27 12 0 15 8.4
37 256 27 8 1 18 d1f25c1f [1, 7, 8, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99994 13 4 1.938 5.30 8 1 3.82 3 0 18 4.7
39 256 27 8 1 3 a51e7c6d [3, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99905 1 4 2.031 5.83 7 1 -513.32 1 0 3 4.9
40 256 27 8 1 16 4bc62819 [1, 9, 10, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 0 1 0 0 0 0 0 0 0 0 0.99995 4 4 2.375 5.50 3 0 -3.37 15 0 2 4.6
41 256 27 8 1 16 7a5295a9 [0, 3, 7, 11] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99982 11 4 2.000 5.66 0 1 -3.16 14 1 4 4.8
42 256 27 8 1 16 e3baafe9 [2, 7, 10, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99989 9 4 2.375 5.50 13 0 3.63 9 2 0 4.9
44 256 27 8 1 14 2d1bd537 [2, 7, 13, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99616 8 4 7.281 50.25 8 2 -512.09 8 2 14 4.7
43 256 27 8 1 19 cd014ac5 [11, 12, 13, 14] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99919 7 4 2.594 9.02 7 1 -127.25 7 1 20 5.1
46 256 27 8 1 24 6472aa9d [3, 9, 10, 13] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99722 4 4 2.703 13.62 4 2 -512.03 4 2 24 5.0
47 256 27 8 1 25 00a713dd [3, 7, 8, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99989 11 4 2.375 5.50 6 0 3.36 7 2 18 5.1
49 256 27 8 1 30 b1cbeac1 [6, 8, 9, 14] 12 10 8 8 8 7 6 6 6 4 6 7 5 1 0 0 0 0 0 0 0 0 0 0.99991 0 4 2.438 5.75 5 0 -2.86 5 0 21 5.1
45 256 27 8 1 18 d9c46e27 [3, 4, 6, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 1 0 0 0 0 0 0 0 0 0 0.99963 13 3 2.812 10.25 13 1 255.79 13 1 18 8.7
50 256 27 8 1 10 2b3dbe09 [7, 13, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99807 5 4 3.500 14.14 5 1 -512.40 5 1 10 6.1
48 256 27 8 1 13 5e051e51 [9, 10, 12, 13] 12 10 8 8 8 7 6 6 6 4 6 7 5 1 0 0 0 0 0 0 0 0 0 0.99986 14 3 2.500 6.00 11 0 -2.94 5 0 21 7.6
54 256 27 8 1 31 24b4a1e5 [5, 10, 13, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99994 12 4 2.375 5.50 10 0 2.77 11 2 14 5.3
51 256 27 8 1 3 d94b2ac7 [0, 2, 4, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99993 12 4 2.312 5.25 3 0 -3.88 6 1 15 8.8
55 256 27 8 1 7 0e0c23b9 [1, 5, 13, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99625 7 4 2.312 5.25 8 0 -511.26 7 2 7 5.3
53 256 27 8 1 9 7ec0e095 [1, 8, 9, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99949 15 3 2.500 6.00 13 0 159.62 15 2 9 8.8
52 256 27 8 1 12 dd60e49d [2, 4, 12, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99618 14 4 8.078 56.62 14 2 -512.06 14 2 12 9.4
57 256 27 8 1 25 2bfb510f [0, 3, 5, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99997 11 4 1.938 5.30 10 1 -3.40 2 0 19 6.1
59 256 27 8 1 7 ab70a8c7 [2, 3, 8, 10] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99993 14 3 2.094 6.19 15 1 -11.71 13 0 7 5.1
61 256 27 8 1 4 99ec1a13 [3, 8, 13, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99909 1 4 2.375 5.50 9 0 -512.35 1 0 4 5.0
58 256 27 8 1 30 2faae5d7 [1, 5, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99987 7 3 1.969 5.48 14 1 3.57 8 1 3 9.0
56 256 27 8 1 24 dc5e362b [6, 7, 9, 10] 12 10 8 8 8 7 6 6 6 4 4 5 3 0 0 0 0 0 0 0 0 1 0 0.99995 2 4 2.312 5.25 3 0 3.51 8 1 6 c2:965 11.7
65 256 27 8 1 23 8d7fa8fb [1, 10, 11, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 0 1 0 0 0 0 0 0 0 0 0.99811 4 4 2.562 12.50 4 2 -449.07 4 2 23 5.0
64 256 27 8 1 8 f7401b9f [4, 7, 10, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 1 4 2.562 6.25 0 0 -68.29 0 0 8 6.1
60 256 27 8 1 4 cf5e9ceb [0, 2, 5, 8] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99989 8 3 2.250 5.00 15 0 -108.06 2 2 5 9.0
62 256 27 8 1 11 ae89e4ab [3, 5, 8, 13] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99815 9 3 2.203 9.62 9 2 -343.68 9 2 11 8.9
63 256 27 8 1 20 eda85b67 [0, 3, 9, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99988 2 4 2.375 5.50 4 0 -64.53 14 0 21 9.3
1 k shape reps mixer width R M pos w_add w_xor w_mul w_mad w_shfl w_rotl w_sub w_mulhi w_rotr w_or attempt candidates a_prime a b c_const c_lane c_sat c_bias c_distinct c1_sat_source c2_low_entropy c3_hot_item min_ratio min_site top_count_max bucket_ratio_max bucket_z_max bucket_site bucket_win bit_z_max bit_site bit_win bit last_resort_k c3_ratios secs
2 8 256 27 8 1 22 573e71b3 [1, 4, 7, 12] 12 10 8 8 8 7 6 6 6 4 2 3 1 1 0 0 0 0 0 0 0 0 0 0.99628 14 4 3.719 21.75 14 2 -512.76 6 1 22 4.6
3 2 256 27 8 1 4 bf0fab63 [2, 3, 7, 15] 12 10 8 8 8 7 6 6 6 4 5 6 4 0 1 0 0 0 0 0 0 0 0 0.99994 10 3 1.688 5.50 6 2 -2.83 6 2 16 4.7
4 4 256 27 8 1 13 2477779f [5, 10, 11, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99613 1 4 7.172 49.38 1 2 -510.71 1 2 13 4.7
5 6 256 27 8 1 21 05ba4603 [0, 2, 7, 11] 12 10 8 8 8 7 6 6 6 4 6 7 5 0 1 0 0 0 0 0 0 0 0 0.99987 14 4 2.062 6.01 1 1 -3.95 10 2 24 4.8
6 3 256 27 8 1 1 a80102a7 [0, 5, 8, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99968 8 4 2.375 5.50 0 0 257.84 8 1 1 5.0
7 5 256 27 8 1 4 435fd6c5 [0, 3, 11, 12] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 1 3 1.938 5.30 4 1 -2.60 2 0 17 5.0
8 7 256 27 8 1 25 ff347267 [2, 6, 7, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99946 13 4 2.938 7.75 13 0 -511.12 13 0 25 5.1
9 9 256 27 8 1 18 07114293 [0, 3, 11, 14] 12 10 8 8 8 7 6 6 6 4 8 9 7 1 0 0 0 0 0 0 0 0 0 0.99990 6 3 2.438 5.75 10 0 168.61 12 0 18 8.6
10 12 256 27 8 1 16 2fda8d19 [0, 4, 6, 10] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99999 14 4 2.375 5.50 0 0 35.93 0 0 17 4.6
11 11 256 27 8 1 29 b889f389 [3, 5, 9, 12] 12 10 8 8 8 7 6 6 6 4 3 4 2 1 0 0 0 0 0 0 0 0 0 0.99993 12 4 2.312 5.25 3 0 -5.30 1 1 0 4.7
12 13 256 27 8 1 26 3340424b [1, 7, 14, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99994 3 4 2.562 6.25 8 0 144.94 8 0 26 4.7
13 10 256 27 8 1 17 5732bb5d [3, 5, 8, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99626 8 3 6.266 42.12 8 2 -512.88 8 2 17 4.9
14 16 256 27 8 1 1 a6ea3eb1 [1, 4, 7, 10] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99991 8 4 2.375 5.50 9 0 -128.13 4 0 1 4.7
15 14 256 27 8 1 23 55fb3ce5 [2, 5, 8, 11] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99993 1 4 2.375 5.50 9 0 3.25 8 1 0 4.8
16 15 256 27 8 1 26 26f35c81 [0, 2, 14, 15] 12 10 8 8 8 7 6 6 6 4 4 5 2 0 1 0 0 0 0 0 0 1 0 0.99997 10 3 2.500 6.00 1 0 -58.21 0 1 0 c2:943 7.3
17 21 256 27 8 1 22 48825377 [3, 5, 6, 8] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99995 11 4 2.438 5.75 0 0 2.63 0 0 4 4.4
18 20 256 27 8 1 28 aa378839 [0, 3, 7, 10] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99988 14 4 1.906 5.13 7 1 3.34 12 2 24 4.5
19 22 256 27 8 1 25 1d32e3af [7, 9, 11, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99991 7 3 1.938 5.30 1 1 -129.05 6 2 25 4.9
20 23 256 27 8 1 26 d88595c9 [0, 1, 4, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99996 5 4 2.312 5.25 0 0 2.97 5 0 13 5.1
21 19 256 27 8 1 9 69944467 [6, 9, 11, 12] 12 10 8 8 8 7 6 6 6 4 2 3 0 1 0 0 0 0 0 0 0 1 0 0.99995 13 3 1.906 5.13 6 1 4.40 2 0 25 c2:933 6.9
22 18 256 27 8 1 22 83e41bc3 [1, 8, 10, 13] 12 10 8 8 8 7 6 6 6 4 9 10 7 1 0 0 0 0 0 0 0 1 0 0.99992 10 4 2.375 5.50 1 0 3.38 6 1 23 c2:927 7.0
23 17 256 27 8 1 7 fb71a153 [2, 5, 8, 10] 12 10 8 8 8 7 6 6 6 4 3 4 3 0 0 0 0 0 0 0 0 0 0 0.99992 15 4 2.375 5.50 11 0 2.93 14 0 4 8.4
24 24 256 27 8 1 3 44fd49d7 [0, 4, 7, 9] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99985 14 4 1.906 5.13 3 1 -9.35 15 0 6 4.9
25 26 256 27 8 1 19 9f5f0bdb [2, 7, 11, 12] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99910 2 3 6.938 23.75 2 0 -511.00 2 0 19 4.7
26 25 256 27 8 1 14 c619dd6b [2, 6, 8, 15] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99984 2 3 2.250 5.00 11 0 -2.72 13 0 3 4.8
27 27 256 27 8 1 15 ab4deb19 [4, 5, 11, 13] 12 10 8 8 8 7 6 6 6 4 6 7 6 0 0 0 0 0 0 0 0 0 0 0.99899 1 3 8.562 30.25 1 0 -512.72 1 0 15 4.5
28 28 256 27 8 1 26 347b218b [0, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99995 0 3 2.312 5.25 3 0 3.66 1 0 10 4.7
29 29 256 27 8 1 25 e597ba17 [4, 5, 9, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99991 2 4 2.500 6.00 10 0 84.65 12 1 25 4.6
30 30 256 27 8 1 18 ac8f1c1b [3, 4, 11, 12] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 4 3 2.375 5.50 4 0 -2.95 4 0 13 4.6
31 32 256 27 8 1 17 dc6791fd [6, 11, 14, 15] 12 10 8 8 8 7 6 6 6 4 6 7 3 1 0 0 0 2 0 0 0 0 0 0.99878 12 4 8.188 28.75 12 0 -513.54 12 0 17 4.7
32 33 256 27 8 1 6 3e376d09 [0, 3, 4, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99711 0 4 2.312 5.25 10 0 -512.62 7 1 6 4.6
33 35 256 27 8 1 24 96fc94e3 [0, 7, 12, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99986 11 4 1.656 5.25 14 2 -4.81 1 0 25 4.8
34 36 256 27 8 1 27 4c7a6647 [9, 10, 12, 15] 12 10 8 8 8 7 6 6 6 4 12 13 11 1 0 0 0 0 0 0 0 0 0 0.99993 11 4 2.375 5.50 14 0 2.74 6 0 3 4.9
35 34 256 27 8 1 7 2e362f07 [3, 6, 11, 14] 12 10 8 8 8 7 6 6 6 4 1 2 0 0 0 0 0 0 0 0 0 0 1 0.99992 3 4 2.375 5.50 14 0 10.78 4 1 7 c3:992 6.7
36 38 256 27 8 1 19 06d774fb [3, 4, 12, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99993 6 4 2.312 5.25 1 0 -63.05 5 2 19 4.5
37 31 256 27 8 1 14 d4aea2c7 [2, 5, 12, 14] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99994 15 3 2.375 5.50 1 0 7.27 12 0 15 8.4
38 37 256 27 8 1 18 d1f25c1f [1, 7, 8, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99994 13 4 1.938 5.30 8 1 3.82 3 0 18 4.7
39 39 256 27 8 1 3 a51e7c6d [3, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99905 1 4 2.031 5.83 7 1 -513.32 1 0 3 4.9
40 40 256 27 8 1 16 4bc62819 [1, 9, 10, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 0 1 0 0 0 0 0 0 0 0 0.99995 4 4 2.375 5.50 3 0 -3.37 15 0 2 4.6
41 41 256 27 8 1 16 7a5295a9 [0, 3, 7, 11] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99982 11 4 2.000 5.66 0 1 -3.16 14 1 4 4.8
42 42 256 27 8 1 16 e3baafe9 [2, 7, 10, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99989 9 4 2.375 5.50 13 0 3.63 9 2 0 4.9
43 44 256 27 8 1 14 2d1bd537 [2, 7, 13, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99616 8 4 7.281 50.25 8 2 -512.09 8 2 14 4.7
44 43 256 27 8 1 19 cd014ac5 [11, 12, 13, 14] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99919 7 4 2.594 9.02 7 1 -127.25 7 1 20 5.1
45 46 256 27 8 1 24 6472aa9d [3, 9, 10, 13] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99722 4 4 2.703 13.62 4 2 -512.03 4 2 24 5.0
46 47 256 27 8 1 25 00a713dd [3, 7, 8, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99989 11 4 2.375 5.50 6 0 3.36 7 2 18 5.1
47 49 256 27 8 1 30 b1cbeac1 [6, 8, 9, 14] 12 10 8 8 8 7 6 6 6 4 6 7 5 1 0 0 0 0 0 0 0 0 0 0.99991 0 4 2.438 5.75 5 0 -2.86 5 0 21 5.1
48 45 256 27 8 1 18 d9c46e27 [3, 4, 6, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 1 0 0 0 0 0 0 0 0 0 0.99963 13 3 2.812 10.25 13 1 255.79 13 1 18 8.7
49 50 256 27 8 1 10 2b3dbe09 [7, 13, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99807 5 4 3.500 14.14 5 1 -512.40 5 1 10 6.1
50 48 256 27 8 1 13 5e051e51 [9, 10, 12, 13] 12 10 8 8 8 7 6 6 6 4 6 7 5 1 0 0 0 0 0 0 0 0 0 0.99986 14 3 2.500 6.00 11 0 -2.94 5 0 21 7.6
51 54 256 27 8 1 31 24b4a1e5 [5, 10, 13, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99994 12 4 2.375 5.50 10 0 2.77 11 2 14 5.3
52 51 256 27 8 1 3 d94b2ac7 [0, 2, 4, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99993 12 4 2.312 5.25 3 0 -3.88 6 1 15 8.8
53 55 256 27 8 1 7 0e0c23b9 [1, 5, 13, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99625 7 4 2.312 5.25 8 0 -511.26 7 2 7 5.3
54 53 256 27 8 1 9 7ec0e095 [1, 8, 9, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99949 15 3 2.500 6.00 13 0 159.62 15 2 9 8.8
55 52 256 27 8 1 12 dd60e49d [2, 4, 12, 14] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99618 14 4 8.078 56.62 14 2 -512.06 14 2 12 9.4
56 57 256 27 8 1 25 2bfb510f [0, 3, 5, 9] 12 10 8 8 8 7 6 6 6 4 4 5 4 0 0 0 0 0 0 0 0 0 0 0.99997 11 4 1.938 5.30 10 1 -3.40 2 0 19 6.1
57 59 256 27 8 1 7 ab70a8c7 [2, 3, 8, 10] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99993 14 3 2.094 6.19 15 1 -11.71 13 0 7 5.1
58 61 256 27 8 1 4 99ec1a13 [3, 8, 13, 14] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99909 1 4 2.375 5.50 9 0 -512.35 1 0 4 5.0
59 58 256 27 8 1 30 2faae5d7 [1, 5, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99987 7 3 1.969 5.48 14 1 3.57 8 1 3 9.0
60 56 256 27 8 1 24 dc5e362b [6, 7, 9, 10] 12 10 8 8 8 7 6 6 6 4 4 5 3 0 0 0 0 0 0 0 0 1 0 0.99995 2 4 2.312 5.25 3 0 3.51 8 1 6 c2:965 11.7
61 65 256 27 8 1 23 8d7fa8fb [1, 10, 11, 13] 12 10 8 8 8 7 6 6 6 4 3 4 2 0 1 0 0 0 0 0 0 0 0 0.99811 4 4 2.562 12.50 4 2 -449.07 4 2 23 5.0
62 64 256 27 8 1 8 f7401b9f [4, 7, 10, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 1 4 2.562 6.25 0 0 -68.29 0 0 8 6.1
63 60 256 27 8 1 4 cf5e9ceb [0, 2, 5, 8] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99989 8 3 2.250 5.00 15 0 -108.06 2 2 5 9.0
64 62 256 27 8 1 11 ae89e4ab [3, 5, 8, 13] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99815 9 3 2.203 9.62 9 2 -343.68 9 2 11 8.9
65 63 256 27 8 1 20 eda85b67 [0, 3, 9, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99988 2 4 2.375 5.50 4 0 -64.53 14 0 21 9.3

13
docs/analysis/class-v6/logs/f8space-p212-225-family_gate_era_census-212-14.log Normal file
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@ -0,0 +1,13 @@
binary bc21542a5b421170 commit fg7 test family_gate_era_census from 212 seeds 14 threads 4 start 2026-10-08T13:05:16Z
lease: 0 of 4 pool cores free (88 leased); waiting
lease: holding 4 pool cores (28,29,30,31, waited 1217 s, class measure): family gate: family_gate_era_census f8space-p212-225 seeds 212+14
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 14 eras 212..226 in 35 s on 4 threads -> /srv/builds/_adv-family-gate/logs/f8space-p212-225-family_gate_era_census-212-14.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 34.69s
Terminated
lease: released 4 pool cores after 1252 s, exit 0
end 2026-10-08T13:26:08Z rc 0

15
docs/analysis/class-v6/logs/f8space-p212-225-family_gate_era_census-212-14.tsv Normal file
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@ -0,0 +1,15 @@
k shape reps mixer width R M pos w_add w_xor w_mul w_mad w_shfl w_rotl w_sub w_mulhi w_rotr w_or attempt candidates a_prime a b c_const c_lane c_sat c_bias c_distinct c1_sat_source c2_low_entropy c3_hot_item min_ratio min_site top_count_max bucket_ratio_max bucket_z_max bucket_site bucket_win bit_z_max bit_site bit_win bit last_resort_k c3_ratios secs
215 256 27 8 1 7 9f95aef9 [3, 4, 7, 14] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99969 6 3 2.000 5.66 10 1 -256.22 6 1 7 8.7
213 256 27 8 1 31 04aeeee3 [0, 1, 3, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99995 13 3 1.938 5.30 5 1 3.02 3 1 0 8.8
214 256 27 8 1 1 04870f7f [1, 2, 6, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 13 3 2.438 5.75 14 0 -10.66 13 0 2 8.9
212 256 27 8 1 8 d56f9b19 [5, 7, 13, 15] 12 10 8 8 8 7 6 6 6 4 4 5 3 0 0 0 0 0 0 0 0 0 1 0.99577 9 4 1.719 5.75 9 2 -512.14 9 2 8 c3:991 13.0
216 256 27 8 1 30 ddd46ce1 [0, 1, 7, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99987 8 3 2.312 5.25 3 0 -3.32 12 0 20 8.5
217 256 27 8 1 15 2bb44f89 [10, 11, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99987 8 3 2.312 5.25 3 0 -64.88 0 1 15 8.7
218 256 27 8 1 10 210c1f81 [3, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99934 5 4 2.000 5.66 5 1 -353.27 5 1 11 9.2
219 256 27 8 1 2 fbc1458b [2, 8, 13, 14] 12 10 8 8 8 7 6 6 6 4 2 3 1 1 0 0 0 0 0 0 0 0 0 0.99993 12 3 2.312 5.25 3 0 2.83 9 2 4 9.1
221 256 27 8 1 16 147a60c9 [2, 6, 9, 11] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99900 14 3 7.688 26.75 14 0 -512.53 14 0 16 8.0
220 256 27 8 1 16 3b974b5b [0, 1, 9, 10] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99872 1 4 6.812 32.88 1 1 -438.52 1 1 16 8.6
222 256 27 8 1 27 38ebb1bd [0, 5, 8, 10] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99987 0 4 2.375 5.50 0 0 -122.37 1 0 27 8.9
223 256 27 8 1 17 195d676f [0, 6, 8, 13] 12 10 8 8 8 7 6 6 6 4 4 5 3 1 0 0 0 0 0 0 0 0 0 0.99993 6 3 2.031 5.83 1 1 3.29 15 1 4 8.5
224 256 27 8 1 18 8a4c7517 [1, 2, 3, 6] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99987 12 4 1.656 5.25 13 2 3.29 2 0 17 8.7
225 256 27 8 1 2 2ef225c7 [0, 12, 14, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99740 4 3 2.375 5.50 5 0 -567.19 4 1 2 8.9
1 k shape reps mixer width R M pos w_add w_xor w_mul w_mad w_shfl w_rotl w_sub w_mulhi w_rotr w_or attempt candidates a_prime a b c_const c_lane c_sat c_bias c_distinct c1_sat_source c2_low_entropy c3_hot_item min_ratio min_site top_count_max bucket_ratio_max bucket_z_max bucket_site bucket_win bit_z_max bit_site bit_win bit last_resort_k c3_ratios secs
2 215 256 27 8 1 7 9f95aef9 [3, 4, 7, 14] 12 10 8 8 8 7 6 6 6 4 5 6 4 1 0 0 0 0 0 0 0 0 0 0.99969 6 3 2.000 5.66 10 1 -256.22 6 1 7 8.7
3 213 256 27 8 1 31 04aeeee3 [0, 1, 3, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99995 13 3 1.938 5.30 5 1 3.02 3 1 0 8.8
4 214 256 27 8 1 1 04870f7f [1, 2, 6, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99990 13 3 2.438 5.75 14 0 -10.66 13 0 2 8.9
5 212 256 27 8 1 8 d56f9b19 [5, 7, 13, 15] 12 10 8 8 8 7 6 6 6 4 4 5 3 0 0 0 0 0 0 0 0 0 1 0.99577 9 4 1.719 5.75 9 2 -512.14 9 2 8 c3:991 13.0
6 216 256 27 8 1 30 ddd46ce1 [0, 1, 7, 9] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99987 8 3 2.312 5.25 3 0 -3.32 12 0 20 8.5
7 217 256 27 8 1 15 2bb44f89 [10, 11, 14, 15] 12 10 8 8 8 7 6 6 6 4 1 2 0 1 0 0 0 0 0 0 0 0 0 0.99987 8 3 2.312 5.25 3 0 -64.88 0 1 15 8.7
8 218 256 27 8 1 10 210c1f81 [3, 6, 12, 13] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99934 5 4 2.000 5.66 5 1 -353.27 5 1 11 9.2
9 219 256 27 8 1 2 fbc1458b [2, 8, 13, 14] 12 10 8 8 8 7 6 6 6 4 2 3 1 1 0 0 0 0 0 0 0 0 0 0.99993 12 3 2.312 5.25 3 0 2.83 9 2 4 9.1
10 221 256 27 8 1 16 147a60c9 [2, 6, 9, 11] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99900 14 3 7.688 26.75 14 0 -512.53 14 0 16 8.0
11 220 256 27 8 1 16 3b974b5b [0, 1, 9, 10] 12 10 8 8 8 7 6 6 6 4 2 3 2 0 0 0 0 0 0 0 0 0 0 0.99872 1 4 6.812 32.88 1 1 -438.52 1 1 16 8.6
12 222 256 27 8 1 27 38ebb1bd [0, 5, 8, 10] 12 10 8 8 8 7 6 6 6 4 1 2 1 0 0 0 0 0 0 0 0 0 0 0.99987 0 4 2.375 5.50 0 0 -122.37 1 0 27 8.9
13 223 256 27 8 1 17 195d676f [0, 6, 8, 13] 12 10 8 8 8 7 6 6 6 4 4 5 3 1 0 0 0 0 0 0 0 0 0 0.99993 6 3 2.031 5.83 1 1 3.29 15 1 4 8.5
14 224 256 27 8 1 18 8a4c7517 [1, 2, 3, 6] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99987 12 4 1.656 5.25 13 2 3.29 2 0 17 8.7
15 225 256 27 8 1 2 2ef225c7 [0, 12, 14, 15] 12 10 8 8 8 7 6 6 6 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0.99740 4 3 2.375 5.50 5 0 -567.19 4 1 2 8.9

15
docs/analysis/class-v6/logs/fg-records.py
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@ -1,6 +1,6 @@
#!/usr/bin/env python3
"""family-gate lane: one gate-record JSON per drawn era from the census TSV rows (the format of family-gate.md section 4.3).
usage: fg-records.py <outdir> <stratum>=<tsv>[,<tsv>] ... ; the harness binary sha and box from the matching .log header."""
"""family-gate lane: one gate-record JSON per drawn era (the format of family-gate.md section 4.3) from the census TSV rows, written as ONE JSON-lines file per stratum under <outdir> (25,000 files would not belong in a repository).
usage: fg-records.py <outdir> <stratum>::<tsv>[,<tsv>] ... ; the harness binary sha from the matching .log header."""
import sys, csv, json, os, pathlib, hashlib
FAMILY = {"id": "class-v6-draft-2026-10-08", "spec": "docs/spec/01-lottery-hash.md 1.4.6, 1.13.1 (the family's bands in docs/analysis/class-v6/family-gate.md section 1)",
"object": "igneum-pow class-v5 8f481459 plus the harness (branch family-gate-v5), the acceptance keyed on the family's shapes behind IGNEUM_FAMILY_GATE"}
@ -13,14 +13,14 @@ def header(logpath):
out = pathlib.Path(sys.argv[1]); out.mkdir(parents=True, exist_ok=True)
n = 0
for arg in sys.argv[2:]:
stratum, paths = arg.split('=', 1)
stratum, paths = arg.split('::', 1)
for p in paths.split(','):
if not os.path.exists(p): continue
h = header(p[:-4] + '.log')
with open(p) as f:
for r in csv.DictReader(f, delimiter='\t'):
acc = r['attempt'] not in ('', '-1')
rec = {"family": FAMILY, "label": "internal research, not an independent review",
rec = {"family": FAMILY["id"], "label": "internal research, not an independent review",
"era": {"label": f"igneum-family-gate/era/{r['k']}", "stratum": stratum,
"draw": {"m": int(r['mixer']), "weights": [int(r[k]) for k in ['w_add','w_xor','w_mul','w_mad','w_shfl','w_rotl','w_sub','w_mulhi','w_rotr','w_or']],
"width_words": int(r['width']), "shape": [int(r['shape']), int(r['reps'])], "R": int(r['R']), "M": "0x" + r['M'], "pos": json.loads(r['pos'])}},
@ -31,8 +31,9 @@ for arg in sys.argv[2:]:
"exhausted": not acc, "verdict": "PASS" if acc else "EXHAUSTED"},
{"name": "c2-c3-ratio", "floor": [0.98, 0.995], "min_ratio": float(r['min_ratio']) if acc else None, "min_site": int(r['min_site']) if acc else None, "verdict": "PASS" if acc else "n/a"},
{"name": "bucket-256-items", "max_ratio": float(r['bucket_ratio_max']) if acc else None, "max_sigma": float(r.get('bucket_z_max') or 'nan') if acc else None, "site": int(r['bucket_site']) if acc else None, "window": int(r.get('bucket_win') or -1) if acc else None, "bound": "not yet set (the clean spread is this census)", "verdict": "RECORD"},
{"name": "last-resort-scan", "first_passing_k": (r.get('last_resort_k') or None) if not acc else None, "verdict": "n/a" if acc else ("PASS" if (r.get('last_resort_k') or '') not in ('', 'fallback') else "FALLBACK")},
{"name": "index-bit-bias", "max_sigma": float(r['bit_z_max']) if acc else None, "site": int(r['bit_site']) if acc else None, "bit": int(r['bit']) if acc else None, "window": int(r.get('bit_win') or -1) if acc else None, "band_sigma": 6, "over_band": (abs(float(r['bit_z_max'])) > 6) if acc else None, "verdict": "RECORD"}]}
(out / stratum).mkdir(exist_ok=True)
(out / stratum / f"era-{r['k']}.json").write_text(json.dumps(rec, indent=1))
with open(out / f"{stratum}.jsonl", "a") as fh:
fh.write(json.dumps(rec, separators=(',', ':')) + "\n")
n += 1
print(f"{n} records under {out}")
print(f"{n} records under {out} (the family block: {json.dumps(FAMILY)})")

45
docs/analysis/class-v6/logs/floor-read-A.log Normal file
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lease: 0 of 4 pool cores free (24 leased); waiting
lease: holding 8 pool cores (8,9,10,11,12,13,14,15, waited 693 s, class measure): family gate: the (c3) floor read on point A 64 seeds (v5_hot_census under the band weights)
running 1 test
test accept::tests::v5_hot_census ... v5_hot_census: 64 seeds 2..66 in 79 s on 8 threads
class v4 sub-version 3 accepted programs' minimum site ratio: min 0.9932 p0.1 0.9932 p1 0.9933 p5 0.9962 median 0.9999 max 1.0000
floor 0.980: 0 of 64 class v4 accepted programs under it (0.000 percent)
floor 0.990: 0 of 64 class v4 accepted programs under it (0.000 percent)
floor 0.995: 3 of 64 class v4 accepted programs under it (4.688 percent)
floor 0.998: 6 of 64 class v4 accepted programs under it (9.375 percent)
floor 0.999: 11 of 64 class v4 accepted programs under it (17.188 percent)
low: seed 38 v4 attempt 0 min site 0 ratio 0.9932; v5 attempt 1 min ratio 0.9999
low: seed 11 v4 attempt 1 min site 10 ratio 0.9933; v5 attempt 2 min ratio 0.9999
low: seed 54 v4 attempt 0 min site 12 ratio 0.9945; v5 attempt 1 min ratio 0.9999
low: seed 55 v4 attempt 0 min site 3 ratio 0.9962; v5 attempt 0 min ratio 0.9962
low: seed 4 v4 attempt 0 min site 1 ratio 0.9963; v5 attempt 0 min ratio 0.9963
low: seed 24 v4 attempt 1 min site 2 ratio 0.9969; v5 attempt 1 min ratio 0.9969
low: seed 32 v4 attempt 0 min site 8 ratio 0.9980; v5 attempt 0 min ratio 0.9980
low: seed 48 v4 attempt 2 min site 0 ratio 0.9981; v5 attempt 2 min ratio 0.9981
low: seed 61 v4 attempt 0 min site 5 ratio 0.9987; v5 attempt 0 min ratio 0.9987
low: seed 45 v4 attempt 0 min site 0 ratio 0.9988; v5 attempt 0 min ratio 0.9988
low: seed 39 v4 attempt 0 min site 2 ratio 0.9990; v5 attempt 0 min ratio 0.9990
low: seed 3 v4 attempt 1 min site 4 ratio 0.9991; v5 attempt 1 min ratio 0.9991
low: seed 17 v4 attempt 2 min site 1 ratio 0.9991; v5 attempt 2 min ratio 0.9991
low: seed 14 v4 attempt 0 min site 12 ratio 0.9992; v5 attempt 0 min ratio 0.9992
low: seed 53 v4 attempt 0 min site 4 ratio 0.9992; v5 attempt 0 min ratio 0.9992
low: seed 42 v4 attempt 0 min site 13 ratio 0.9994; v5 attempt 0 min ratio 0.9994
low: seed 40 v4 attempt 1 min site 1 ratio 0.9995; v5 attempt 1 min ratio 0.9995
low: seed 15 v4 attempt 0 min site 2 ratio 0.9995; v5 attempt 0 min ratio 0.9995
low: seed 7 v4 attempt 0 min site 0 ratio 0.9995; v5 attempt 0 min ratio 0.9995
low: seed 60 v4 attempt 0 min site 8 ratio 0.9997; v5 attempt 0 min ratio 0.9997
low: seed 6 v4 attempt 0 min site 15 ratio 0.9997; v5 attempt 0 min ratio 0.9997
low: seed 25 v4 attempt 1 min site 9 ratio 0.9997; v5 attempt 1 min ratio 0.9997
low: seed 49 v4 attempt 0 min site 15 ratio 0.9997; v5 attempt 0 min ratio 0.9997
low: seed 57 v4 attempt 0 min site 13 ratio 0.9998; v5 attempt 0 min ratio 0.9998
low: seed 35 v4 attempt 0 min site 8 ratio 0.9998; v5 attempt 0 min ratio 0.9998
attempts histogram class v4 (mean 0.297): {0: 49, 1: 12, 2: 2, 3: 1}
attempts histogram class v5 (mean 0.344): {0: 47, 1: 13, 2: 3, 3: 1}
seeds whose class v5 draw lands on another attempt than the class v4 draw: 3 of 64 (4.688 percent)
class v5 accepted programs under the class v5 floor 0.995: 0 (must be 0)
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 78.69s
lease: released 8 pool cores after 771 s, exit 0

44
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lease: holding 8 pool cores (8,9,10,11,12,13,14,15, waited 0 s, class measure): family gate: the (c3) floor read on point B 64 seeds (shape 64, band era 5 weights)
running 1 test
test accept::tests::v5_hot_census ... v5_hot_census: 64 seeds 2..66 in 77 s on 8 threads
class v4 sub-version 3 accepted programs' minimum site ratio: min 0.9934 p0.1 0.9934 p1 0.9957 p5 0.9962 median 0.9999 max 1.0000
floor 0.980: 0 of 64 class v4 accepted programs under it (0.000 percent)
floor 0.990: 0 of 64 class v4 accepted programs under it (0.000 percent)
floor 0.995: 1 of 64 class v4 accepted programs under it (1.562 percent)
floor 0.998: 12 of 64 class v4 accepted programs under it (18.750 percent)
floor 0.999: 14 of 64 class v4 accepted programs under it (21.875 percent)
low: seed 15 v4 attempt 1 min site 12 ratio 0.9934; v5 attempt 4 min ratio 0.9993
low: seed 64 v4 attempt 1 min site 4 ratio 0.9957; v5 attempt 1 min ratio 0.9957
low: seed 54 v4 attempt 1 min site 14 ratio 0.9958; v5 attempt 1 min ratio 0.9958
low: seed 39 v4 attempt 0 min site 4 ratio 0.9962; v5 attempt 0 min ratio 0.9962
low: seed 42 v4 attempt 1 min site 4 ratio 0.9962; v5 attempt 1 min ratio 0.9962
low: seed 52 v4 attempt 1 min site 14 ratio 0.9962; v5 attempt 1 min ratio 0.9962
low: seed 55 v4 attempt 0 min site 3 ratio 0.9963; v5 attempt 0 min ratio 0.9963
low: seed 10 v4 attempt 0 min site 8 ratio 0.9963; v5 attempt 0 min ratio 0.9963
low: seed 18 v4 attempt 0 min site 14 ratio 0.9969; v5 attempt 0 min ratio 0.9969
low: seed 24 v4 attempt 1 min site 2 ratio 0.9971; v5 attempt 1 min ratio 0.9971
low: seed 41 v4 attempt 0 min site 14 ratio 0.9979; v5 attempt 0 min ratio 0.9979
low: seed 47 v4 attempt 4 min site 11 ratio 0.9980; v5 attempt 4 min ratio 0.9980
low: seed 32 v4 attempt 0 min site 9 ratio 0.9980; v5 attempt 0 min ratio 0.9980
low: seed 17 v4 attempt 0 min site 3 ratio 0.9982; v5 attempt 0 min ratio 0.9982
low: seed 34 v4 attempt 3 min site 4 ratio 0.9990; v5 attempt 3 min ratio 0.9990
low: seed 53 v4 attempt 1 min site 15 ratio 0.9991; v5 attempt 1 min ratio 0.9991
low: seed 5 v4 attempt 0 min site 11 ratio 0.9991; v5 attempt 0 min ratio 0.9991
low: seed 3 v4 attempt 1 min site 10 ratio 0.9994; v5 attempt 1 min ratio 0.9994
low: seed 7 v4 attempt 1 min site 13 ratio 0.9996; v5 attempt 1 min ratio 0.9996
low: seed 49 v4 attempt 0 min site 4 ratio 0.9996; v5 attempt 0 min ratio 0.9996
low: seed 40 v4 attempt 0 min site 0 ratio 0.9996; v5 attempt 0 min ratio 0.9996
low: seed 37 v4 attempt 2 min site 14 ratio 0.9997; v5 attempt 2 min ratio 0.9997
low: seed 43 v4 attempt 1 min site 3 ratio 0.9997; v5 attempt 1 min ratio 0.9997
low: seed 61 v4 attempt 1 min site 13 ratio 0.9998; v5 attempt 1 min ratio 0.9998
low: seed 20 v4 attempt 0 min site 14 ratio 0.9998; v5 attempt 0 min ratio 0.9998
attempts histogram class v4 (mean 1.453): {0: 22, 1: 21, 2: 8, 3: 3, 4: 4, 5: 5, 6: 1}
attempts histogram class v5 (mean 1.500): {0: 22, 1: 20, 2: 8, 3: 3, 4: 5, 5: 5, 6: 1}
seeds whose class v5 draw lands on another attempt than the class v4 draw: 1 of 64 (1.562 percent)
class v5 accepted programs under the class v5 floor 0.995: 0 (must be 0)
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 77.21s
lease: released 8 pool cores after 77 s, exit 0

3000
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binary 42f2c77ff7e5216e commit fg6 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T11:26:56Z
lease: holding 16 pool cores (21,22,23,24,25,27,28,29,30,31,32,33,52,53,54,55, waited 0 s, class measure): family gate: family_gate_era_census lossyplus1 seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 46 s
family_gate_era_census: 200 eras in 89 s
family_gate_era_census: 300 eras in 133 s
family_gate_era_census: 400 eras in 178 s
family_gate_era_census: 500 eras in 241 s
family_gate_era_census: 600 eras in 305 s
family_gate_era_census: 700 eras in 372 s
family_gate_era_census: 800 eras in 436 s
family_gate_era_census: 900 eras in 510 s
family_gate_era_census: 1000 eras in 579 s
family_gate_era_census: 1100 eras in 655 s
family_gate_era_census: 1200 eras in 724 s
family_gate_era_census: 1300 eras in 792 s
family_gate_era_census: 1400 eras in 872 s
family_gate_era_census: 1500 eras in 943 s
family_gate_era_census: 1600 eras in 1009 s
family_gate_era_census: 1700 eras in 1069 s
family_gate_era_census: 1800 eras in 1133 s
family_gate_era_census: 1900 eras in 1190 s
family_gate_era_census: 2000 eras in 1246 s
family_gate_era_census: 2100 eras in 1302 s
family_gate_era_census: 2200 eras in 1358 s
family_gate_era_census: 2300 eras in 1418 s
family_gate_era_census: 2400 eras in 1476 s
family_gate_era_census: 2500 eras in 1531 s
family_gate_era_census: 2600 eras in 1593 s
family_gate_era_census: 2700 eras in 1649 s
family_gate_era_census: 2800 eras in 1711 s
family_gate_era_census: 2900 eras in 1767 s
family_gate_era_census: 3000 eras in 1820 s
family_gate_era_census: 3000 eras 0..3000 in 1820 s on 16 threads -> /srv/builds/_adv-family-gate/logs/lossyplus1-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 1820.39s
Terminated
lease: released 16 pool cores after 1821 s, exit 0
end 2026-10-08T11:57:17Z rc 0

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binary 42f2c77ff7e5216e commit fg6 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T11:26:56Z
lease: holding 16 pool cores (34,35,36,37,38,39,40,41,44,45,46,47,48,49,50,51, waited 0 s, class measure): family gate: family_gate_era_census lossyplus2 seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 41 s
family_gate_era_census: 200 eras in 79 s
family_gate_era_census: 300 eras in 117 s
family_gate_era_census: 400 eras in 161 s
family_gate_era_census: 500 eras in 207 s
family_gate_era_census: 600 eras in 269 s
family_gate_era_census: 700 eras in 332 s
family_gate_era_census: 800 eras in 392 s
family_gate_era_census: 900 eras in 456 s
family_gate_era_census: 1000 eras in 526 s
family_gate_era_census: 1100 eras in 594 s
family_gate_era_census: 1200 eras in 658 s
family_gate_era_census: 1300 eras in 726 s
family_gate_era_census: 1400 eras in 791 s
family_gate_era_census: 1500 eras in 865 s
family_gate_era_census: 1600 eras in 936 s
family_gate_era_census: 1700 eras in 997 s
family_gate_era_census: 1800 eras in 1051 s
family_gate_era_census: 1900 eras in 1111 s
family_gate_era_census: 2000 eras in 1163 s
family_gate_era_census: 2100 eras in 1219 s
family_gate_era_census: 2200 eras in 1268 s
family_gate_era_census: 2300 eras in 1325 s
family_gate_era_census: 2400 eras in 1385 s
family_gate_era_census: 2500 eras in 1440 s
family_gate_era_census: 2600 eras in 1496 s
family_gate_era_census: 2700 eras in 1547 s
family_gate_era_census: 2800 eras in 1608 s
family_gate_era_census: 2900 eras in 1660 s
family_gate_era_census: 3000 eras in 1722 s
family_gate_era_census: 3000 eras 0..3000 in 1722 s on 16 threads -> /srv/builds/_adv-family-gate/logs/lossyplus2-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 1722.38s
Terminated
lease: released 16 pool cores after 1723 s, exit 0
end 2026-10-08T11:55:39Z rc 0

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binary 42f2c77ff7e5216e commit fg6 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T11:26:56Z
lease: holding 16 pool cores (56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71, waited 0 s, class measure): family gate: family_gate_era_census lossyplus3 seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 63 s
family_gate_era_census: 200 eras in 122 s
family_gate_era_census: 300 eras in 186 s
family_gate_era_census: 400 eras in 258 s
family_gate_era_census: 500 eras in 332 s
family_gate_era_census: 600 eras in 407 s
family_gate_era_census: 700 eras in 486 s
family_gate_era_census: 800 eras in 564 s
family_gate_era_census: 900 eras in 648 s
family_gate_era_census: 1000 eras in 731 s
family_gate_era_census: 1100 eras in 810 s
family_gate_era_census: 1200 eras in 901 s
family_gate_era_census: 1300 eras in 972 s
family_gate_era_census: 1400 eras in 1042 s
family_gate_era_census: 1500 eras in 1118 s
family_gate_era_census: 1600 eras in 1186 s
family_gate_era_census: 1700 eras in 1252 s
family_gate_era_census: 1800 eras in 1315 s
family_gate_era_census: 1900 eras in 1389 s
family_gate_era_census: 2000 eras in 1457 s
family_gate_era_census: 2100 eras in 1525 s
family_gate_era_census: 2200 eras in 1592 s
family_gate_era_census: 2300 eras in 1658 s
family_gate_era_census: 2400 eras in 1727 s
family_gate_era_census: 2500 eras in 1791 s
family_gate_era_census: 2600 eras in 1848 s
family_gate_era_census: 2700 eras in 1905 s
family_gate_era_census: 2800 eras in 1955 s
family_gate_era_census: 2900 eras in 2007 s
family_gate_era_census: 3000 eras in 2058 s
family_gate_era_census: 3000 eras 0..3000 in 2058 s on 16 threads -> /srv/builds/_adv-family-gate/logs/lossyplus3-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 2058.46s
Terminated
lease: released 16 pool cores after 2059 s, exit 0
end 2026-10-08T12:01:15Z rc 0

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binary 42f2c77ff7e5216e commit fg6 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T11:26:56Z
lease: holding 16 pool cores (8,9,10,11,12,13,14,15,16,17,18,19,20,26,42,43, waited 0 s, class measure): family gate: family_gate_era_census lossyplus4 seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 62 s
family_gate_era_census: 200 eras in 121 s
family_gate_era_census: 300 eras in 184 s
family_gate_era_census: 400 eras in 259 s
family_gate_era_census: 500 eras in 331 s
family_gate_era_census: 600 eras in 410 s
family_gate_era_census: 700 eras in 497 s
family_gate_era_census: 800 eras in 578 s
family_gate_era_census: 900 eras in 666 s
family_gate_era_census: 1000 eras in 760 s
family_gate_era_census: 1100 eras in 844 s
family_gate_era_census: 1200 eras in 936 s
family_gate_era_census: 1300 eras in 1012 s
family_gate_era_census: 1400 eras in 1085 s
family_gate_era_census: 1500 eras in 1156 s
family_gate_era_census: 1600 eras in 1226 s
family_gate_era_census: 1700 eras in 1291 s
family_gate_era_census: 1800 eras in 1364 s
family_gate_era_census: 1900 eras in 1433 s
family_gate_era_census: 2000 eras in 1498 s
family_gate_era_census: 2100 eras in 1565 s
family_gate_era_census: 2200 eras in 1630 s
family_gate_era_census: 2300 eras in 1696 s
family_gate_era_census: 2400 eras in 1767 s
family_gate_era_census: 2500 eras in 1830 s
family_gate_era_census: 2600 eras in 1892 s
family_gate_era_census: 2700 eras in 1953 s
family_gate_era_census: 2800 eras in 2010 s
family_gate_era_census: 2900 eras in 2063 s
family_gate_era_census: 3000 eras in 2096 s
family_gate_era_census: 3000 eras 0..3000 in 2096 s on 16 threads -> /srv/builds/_adv-family-gate/logs/lossyplus4-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 2096.29s
lease: released 16 pool cores after 2097 s, exit 0
end 2026-10-08T12:01:53Z rc 0

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class seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads max_item control_max reads
mx8+shl4096x1 4 0 8b26974db22f7adb 1.00013 6 0.002493 0.002377 1.0489 28 0 29 134217728
mx8+shl4096x1 2 0 3764a916ec848654 0.98948 4 0.002514 0.002380 1.0564 29 0 29 134217728
mx8+shl4096x1 3 0 8760a65b01a4eec3 1.00012 6 0.002712 0.002380 1.1392 31 0 28 134217728
mx8+shl4096x1 7 2 0bf5a36c962d1298 1.00012 15 0.002754 0.002379 1.1579 31 0 27 134217728
mx8+shl4096x1 6 3 407564abd1ecf8fb 1.00009 12 0.002930 0.002380 1.2311 33 0 28 134217728
mx8+shl4096x1 1 8 c5ea07d99fabfede 1.00013 7 0.002863 0.002381 1.2024 32 0 27 134217728
mx8+shl4096x1 5 8 25cec98741f2d310 1.00006 14 0.002593 0.002379 1.0899 29 0 28 134217728
mx8+shl4096x1 0 21 c1b0bf25a44c43a5 1.00014 9 0.002755 0.002382 1.1562 30 0 27 134217728
mx8+shl4096x1 8 1 badfcc7b19f88069 1.00012 5 0.002499 0.002379 1.0504 30 0 27 134217728
mx8+shl4096x1 11 1 b71c56b0cac71afe 1.00012 11 0.003118 0.002382 1.3092 34 0 27 134217728
mx8+shl4096x1 10 5 ea04e485b78bb7d7 0.99892 15 0.003545 0.002381 1.4886 38 0 27 134217728
mx8+shl4096x1 12 8 1604cd82d168e803 1.00013 12 0.002596 0.002381 1.0900 30 0 27 134217728
mx8+shl4096x1 14 3 3ec256c4201b2dc5 0.99948 0 0.002945 0.002382 1.2364 33 0 27 134217728
mx8+shl4096x1 13 6 1b7583111f414673 0.99928 8 0.002865 0.002383 1.2025 31 0 27 134217728
mx8+shl4096x1 9 0 dfc9d1d5817b06e1 0.99877 1 0.002489 0.002380 1.0458 28 0 28 134217728
mx8+shl4096x1 15 14 6eb7067aed8aa8d2 1.00010 8 0.002383 0.002380 1.0011 29 0 27 134217728
mx8+shl4096x1 17 3 aa67aa41a40c765a 1.00008 10 0.002851 0.002380 1.1983 34 0 27 134217728
mx8+shl4096x1 18 0 d05ff66c095ed53c 0.99449 2 0.002707 0.002381 1.1369 31 0 27 134217728
mx8+shl4096x1 19 1 5b8a713ce263bc37 1.00013 11 0.003129 0.002381 1.3141 35 0 27 134217728
mx8+shl4096x1 22 6 32c7c11e24f33a82 1.00010 15 0.002599 0.002382 1.0911 28 0 27 134217728
mx8+shl4096x1 16 14 cdc7f03fd8219abe 1.00013 13 0.002673 0.002381 1.1226 30 0 27 134217728
mx8+shl4096x1 20 7 f61563c3ada11f92 0.99447 0 0.002509 0.002378 1.0549 29 0 27 134217728
mx8+shl4096x1 23 1 0d9ab5e5702fde85 0.99943 11 0.002514 0.002378 1.0569 29 0 28 134217728
mx8+shl4096x1 21 19 82bdbb697373a55f 1.00013 8 0.002611 0.002382 1.0959 31 0 28 134217728
mx8+shl4096x1 25 3 33a74cae3a54731e 0.99711 5 0.002762 0.002381 1.1602 32 0 26 134217728
mx8+shl4096x1 24 2 0e31b5c579eb7b1f 1.00009 4 0.002454 0.002380 1.0311 28 0 28 134217728
mx8+shl4096x1 26 8 8aabdea5da1f5b24 0.97847 14 0.003071 0.002380 1.2904 542 0 26 134217728
mx8+shl4096x1 28 2 c888297c45360309 0.99562 4 0.002733 0.002380 1.1483 31 0 28 134217728
mx8+shl4096x1 27 1 ae243b93dc021c19 0.95594 10 0.002622 0.002381 1.1011 1938 0 26 134217728
mx8+shl4096x1 31 0 651940b69196cd6b 1.00017 14 0.002944 0.002382 1.2361 33 0 28 134217728
mx8+shl4096x1 29 2 32e42bd966e953a2 1.00009 0 0.003115 0.002379 1.3092 35 0 27 134217728
mx8+shl4096x1 30 1 c925e0019bb99b3c 1.00010 1 0.002883 0.002381 1.2108 35 0 27 134217728
mx8+shl4096x1 32 0 b4ee4da03147256f 1.00009 7 0.002862 0.002379 1.2028 33 0 28 134217728
mx8+shl4096x1 34 1 becdff9e1b454a3c 0.99452 8 0.002497 0.002381 1.0487 28 0 27 134217728
mx8+shl4096x1 36 7 67e99c1c77fadd85 1.00010 1 0.002860 0.002380 1.2016 32 0 28 134217728
mx8+shl4096x1 35 3 7def70357c164f66 1.00008 7 0.002753 0.002381 1.1564 32 0 28 134217728
mx8+shl4096x1 37 1 6e89e5149a77ac35 0.99987 9 0.002703 0.002380 1.1356 32 0 27 134217728
mx8+shl4096x1 38 0 4e94a6b9f384ada9 1.00013 5 0.002864 0.002380 1.2030 32 0 27 134217728
mx8+shl4096x1 33 9 e79c351e73c42fa6 1.00010 5 0.003117 0.002381 1.3094 36 0 28 134217728
mx8+shl4096x1 39 0 c7594ad92bc0fffa 0.99946 0 0.002413 0.002382 1.0132 28 0 27 134217728
mx8+shl4096x1 43 0 80b52717c66fed64 1.00013 7 0.002595 0.002381 1.0898 29 0 27 134217728
mx8+shl4096x1 41 1 8165d35c308b82f7 1.00013 2 0.003193 0.002383 1.3399 37 0 27 134217728
mx8+shl4096x1 40 16 89bd764c12b883e7 1.00016 7 0.002514 0.002381 1.0558 29 0 27 134217728
mx8+shl4096x1 46 1 3619ccc0ca59e780 1.00009 10 0.002753 0.002381 1.1565 34 0 28 134217728
mx8+shl4096x1 44 4 0eda24762c7f7ddf 0.99983 0 0.003121 0.002381 1.3109 36 0 27 134217728
mx8+shl4096x1 45 2 9f4e0b6895695441 0.99928 9 0.002677 0.002382 1.1236 31 0 26 134217728
mx8+shl4096x1 42 20 6dd422548d7374b7 1.00010 4 0.002791 0.002381 1.1724 33 0 26 134217728
mx8+shl4096x1 47 3 e5b9bcfb8fc594a1 1.00008 12 0.002714 0.002378 1.1412 30 0 28 134217728
mx8+shl4096x1 48 4 ae73b91c8cb0eb65 1.00011 15 0.002603 0.002381 1.0931 30 0 28 134217728
mx8+shl4096x1 51 7 54eedec66fd25844 0.99999 13 0.003019 0.002378 1.2694 34 0 27 134217728
mx8+shl4096x1 54 2 5dfbe68ec52215f6 1.00013 10 0.003379 0.002380 1.4197 38 0 26 134217728
mx8+shl4096x1 50 6 3f568f23f1d5726f 0.93998 9 0.002711 0.002379 1.1395 66 0 27 134217728
mx8+shl4096x1 53 2 e29d6c9e80086a64 1.00015 1 0.003285 0.002380 1.3800 36 0 27 134217728
mx8+shl4096x1 49 9 7f698114a589e47a 1.00012 15 0.002593 0.002381 1.0895 30 0 27 134217728
mx8+shl4096x1 52 12 38be51c6ea080fdd 1.00014 6 0.002514 0.002379 1.0566 28 0 28 134217728
mx8+shl4096x1 55 2 8e59845a615ccda4 1.00013 14 0.002589 0.002380 1.0878 28 0 27 134217728
mx8+shl4096x1 56 10 4a9cf666fd0e201b 1.00007 12 0.002667 0.002381 1.1202 30 0 28 134217728
mx8+shl4096x1 57 2 fc4851c828a7453a 1.00012 8 0.002849 0.002382 1.1960 32 0 27 134217728
mx8+shl4096x1 62 0 1c1c19b6b075c89f 1.00014 4 0.002593 0.002380 1.0894 30 0 27 134217728
mx8+shl4096x1 58 2 9eaad3e9dbac56eb 1.00012 12 0.002928 0.002380 1.2301 32 0 26 134217728
mx8+shl4096x1 61 2 47f5d446f055699e 1.00015 7 0.003035 0.002383 1.2736 36 0 29 134217728
mx8+shl4096x1 60 15 1a38df895c6de9be 1.00016 13 0.002613 0.002380 1.0979 29 0 26 134217728
mx8+shl4096x1 59 1 d662101d18a15ee9 1.00011 13 0.002668 0.002381 1.1203 31 0 27 134217728
mx8+shl4096x1 63 2 42652ca40c92d654 0.99958 11 0.003121 0.002381 1.3108 35 0 26 134217728
1 class seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads max_item control_max reads
2 mx8+shl4096x1 4 0 8b26974db22f7adb 1.00013 6 0.002493 0.002377 1.0489 28 0 29 134217728
3 mx8+shl4096x1 2 0 3764a916ec848654 0.98948 4 0.002514 0.002380 1.0564 29 0 29 134217728
4 mx8+shl4096x1 3 0 8760a65b01a4eec3 1.00012 6 0.002712 0.002380 1.1392 31 0 28 134217728
5 mx8+shl4096x1 7 2 0bf5a36c962d1298 1.00012 15 0.002754 0.002379 1.1579 31 0 27 134217728
6 mx8+shl4096x1 6 3 407564abd1ecf8fb 1.00009 12 0.002930 0.002380 1.2311 33 0 28 134217728
7 mx8+shl4096x1 1 8 c5ea07d99fabfede 1.00013 7 0.002863 0.002381 1.2024 32 0 27 134217728
8 mx8+shl4096x1 5 8 25cec98741f2d310 1.00006 14 0.002593 0.002379 1.0899 29 0 28 134217728
9 mx8+shl4096x1 0 21 c1b0bf25a44c43a5 1.00014 9 0.002755 0.002382 1.1562 30 0 27 134217728
10 mx8+shl4096x1 8 1 badfcc7b19f88069 1.00012 5 0.002499 0.002379 1.0504 30 0 27 134217728
11 mx8+shl4096x1 11 1 b71c56b0cac71afe 1.00012 11 0.003118 0.002382 1.3092 34 0 27 134217728
12 mx8+shl4096x1 10 5 ea04e485b78bb7d7 0.99892 15 0.003545 0.002381 1.4886 38 0 27 134217728
13 mx8+shl4096x1 12 8 1604cd82d168e803 1.00013 12 0.002596 0.002381 1.0900 30 0 27 134217728
14 mx8+shl4096x1 14 3 3ec256c4201b2dc5 0.99948 0 0.002945 0.002382 1.2364 33 0 27 134217728
15 mx8+shl4096x1 13 6 1b7583111f414673 0.99928 8 0.002865 0.002383 1.2025 31 0 27 134217728
16 mx8+shl4096x1 9 0 dfc9d1d5817b06e1 0.99877 1 0.002489 0.002380 1.0458 28 0 28 134217728
17 mx8+shl4096x1 15 14 6eb7067aed8aa8d2 1.00010 8 0.002383 0.002380 1.0011 29 0 27 134217728
18 mx8+shl4096x1 17 3 aa67aa41a40c765a 1.00008 10 0.002851 0.002380 1.1983 34 0 27 134217728
19 mx8+shl4096x1 18 0 d05ff66c095ed53c 0.99449 2 0.002707 0.002381 1.1369 31 0 27 134217728
20 mx8+shl4096x1 19 1 5b8a713ce263bc37 1.00013 11 0.003129 0.002381 1.3141 35 0 27 134217728
21 mx8+shl4096x1 22 6 32c7c11e24f33a82 1.00010 15 0.002599 0.002382 1.0911 28 0 27 134217728
22 mx8+shl4096x1 16 14 cdc7f03fd8219abe 1.00013 13 0.002673 0.002381 1.1226 30 0 27 134217728
23 mx8+shl4096x1 20 7 f61563c3ada11f92 0.99447 0 0.002509 0.002378 1.0549 29 0 27 134217728
24 mx8+shl4096x1 23 1 0d9ab5e5702fde85 0.99943 11 0.002514 0.002378 1.0569 29 0 28 134217728
25 mx8+shl4096x1 21 19 82bdbb697373a55f 1.00013 8 0.002611 0.002382 1.0959 31 0 28 134217728
26 mx8+shl4096x1 25 3 33a74cae3a54731e 0.99711 5 0.002762 0.002381 1.1602 32 0 26 134217728
27 mx8+shl4096x1 24 2 0e31b5c579eb7b1f 1.00009 4 0.002454 0.002380 1.0311 28 0 28 134217728
28 mx8+shl4096x1 26 8 8aabdea5da1f5b24 0.97847 14 0.003071 0.002380 1.2904 542 0 26 134217728
29 mx8+shl4096x1 28 2 c888297c45360309 0.99562 4 0.002733 0.002380 1.1483 31 0 28 134217728
30 mx8+shl4096x1 27 1 ae243b93dc021c19 0.95594 10 0.002622 0.002381 1.1011 1938 0 26 134217728
31 mx8+shl4096x1 31 0 651940b69196cd6b 1.00017 14 0.002944 0.002382 1.2361 33 0 28 134217728
32 mx8+shl4096x1 29 2 32e42bd966e953a2 1.00009 0 0.003115 0.002379 1.3092 35 0 27 134217728
33 mx8+shl4096x1 30 1 c925e0019bb99b3c 1.00010 1 0.002883 0.002381 1.2108 35 0 27 134217728
34 mx8+shl4096x1 32 0 b4ee4da03147256f 1.00009 7 0.002862 0.002379 1.2028 33 0 28 134217728
35 mx8+shl4096x1 34 1 becdff9e1b454a3c 0.99452 8 0.002497 0.002381 1.0487 28 0 27 134217728
36 mx8+shl4096x1 36 7 67e99c1c77fadd85 1.00010 1 0.002860 0.002380 1.2016 32 0 28 134217728
37 mx8+shl4096x1 35 3 7def70357c164f66 1.00008 7 0.002753 0.002381 1.1564 32 0 28 134217728
38 mx8+shl4096x1 37 1 6e89e5149a77ac35 0.99987 9 0.002703 0.002380 1.1356 32 0 27 134217728
39 mx8+shl4096x1 38 0 4e94a6b9f384ada9 1.00013 5 0.002864 0.002380 1.2030 32 0 27 134217728
40 mx8+shl4096x1 33 9 e79c351e73c42fa6 1.00010 5 0.003117 0.002381 1.3094 36 0 28 134217728
41 mx8+shl4096x1 39 0 c7594ad92bc0fffa 0.99946 0 0.002413 0.002382 1.0132 28 0 27 134217728
42 mx8+shl4096x1 43 0 80b52717c66fed64 1.00013 7 0.002595 0.002381 1.0898 29 0 27 134217728
43 mx8+shl4096x1 41 1 8165d35c308b82f7 1.00013 2 0.003193 0.002383 1.3399 37 0 27 134217728
44 mx8+shl4096x1 40 16 89bd764c12b883e7 1.00016 7 0.002514 0.002381 1.0558 29 0 27 134217728
45 mx8+shl4096x1 46 1 3619ccc0ca59e780 1.00009 10 0.002753 0.002381 1.1565 34 0 28 134217728
46 mx8+shl4096x1 44 4 0eda24762c7f7ddf 0.99983 0 0.003121 0.002381 1.3109 36 0 27 134217728
47 mx8+shl4096x1 45 2 9f4e0b6895695441 0.99928 9 0.002677 0.002382 1.1236 31 0 26 134217728
48 mx8+shl4096x1 42 20 6dd422548d7374b7 1.00010 4 0.002791 0.002381 1.1724 33 0 26 134217728
49 mx8+shl4096x1 47 3 e5b9bcfb8fc594a1 1.00008 12 0.002714 0.002378 1.1412 30 0 28 134217728
50 mx8+shl4096x1 48 4 ae73b91c8cb0eb65 1.00011 15 0.002603 0.002381 1.0931 30 0 28 134217728
51 mx8+shl4096x1 51 7 54eedec66fd25844 0.99999 13 0.003019 0.002378 1.2694 34 0 27 134217728
52 mx8+shl4096x1 54 2 5dfbe68ec52215f6 1.00013 10 0.003379 0.002380 1.4197 38 0 26 134217728
53 mx8+shl4096x1 50 6 3f568f23f1d5726f 0.93998 9 0.002711 0.002379 1.1395 66 0 27 134217728
54 mx8+shl4096x1 53 2 e29d6c9e80086a64 1.00015 1 0.003285 0.002380 1.3800 36 0 27 134217728
55 mx8+shl4096x1 49 9 7f698114a589e47a 1.00012 15 0.002593 0.002381 1.0895 30 0 27 134217728
56 mx8+shl4096x1 52 12 38be51c6ea080fdd 1.00014 6 0.002514 0.002379 1.0566 28 0 28 134217728
57 mx8+shl4096x1 55 2 8e59845a615ccda4 1.00013 14 0.002589 0.002380 1.0878 28 0 27 134217728
58 mx8+shl4096x1 56 10 4a9cf666fd0e201b 1.00007 12 0.002667 0.002381 1.1202 30 0 28 134217728
59 mx8+shl4096x1 57 2 fc4851c828a7453a 1.00012 8 0.002849 0.002382 1.1960 32 0 27 134217728
60 mx8+shl4096x1 62 0 1c1c19b6b075c89f 1.00014 4 0.002593 0.002380 1.0894 30 0 27 134217728
61 mx8+shl4096x1 58 2 9eaad3e9dbac56eb 1.00012 12 0.002928 0.002380 1.2301 32 0 26 134217728
62 mx8+shl4096x1 61 2 47f5d446f055699e 1.00015 7 0.003035 0.002383 1.2736 36 0 29 134217728
63 mx8+shl4096x1 60 15 1a38df895c6de9be 1.00016 13 0.002613 0.002380 1.0979 29 0 26 134217728
64 mx8+shl4096x1 59 1 d662101d18a15ee9 1.00011 13 0.002668 0.002381 1.1203 31 0 27 134217728
65 mx8+shl4096x1 63 2 42652ca40c92d654 0.99958 11 0.003121 0.002381 1.3108 35 0 26 134217728

42
docs/analysis/class-v6/logs/w1band-family_gate_era_census-0-3000.log Normal file
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@ -0,0 +1,42 @@
binary bc21542a5b421170 commit fg7 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T12:27:36Z
lease: 0 of 8 pool cores free (80 leased), a higher class waits ahead; waiting
lease: holding 16 pool cores (59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74, waited 381 s, class measure): family gate: family_gate_era_census w1band seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 65 s
family_gate_era_census: 200 eras in 118 s
family_gate_era_census: 300 eras in 156 s
family_gate_era_census: 400 eras in 194 s
family_gate_era_census: 500 eras in 229 s
family_gate_era_census: 600 eras in 267 s
family_gate_era_census: 700 eras in 301 s
family_gate_era_census: 800 eras in 334 s
family_gate_era_census: 900 eras in 366 s
family_gate_era_census: 1000 eras in 400 s
family_gate_era_census: 1100 eras in 435 s
family_gate_era_census: 1200 eras in 472 s
family_gate_era_census: 1300 eras in 518 s
family_gate_era_census: 1400 eras in 573 s
family_gate_era_census: 1500 eras in 624 s
family_gate_era_census: 1600 eras in 672 s
family_gate_era_census: 1700 eras in 725 s
family_gate_era_census: 1800 eras in 775 s
family_gate_era_census: 1900 eras in 824 s
family_gate_era_census: 2000 eras in 870 s
family_gate_era_census: 2100 eras in 915 s
family_gate_era_census: 2200 eras in 963 s
family_gate_era_census: 2300 eras in 1009 s
family_gate_era_census: 2400 eras in 1061 s
family_gate_era_census: 2500 eras in 1110 s
family_gate_era_census: 2600 eras in 1159 s
family_gate_era_census: 2700 eras in 1210 s
family_gate_era_census: 2800 eras in 1261 s
family_gate_era_census: 2900 eras in 1309 s
family_gate_era_census: 3000 eras in 1356 s
family_gate_era_census: 3000 eras 0..3000 in 1356 s on 16 threads -> /srv/builds/_adv-family-gate/logs/w1band-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 1356.41s
lease: released 16 pool cores after 1737 s, exit 0
end 2026-10-08T12:56:33Z rc 0

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docs/analysis/class-v6/logs/w4band-family_gate_era_census-0-3000.log Normal file
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@ -0,0 +1,42 @@
binary bc21542a5b421170 commit fg7 test family_gate_era_census from 0 seeds 3000 threads 8 start 2026-10-08T12:24:08Z
lease: holding 8 pool cores (8,9,10,11,12,13,14,15, waited 0 s, class measure): family gate: family_gate_era_census w4band seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 107 s
family_gate_era_census: 200 eras in 197 s
family_gate_era_census: 300 eras in 249 s
family_gate_era_census: 400 eras in 304 s
family_gate_era_census: 500 eras in 358 s
family_gate_era_census: 600 eras in 411 s
family_gate_era_census: 700 eras in 464 s
family_gate_era_census: 800 eras in 519 s
family_gate_era_census: 900 eras in 574 s
family_gate_era_census: 1000 eras in 634 s
family_gate_era_census: 1100 eras in 694 s
family_gate_era_census: 1200 eras in 754 s
family_gate_era_census: 1300 eras in 819 s
family_gate_era_census: 1400 eras in 910 s
family_gate_era_census: 1500 eras in 1002 s
family_gate_era_census: 1600 eras in 1086 s
family_gate_era_census: 1700 eras in 1166 s
family_gate_era_census: 1800 eras in 1244 s
family_gate_era_census: 1900 eras in 1323 s
family_gate_era_census: 2000 eras in 1416 s
family_gate_era_census: 2100 eras in 1505 s
family_gate_era_census: 2200 eras in 1603 s
family_gate_era_census: 2300 eras in 1687 s
family_gate_era_census: 2400 eras in 1785 s
family_gate_era_census: 2500 eras in 1890 s
family_gate_era_census: 2600 eras in 1980 s
family_gate_era_census: 2700 eras in 2065 s
family_gate_era_census: 2800 eras in 2158 s
family_gate_era_census: 2900 eras in 2252 s
family_gate_era_census: 3000 eras in 2328 s
family_gate_era_census: 3000 eras 0..3000 in 2328 s on 8 threads -> /srv/builds/_adv-family-gate/logs/w4band-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 2328.38s
Terminated
lease: released 8 pool cores after 2328 s, exit 0
end 2026-10-08T13:02:56Z rc 0

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42
docs/analysis/class-v6/logs/w4shape64-family_gate_era_census-0-3000.log Normal file
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@ -0,0 +1,42 @@
binary e7a50f8dcf57a14b commit fg5 test family_gate_era_census from 0 seeds 3000 threads 16 start 2026-10-08T12:27:03Z
lease: 0 of 8 pool cores free (88 leased); waiting
lease: holding 16 pool cores (16,17,21,22,23,24,25,26,80,81,82,83,84,85,86,95, waited 152 s, class measure): family gate: family_gate_era_census w4shape64 seeds 0+3000
running 1 test
test accept::tests::family_gate_era_census ... family_gate_era_census: 100 eras in 73 s
family_gate_era_census: 200 eras in 131 s
family_gate_era_census: 300 eras in 194 s
family_gate_era_census: 400 eras in 258 s
family_gate_era_census: 500 eras in 324 s
family_gate_era_census: 600 eras in 383 s
family_gate_era_census: 700 eras in 448 s
family_gate_era_census: 800 eras in 517 s
family_gate_era_census: 900 eras in 586 s
family_gate_era_census: 1000 eras in 655 s
family_gate_era_census: 1100 eras in 726 s
family_gate_era_census: 1200 eras in 792 s
family_gate_era_census: 1300 eras in 863 s
family_gate_era_census: 1400 eras in 927 s
family_gate_era_census: 1500 eras in 990 s
family_gate_era_census: 1600 eras in 1058 s
family_gate_era_census: 1700 eras in 1126 s
family_gate_era_census: 1800 eras in 1200 s
family_gate_era_census: 1900 eras in 1274 s
family_gate_era_census: 2000 eras in 1356 s
family_gate_era_census: 2100 eras in 1438 s
family_gate_era_census: 2200 eras in 1521 s
family_gate_era_census: 2300 eras in 1603 s
family_gate_era_census: 2400 eras in 1678 s
family_gate_era_census: 2500 eras in 1755 s
family_gate_era_census: 2600 eras in 1825 s
family_gate_era_census: 2700 eras in 1888 s
family_gate_era_census: 2800 eras in 1948 s
family_gate_era_census: 2900 eras in 2007 s
family_gate_era_census: 3000 eras in 2073 s
family_gate_era_census: 3000 eras 0..3000 in 2073 s on 16 threads -> /srv/builds/_adv-family-gate/logs/w4shape64-family_gate_era_census-0-3000.tsv
ok
test result: ok. 1 passed; 0 failed; 0 ignored; 0 measured; 80 filtered out; finished in 2073.12s
lease: released 16 pool cores after 2226 s, exit 0
end 2026-10-08T13:04:09Z rc 0

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331
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2
docs/plans/counter-asic-3-public-text-2026-10-07.md
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@ -4,6 +4,8 @@ Three texts and one ledger row, written by the Counter ASIC lane, which owns the
## 1. The home page's chip line (replaces the hero sentence served since 6 October 16:21Z)
SUPERSEDED on the served pages on 8 October 2026 (the class v6 floor close, docs/design/class-v6-rotating-family.md section 10, amended into three statements at the founder's word): the served chip text is now the audit lane's spec-accept-23 wording (the 64-register window, 2.2x to 2.4x modelled against the GPU tier, 2.0x on the GPU's own node; economic resistance stated as conditions, not a forecast; response capability per boundary), with the 2.1x/3.4x line, the 5x to 9x baseline, the k about 0.33 column and the lifetime claim struck. The text below is the 7 October wording, kept as the record of what was served between 7 October and the 8 October landing.
Built for graphics cards. At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block; a 5090 locked at its knee pays 82 W for that shadow work. Class v5 then makes the dataset the chain's own state, so a chip that stores it or recomputes it is wrong on every item. Without class v4 the same chip would reach 5x to 9x. The model and every measurement are public.
## 2. The litepaper's chip section (replaces the paragraph that begins "The chip model: 5x to 9x per joule")

2
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168
igneum-pow/src/accept.rs
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@ -92,6 +92,12 @@ pub enum Reject {
OutputBias { bit: u8, ones: u32 },
/// (c): the distinct-address sum was `sum`.
DistinctAddresses { sum: u64 },
/// (c, the per-load shadow class only; Counter ASIC 4.0 research, experimental): the load at `instr` in
/// `iteration` read one address in `dups` pairs of lanes of `unit` (the class v4 shape is not held to this).
DuplicateLanes { iteration: u8, instr: u8, unit: u8, dups: u8 },
/// (c, the per-load shadow class only; Counter ASIC 4.0 research, the adv-cache-2 requirement): index bit `bit` at
/// load site `site` was set in `ones` of the 16,384 addresses of the 64 units, outside the 6-sigma band.
BiasedIndexBit { site: u8, bit: u8, ones: u32 },
}
impl std::fmt::Display for Reject {
@ -102,6 +108,12 @@ impl std::fmt::Display for Reject {
}
Reject::NoInjectingWrite { reg } => write!(f, "(b) r{reg} has no add, sub, xor, mad, shfl or load write"),
Reject::ConstantBit { reg, bits } => write!(f, "(c) r{reg} has {bits} nonce-independent bits"),
Reject::BiasedIndexBit { site, bit, ones } => {
write!(f, "(c, per-load shadow) index bit {bit} at load site {site} set in {ones} of 16,384 addresses")
}
Reject::DuplicateLanes { iteration, instr, unit, dups } => {
write!(f, "(c, per-load shadow) load at iteration {iteration} instruction {instr} reads a duplicate address in {dups} lanes of unit {unit}")
}
Reject::LaneConstantSite { iteration, instr, unit } => {
write!(f, "(c) load at iteration {iteration} instruction {instr} reads one address in all lanes of unit {unit}")
}
@ -231,6 +243,7 @@ pub fn distinct_indices_v4(p: &Program, units: usize) -> Result<Vec<u32>, Reject
saturated: 0,
bit_ones: [0; 64],
distinct_sum: 0,
site_bit_ones: Vec::new(),
};
let mut lane_addrs = vec![0u32; LANES * loads];
for (unit, &base) in accept_base_nonces_n(&p.seed, units).iter().enumerate() {
@ -356,6 +369,84 @@ struct Acc {
saturated: u32,
bit_ones: [u32; 64],
distinct_sum: u64,
/// Counter ASIC 4.0 research (the per-load class only): one-count of every index bit per load site over the units.
site_bit_ones: Vec<[u32; 32]>,
}
/// One ALU instruction of a shadow sub-block on the register file (the same arithmetic as the arms of `run_unit`;
/// no load, scratch or hot op is ever in a sub-block). Counter ASIC 4.0 research: the per-load shadow class runs its
/// sub-blocks inside the acceptance test, so the test judges the order the class executes.
fn alu_step(ins: &Instr, r: &mut [[u32; LANES]; 8], sel: &[u32; LANES]) {
let d = ins.dst as usize;
let a = ins.src as usize;
match ins.op {
Op::Add => {
let (imm, imm2, bit) = (ins.imm, ins.imm2, ins.bit as u32);
let src = r[a];
for lane in 0..LANES {
let s = (sel[lane] >> bit) & 1;
let c = if s != 0 { imm2 } else { imm };
r[d][lane] = r[d][lane].wrapping_add(src[lane]).wrapping_add(c);
}
}
Op::Sub => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] = r[d][lane].wrapping_sub(src[lane]);
}
}
Op::Mul => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] = r[d][lane].wrapping_mul(src[lane]);
}
}
Op::MulHi => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] = mulhi32(r[d][lane], src[lane]);
}
}
Op::Xor => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] ^= src[lane];
}
}
Op::Or => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] |= src[lane];
}
}
Op::Rotl => {
let n = ins.rot;
for lane in 0..LANES {
r[d][lane] = r[d][lane].rotate_left(n);
}
}
Op::Rotr => {
let src = r[a];
for lane in 0..LANES {
r[d][lane] = r[d][lane].rotate_right(src[lane] & 31);
}
}
Op::Mad => {
let src = r[a];
let src2 = r[ins.src2 as usize];
for lane in 0..LANES {
r[d][lane] = src[lane].wrapping_mul(src2[lane]).wrapping_add(r[d][lane]);
}
}
Op::Shfl => {
let src = r[a];
let m = ins.mask as usize;
for lane in 0..LANES {
r[d][lane] ^= src[lane ^ m];
}
}
Op::Load | Op::WLoad | Op::Scratch | Op::Hot => unreachable!("a shadow sub-block holds ALU instructions only"),
}
}
/// One unit of the dynamic test: the interpreter of `verify.rs` with the closed-form dataset, instrumented.
@ -386,13 +477,21 @@ fn run_unit(p: &Program, unit: usize, base: u32, acc: &mut Acc, lane_addrs: &mut
// after instruction 63 of every iteration, `reps` times with the iteration's `sel`, exactly as the hash does
// (verify.rs). Until this commit it ran the 64 base instructions only, so every dynamic test (c) judged a class v4
// program the chain never hashes. The shadow block holds no load, so its instructions take the same arms.
let shadow_reps = p.shadow_reps();
// Counter ASIC 4.0 research: under the per-load placement the block runs as sub-blocks inside the loop below
// (per_load_after), so the end-of-iteration pass is empty for that class.
let per_load = p.shadow_per_load();
let shadow_reps = if per_load { 0 } else { p.shadow_reps() };
for it in 0..ITERATIONS {
let sel = r[0];
let mut load_j = 0usize;
let shadow_pass = (0..shadow_reps).flat_map(|_| p.shadow.iter().enumerate().map(|(k, i)| (INSTR_COUNT + k, i)));
for (k, ins) in p.instrs.iter().enumerate().chain(shadow_pass) {
let d = ins.dst as usize;
let a = ins.src as usize;
// Counter ASIC 4.0 research (the per-load shadow class): sub-block j runs reps times right after the
// j-th memory operation, as the class executes it, so the saturation and distinctness tests below see
// the register file the loads actually read from
let per_load_after = per_load && ins.op.is_load();
match ins.op {
Op::Scratch => {
// Variant 5: the slot stands in for the address (bit 31 set so it never aliases a dataset word).
@ -494,6 +593,24 @@ fn run_unit(p: &Program, unit: usize, base: u32, acc: &mut Acc, lane_addrs: &mut
if idx.iter().all(|&x| x == idx[0]) {
return Err(Reject::LaneConstantSite { iteration: it as u8, instr: k as u8, unit: unit as u8 });
}
if per_load {
let mut sorted = idx;
sorted.sort_unstable();
let dups = sorted.windows(2).filter(|w| w[0] == w[1]).count();
if dups > 0 {
return Err(Reject::DuplicateLanes { iteration: it as u8, instr: k as u8, unit: unit as u8, dups: dups as u8 });
}
// the bit one-counts are sized by check_dynamic; the (c'') pass (distinct_indices_v4) runs this
// unit with no table and judges indices only
if !acc.site_bit_ones.is_empty() {
let site = load_j % acc.site_bit_ones.len();
for &x in &idx {
for b in 0..32 {
acc.site_bit_ones[site][b] += (x >> b) & 1;
}
}
}
}
for lane in 0..LANES {
if width == 1 {
r[d][lane] ^= dataset_elem(idx[lane], d0, d1);
@ -533,6 +650,14 @@ fn run_unit(p: &Program, unit: usize, base: u32, acc: &mut Acc, lane_addrs: &mut
nload += 1;
}
}
if per_load_after {
for _ in 0..p.shadow_reps() {
for sh in p.shadow_sub_block(load_j) {
alu_step(sh, &mut r, &sel);
}
}
load_j += 1;
}
}
}
for i in 0..8 {
@ -578,11 +703,42 @@ pub fn check_dynamic(p: &Program) -> Result<AcceptReport, Reject> {
saturated: 0,
bit_ones: [0; 64],
distinct_sum: 0,
site_bit_ones: Vec::new(),
};
if p.shadow_per_load() {
acc.site_bit_ones = vec![[0u32; 32]; p.instrs.iter().filter(|i| i.op.is_load()).count().max(1)];
}
let mut lane_addrs = vec![0u32; LANES * loads];
for (unit, &base) in accept_base_nonces(&p.seed).iter().enumerate() {
run_unit(p, unit, base, &mut acc, &mut lane_addrs)?;
}
if p.shadow_per_load() {
// the value-level test (the adv-cache-2 requirement, 7 October 2026): an index bit whose one-count over the
// 64 units' 16,384 addresses at one site sits outside 6 sigma of n / 2 (n / 2 = 8,192, sigma 64, band 384) is a
// biased address bit (a product's low bit placed by the stride rotation reads 1/4 or 3/4: 4,096 off, 64 sigma)
let n = (ACCEPT_UNITS * ITERATIONS * LANES) as u32;
let band = 6 * ((n as f64) / 4.0).sqrt() as u32;
// the bits judged are those inside the site's era window (verify::window): under an era the top k bits of a
// narrow-window site are fixed by design (the invention lane, 8 October 2026: the first form of this test counted
// them as biased and read 0 of 256 under every drawn era); without an era every index bit is judged
let load_sites: Vec<&Instr> = p.instrs.iter().filter(|i| i.op.is_load()).collect();
let mask: u32 = (1u32 << ACCEPT_DATASET_LOG2) - 1;
for (site, bits) in acc.site_bit_ones.iter().enumerate() {
let judged = match (p.class.era, load_sites.get(site)) {
(Some(_), Some(ins)) => crate::verify::window(ins, mask, ACCEPT_DATASET_LOG2).0,
_ => mask,
};
for bit in 0..ACCEPT_DATASET_LOG2 as usize {
if (judged >> bit) & 1 == 0 {
continue;
}
let ones = bits[bit];
if ones.abs_diff(n / 2) > band {
return Err(Reject::BiasedIndexBit { site: site as u8, bit: bit as u8, ones });
}
}
}
}
for reg in 0..8 {
let bits = (acc.and_acc[reg] | !acc.or_acc[reg]).count_ones();
if bits != 0 {
@ -656,7 +812,7 @@ mod tests {
let ds = DatasetSource::from_key(p.seed, DatasetMode::ClosedForm, ACCEPT_DATASET_LOG2);
let bases = accept_base_nonces(&p.seed);
let loads = p.loads_per_hash();
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0 };
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0, site_bit_ones: Vec::new() };
let mut la = vec![0u32; LANES * loads];
let mut ones = [0u32; 64];
for (u, &b) in bases.iter().enumerate() {
@ -691,7 +847,7 @@ mod tests {
assert_eq!(p.shadow_reps(), 27);
let ds = DatasetSource::from_key(p.seed, DatasetMode::ClosedForm, ACCEPT_DATASET_LOG2);
let bases = accept_base_nonces(&p.seed);
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0 };
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0, site_bit_ones: Vec::new() };
let mut la = vec![0u32; LANES * p.loads_per_hash()];
let mut ones = [0u32; 64];
for (u, &b) in bases.iter().enumerate() {
@ -706,7 +862,7 @@ mod tests {
// and the same program with its shadow stripped hashes differently: the shadow is executed, not skipped
let mut bare = p.clone();
bare.shadow.clear();
let mut acc2 = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0 };
let mut acc2 = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0, site_bit_ones: Vec::new() };
for (u, &b) in bases.iter().enumerate() {
let _ = run_unit(&bare, u, b, &mut acc2, &mut la);
}
@ -722,7 +878,7 @@ mod tests {
let p = candidate(&s, s.as_bytes(), 0);
let ds = DatasetSource::from_key(p.seed, DatasetMode::ClosedForm, ACCEPT_DATASET_LOG2);
let bases = accept_base_nonces(&p.seed);
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0 };
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0, site_bit_ones: Vec::new() };
let mut la = vec![0u32; LANES * p.loads_per_hash()];
let mut ones = [0u32; 64];
let mut any = false;
@ -765,7 +921,7 @@ mod tests {
let p = generate_class("igneum-genesis", LoadClass::hot(96, 4));
let words = p.hot_words();
let loads = p.loads_per_hash();
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0 };
let mut acc = Acc { sources: None, indices: None, sat_source: vec![0; 64], and_acc: [u32::MAX; 8], or_acc: [0; 8], saturated: 0, bit_ones: [0; 64], distinct_sum: 0, site_bit_ones: Vec::new() };
let mut la = vec![0u32; LANES * loads];
let mut buckets = [0u64; 16];
let mut hot_count = 0u64;

146
igneum-pow/src/emit.rs
View file

@ -364,8 +364,8 @@ fn shadow_instr_line(dialect: CoreDialect, ins: &Instr) -> String {
/// iteration loop, after the program's last instruction: `reps` passes over the block with the iteration's `sel`.
/// Empty for every program without a shadow, so the pinned v2 and v3 packs do not change by a byte.
fn shadow_block(p: &Program, dialect: CoreDialect) -> String {
if !p.has_shadow() {
return String::new();
if !p.has_shadow() || p.shadow_per_load() {
return tile_block(p, dialect);
}
let reps = p.shadow_reps();
let mut s = String::with_capacity(64 * p.shadow.len() + 200);
@ -379,9 +379,92 @@ fn shadow_block(p: &Program, dialect: CoreDialect) -> String {
s.push_str(&format!(" {} // s{k} {}\n", shadow_instr_line(dialect, ins), ins.op.name()));
}
s.push_str(" }\n");
s.push_str(&tile_block(p, dialect));
s
}
/// Counter ASIC 4.0 research (experimental, `docs/analysis/counter-asic-4-research.md` section 16): sub-block `j` of a
/// per-load shadow, emitted right after the `j`-th load line, `reps` passes with the iteration's `sel`. Empty for every
/// program whose shadow is not placed per load, so no pinned pack changes.
fn shadow_sub_block(p: &Program, dialect: CoreDialect, j: usize) -> String {
if !p.shadow_per_load() {
return String::new();
}
let reps = p.shadow_reps();
let sub = p.shadow_sub_block(j);
let n = sub.len();
let mut s = String::with_capacity(64 * n + 120);
let ty = if dialect == CoreDialect::Cuda { "uint32_t" } else { "uint" };
s.push_str(&format!(" // per-load shadow sub-block {j} (Counter ASIC 4.0 research): {n} ALU instructions x {reps} passes after load {j}\n"));
s.push_str(&format!(" for ({ty} sh{j} = 0u; sh{j} < {reps}u; ++sh{j}) {{\n"));
for (k, ins) in sub.iter().enumerate() {
s.push_str(&format!(" {} // s{} {}\n", shadow_instr_line(dialect, ins), j * n + k, ins.op.name()));
}
s.push_str(" }\n");
s
}
/// Counter ASIC 4.0 research (experimental, section 15.2): the int8 tile block after the shadow, once per iteration.
/// CUDA runs the PTX `mma.m8n8k16 u8` tile natively (the form bit-exact on the 4090 and 5090, `proto-newpow/mma-shadow`);
/// Metal and OpenCL run the shuffle-and-byte-product reference (`mm8_ref`, emitted by [`tile_prelude`]). Both outputs
/// are added after both are computed, so `c` may equal `a` or `b`. Empty without tiles, so no pinned pack changes.
fn tile_block(p: &Program, dialect: CoreDialect) -> String {
if !p.has_tiles() {
return String::new();
}
let mut s = String::with_capacity(160 * p.tiles.len() + 200);
s.push_str(&format!(" // int8 tile block (Counter ASIC 4.0 research, experimental): {} mma.m8n8k16 u8 tiles per iteration, both outputs consumed\n", p.tiles.len()));
for (k, d) in p.tiles.iter().enumerate() {
let (a, b, c, c2) = (format!("r{}", d[0]), format!("r{}", d[1]), format!("r{}", d[2]), format!("r{}", d[3]));
let line = match dialect {
CoreDialect::Cuda => format!(
"{{ uint32_t d0_, d1_; asm volatile(\"mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {{%0,%1}}, {{%2}}, {{%3}}, {{%4,%5}};\" : \"=r\"(d0_), \"=r\"(d1_) : \"r\"({a}), \"r\"({b}), \"r\"(0u), \"r\"(0u)); {c} += d0_; {c2} += d1_; }}"
),
CoreDialect::Metal => format!("{{ uint d0_, d1_; mm8_ref({a}, {b}, lane, d0_, d1_); {c} += d0_; {c2} += d1_; }}"),
CoreDialect::OpenCl => format!("{{ uint d0_, d1_; IGNEUM_MM8_REF({a}, {b}, d0_, d1_); {c} += d0_; {c2} += d1_; }}"),
};
s.push_str(&format!(" {line} // t{k} mm8 a=r{} b=r{} c=r{} c2=r{}\n", d[0], d[1], d[2], d[3]));
}
s
}
/// The reference tile for the dialects without a native int8 tile (Metal: a function; OpenCL: a macro, because the
/// local-memory exchange needs the kernel's own `xch`, `lid` and `xk`). Empty without tiles.
fn tile_prelude(p: &Program, dialect: CoreDialect) -> String {
if !p.has_tiles() {
return String::new();
}
match dialect {
CoreDialect::Cuda => String::new(),
CoreDialect::Metal => "// int8 tile reference (Counter ASIC 4.0 research): A = the 32 lanes' av as 8 x 16 bytes (lane l holds row l >> 2, bytes 4 (l & 3)..),
// B = bv as 16 x 8 (lane l holds column l >> 2); lane l gets C[l >> 2][2 (l & 3)] and C[l >> 2][2 (l & 3) + 1]; the PTX mma.m8n8k16 u8 layout.
static inline void mm8_ref(uint av, uint bv, uint lane, thread uint& d0, thread uint& d1) {
uint row = lane >> 2, col0 = 2u * (lane & 3u);
uint acc0 = 0u, acc1 = 0u;
for (uint j = 0u; j < 4u; ++j) {
uint aw = simd_shuffle(av, (ushort)(4u * row + j));
uint bw0 = simd_shuffle(bv, (ushort)(4u * col0 + j));
uint bw1 = simd_shuffle(bv, (ushort)(4u * (col0 + 1u) + j));
for (uint t = 0u; t < 4u; ++t) {
uint ab = (aw >> (8u * t)) & 0xffu;
acc0 += ab * ((bw0 >> (8u * t)) & 0xffu);
acc1 += ab * ((bw1 >> (8u * t)) & 0xffu);
}
}
d0 = acc0; d1 = acc1;
}
".to_string(),
CoreDialect::OpenCl => "// int8 tile reference (Counter ASIC 4.0 research): 12 index shuffles and 32 byte products per lane; the PTX mma.m8n8k16 u8 layout.
#define IGNEUM_MM8_REF(av, bv, d0, d1) { uint row_ = lane >> 2, col0_ = 2u * (lane & 3u); uint acc0_ = 0u, acc1_ = 0u; \
for (uint j_ = 0u; j_ < 4u; ++j_) { uint aw_, bw0_, bw1_; IGNEUM_SHFL_IDX(aw_, (av), 4u * row_ + j_); IGNEUM_SHFL_IDX(bw0_, (bv), 4u * col0_ + j_); IGNEUM_SHFL_IDX(bw1_, (bv), 4u * (col0_ + 1u) + j_); \
for (uint t_ = 0u; t_ < 4u; ++t_) { uint ab_ = (aw_ >> (8u * t_)) & 0xffu; acc0_ += ab_ * ((bw0_ >> (8u * t_)) & 0xffu); acc1_ += ab_ * ((bw1_ >> (8u * t_)) & 0xffu); } } \
d0 = acc0_; d1 = acc1_; }
".to_string(),
}
}
/// The shadow lines of program.h (empty without a shadow).
fn shadow_header_lines(p: &Program) -> String {
let Some(sh) = p.class.shadow else { return String::new() };
@ -393,6 +476,15 @@ fn shadow_header_lines(p: &Program) -> String {
s.push_str(&format!("#define IGNEUM_SHADOW_REPS {}\n", sh.reps));
s.push_str(&format!("#define IGNEUM_SHADOW_INSTRS_PER_HASH {}\n", p.shadow_instrs_per_hash()));
s.push_str(&format!("#define IGNEUM_SHADOW_OP_MIX {}\n", jstr(&p.shadow_op_mix())));
if sh.per_load {
s.push_str("// Counter ASIC 4.0 research (experimental): the block is placed per load, sub-block j (instrs / 16) after the j-th load.\n");
s.push_str("#define IGNEUM_SHADOW_PER_LOAD 1\n");
}
if sh.tiles > 0 {
s.push_str("// Counter ASIC 4.0 research (experimental): IGNEUM_MM8_TILES int8 mma.m8n8k16 u8 tiles per iteration after the shadow block.\n");
s.push_str(&format!("#define IGNEUM_MM8_TILES {}\n", sh.tiles));
s.push_str(&format!("#define IGNEUM_MM8_TILES_PER_HASH {}\n", p.tiles_per_hash()));
}
s
}
@ -810,6 +902,7 @@ fn metal_program_impl(p: &Program, dataset_log2: u32, source: LoadSource, bound:
let mut s = String::with_capacity(5000);
s.push_str("#include <metal_stdlib>\n");
s.push_str("using namespace metal;\n");
s.push_str(&tile_prelude(p, CoreDialect::Metal));
s.push('\n');
s.push_str(&format!("#define MASK {}\n", hex(mask)));
s.push_str(&hot_define(p));
@ -864,7 +957,7 @@ fn metal_program_impl(p: &Program, dataset_log2: u32, source: LoadSource, bound:
}
s.push_str(" uint nonce = baseNonce + gid;\n");
s.push_str(" uint r0, r1, r2, r3, r4, r5, r6, r7;\n");
if p.has_wide() {
if p.has_wide() || p.has_tiles() {
s.push_str(" uint lane = gid & 31u;\n");
}
let iw = if bound { "initw" } else { "SEEDW" };
@ -891,6 +984,7 @@ fn metal_program_impl(p: &Program, dataset_log2: u32, source: LoadSource, bound:
LoadSource::InlineMemhard(_) => format!("mh_word(cache, {idx})"),
}
};
let mut load_j = 0usize;
for (k, ins) in p.instrs.iter().enumerate() {
let d = format!("r{}", ins.dst);
let a = format!("r{}", ins.src);
@ -925,6 +1019,10 @@ fn metal_program_impl(p: &Program, dataset_log2: u32, source: LoadSource, bound:
Op::Hot => hot_stmt(CoreDialect::Metal, &d, &a),
};
s.push_str(&format!(" {line} // {k}\n"));
if p.shadow_per_load() && ins.op.is_load() {
s.push_str(&shadow_sub_block(p, CoreDialect::Metal, load_j));
load_j += 1;
}
}
s.push_str(&shadow_block(p, CoreDialect::Metal));
s.push_str(" }\n");
@ -965,6 +1063,7 @@ fn init_line(p: &Program, u: &str, i: usize) -> String {
fn cuda_instr_lines(p: &Program, dataset_log2: u32) -> String {
let mut s = String::with_capacity(6000);
let era = p.class.era;
let mut load_j = 0usize;
for (k, ins) in p.instrs.iter().enumerate() {
let d = format!("r{}", ins.dst);
let a = format!("r{}", ins.src);
@ -995,6 +1094,10 @@ fn cuda_instr_lines(p: &Program, dataset_log2: u32) -> String {
Op::Hot => hot_stmt(CoreDialect::Cuda, &d, &a),
};
s.push_str(&format!(" {line} // {k} {}\n", ins.op.name()));
if p.shadow_per_load() && ins.op.is_load() {
s.push_str(&shadow_sub_block(p, CoreDialect::Cuda, load_j));
load_j += 1;
}
}
s
}
@ -1288,6 +1391,7 @@ pub fn cuda_kernel_bound_at(p: &Program, memhard: Option<&MixParams>, dataset_lo
fn opencl_instr_lines(p: &Program, dataset_log2: u32) -> String {
let mut s = String::with_capacity(6000);
let era = p.class.era;
let mut load_j = 0usize;
for (k, ins) in p.instrs.iter().enumerate() {
let d = format!("r{}", ins.dst);
let a = format!("r{}", ins.src);
@ -1317,6 +1421,10 @@ fn opencl_instr_lines(p: &Program, dataset_log2: u32) -> String {
Op::Hot => hot_stmt(CoreDialect::OpenCl, &d, &a),
};
s.push_str(&format!(" {line} // {k} {}\n", ins.op.name()));
if p.shadow_per_load() && ins.op.is_load() {
s.push_str(&shadow_sub_block(p, CoreDialect::OpenCl, load_j));
load_j += 1;
}
}
s
}
@ -1368,8 +1476,11 @@ pub fn opencl_kernel_bound_at(p: &Program, memhard: Option<&MixParams>, dataset_
s.push_str(" (void)lid;\n");
s.push_str("#endif\n");
}
if p.has_wide() || p.has_tiles() {
s.push_str(" uint lane = lid & 31u;\n");
}
if p.has_wide() {
s.push_str(" uint lane = lid & 31u;\n uint wmask = mask & ~31u;\n");
s.push_str(" uint wmask = mask & ~31u;\n");
}
for i in 0..8 {
s.push_str(&format!(
@ -1431,9 +1542,15 @@ pub fn opencl_kernel_at(p: &Program, memhard: Option<&MixParams>, dataset_log2:
s.push_str("#if IGNEUM_EXCHANGE == 1\n");
s.push_str("#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))\n");
s.push_str("#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)\n");
if p.has_tiles() {
s.push_str("#define IGNEUM_SHFL_IDX(dst, a, i) dst = sub_group_shuffle((a), (uint)(i))\n");
}
s.push_str("#elif IGNEUM_EXCHANGE == 2\n");
s.push_str("#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))\n");
s.push_str("#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)\n");
if p.has_tiles() {
s.push_str("#define IGNEUM_SHFL_IDX(dst, a, i) dst = intel_sub_group_shuffle((a), (uint)(i))\n");
}
s.push_str("#else\n");
s.push_str("// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per\n");
s.push_str("// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane\n");
@ -1443,8 +1560,12 @@ pub fn opencl_kernel_at(p: &Program, memhard: Option<&MixParams>, dataset_log2:
);
s.push_str("#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }\n");
s.push_str("#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }\n");
if p.has_tiles() {
s.push_str("#define IGNEUM_SHFL_IDX(dst, a, i) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u) + (uint)(i)]; xk += 1u; }\n");
}
s.push_str("#endif\n");
s.push('\n');
s.push_str(&tile_prelude(p, CoreDialect::OpenCl));
s.push_str(&hot_define(p));
s.push_str("static inline uint splitmix32(uint x) {\n");
s.push_str(" x ^= x >> 16; x *= 0x7feb352du;\n");
@ -1530,8 +1651,11 @@ pub fn opencl_kernel_at(p: &Program, memhard: Option<&MixParams>, dataset_log2:
s.push_str(" (void)lid;\n");
s.push_str("#endif\n");
}
if p.has_wide() || p.has_tiles() {
s.push_str(" uint lane = lid & 31u;\n");
}
if p.has_wide() {
s.push_str(" uint lane = lid & 31u;\n uint wmask = mask & ~31u;\n");
s.push_str(" uint wmask = mask & ~31u;\n");
}
for i in 0..8 {
s.push_str(&init_line(p, "uint", i));
@ -2015,6 +2139,18 @@ pub fn program_json(p: &Program, day: &str, ds: &DatasetSource) -> String {
));
}
s.push_str(" ]},\n");
// Counter ASIC 4.0 research (experimental): the placement and the tile block, only when set
if sh.per_load {
s.push_str(" \"shadow_placement\": \"per_load\",\n");
}
if !p.tiles.is_empty() {
s.push_str(&format!(
" \"mm8_tiles\": {{\"tiles\": {}, \"tiles_per_hash\": {}, \"rule\": \"Counter ASIC 4.0 research (docs/analysis/counter-asic-4-research.md 15.2): after the shadow draws the stream draws tiles descriptors a, b, c (below 8 each) and c2 (below 7, skipping c); each tile is the PTX mma.m8n8k16 u8 product of the 32 lanes' r[a] (8 x 16 bytes) and r[b] (16 x 8), lane l adds C[l >> 2][2 (l & 3)] into r[c] and C[l >> 2][2 (l & 3) + 1] into r[c2] modulo 2^32; the block runs once per iteration after the shadow\", \"program_id_suffix\": \"'mm8/' || tiles_le16\", \"descriptors\": [{}]}},\n",
p.tiles.len(),
p.tiles_per_hash(),
p.tiles.iter().map(|d| format!("[{},{},{},{}]", d[0], d[1], d[2], d[3])).collect::<Vec<_>>().join(",")
));
}
}
s.push_str(" \"instructions\": [\n");
let n = p.instrs.len();

210
igneum-pow/src/generator.rs
View file

@ -201,6 +201,10 @@ pub struct Program {
/// The latency-shadow block (Counter ASIC 3.0 item 8): `class.shadow.instrs` ALU instructions, run
/// `class.shadow.reps` times at the end of every iteration. Empty for every class without a shadow.
pub shadow: Vec<Instr>,
/// Counter ASIC 4.0 research (7 October 2026, experimental, never a chain class): the int8 tile block, one
/// `[a, b, c, c2]` register descriptor per tile (`a != b` is not required; `c != c2`), run once per iteration
/// after the shadow block. Empty for every class with `shadow.tiles == 0`.
pub tiles: Vec<[u8; 4]>,
}
/// The widths a `load` may read, in words: 4, 16 and 64 bytes.
@ -379,10 +383,20 @@ pub struct HotClass {
/// hash and no load. `None` on every other class: version 2 and class v3 draw nothing and emit nothing.
#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
pub struct ShadowClass {
/// Instructions in the shadow block (1..=4096).
/// Instructions in the shadow block (1..=4096; 0 only on a tiles-only experimental class).
pub instrs: u16,
/// Times the block runs per iteration (1..=1024).
/// Times the block runs per iteration (1..=1024; 0 only on a tiles-only experimental class).
pub reps: u16,
/// Counter ASIC 4.0 research (7 October 2026, `docs/analysis/counter-asic-4-research.md` section 16, experimental,
/// never a chain class): the block is split into [`LOAD_SLOTS`] sub-blocks of `instrs / LOAD_SLOTS` consecutive
/// instructions and sub-block `j` runs `reps` times right after the `j`-th load of the base program, instead of
/// the whole block once after instruction 63. The same instructions, the same count per hash, a different
/// placement (the chip's core then sits inside every read's dependency). Name suffix `+shl<S>x<R>`.
pub per_load: bool,
/// Counter ASIC 4.0 research (section 15.2, experimental): `tiles` int8 tile steps per iteration after the shadow
/// block, each the PTX `mma.m8n8k16 u8` tile over two registers with both outputs consumed (the
/// `proto-newpow/mma-shadow` form, bit-exact on the RTX 4090 and 5090 on 6 October 2026). Name suffix `+mm<R>`.
pub tiles: u16,
}
impl ShadowClass {
@ -390,6 +404,18 @@ impl ShadowClass {
pub fn instrs_per_hash(&self) -> usize {
ITERATIONS * self.instrs as usize * self.reps as usize
}
/// The block of `instrs` run `reps` times at the end of every iteration (the class v4 shape).
pub const fn block(instrs: u16, reps: u16) -> ShadowClass {
ShadowClass { instrs, reps, per_load: false, tiles: 0 }
}
/// Instructions per per-load sub-block (0 unless `per_load`).
pub fn sub_block_len(&self) -> usize {
if self.per_load { self.instrs as usize / LOAD_SLOTS } else { 0 }
}
/// Tile steps per hash: `ITERATIONS x tiles`.
pub fn tiles_per_hash(&self) -> usize {
ITERATIONS * self.tiles as usize
}
}
/// Scratch geometry (variant 5): 16-byte slots, lane-major, 32 lanes per warp; `scratch_kb` KiB per warp gives
@ -544,7 +570,27 @@ impl LoadClass {
/// The class with a latency-shadow block of `instrs` instructions run `reps` times per iteration ("mx8+sh256x13").
pub fn with_shadow(self, instrs: u16, reps: u16) -> LoadClass {
assert!((1..=4096).contains(&instrs) && (1..=1024).contains(&reps), "shadow block: 1..=4096 instructions, 1..=1024 reps");
LoadClass { shadow: Some(ShadowClass { instrs, reps }), ..self }
LoadClass { shadow: Some(ShadowClass::block(instrs, reps)), ..self }
}
/// Counter ASIC 4.0 research (experimental): the shadow block placed per load, `instrs` a multiple of
/// [`LOAD_SLOTS`] ("mx8+shl256x27": 16 sub-blocks of 16 instructions, each run 27 times after its load).
pub fn with_shadow_per_load(self, instrs: u16, reps: u16) -> LoadClass {
assert!((1..=4096).contains(&instrs) && (1..=1024).contains(&reps) && instrs as usize % LOAD_SLOTS == 0, "per-load shadow: 16..=4096 instructions in multiples of 16, 1..=1024 reps");
LoadClass { shadow: Some(ShadowClass { instrs, reps, per_load: true, tiles: 0 }), ..self }
}
/// Counter ASIC 4.0 research (experimental): `tiles` int8 tile steps per iteration over this class (with or
/// without a shadow block; "mx8+mm512", "mx8+sh256x27+mm128").
pub fn with_tiles(self, tiles: u16) -> LoadClass {
assert!((1..=4096).contains(&tiles), "tile block: 1..=4096 tiles per iteration");
let sh = self.shadow.unwrap_or(ShadowClass { instrs: 0, reps: 0, per_load: false, tiles: 0 });
LoadClass { shadow: Some(ShadowClass { tiles, ..sh }), ..self }
}
/// Tile steps per hash (0 without a tile block).
pub fn tiles_per_hash(&self) -> usize {
self.shadow.map(|s| s.tiles_per_hash()).unwrap_or(0)
}
/// Shadow instructions per hash (0 without a shadow).
@ -578,6 +624,23 @@ impl LoadClass {
/// "mx4": the v3 construction; a trailing "m<mult>" and "g" set the mixer multiplier and the growth rule on any
/// load class, "w16m4g" for example).
pub fn parse(s: &str) -> Option<LoadClass> {
// "<class>+mm<tiles>": the int8 tile block over any class (Counter ASIC 4.0 research, experimental)
if let Some((base, t)) = s.rsplit_once("+mm") {
let tiles: u16 = t.parse().ok()?;
if !(1..=4096).contains(&tiles) {
return None;
}
return Some(LoadClass::parse(base)?.with_tiles(tiles));
}
// "<class>+shl<instrs>x<reps>": the shadow block placed per load (Counter ASIC 4.0 research, experimental)
if let Some((base, sh)) = s.rsplit_once("+shl") {
let (instrs, reps) = sh.split_once('x')?;
let (instrs, reps): (u16, u16) = (instrs.parse().ok()?, reps.parse().ok()?);
if !(1..=4096).contains(&instrs) || !(1..=1024).contains(&reps) || instrs as usize % LOAD_SLOTS != 0 {
return None;
}
return Some(LoadClass::parse(base)?.with_shadow_per_load(instrs, reps));
}
// "<class>+sh<instrs>x<reps>": the latency-shadow block over any class (Counter ASIC 3.0 item 8)
if let Some((base, sh)) = s.rsplit_once("+sh") {
let (instrs, reps) = sh.split_once('x')?;
@ -702,8 +765,14 @@ impl LoadClass {
/// A hot class appends "hot<S>k<k>[a]" ("hot64k4", "scr4k32+hot64k4a"; measured and not adopted).
pub fn name(&self) -> String {
if let Some(sh) = self.shadow {
// "<class>+sh<instrs>x<reps>": the shadow block is a suffix on any class ("mx8+sh256x13")
return format!("{}+sh{}x{}", LoadClass { shadow: None, ..*self }.name(), sh.instrs, sh.reps);
// "<class>+sh<instrs>x<reps>": the shadow block is a suffix on any class ("mx8+sh256x13"); "+shl" when it
// is placed per load and "+mm<tiles>" after it for the tile block (Counter ASIC 4.0 research, experimental)
let base = LoadClass { shadow: None, ..*self }.name();
let mut n = if sh.instrs > 0 { format!("{base}+sh{}{}x{}", if sh.per_load { "l" } else { "" }, sh.instrs, sh.reps) } else { base };
if sh.tiles > 0 {
n.push_str(&format!("+mm{}", sh.tiles));
}
return n;
}
if let Some(e) = self.era {
let base = LoadClass { era: None, ..*self };
@ -821,7 +890,7 @@ pub const V3_CLASS: LoadClass = LoadClass { era: None, hot: None, ..LoadClass::M
/// of 256 ALU instructions run 27 times per iteration ("mx8+sh256x27", 55,296 shadow instructions per hash). The
/// base program, the 16 loads, the item construction, the cache growth rule and the era draw are class v3's, draw
/// for draw, so a v4 epoch's day cache and dataset are the v3 day's. Composed with the era exactly as V3 is.
pub const V4_CLASS: LoadClass = LoadClass { shadow: Some(ShadowClass { instrs: V4_SHADOW_INSTRS, reps: V4_SHADOW_REPS }), ..V3_CLASS };
pub const V4_CLASS: LoadClass = LoadClass { shadow: Some(ShadowClass::block(V4_SHADOW_INSTRS, V4_SHADOW_REPS)), ..V3_CLASS };
/// The shadow block size of class v4 at every rung of the latency ladder (`docs/design/latency-ladder.md`): 256
/// instructions. The ladder moves the pass count alone.
@ -837,7 +906,7 @@ pub fn v4_class_at(reps: u16) -> LoadClass {
if reps == 0 {
V4_CLASS
} else {
LoadClass { shadow: Some(ShadowClass { instrs: V4_SHADOW_INSTRS, reps }), ..V3_CLASS }
LoadClass { shadow: Some(ShadowClass::block(V4_SHADOW_INSTRS, reps)), ..V3_CLASS }
}
}
@ -846,7 +915,7 @@ pub fn v4_class_at(reps: u16) -> LoadClass {
pub fn v4_rung_reps(class: &LoadClass) -> Option<u16> {
let base = LoadClass { era: None, ..*class };
match base.shadow {
Some(ShadowClass { instrs: V4_SHADOW_INSTRS, reps }) if LoadClass { shadow: None, ..base } == V3_CLASS => Some(reps),
Some(ShadowClass { instrs: V4_SHADOW_INSTRS, reps, per_load: false, tiles: 0 }) if LoadClass { shadow: None, ..base } == V3_CLASS => Some(reps),
_ => None,
}
}
@ -996,6 +1065,26 @@ impl Program {
pub fn has_shadow(&self) -> bool {
self.class.shadow.is_some() && !self.shadow.is_empty()
}
/// Whether the shadow block is placed per load (Counter ASIC 4.0 research, experimental).
pub fn shadow_per_load(&self) -> bool {
self.has_shadow() && self.class.shadow.map(|s| s.per_load).unwrap_or(false)
}
/// The `j`-th per-load sub-block of the shadow (empty unless placed per load).
pub fn shadow_sub_block(&self, j: usize) -> &[Instr] {
if !self.shadow_per_load() {
return &[];
}
let n = self.class.shadow.map(|s| s.sub_block_len()).unwrap_or(0);
&self.shadow[j * n..(j + 1) * n]
}
/// Whether the program carries an int8 tile block (Counter ASIC 4.0 research, experimental).
pub fn has_tiles(&self) -> bool {
!self.tiles.is_empty()
}
/// Tile steps per hash: `ITERATIONS x tiles`.
pub fn tiles_per_hash(&self) -> usize {
self.tiles.len() * ITERATIONS
}
/// Times the shadow block runs per iteration (0 without one).
pub fn shadow_reps(&self) -> usize {
self.class.shadow.map(|s| s.reps as usize).unwrap_or(0)
@ -1206,6 +1295,15 @@ pub fn program_id_class_recipe(generator: u32, seed: &[u32; 8], attempt: u32, cl
r.lit(b"shadow/");
r.field(&sh.instrs.to_le_bytes(), "shadow_instrs_le16");
r.field(&sh.reps.to_le_bytes(), "shadow_reps_le16");
// Counter ASIC 4.0 research (experimental): the placement and the tile block are part of the construction;
// nothing is appended for the class v4 shape, so every v4 id stands
if sh.per_load {
r.lit(b"perload");
}
if sh.tiles > 0 {
r.lit(b"mm8/");
r.field(&sh.tiles.to_le_bytes(), "mm8_tiles_le16");
}
}
if let Some(h) = class.hot {
r.lit(b"hot/");
@ -1427,7 +1525,14 @@ pub fn candidate_from_words_class(
// the era windows included when the class takes them, drawn and ignored) so the stream shape is the program's.
let mut shadow = Vec::new();
if let Some(sh) = class.shadow {
for _ in 0..sh.instrs {
// Counter ASIC 4.0 research (the per-load placement, 7 October 2026, 22:3x UTC): the source register of every
// load in program order, so a per-load sub-block can refuse a lossy writer of the NEXT load's source. Found by
// the trace of the first export (tests/ca4_trace.rs): sub-blocks whose last writer of the next load's source was
// `mul` (a 27-pass `d = d * a` with an even `a` clears the low bits) made 11 to 12 percent of a warp's reads land
// on one item (10,728 distinct of 12,288 over three units; sites 8, 10 and 15; shuffles and rotates were clean).
let load_srcs: Vec<usize> = instrs.iter().filter(|i| i.op.is_load()).map(|i| i.src as usize).collect();
let sub_len = sh.sub_block_len();
for k in 0..sh.instrs as usize {
let mut roll = rng.below(75);
let mut op = Op::Add;
for &(o, w) in &NONLOAD_WEIGHTS {
@ -1438,6 +1543,24 @@ pub fn candidate_from_words_class(
roll -= w;
}
let dst = rng.below(8);
if sh.per_load && sub_len > 0 && !load_srcs.is_empty() {
// the rule: a sub-block instruction that writes the next load's source register is drawn from the
// non-product injecting families only (add, sub, xor, shfl); mul, mulhi, or and mad are redrawn (the biased-product-bit class of 22:3x UTC) from
// the injecting table (sub-version 3's source rule applied to the order this class executes)
let j = k / sub_len;
let next_src = load_srcs[(j + 1) % load_srcs.len()];
if dst as usize == next_src && matches!(op, Op::Mul | Op::MulHi | Op::Or | Op::Mad) {
let inj: [(Op, u64); 4] = [(Op::Add, 12), (Op::Sub, 6), (Op::Xor, 10), (Op::Shfl, 8)];
let mut r2 = rng.below(36);
for &(o, w) in &inj {
if r2 < w {
op = o;
break;
}
r2 -= w;
}
}
}
let a = rng.below(7);
let src = if a >= dst { a + 1 } else { a };
let b = rng.below(8);
@ -1456,6 +1579,20 @@ pub fn candidate_from_words_class(
shadow.push(Instr { op, dst: dst as u8, src: src as u8, src2: b as u8, imm, imm2, rot, bit: bit as u8, mask, width: 1, win: 0, off: 0 });
}
}
// (4) Counter ASIC 4.0 research (experimental): the tile descriptors, drawn after the shadow block from the same
// stream: a = below(8), b = below(8), c = below(8), c2 = below(7) skipping c (both outputs land in different
// registers, so every tile is load-bearing; the proto-newpow/mma-shadow form).
let mut tiles = Vec::new();
if let Some(sh) = class.shadow {
for _ in 0..sh.tiles {
let a = rng.below(8) as u8;
let b = rng.below(8) as u8;
let c = rng.below(8) as u8;
let c2r = rng.below(7) as u8;
let c2 = if c2r >= c { c2r + 1 } else { c2r };
tiles.push([a, b, c, c2]);
}
}
Program {
seed_string: seed_string.to_string(),
seed_bytes: seed_bytes.to_vec(),
@ -1466,6 +1603,7 @@ pub fn candidate_from_words_class(
era_bytes: None,
instrs,
shadow,
tiles,
}
}
@ -1709,6 +1847,7 @@ pub fn generate_v1_from_words(seed_string: &str, seed: [u32; 8], cfg: &Generator
era_bytes: None,
instrs,
shadow: Vec::new(),
tiles: Vec::new(),
}
}
@ -2516,3 +2655,56 @@ mod tests {
assert_eq!(e.width_words, 1);
}
}
#[cfg(test)]
mod ca4_tests {
//! Counter ASIC 4.0 research (experimental classes): the names, the ids and the draws of the per-load shadow and the tile block.
use super::*;
#[test]
fn per_load_and_tile_classes_parse_name_and_differ_in_id_from_class_v4_shapes() {
let v4 = LoadClass::parse("mx8+sh256x27").unwrap();
let pl = LoadClass::parse("mx8+shl256x27").unwrap();
let mm = LoadClass::parse("mx8+mm512").unwrap();
let both = LoadClass::parse("mx8+sh256x27+mm128").unwrap();
assert_eq!(pl.name(), "mx8+shl256x27");
assert_eq!(mm.name(), "mx8+mm512");
assert_eq!(both.name(), "mx8+sh256x27+mm128");
assert!(pl.shadow.unwrap().per_load && pl.shadow.unwrap().sub_block_len() == 16);
assert_eq!(mm.shadow.unwrap().instrs, 0);
assert!(LoadClass::parse("mx8+shl250x27").is_none(), "a per-load block is a multiple of 16");
assert_eq!(V4_CLASS.name(), "mx8+sh256x27", "the class v4 name is unchanged");
let seed = b"igneum-genesis";
let p4 = generate_from_seed_bytes_class("t", seed, v4);
// the per-load 16 x 27 construction is refused by the acceptance rule on every attempt once the rule steps the
// sub-blocks in execution order (22:4x UTC, tests/ca4_trace.rs): its candidates are read, never accepted
let pl_attempts = attempts_class("t", seed, pl);
assert!(pl_attempts.len() > 8, "the per-load class accepts 1.4 percent of candidates (22:4x UTC); seed t took {} attempts", pl_attempts.len());
let pp = pl_attempts[0].0.clone();
let pm = generate_from_seed_bytes_class("t", seed, mm);
let pb = generate_from_seed_bytes_class("t", seed, both);
// the per-load class takes the dynamic acceptance test in its own execution order (accept.rs DuplicateLanes),
// so a candidate the class v4 shape accepts may be rejected here and the accepted program is a later attempt;
// when the attempt is the same the base program is the class v4 shape's draw for draw
if pp.attempt == p4.attempt {
assert_eq!(p4.instrs, pp.instrs, "the base program is the class's without the shadow, draw for draw");
}
assert_eq!(p4.shadow.len(), pp.shadow.len(), "the per-load shadow holds a block of the same size");
assert!(p4.tiles.is_empty() && pp.tiles.is_empty());
assert_eq!(pm.tiles.len(), 512);
assert_eq!(pb.tiles.len(), 128);
assert_eq!(pb.shadow, p4.shadow, "the tile draws come after the shadow draws");
assert!(pm.tiles.iter().all(|d| d[2] != d[3] && d.iter().all(|&x| x < 8)));
let ids = [p4.program_id(), pp.program_id(), pm.program_id(), pb.program_id()];
for i in 0..4 {
for j in 0..4 {
if i != j {
assert_ne!(ids[i], ids[j], "ids {i} {j}");
}
}
}
for j in 0..LOAD_SLOTS {
assert_eq!(pp.shadow_sub_block(j), &pp.shadow[16 * j..16 * j + 16]);
}
}
}

1
igneum-pow/src/lib.rs
View file

@ -28,6 +28,7 @@ pub mod derive;
pub mod emit;
pub mod generator;
pub mod memhard;
pub mod mm8;
pub mod packcheck;
pub mod seed;
pub mod verify;

179
igneum-pow/src/mm8.rs Normal file
View file

@ -0,0 +1,179 @@
//! Counter ASIC 4.0 research (7 October 2026, `docs/analysis/counter-asic-4-research.md` section 15.2; experimental,
//! never a chain class): the int8 tile step on a warp's register file, the CPU side of the PTX `mma.m8n8k16 u8` tile
//! as `proto-newpow/mma-shadow` defined it (bit-exact against the RTX 4090 and 5090 on 6 October 2026).
//!
//! The tile: `A` is the 32 lanes' `r[a]` read as an 8 x 16 matrix of bytes (lane `l` holds row `l >> 2`, bytes
//! `4 (l & 3) .. 4 (l & 3) + 3`, byte 0 the lowest), `B` the 32 lanes' `r[b]` as 16 x 8 (lane `l` holds column
//! `l >> 2`, rows `4 (l & 3) ..`), `C = A x B` exact in 32-bit arithmetic (at most 16 x 255 x 255), and lane `l`
//! adds `C[l >> 2][2 (l & 3)]` into `r[c]` and `C[l >> 2][2 (l & 3) + 1]` into `r[c2]` modulo 2^32, both outputs
//! consumed. The scalar form is the reference; the AVX2 form (x86-64, detected at run time) computes the same 64 dot
//! products with `maddubs` on a 4-way split of `B` (`B = 4 (B >> 2) + (B & 3)`, so no 16-bit lane saturates) and is
//! checked against the scalar form by the unit test below.
use crate::generator::LANES;
/// One tile step on the register file: `r[c] += C[row][col0]`, `r[c2] += C[row][col0 + 1]` per lane.
pub fn tile_step(r: &mut [[u32; LANES]; 8], d: [u8; 4]) {
let (a, b, c, c2) = (d[0] as usize, d[1] as usize, d[2] as usize, d[3] as usize);
let av = r[a];
let bv = r[b];
let mut cm = [[0u32; 8]; 8];
product(&av, &bv, &mut cm);
for l in 0..LANES {
let row = l >> 2;
let col0 = 2 * (l & 3);
r[c][l] = r[c][l].wrapping_add(cm[row][col0]);
r[c2][l] = r[c2][l].wrapping_add(cm[row][col0 + 1]);
}
}
/// `C = A x B` for the tile's layouts, into `cm[row][col]`.
pub fn product(av: &[u32; LANES], bv: &[u32; LANES], cm: &mut [[u32; 8]; 8]) {
#[cfg(target_arch = "x86_64")]
{
if avx2_available() {
// SAFETY: the feature was detected at run time.
unsafe { product_avx2(av, bv, cm) };
return;
}
}
product_scalar(av, bv, cm);
}
/// The reference: 64 dot products of 16 bytes in plain integer code.
pub fn product_scalar(av: &[u32; LANES], bv: &[u32; LANES], cm: &mut [[u32; 8]; 8]) {
for row in 0..8 {
for col in 0..8 {
let mut acc = 0u32;
for k in 0..16 {
let ab = (av[row * 4 + k / 4] >> (8 * (k % 4))) & 0xff;
let bb = (bv[col * 4 + k / 4] >> (8 * (k % 4))) & 0xff;
acc = acc.wrapping_add(ab * bb);
}
cm[row][col] = acc;
}
}
}
#[cfg(target_arch = "x86_64")]
fn avx2_available() -> bool {
use std::sync::atomic::{AtomicU8, Ordering};
static STATE: AtomicU8 = AtomicU8::new(0);
match STATE.load(Ordering::Relaxed) {
1 => true,
2 => false,
_ => {
// IGNEUM_MM8_SCALAR=1 forces the reference path (for the bench's scalar row)
let yes = std::is_x86_feature_detected!("avx2") && std::env::var_os("IGNEUM_MM8_SCALAR").is_none();
STATE.store(if yes { 1 } else { 2 }, Ordering::Relaxed);
yes
}
}
}
/// Whether the SIMD path is in use on this machine (for the bench's report line).
pub fn simd_path() -> &'static str {
#[cfg(target_arch = "x86_64")]
{
if avx2_available() {
return "avx2";
}
}
"scalar"
}
#[cfg(target_arch = "x86_64")]
#[target_feature(enable = "avx2")]
unsafe fn product_avx2(av: &[u32; LANES], bv: &[u32; LANES], cm: &mut [[u32; 8]; 8]) {
use std::arch::x86_64::*;
let a_bytes = av.as_ptr() as *const u8;
let b_bytes = bv.as_ptr() as *const u8;
let ones = _mm256_set1_epi16(1);
let m3 = _mm256_set1_epi8(3);
let m63 = _mm256_set1_epi8(63);
for row in 0..8 {
// the row's 16 bytes in both 128-bit halves
let ar = _mm_loadu_si128(a_bytes.add(16 * row) as *const __m128i);
let a2 = _mm256_broadcastsi128_si256(ar);
for colp in 0..4 {
// columns 2 colp and 2 colp + 1: 32 contiguous bytes of B
let b2 = _mm256_loadu_si256(b_bytes.add(32 * colp) as *const __m256i);
let bq = _mm256_and_si256(_mm256_srli_epi16(b2, 2), m63); // B >> 2 per byte (0..63)
let br = _mm256_and_si256(b2, m3); // B & 3
// u8 x s8 pairs summed to i16: at most 2 x 255 x 63 = 32,130, no saturation
let pq = _mm256_maddubs_epi16(a2, bq);
let pr = _mm256_maddubs_epi16(a2, br);
let sq = _mm256_madd_epi16(pq, ones); // 8 x i32: 4 per column
let sr = _mm256_madd_epi16(pr, ones);
let s = _mm256_add_epi32(_mm256_slli_epi32(sq, 2), sr);
let mut t = [0i32; 8];
_mm256_storeu_si256(t.as_mut_ptr() as *mut __m256i, s);
let c0 = (t[0] as u32).wrapping_add(t[1] as u32).wrapping_add(t[2] as u32).wrapping_add(t[3] as u32);
let c1 = (t[4] as u32).wrapping_add(t[5] as u32).wrapping_add(t[6] as u32).wrapping_add(t[7] as u32);
cm[row][2 * colp] = c0;
cm[row][2 * colp + 1] = c1;
}
}
}
#[cfg(test)]
mod tests {
use super::*;
fn mix(mut x: u32) -> u32 {
x ^= x >> 16;
x = x.wrapping_mul(0x7feb352d);
x ^= x >> 15;
x = x.wrapping_mul(0x846ca68b);
x ^= x >> 16;
x
}
#[test]
fn simd_product_equals_the_scalar_reference() {
for seed in 0..64u32 {
let mut av = [0u32; LANES];
let mut bv = [0u32; LANES];
for l in 0..LANES {
av[l] = mix(seed * 97 + l as u32);
bv[l] = mix(seed * 131 + 1000 + l as u32);
}
// the saturation edge: all-ones bytes everywhere
if seed == 63 {
av = [0xffff_ffff; LANES];
bv = [0xffff_ffff; LANES];
}
let mut c1 = [[0u32; 8]; 8];
let mut c2 = [[0u32; 8]; 8];
product_scalar(&av, &bv, &mut c1);
product(&av, &bv, &mut c2);
assert_eq!(c1, c2, "seed {seed}, path {}", simd_path());
if seed == 63 {
assert_eq!(c1[0][0], 16 * 255 * 255);
}
}
}
#[test]
fn a_tile_step_adds_both_outputs_and_a_zero_operand_adds_nothing() {
let mut r = [[0u32; LANES]; 8];
for l in 0..LANES {
r[1][l] = mix(l as u32 + 7);
r[2][l] = mix(l as u32 + 99);
r[3][l] = 5;
r[4][l] = 9;
}
let before = r;
tile_step(&mut r, [1, 2, 3, 4]);
assert!(r[3] != before[3] && r[4] != before[4]);
let mut cm = [[0u32; 8]; 8];
product_scalar(&before[1], &before[2], &mut cm);
for l in 0..LANES {
assert_eq!(r[3][l], 5u32.wrapping_add(cm[l >> 2][2 * (l & 3)]));
assert_eq!(r[4][l], 9u32.wrapping_add(cm[l >> 2][2 * (l & 3) + 1]));
}
let mut z = before;
tile_step(&mut z, [0, 2, 3, 4]); // r[0] is all zero: C is zero
assert_eq!(z, before);
}
}

80
igneum-pow/src/verify.rs
View file

@ -329,6 +329,62 @@ pub fn interpret_warp_init(program: &Program, seed: &[u32; 8], base_nonce: u32,
interpret_warp_scratch(program, seed, base_nonce, ds, false).0
}
/// Counter ASIC 4.0 research (diagnostic, experimental classes): the dataset index every lane reads at every load of
/// the unit, in execution order (`ITERATIONS x loads` rows of 32), so a test can count duplicates within a warp per load
/// site and across iterations. Runs the program exactly as [`interpret_warp_init`] does (the per-load sub-blocks and the
/// tile block included); scratch and hot classes are not traced here.
pub fn trace_load_indices(program: &Program, seed: &[u32; 8], base_nonce: u32, ds: &DatasetSource) -> Vec<[u32; LANES]> {
assert!(!program.has_scratch() && !program.has_hot(), "trace_load_indices: ALU, load, shadow and tile programs only");
let mask = ds.mask;
let log2 = ds.log2_words;
let era = program.class.era;
let layout = program.class.layout();
let mut r = [[0u32; LANES]; 8];
for lane in 0..LANES {
let nonce = base_nonce.wrapping_add(lane as u32);
for i in 0..8 {
let mut x = nonce ^ seed[i];
x = x.wrapping_add(0x9e3779b9u32.wrapping_mul(i as u32 + 1));
x = splitmix32(x);
r[i][lane] = x ^ seed[(i + 1) & 7];
}
}
let mut items_derived = 0usize;
let mut idx = [0u32; LANES];
let mut val = [0u32; LANES];
let mut out = Vec::new();
let per_load = program.shadow_per_load();
for _ in 0..ITERATIONS {
let sel = r[0];
let mut load_j = 0usize;
for ins in &program.instrs {
step(ins, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
if ins.op.is_load() {
out.push(idx);
if per_load {
for _ in 0..program.shadow_reps() {
for sh in program.shadow_sub_block(load_j) {
step(sh, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
}
}
load_j += 1;
}
}
}
if !per_load {
for _ in 0..program.shadow_reps() {
for ins in &program.shadow {
step(ins, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
}
}
}
for d in &program.tiles {
crate::mm8::tile_step(&mut r, *d);
}
}
out
}
/// [`interpret_warp_init`] that also returns every scratch read-modify-write of the unit in execution order
/// (lane-minor within an instruction, as the interpreter runs them) when `trace` is set; empty otherwise and for
/// a class without a scratch. For the soundness tests of variant 5 only.
@ -367,10 +423,22 @@ pub fn interpret_warp_scratch(
let h = ds.hot.as_ref().expect("a hot-table program needs the epoch's hot table on the dataset source");
assert_eq!(h.n_words(), program.hot_words(), "the hot table's size is the class's");
}
let per_load = program.shadow_per_load();
for _ in 0..ITERATIONS {
let sel = r[0];
let mut load_j = 0usize;
for ins in &program.instrs {
step(ins, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
// Counter ASIC 4.0 research (experimental): the shadow placed per load runs sub-block j right after the
// j-th load, `reps` times, with the iteration's `sel`
if per_load && ins.op.is_load() {
for _ in 0..program.shadow_reps() {
for sh in program.shadow_sub_block(load_j) {
step(sh, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
}
}
load_j += 1;
}
if ins.op == Op::Scratch {
let m = scratch.as_mut().expect("a scratch op needs a scratch class");
let (d, a) = (ins.dst as usize, ins.src as usize);
@ -382,11 +450,17 @@ pub fn interpret_warp_scratch(
}
// Latency-shadow block (Counter ASIC 3.0 item 8): the block runs `reps` times after instruction 63 with the
// iteration's `sel`; it is empty on every class without a shadow, so version 2 and class v3 run nothing here.
for _ in 0..program.shadow_reps() {
for ins in &program.shadow {
step(ins, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
if !per_load {
for _ in 0..program.shadow_reps() {
for ins in &program.shadow {
step(ins, &mut r, &sel, mask, log2, era.as_ref(), layout, ds, &mut idx, &mut val, &mut items_derived);
}
}
}
// Counter ASIC 4.0 research (experimental): the int8 tile block after the shadow, once per iteration
for d in &program.tiles {
crate::mm8::tile_step(&mut r, *d);
}
}
let mut hashes = [0u64; LANES];
for lane in 0..LANES {

223
igneum-pow/tests/ca4_trace.rs Normal file
View file

@ -0,0 +1,223 @@
//! Counter ASIC 4.0 research (diagnostic): where the per-load shadow's duplicate reads come from. Prints, for the class
//! v4 shape and the per-load shape over the same seed and day on a 2^24-word closed-form dataset (the index pattern is
//! the program's, not the dataset's), the distinct indices per load site across the 32 lanes and the distinct items per
//! unit across all 128 reads, plus the shadow sub-block's last writer of each load's source register.
use igneum_pow::generator::{generate_from_seed_bytes_class, LoadClass};
use igneum_pow::verify::{trace_load_indices, DatasetMode, DatasetSource};
use std::collections::HashSet;
#[test]
fn per_load_shadow_duplicate_reads_are_counted_per_site() {
let ds = DatasetSource::new("2026-10-03", DatasetMode::ClosedForm, 24);
let seed = igneum_pow::seed::seed_words_from_bytes(b"igneum-genesis");
for name in ["mx8+sh256x27", "mx8+shl256x27"] {
let class = LoadClass::parse(name).unwrap();
// the per-load class is refused by the acceptance rule on every attempt (22:4x UTC): its candidate 0 is read here
// as the known-failed record (the first export's program), the class v4 shape through the accepted program
let p = if name == "mx8+shl256x27" {
let v = igneum_pow::generator::attempts_class("igneum-genesis", b"igneum-genesis", class);
println!("CA4VERDICT igneum-genesis per-load 16 x 27: {} candidates, accepted {}", v.len(), v.iter().filter(|(_, r)| r.is_ok()).count());
v.into_iter().next().unwrap().0
} else {
generate_from_seed_bytes_class("igneum-genesis", b"igneum-genesis", class)
};
let mut total_distinct = 0usize;
let mut per_site = vec![0usize; 16];
let mut dup_pairs_same_iter = 0usize;
let mut all: HashSet<u32> = HashSet::new();
for base in [0u32, 4096, 1_000_000] {
let rows = trace_load_indices(&p, &seed, base, &ds);
assert_eq!(rows.len(), 128);
let mut unit: HashSet<u32> = HashSet::new();
for (k, row) in rows.iter().enumerate() {
let site = k % 16;
let s: HashSet<u32> = row.iter().copied().collect();
per_site[site] += 32 - s.len();
dup_pairs_same_iter += 32 - s.len();
for &x in row {
unit.insert(x);
}
}
total_distinct += unit.len();
all.extend(unit);
}
// the shadow's last writer of each load's source, in the per-load order (sub-block j precedes load j + 1)
let mut writers = Vec::new();
if p.shadow_per_load() {
let loads: Vec<_> = p.instrs.iter().filter(|i| i.op.is_load()).collect();
for (j, ld) in loads.iter().enumerate() {
let prev = if j == 0 { 15 } else { j - 1 };
let sub = p.shadow_sub_block(prev);
let w = sub.iter().rev().find(|i| i.dst == ld.src).map(|i| i.op.name()).unwrap_or("none");
writers.push(format!("load{j} src r{} <- {w}", ld.src));
}
}
if name == "mx8+shl256x27" {
// the known-failed record (the first export, 22:1x UTC): 10,728 distinct of 12,288 over three units and
// 1,482 same-iteration duplicate lanes at sites 8, 10 and 15, whose sub-block last writer of the load's
// source was `mul`; after the 22:3x UTC rule the class must read 0 duplicates like the class v4 shape
// the known-failed record (the first export, id 854050a4293f0615: 10,728 distinct of 12,288, 1,482 duplicate
// lanes) was drawn before the static redraw layer; today's candidate 0 is another program, so its figures are
// printed, not asserted (the file carries the record; the pack proto-cuda/packs-ca4/mx8_shl256x27 is the program)
let _ = (dup_pairs_same_iter, total_distinct);
}
println!(
"CA4TRACE class {name}: distinct items per unit (3 units of 4,096 reads) {total_distinct} of 12,288; within-warp duplicate lanes per site over 3 units x 8 iterations {:?}; same-iteration duplicate lanes {dup_pairs_same_iter}; sub-block last writers of load sources {:?}",
per_site, writers
);
}
}
#[test]
fn per_load_shadow_census_64_seeds_is_refused_on_every_attempt() {
// the verdict of 22:4x UTC: with the acceptance rule stepping the per-load sub-blocks in the order the class
// executes (duplicate lanes at a load row, biased index bits at a site over the 64 units), no candidate of the
// 16 x 27 construction passes; the histogram of first failing tests is the record
use igneum_pow::generator::attempts_class;
let class = LoadClass::parse("mx8+shl256x27").unwrap();
let mut accepted = 0usize;
let mut attempts_total = 0usize;
let mut hist: std::collections::BTreeMap<String, usize> = std::collections::BTreeMap::new();
for n in 0..64u32 {
let label = format!("ca4-census/{n}");
let v = attempts_class(&label, label.as_bytes(), class);
attempts_total += v.len();
for (_, r) in &v {
match r {
Ok(()) => accepted += 1,
Err(e) => {
let s = e.to_string();
let key = if s.contains("duplicate address") { "(c) per-load duplicate lanes" } else if s.contains("index bit") { "(c) per-load biased index bit" } else if s.starts_with("(a)") { "(a) stale source" } else if s.starts_with("(b)") { "(b) no injecting write" } else { "(c) base rule" };
*hist.entry(key.to_string()).or_insert(0) += 1;
}
}
}
}
let seeds_without = 64 - accepted;
println!("CA4CENSUS per-load 16 x 27 over 64 seeds: {accepted} accepted of {attempts_total} candidates ({:.1} percent); {seeds_without} of 64 seeds exhaust the chain's 32 attempts; first failing test {hist:?}", accepted as f64 / attempts_total as f64 * 100.0);
// the record of 22:4x UTC: 22 of 1,621 (1.4 percent), 42 seeds without a program; a construction that accepts
// under 5 percent of its candidates is dead as a chain class at the 32-attempt cap
assert!((accepted as f64) < 0.05 * attempts_total as f64, "the acceptance rate moved: {accepted} of {attempts_total}");
}
#[test]
fn per_load_shadow_census_over_16_drawn_eras_splits_by_stride_rotation() {
// the Counter lane's ask (adv-cache-2, 7 October 2026, 23:1x UK): read the per-load class's duplicate reads across
// drawn eras, split by the stride rotation R (R 28 and up cuts a product's biased low bits out of the index;
// R 3 to 22 keeps them in), not the devnet era alone
use igneum_pow::generator::{generate_era, EraParams, V3_ALLOWED};
let ds = DatasetSource::new("2026-10-03", DatasetMode::ClosedForm, 24);
let mut low = (0usize, 0usize, 0usize); // eras, rows, duplicate pairs with R under 28
let mut high = (0usize, 0usize, 0usize);
let mut lines = Vec::new();
for n in 0..16u32 {
let label = format!("igneum-era-test/{n}");
let eb = EraParams::test_era_bytes(&label);
// the per-load class is refused on every attempt (22:4x UTC), so generate_era would panic: the era rows below
// read the class v4 shape as the control of the duplicate-lane statistic across the drawn eras
let p = generate_era("igneum-genesis", b"igneum-genesis", LoadClass::parse("mx8+sh256x27").unwrap(), &eb, &V3_ALLOWED);
let era = p.class.era.expect("an era class");
let seed = igneum_pow::seed::seed_words_from_bytes(b"igneum-genesis");
let mut dups = 0usize;
let mut rows = 0usize;
for base in [0u32, 1 << 20] {
for row in trace_load_indices(&p, &seed, base, &ds) {
let s: HashSet<u32> = row.iter().copied().collect();
dups += 32 - s.len();
rows += 1;
}
}
let bucket = if era.stride_rot >= 28 { &mut high } else { &mut low };
bucket.0 += 1;
bucket.1 += rows;
bucket.2 += dups;
lines.push(format!("era {n} R={} attempt {} dups {dups}", era.stride_rot, p.attempt));
}
println!("CA4ERA class v4 shape (the control; the per-load class is refused on every attempt) over 16 drawn eras: R under 28: {} eras, {} rows, {} duplicate pairs; R 28 and up: {} eras, {} rows, {} duplicate pairs; per era {:?}", low.0, low.1, low.2, high.0, high.1, high.2, lines);
assert!(low.2 + high.2 <= 4, "duplicate reads beyond the chance floor across eras");
}
/// The value-level test 20.2b names: for every load site, the one-count of each index bit over the units' lanes and
/// iterations; a bit outside the binomial band (mean n/2, tolerance 5 sigma) at any site is a biased address bit. Reads
/// the class v4 shape and the per-load class over the devnet-style seed and 16 drawn eras, split by the stride rotation.
#[test]
fn index_bit_bias_per_site_across_eras() {
use igneum_pow::generator::{generate_era, EraParams, V3_ALLOWED};
let ds = DatasetSource::new("2026-10-03", DatasetMode::ClosedForm, 24);
let seed = igneum_pow::seed::seed_words_from_bytes(b"igneum-genesis");
for name in ["mx8+sh256x27", "mx8+shl256x27"] {
let class = LoadClass::parse(name).unwrap();
let mut report = Vec::new();
let mut flagged: Vec<String> = Vec::new();
for n in 0..17u32 {
let (p, r_label) = if n == 16 {
if name == "mx8+shl256x27" {
// candidate 0 of the refused per-load class (the known-failed record)
(igneum_pow::generator::attempts_class("igneum-genesis", b"igneum-genesis", class).into_iter().next().unwrap().0, "none".to_string())
} else {
(generate_from_seed_bytes_class("igneum-genesis", b"igneum-genesis", class), "none".to_string())
}
} else {
if name == "mx8+shl256x27" {
continue; // generate_era has no candidate path and the class is refused; the bare-class row stands
}
let eb = EraParams::test_era_bytes(&format!("igneum-era-test/{n}"));
let p = generate_era("igneum-genesis", b"igneum-genesis", class, &eb, &V3_ALLOWED);
let r = p.class.era.unwrap().stride_rot;
(p, r.to_string())
};
// ones[site][bit] over 4 units x 8 iterations x 32 lanes = 1,024 samples per site
let mut ones = vec![[0u32; 24]; 16];
let mut samples = 0u32;
for base in [0u32, 1 << 20, 7 << 20, 0x0123_4560] {
for (k, row) in trace_load_indices(&p, &seed, base, &ds).iter().enumerate() {
for &x in row {
for b in 0..24 {
ones[k % 16][b] += (x >> b) & 1;
}
}
}
samples += 8 * 32;
}
let mean = samples as f64 / 2.0;
let sigma = (samples as f64 / 4.0).sqrt();
let mut worst = (0.0f64, 0usize, 0usize);
for site in 0..16 {
for b in 0..24 {
let z = (ones[site][b] as f64 - mean).abs() / sigma;
if z > worst.0 {
worst = (z, site, b);
}
}
}
let loads: Vec<_> = p.instrs.iter().filter(|i| i.op.is_load()).collect();
let ld = loads[worst.1];
let writer = p.instrs.iter().take_while(|i| !std::ptr::eq(*i, ld)).filter(|i| i.dst == ld.src).last().map(|i| i.op.name()).unwrap_or("none");
let sub_writer = if p.shadow_per_load() {
let prev = if worst.1 == 0 { 15 } else { worst.1 - 1 };
p.shadow_sub_block(prev).iter().filter(|i| i.dst == ld.src).last().map(|i| i.op.name()).unwrap_or("none")
} else { "n/a" };
report.push(format!("R={r_label} worst z {:.1} at site {} bit {} (ones {} of {samples}; base writer {writer}, sub-block writer {sub_writer})", worst.0, worst.1, worst.2, ones[worst.1][worst.2]));
if worst.0 >= 5.0 {
flagged.push(report.last().unwrap().clone());
}
}
println!("CA4BIAS class {name}: index bit one-counts over 1,024 samples per site, 16 sites x 24 bits, 16 drawn eras plus the bare class: {:?}; flagged (z at or over 5) {}", report, flagged.len());
// a report, not a gate: on this generator (master, before the sub-version 3 source rule) the class v4 shape itself
// carries the biased product bit at address bit R (adv-cache-2, 7 October 2026); the per-load class is read beside it
if name == "mx8+shl256x27" {
assert!(!flagged.is_empty(), "candidate 0 of the per-load class carries the biased product bit (the record)");
}
}
}
#[test]
fn per_load_attempt_verdicts_on_the_test_seed() {
use igneum_pow::generator::attempts_class;
let class = LoadClass::parse("mx8+shl256x27").unwrap();
for seed in ["t", "igneum-genesis", "ca4-census/0", "ca4-census/1"] {
let v = attempts_class(seed, seed.as_bytes(), class);
let verdicts: Vec<String> = v.iter().map(|(p, r)| format!("a{} {}", p.attempt, match r { Ok(()) => "OK".to_string(), Err(e) => e.to_string() })).collect();
println!("CA4ATTEMPTS seed {seed}: {} attempts; {:?}", v.len(), verdicts);
}
}

1
igneum-pow/tests/scratch.rs
View file

@ -264,6 +264,7 @@ fn edge(name: &str, c: LoadClass, instrs: Vec<Instr>) -> Program {
era_bytes: None,
instrs,
shadow: Vec::new(),
tiles: Vec::new(),
}
}

46
igneum-pow/tests/v6_window_bits.rs Normal file
View file

@ -0,0 +1,46 @@
//! Class v6 invention lane (8 October 2026): the per-load acceptance's value-level bias test must not judge the era
//! window's fixed top index bits. Known-failed first: at counter-asic-4 5984ffab every per-load form under every drawn
//! era was refused with "index bit 26 (or 27) at load site s set in 0 (or 16,384) of 16,384" (0 of 256 seeds on 11
//! forms, build-1, 11:0x UK); with the window bits skipped the sound form accepts under an era as it does without one.
//! Offered by the invention lane (tools/attack/v6-invention/v6_window_bits.rs.offered on class-v6-invention), landed
//! here by the research lane against 0ab27582's fix.
use igneum_pow::accept::Reject;
use igneum_pow::generator::{attempts_class, LoadClass};
use igneum_pow::seed::seed_words_from_bytes;
fn era_class(name: &str, n: u32) -> LoadClass {
let era_seed = seed_words_from_bytes(format!("igneum-era-test/{n}").as_bytes());
let mut bytes = Vec::new();
for w in era_seed {
bytes.extend_from_slice(&w.to_le_bytes());
}
LoadClass::era(LoadClass::parse(name).unwrap(), &bytes, &igneum_pow::generator::V3_ALLOWED)
}
#[test]
fn per_load_bias_test_skips_the_era_window_bits() {
let mut accepted = 0usize;
let mut window_bit_rejections = 0usize;
for i in 0..8u32 {
let class = era_class("mx8+shl4096x1", i);
let label = format!("igneum-v6inv/{i}");
for (_, verdict) in attempts_class(&label, label.as_bytes(), class) {
match verdict {
Ok(()) => accepted += 1,
Err(Reject::BiasedIndexBit { bit, ones, .. }) if bit >= 26 && (ones == 0 || ones == 16_384) => window_bit_rejections += 1,
Err(_) => {}
}
}
}
assert_eq!(window_bit_rejections, 0, "a window's fixed top bit was judged as biased");
assert!(accepted >= 4, "the sound per-load form accepted on {accepted} of 8 seeds under drawn eras (0 before the fix)");
}
#[test]
fn per_load_bias_test_still_refuses_a_biased_real_bit_without_an_era() {
let class = LoadClass::parse("mx8+shl4096x1").unwrap();
let label = "igneum-v6inv/3";
let v = attempts_class(label, label.as_bytes(), class);
assert!(v.iter().all(|(_, r)| r.is_err()), "seed 3 exhausted the cap on the no-era census (0 of 32) and must still");
assert!(v.iter().any(|(_, r)| matches!(r, Err(Reject::BiasedIndexBit { bit: 0, .. }))), "a bit-0 refusal on seed 3 stands");
}

67
infra/build-server/lease.sh
View file

@ -56,6 +56,17 @@ held_cores() { # the cores whose lease file is flocked right now, as a space l
exec 8>>"$f"; if ! flock -n 8; then out="$out $c"; fi; exec 8>&-; done
echo "${out# }"
}
residents_gb() { # the box's resident set outside the pool: every igneumd and the sccache server, GB from /proc (LEASE_RESIDENT_GB overrides for the self-test)
[ -n "${LEASE_RESIDENT_GB:-}" ] && { echo "$LEASE_RESIDENT_GB"; return; }
local kb=0 p
for p in $(pgrep -x igneumd; pgrep -x sccache); do kb=$(( kb + $(awk '/^VmRSS:/ {print $2}' /proc/$p/status 2>/dev/null || echo 0) )); done
echo $(( kb / 1048576 ))
}
held_mem_gb() { # the declared memory of every live holder, GB (the "mem N GB" field of lease-* files whose pid is alive)
local f p m=0 n
for f in "$LOCKS"/lease-* ; do [ -e "$f" ] || continue; p=$(pid_of "$f"); [ -n "$p" ] && kill -0 "$p" 2>/dev/null || continue; n=$(sed -n 's/.* mem \([0-9][0-9]*\) GB.*/\1/p' "$f" | head -1); m=$(( m + ${n:-0} )); done
echo "$m"
}
any_slot_held() { local n f k; n=$(cat "$LOCKS/slots" 2>/dev/null || echo 1); for ((k = 0; k < n; k++)); do f="$LOCKS/build-$k"; [ -e "$f" ] || continue; exec 8>>"$f"; if ! flock -n 8; then exec 8>&-; return 0; fi; exec 8>&-; done; return 1; }
pid_of() { sed -n 's/^pid \([0-9]*\) .*/\1/p' "$1" 2>/dev/null | head -1; }
reap() { # stopped holders older than REAP_S are killed, their files cleared, one line each in reaped.log
@ -106,8 +117,8 @@ run_cores() {
exit $rc
}
run_pool() {
local want="$1"; shift; local label="" owner="${IGNEUM_AGENT:-unknown}" nice=10 min="" reserve="${LEASE_POOL_RESERVE:-8}" class="" rank
while [ $# -gt 0 ]; do case "$1" in --label) label="$2"; shift 2 ;; --owner) owner="$2"; shift 2 ;; --nice) nice="$2"; shift 2 ;; --min) min="$2"; shift 2 ;; --class) class="$2"; shift 2 ;; --priority) class=v5; shift ;; --) shift; break ;; *) say "unknown option $1"; exit 2 ;; esac; done
local want="$1"; shift; local label="" owner="${IGNEUM_AGENT:-unknown}" nice=10 min="" reserve="${LEASE_POOL_RESERVE:-8}" class="" rank mem=""
while [ $# -gt 0 ]; do case "$1" in --label) label="$2"; shift 2 ;; --owner) owner="$2"; shift 2 ;; --nice) nice="$2"; shift 2 ;; --min) min="$2"; shift 2 ;; --class) class="$2"; shift 2 ;; --priority) class=v5; shift ;; --mem) mem="$2"; shift 2 ;; --) shift; break ;; *) say "unknown option $1"; exit 2 ;; esac; done
if [ -z "$class" ]; then
case "$owner" in release|shipper|build-server) class=release ;; class-v5) class=v5 ;; measure*) class=measure ;; esac
[ -n "$class" ] || case "$label" in *release*|*canary*|*pair*) class=release ;; *"v5 gate"*|*"v5 kit"*) class=v5 ;; *measure*) class=measure ;; *) class=adv ;; esac
@ -120,7 +131,19 @@ run_pool() {
[ $# -gt 0 ] || { say "no command"; exit 2; }
local ncpu; ncpu="${LEASE_POOL_NCPU:-$(nproc)}"; local size=$((ncpu - reserve)); [ "$want" -gt "$size" ] && want=$size
[ -n "$min" ] || min=$(( want < 16 ? want : 16 )); [ "$min" -gt "$want" ] && min=$want
local t0 waited=0 line waitfile="$LOCKS/wait-$$" fds=() cores=() c fd taken said=0
# MEMORY (the shipper, 8 Oct 2026 12:3x BST, after the kernel OOM killer took the Devnet 3 seed at 11:06Z and node1-dn3 at 10:54Z on
# build-1 while a 31 GB attack binary ran under a 24-core lease): a lease declares its resident memory in GB (--mem N, or "about N GB"
# in the label; else LEASE_MEM_DEFAULT_GB, 8), and the pool refuses to START a lease while the box's residents (every igneumd and the
# sccache server, from /proc) plus the held leases' declared memory plus this ask would pass LEASE_MEM_CEILING_GB (100): it waits
# like a core-short lease, with the three numbers on its wait line, and gives up after 2 h (exit 76). An ask above the ceiling alone
# is refused at once (exit 2). The declared figure is on the holder line ("mem N GB") for the next lane and `lease status`.
[ -n "$mem" ] || mem=$(printf '%s' "$label" | sed -n 's/.*about \([0-9][0-9]*\) GB.*/\1/p' | head -1)
[ -n "$mem" ] || mem=$(printf '%s' "$label" | sed -n 's/.*[^0-9]\([0-9][0-9]*\) GB.*/\1/p' | head -1)
[ -n "$mem" ] || mem="${LEASE_MEM_DEFAULT_GB:-8}"
[ "$mem" -ge 0 ] 2>/dev/null || { say "--mem takes whole GB"; exit 2; }
local ceiling="${LEASE_MEM_CEILING_GB:-100}"
[ "$mem" -le "$ceiling" ] || { say "a lease of $mem GB is over the box ceiling of $ceiling GB; nothing could ever start it"; exit 2; }
local t0 waited=0 line waitfile="$LOCKS/wait-$$" fds=() cores=() c fd taken said=0 resid heldm memshort
mkdir -p "$LOCKS"; t0=$(date +%s)
line="pid $$ since $(now) waited 0 s: lease pool $want (min $min) class $class/$rank: $label; owner=$owner"; printf '%s\n' "$line" > "$waitfile"
trap 'rm -f "$waitfile" "$LOCKS/lease-$$"' EXIT
@ -134,12 +157,18 @@ run_pool() {
exec {fd}>>"$LOCKS/core-$c"
if flock -n "$fd"; then fds+=("$fd"); cores+=("$c"); taken=$((taken + 1)); else exec {fd}>&-; fi
done
[ "$taken" -ge "$min" ] && break
memshort=""
if [ "$taken" -ge "$min" ]; then
resid=$(residents_gb); heldm=$(held_mem_gb)
if [ $(( resid + heldm + mem )) -le "$ceiling" ]; then break; fi
memshort="memory: residents $resid GB + held leases $heldm GB + ask $mem GB > ceiling $ceiling GB"
fi
for fd in "${fds[@]}"; do exec {fd}>&-; done
fi
waited=$(( $(date +%s) - t0 )); [ "$waited" -ge 7200 ] && { say "gave up waiting for $min free pool cores after 2 h"; exit 75; }
[ "$said" = 0 ] && { say "$taken of $min pool cores free ($(held_cores | wc -w) leased)$([ -n "$higher" ] && echo ', a higher class waits ahead'); waiting"; said=1; }
printf '%s\n' "pid $$ since $(now) waited $waited s: lease pool $want (min $min, $taken free) class $class/$rank: $label; owner=$owner" > "$waitfile"
waited=$(( $(date +%s) - t0 ))
[ "$waited" -ge 7200 ] && { if [ -n "$memshort" ]; then say "gave up after 2 h: $memshort"; exit 76; else say "gave up waiting for $min free pool cores after 2 h"; exit 75; fi; }
[ "$said" = 0 ] && { say "$taken of $min pool cores free ($(held_cores | wc -w) leased)$([ -n "$higher" ] && echo ', a higher class waits ahead')${memshort:+; $memshort}; waiting"; said=1; }
printf '%s\n' "pid $$ since $(now) waited $waited s: lease pool $want (min $min, $taken free) class $class/$rank: $label; owner=$owner${memshort:+; $memshort}" > "$waitfile"
# PRE-EMPTION (main, 7 Oct 2026 22:2x UK; the F8 gate sat behind two adv leases of 32 and 30 with the pool full): a release or v5
# waiter that has waited preempt_s (120 s) sends TERM to adv-class holders at ANY size, OLDEST first, as many as it takes to cover
# its ask (min), one pass per preempt_s; measure-class holders above preempt_min (32) the same after preempt_measure_s (300 s).
@ -170,14 +199,14 @@ run_pool() {
done
waited=$(( $(date +%s) - t0 ))
local set; set=$(printf '%s,' "${cores[@]}"); set=${set%,}
line="pid $$ since $(now) waited $waited s: lease pool $taken of $want cores $set class $class/$rank: $label; owner=$owner"; printf '%s\n' "$line" > "$LOCKS/lease-$$"; rm -f "$waitfile"
say "holding $taken pool cores ($set, waited $waited s, class $class): $label"
line="pid $$ since $(now) waited $waited s: lease pool $taken of $want cores $set class $class/$rank mem $mem GB: $label; owner=$owner"; printf '%s\n' "$line" > "$LOCKS/lease-$$"; rm -f "$waitfile"
say "holding $taken pool cores ($set, waited $waited s, class $class, mem $mem GB): $label"
local args=() a; for a in "$@"; do a=${a//\{cores\}/$taken}; a=${a//\{cpuset\}/$set}; args+=("$a"); done
export LEASE_CORES="$taken" LEASE_CPUSET="$set"
local cmdpid
if [ "${LEASE_NO_PIN:-0}" = 1 ]; then "${args[@]}" & else nice -n "$nice" taskset -c "$set" "${args[@]}" & fi; cmdpid=$!
# the command's pid in the holder line (a rank P waiter's TERM goes to it, never to the lease or its keeper)
line="pid $$ since $(now) waited $waited s: lease pool $taken of $want cores $set class $class/$rank cmd $cmdpid; $label; owner=$owner"; printf '%s\n' "$line" > "$LOCKS/lease-$$"
line="pid $$ since $(now) waited $waited s: lease pool $taken of $want cores $set class $class/$rank cmd $cmdpid; mem $mem GB; $label; owner=$owner"; printf '%s\n' "$line" > "$LOCKS/lease-$$"
( for fd in "${fds[@]}"; do exec {fd}>&-; done; while kill -0 $$ 2>/dev/null; do touch "$LOCKS/lease-$$" 2>/dev/null; [ -s "$LOCKS/lease-$$" ] || printf '%s\n' "$line" > "$LOCKS/lease-$$"; sleep 20; done ) & local keeper=$!
trap 'kill -TERM "$cmdpid" 2>/dev/null' TERM INT
wait "$cmdpid"; local rc=$?; trap - TERM INT
@ -210,7 +239,10 @@ self_test() {
t=$(mktemp -d); trap 'rm -rf "$t"' EXIT
# a PRIVATE lock directory (never the live _locks) and no pinning: the test is about the locks, and it must read the same on an
# idle box and on one at load 120 (the horizon lane, 7 Oct 2026: one red on a full gate, green a minute later)
export IGNEUM_BUILD_SLOTS_DIR="$t/locks" IGNEUM_BUILD_LOG_DIR="$t/log" LEASE_REAP_S=2 LEASE_NO_PIN=1; mkdir -p "$t/locks"; echo 2 > "$t/locks/slots"
# LEASE_RESIDENT_GB=0: the memory rule reads the box's live igneumd and sccache residents from /proc, and on build-1 at 80 GB of hands
# every pool case of this test would wait at the ceiling for two hours (three gates hung on the box, 8 Oct 2026 13:0x BST); the
# memory case sets its own figure
export IGNEUM_BUILD_SLOTS_DIR="$t/locks" IGNEUM_BUILD_LOG_DIR="$t/log" LEASE_REAP_S=2 LEASE_NO_PIN=1 LEASE_RESIDENT_GB=0; mkdir -p "$t/locks"; echo 2 > "$t/locks/slots"
local me="$0" fail=0
f() { echo "lease self-test: FAIL: $*"; fail=1; }
# 1. two leases on disjoint cores run together; the same core waits
@ -285,7 +317,18 @@ self_test() {
sleep 3; [ -s "$t/m.termed" ] && f "a measure holder under the floor was pre-empted"
wait; unset LEASE_PREEMPT_S LEASE_POOL_STEP_S LEASE_POOL_NCPU LEASE_PREEMPT_MIN_CORES
[ -z "$(ls "$t/locks" | grep -E '^(lease|wait)-')" ] || f "pool lease or wait files left behind: $(ls "$t/locks")"
[ "$fail" = 0 ] && echo "lease self-test: disjoint leases run together, a shared core waits, quiet is refused beside a slot or a lease and capped, a stopped holder is reaped after the window, a running one is kept, a pool run takes the free pool cores and the next waits for them, a higher class is served before a lower one whatever the arrival order, a v5 waiter pre-empts adv holders at any size oldest first until its ask is met and leaves a small measure row alone, ca4 research is first among measure rows"
# 9. MEMORY (known-failed first): with a 10 GB ceiling and 3 GB of residents, an 11 GB ask is refused at once; a 5 GB holder runs;
# a 4 GB ask (3 + 5 + 4 = 12) waits for it; a 2 GB ask (3 + 5 + 2 = 10) runs beside it; the holder line carries "mem 5 GB"
export LEASE_POOL_NCPU=12 LEASE_MEM_CEILING_GB=10 LEASE_RESIDENT_GB=3 LEASE_POOL_STEP_S=1
bash "$me" pool 1 --min 1 --mem 11 --label M0 -- true 2>/dev/null; [ $? = 2 ] || f "an ask over the ceiling was not refused at once"
bash "$me" pool 1 --min 1 --mem 5 --label M1 -- bash -c "date +%s.%N > '$t/m1.start'; sleep 6; date +%s.%N > '$t/m1.end'" 2>/dev/null & for i in $(seq 1 60); do [ -f "$t/m1.start" ] && break; sleep 0.1; done
grep -q " mem 5 GB" "$t"/locks/lease-* 2>/dev/null || f "the holder line does not carry its declared memory"
bash "$me" pool 1 --min 1 --mem 2 --label M3 -- bash -c "date +%s.%N > '$t/m3.start'" 2>/dev/null
python3 -c "import sys; sys.exit(0 if float(open('$t/m3.start').read()) < float(open('$t/m1.start').read()) + 5.5 else 1)" || f "a lease inside the ceiling waited for an unrelated holder"
bash "$me" pool 1 --min 1 --mem 4 --label M2 -- bash -c "date +%s.%N > '$t/m2.start'" 2>/dev/null
python3 -c "import sys; sys.exit(0 if float(open('$t/m2.start').read()) >= float(open('$t/m1.end').read()) else 1)" || f "a lease past the ceiling started before the holder released its memory"
wait; unset LEASE_MEM_CEILING_GB LEASE_POOL_STEP_S; export LEASE_RESIDENT_GB=0
[ "$fail" = 0 ] && echo "lease self-test: disjoint leases run together, a shared core waits, quiet is refused beside a slot or a lease and capped, a stopped holder is reaped after the window, a running one is kept, a pool run takes the free pool cores and the next waits for them, a higher class is served before a lower one whatever the arrival order, a v5 waiter pre-empts adv holders at any size oldest first until its ask is met and leaves a small measure row alone, ca4 research is first among measure rows, a lease declares its memory and waits at the box ceiling"
return $fail
}
case "${1:-}" in

4
proto-cuda/nvrtc/cuda_api.h
View file

@ -34,6 +34,10 @@ struct Drv {
decltype(&cuOccupancyMaxActiveBlocksPerMultiprocessor) occupancy = nullptr;
decltype(&cuGetErrorString) getErrorString = nullptr;
decltype(&cuGetErrorName) getErrorName = nullptr;
// Counter ASIC 4.0 research (7 October 2026): the --microbench texture probes; optional (the probes that need
// them are skipped when the driver has no symbol, which no shipped driver lacks)
decltype(&cuTexObjectCreate) texObjectCreate = nullptr;
decltype(&cuTexObjectDestroy) texObjectDestroy = nullptr;
};
struct Rtc {

5
proto-cuda/nvrtc/emu/list-race-stubs.cpp Normal file
View file

@ -0,0 +1,5 @@
// emu/list-race-stubs.cpp (Counter ASIC 4.0 research, 8 October 2026): the two emulation entry points, so worker.cpp
// itself links as a Linux binary for the card-free --list-race check on the box (nothing opens a device there).
#include "cuda_api.h"
void emu_fill_driver(Drv&) {}
void emu_fill_nvrtc(Rtc&) {}

51
proto-cuda/nvrtc/emu/variant-test.cpp Normal file
View file

@ -0,0 +1,51 @@
// emu/variant-test.cpp (Counter ASIC 4.0 research, 8 October 2026): the known-failed pair for the --bench --variant fix,
// on the host with no card. Includes the worker with its main renamed and reads the pure pieces: the bench's race
// switch, the variant lookup, the kernel-text rewrite on a real class v4 pack, and the launch shape.
// (1) --bench with no --variant: the race is off and the shape is nonces / block blocks ("variant base");
// (2) --bench --variant sp43-w32: the race is on, the name resolves to 43 sparse blocks of 32 warps, the rewrite of the
// pack's bound kernel carries the `nonces` argument and the unit function, and the shape is 43 blocks.
// The run of 7 October (run-ca4-pc1-ca4sparse-5090-20261007) is the failed case this test reproduces: before the fix
// (1) and (2) read the same shape and the same "variant base".
#define main igneum_worker_main
#include "../worker.cpp"
#undef main
#include <cassert>
// the emulation entry points worker.cpp declares under IGNEUM_EMU: this test never opens a device, so they are stubs
void emu_fill_driver(Drv&) {}
void emu_fill_nvrtc(Rtc&) {}
int main(int argc, char** argv) {
if (argc < 2) { std::printf("usage: variant-test <pack dir with kernel_bound.cu>\n"); return 2; }
bool ok = true;
std::string text = readText(std::string(argv[1]) + "/kernel_bound.cu", ok);
if (!ok) { std::printf("FAIL: cannot read %s/kernel_bound.cu\n", argv[1]); return 2; }
std::string err;
std::string boundDev;
if (!deviceOnly(text, boundDev, err)) { std::printf("FAIL: device text: %s\n", err.c_str()); return 2; }
const uint32_t nonces = 1u << 24;
// (1) the base run
const bool raceOffBase = benchRaceOff(true, "");
unsigned gridBase = launchGridBlocks(0, nonces, 32);
std::printf("RESULT variant-test case=base race_off=%d grid_blocks=%u block=32 variant=base\n", raceOffBase ? 1 : 0, gridBase);
// (2) the sparse run
std::vector<Variant> all = allVariants();
const Variant* v = findVariant(all, "sp43-w32");
const bool raceOffSparse = benchRaceOff(true, "sp43-w32");
std::string src, why;
bool rewritten = v && variantSource(boundDev, *v, v->blockWarps, src, why);
bool hasArg = rewritten && src.find("igneum_hash_bound(") != std::string::npos && src.find(", uint32_t nonces) {") != std::string::npos;
bool hasUnit = rewritten && src.find("igneum_hash_bound_unit(") != std::string::npos && src.find("gid += gridDim.x * blockDim.x") != std::string::npos;
unsigned gridSparse = v ? launchGridBlocks(v->sparseBlocks, nonces, 32u * (uint32_t)v->blockWarps) : 0;
std::printf("RESULT variant-test case=sp43-w32 race_off=%d resolved=%d sparse_blocks=%d block_warps=%d rewritten=%d nonces_arg=%d unit_fn=%d grid_blocks=%u block=%d why=\"%s\"\n",
raceOffSparse ? 1 : 0, v ? 1 : 0, v ? v->sparseBlocks : 0, v ? v->blockWarps : 0, rewritten ? 1 : 0, hasArg ? 1 : 0, hasUnit ? 1 : 0, gridSparse, v ? 32 * v->blockWarps : 0, why.c_str());
// (3) the race's order the bench builds for the pinned variant (the 02:52Z fault: "variants 1 base only")
Tuning noTuning;
std::vector<Variant> order = raceOrder(all, "sp43-w32", noTuning, "on");
std::vector<Variant> orderBase = raceOrder(all, "", noTuning, "off");
bool orderOk = order.size() == 2 && order[0].name == "base" && order[1].name == "sp43-w32" && order[1].sparseBlocks == 43 && orderBase.size() == 1;
std::printf("RESULT variant-test case=race-order pinned=sp43-w32 variants=%zu names=%s%s base_only_variants=%zu\n", order.size(), order.size() > 0 ? order[0].name.c_str() : "", order.size() > 1 ? (std::string(",") + order[1].name).c_str() : "", orderBase.size());
bool pass = raceOffBase && !raceOffSparse && v && v->sparseBlocks == 43 && v->blockWarps == 32 && rewritten && hasArg && hasUnit && gridBase == nonces / 32 && gridSparse == 43 && orderOk;
// the known-failed shape: a base run and a sparse run with the same grid is the 7 October fault
std::printf("RESULT variant-test %s: base grid %u blocks of 32 against sparse grid %u blocks of %d, race %s/%s\n", pass ? "PASS" : "FAIL", gridBase, gridSparse, v ? 32 * v->blockWarps : 0, raceOffBase ? "off" : "on", raceOffSparse ? "off" : "on");
return pass ? 0 : 1;
}

418
proto-cuda/nvrtc/worker.cpp
View file

@ -53,6 +53,7 @@
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
#include <chrono>
#include <string>
#include <vector>
@ -177,6 +178,8 @@ static bool loadDriver(Drv& d, std::string& err, std::string& libName) {
LOAD_SYM(d, occupancy, "cuOccupancyMaxActiveBlocksPerMultiprocessor");
LOAD_SYM(d, getErrorString, "cuGetErrorString");
LOAD_SYM(d, getErrorName, "cuGetErrorName");
d.texObjectCreate = (decltype(d.texObjectCreate))libSym(lib, "cuTexObjectCreate"); // optional, --microbench only
d.texObjectDestroy = (decltype(d.texObjectDestroy))libSym(lib, "cuTexObjectDestroy");
if (!missing.empty()) { err = "the driver library lacks " + missing + " (driver too old; CUDA 11 or newer is needed)"; return false; }
return true;
#endif
@ -195,6 +198,7 @@ static std::vector<std::string> nvrtcCandidates() {
FindClose(h);
}
v.push_back("nvrtc64_120_0.dll");
v.push_back("libnvrtc.so.12"); v.push_back("/usr/local/cuda-12.8/lib64/libnvrtc.so.12"); v.push_back("/usr/local/cuda/lib64/libnvrtc.so.12"); // the box's card-free --list-race check
v.push_back("nvrtc64_130_0.dll");
if (const char* cp = std::getenv("CUDA_PATH")) { v.push_back(std::string(cp) + "\\bin\\nvrtc64_120_0.dll"); v.push_back(std::string(cp) + "\\bin\\nvrtc64_130_0.dll"); }
return v;
@ -423,6 +427,7 @@ struct Pair {
int regs = 0, blocksPerSM = 0;
int blockWarps = 1; // threads per block = 32 x this (the winning variant's, else the worker's default)
std::string variant = "base"; // the bound kernel in service: a variant name (see allVariants)
int sparseBlocks = 0; // the SM-sparse variants (sp<N>): the persistent grid in blocks, 0 = the plain grid
std::string raceLine; // the race's one-line report, emitted by the main thread with "prepared"
double raceMs = 0;
// read-width experiment (5 October 2026): the pack's load class and, for variant 5, the persistent-warp scratch
@ -481,6 +486,17 @@ static void releasePair(Ctx& c, Pair* p) {
struct IgneumInitWordsArg { uint32_t w[8]; };
// The launch shape of a non-persistent dispatch: grid blocks for `nonces` lanes at `block` threads per block, or the
// SM-sparse grid of `sparseBlocks` persistent blocks (Counter ASIC 4.0 research). Pure, so the emulation test can
// read it (emu/variant-test.cpp): the base shape is nonces / block, the sparse shape is the block count itself.
static unsigned launchGridBlocks(int sparseBlocks, uint32_t nonces, uint32_t block) {
return sparseBlocks > 0 ? (unsigned)sparseBlocks : (unsigned)(nonces / block);
}
// Whether a --bench/--memprobe/--microbench run keeps the race off: yes unless --variant names a kernel to serve
// (8 October 2026: the SM-sparse run of 7 October served base on 48 rows because this read true with a --variant).
static bool benchRaceOff(bool bench, const std::string& pinned) { return bench && pinned.empty(); }
// `block` threads per block (32 x warps); `nonces` must be a multiple of it.
static bool launchHash(Ctx& c, Pair* p, CUdeviceptr out, uint32_t baseNonce, const uint32_t iw[8], uint32_t nonces, uint32_t block, CUstream s, std::string& err) {
uint32_t mask = p->words - 1u;
@ -498,8 +514,17 @@ static bool launchHash(Ctx& c, Pair* p, CUdeviceptr out, uint32_t baseNonce, con
DRV_CHECK(c, c.drv.launchKernel(p->fHashBound, warps, 1, 1, 32, 1, 1, 0, s, args, nullptr), "cuLaunchKernel igneum_hash_bound (persistent)");
return true;
}
if (p->sparseBlocks > 0) {
// The SM-sparse wrapper: a grid of sparseBlocks blocks, the trailing argument the dispatch's nonce count (after
// the hot table when the pack has one); a dispatch smaller than the grid leaves the surplus blocks idle.
if (nonces % block != 0u) { err = "nonces not a multiple of the block"; return false; }
void* args[7] = { &p->ds, &out, &baseNonce, &mask, &a, &nonces, nullptr };
if (p->hot) { args[5] = &p->hot; args[6] = &nonces; }
DRV_CHECK(c, c.drv.launchKernel(p->fHashBound, launchGridBlocks(p->sparseBlocks, nonces, block), 1, 1, block, 1, 1, 0, s, args, nullptr), "cuLaunchKernel igneum_hash_bound (SM-sparse)");
return true;
}
void* args[6] = { &p->ds, &out, &baseNonce, &mask, &a, &p->hot };
DRV_CHECK(c, c.drv.launchKernel(p->fHashBound, nonces / block, 1, 1, block, 1, 1, 0, s, args, nullptr), "cuLaunchKernel igneum_hash_bound");
DRV_CHECK(c, c.drv.launchKernel(p->fHashBound, launchGridBlocks(0, nonces, block), 1, 1, block, 1, 1, 0, s, args, nullptr), "cuLaunchKernel igneum_hash_bound");
return true;
}
@ -514,6 +539,10 @@ struct Variant {
int maxrreg = 0; // 0: none; N: --maxrregcount=N (registers per thread, occupancy against spills)
int blockWarps = 0; // 0: the worker's --block-warps; N: 32 x N threads per block
int minBlocks = 0; // N > 0: __launch_bounds__(32 x blockWarps, N) (the compiler fits N blocks per SM)
int sparseBlocks = 0; // N > 0: the SM-sparse shape (Counter ASIC 4.0 research, 7 October 2026): a persistent grid of N
// blocks, every thread looping over the dispatch's nonces with stride gridDim.x * blockDim.x, so the
// hash runs on about N SMs at 32 warps per block and the other SMs idle; the kernel gains a
// trailing `uint32_t nonces` argument. Opt-in by name only (sp<N> or sp<N>-w<W>), never in a race by default
};
// The catalogue. Names are stable: the tuning file and the fleet records use them. "base" is the pack's text as
@ -541,11 +570,36 @@ static std::vector<Variant> allVariants() {
return v;
}
// sp<N> and sp<N>-w<W>: the SM-sparse variants, made on demand (not in the catalogue, so a default race never runs them):
// N persistent blocks (1 to 4096) of W warps (default 32, the largest block, one block per SM at the hash's register count).
static bool parseSparseVariant(const std::string& name, Variant& out) {
if (name.rfind("sp", 0) != 0) return false;
size_t i = 2, n = 0; int blocks = 0, warps = 32;
while (i < name.size() && name[i] >= '0' && name[i] <= '9') { blocks = blocks * 10 + (name[i] - '0'); ++i; ++n; }
if (n == 0 || blocks < 1 || blocks > 4096) return false;
if (i < name.size()) {
if (name.compare(i, 2, "-w") != 0) return false;
i += 2; n = 0; warps = 0;
while (i < name.size() && name[i] >= '0' && name[i] <= '9') { warps = warps * 10 + (name[i] - '0'); ++i; ++n; }
if (n == 0 || i != name.size() || warps < 1 || warps > 32) return false;
}
out = Variant(); out.name = name; out.blockWarps = warps; out.sparseBlocks = blocks;
return true;
}
static const Variant* findVariant(const std::vector<Variant>& all, const std::string& name) {
for (const Variant& v : all) if (v.name == name) return &v;
static std::vector<Variant> made; // the on-demand sparse variants, kept so the pointer stays valid
Variant sp;
if (parseSparseVariant(name, sp)) {
for (const Variant& v : made) if (v.name == name) return &v;
made.reserve(64);
if (made.size() < 64) { made.push_back(sp); return &made.back(); }
}
return nullptr;
}
// The variant's source: the pack's bound-kernel text with the variant's rewrites. Every rewrite has an exact anchor
// in the text igneum-pow emits; a text without the anchor refuses the variant (why), it is never guessed.
static bool variantSource(const std::string& base, const Variant& v, int blockWarps, std::string& out, std::string& why) {
@ -576,6 +630,47 @@ static bool variantSource(const std::string& base, const Variant& v, int blockWa
if (p == std::string::npos) { why = "no kernel declaration anchor"; return false; }
out.replace(p, std::strlen(a), fmt("__global__ void __launch_bounds__(%d, %d) igneum_hash_bound(", 32 * blockWarps, v.minBlocks));
}
if (v.sparseBlocks > 0) {
// The SM-sparse shape: the emitted kernel becomes a per-thread unit function taking its gid, and a persistent
// wrapper of the kernel's name loops the unit over the dispatch's nonces. Anchors: the kernel declaration as
// igneum-pow emits it (no __launch_bounds__ on it: the two rewrites are not combined) and its first line.
if (v.minBlocks > 0) { why = "sp and __launch_bounds__ minBlocks are not combined"; return false; }
// line-ending-agnostic: a pack copied through Windows may carry CRLF; the anchors below are LF, so the text is
// normalised first (the rewritten kernel then has the same bytes from LF and CRLF input)
out.erase(std::remove(out.begin(), out.end(), '\r'), out.end());
const char* a = "__global__ void igneum_hash_bound(";
size_t p = out.find(a);
if (p == std::string::npos) { why = "no kernel declaration anchor"; return false; }
size_t close = out.find(") {", p);
if (close == std::string::npos) { why = "no parameter list close"; return false; }
std::string params = out.substr(p + std::strlen(a), close - (p + std::strlen(a)));
if (params.find("scratch") != std::string::npos || params.find("units") != std::string::npos) { why = "a persistent (variant-5) pack has its own loop"; return false; }
// the argument names: the last token of each parameter
std::string args; size_t from = 0;
while (from <= params.size()) {
size_t comma = params.find(',', from);
std::string one = params.substr(from, comma == std::string::npos ? std::string::npos : comma - from);
size_t e = one.find_last_not_of(" \t");
if (e == std::string::npos) { why = "an empty parameter"; return false; }
size_t b = one.find_last_of(" \t*&", e);
size_t start = b == std::string::npos ? 0 : b + 1;
std::string nm = one.substr(start, e - start + 1); // e is the last character's index: the length is e - start + 1
// (the 03:23Z card run read `d, ou, baseNonc, mas, i`: the length was written e - start and dropped every name's last character)
if (nm.empty()) { why = "a parameter without a name"; return false; }
args += (args.empty() ? "" : ", ") + nm;
if (comma == std::string::npos) break;
from = comma + 1;
}
const char* gidLine = "\n uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;\n";
size_t g = out.find(gidLine, close);
if (g == std::string::npos) { why = "no gid line after the declaration"; return false; }
out.replace(g, std::strlen(gidLine), "\n");
out.replace(p, close - p, "__device__ __forceinline__ void igneum_hash_bound_unit(" + params + ", uint32_t gid");
out += fmt("\n// SM-sparse wrapper (variant %s): %d persistent blocks of %d threads over the dispatch's nonces\n", v.name.c_str(), v.sparseBlocks, 32 * blockWarps);
out += fmt("__global__ void __launch_bounds__(%d) igneum_hash_bound(", 32 * blockWarps) + params + ", uint32_t nonces) {\n";
out += " for (uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x; gid < nonces; gid += gridDim.x * blockDim.x)\n";
out += " igneum_hash_bound_unit(" + args + ", gid);\n}\n";
}
return true;
}
@ -598,6 +693,24 @@ static std::string jsonStringAfter(const std::string& t, size_t from, const char
return e == std::string::npos ? "" : t.substr(q + 1, e - q - 1);
}
// The race's order: base first, then the pinned or tuned candidates, then the rest (or the --race list only). Pure, so
// the emulation test reads it (emu/variant-test.cpp). Membership in `order` is by NAME: findVariant answers for the
// on-demand sp<N> names whatever list it is asked about, which is the fault of the 8 October 02:52Z run (the pinned
// sparse variant was looked up in `order`, found by the on-demand path, and never pushed: "variants 1 base only").
static std::vector<Variant> raceOrder(const std::vector<Variant>& all, const std::string& pinned, const Tuning& tu, const std::string& race) {
std::vector<Variant> order;
auto has = [&](const std::string& n) { for (const Variant& v : order) if (v.name == n) return true; return false; };
auto push = [&](const std::string& n) { const Variant* v = findVariant(all, n); if (v && !has(n)) order.push_back(*v); };
push("base");
if (!pinned.empty()) push(pinned);
else {
for (const std::string& n : tu.candidates) push(n);
if (race != "on" && race != "off") { std::string rest = race; size_t i = 0; while (i <= rest.size()) { size_t j = rest.find(',', i); if (j == std::string::npos) j = rest.size(); if (j > i) push(rest.substr(i, j - i)); i = j + 1; } }
else if (race == "on") for (const Variant& v : all) push(v.name);
}
return order;
}
static Tuning readTuning(const std::string& text, const std::string& device) {
Tuning tu;
if (text.empty()) return tu;
@ -643,7 +756,9 @@ struct RaceEntry {
static bool raceTime(Ctx& c, Pair* p, const PfPack& pk, RaceEntry& e, CUdeviceptr dOut, uint32_t batch, int benchMs, CUstream s, bool selfTest) {
std::lock_guard<std::mutex> hold(gpuMutex);
CUfunction keep = p->fHashBound;
int keepSparse = p->sparseBlocks;
p->fHashBound = e.fn;
p->sparseBlocks = e.v.sparseBlocks;
std::string err;
uint32_t block = 32u * (uint32_t)e.blockWarps;
bool ok = true;
@ -673,6 +788,7 @@ static bool raceTime(Ctx& c, Pair* p, const PfPack& pk, RaceEntry& e, CUdevicept
}
}
p->fHashBound = keep;
p->sparseBlocks = keepSparse;
return ok;
}
@ -684,16 +800,7 @@ static void racePair(Ctx& c, Pair* p, const PfPack& pk, const std::string& bound
std::vector<Variant> all = allVariants();
Tuning tu = readTuning(c.tuning, c.name);
std::string pinned = !c.pinned.empty() ? c.pinned : (tu.found && !tu.race ? tu.variant : "");
// the order: base first, then the pinned or tuned candidates, then the rest (or the --race list only)
std::vector<Variant> order;
auto push = [&](const std::string& n) { const Variant* v = findVariant(all, n); if (v && !findVariant(order, n)) order.push_back(*v); };
push("base");
if (!pinned.empty()) push(pinned);
else {
for (const std::string& n : tu.candidates) push(n);
if (c.race != "on" && c.race != "off") { std::string rest = c.race; size_t i = 0; while (i <= rest.size()) { size_t j = rest.find(',', i); if (j == std::string::npos) j = rest.size(); if (j > i) push(rest.substr(i, j - i)); i = j + 1; } }
else if (c.race == "on") for (const Variant& v : all) push(v.name);
}
std::vector<Variant> order = raceOrder(all, pinned, tu, c.race);
#ifdef IGNEUM_EMU
order.resize(1); // the stand-in checks that the handed-over text is the pack's; no rewrites under emulation
#endif
@ -781,9 +888,10 @@ static void racePair(Ctx& c, Pair* p, const PfPack& pk, const std::string& bound
RaceEntry& w = entries[win];
c.drv.moduleUnload(p->modBound);
p->modBound = w.mod; p->fHashBound = w.fn; p->regs = w.regs; p->blocksPerSM = w.blocksPerSM; p->blockWarps = w.blockWarps; p->variant = w.v.name;
p->sparseBlocks = w.v.sparseBlocks;
w.mod = nullptr;
} else {
p->blockWarps = c.blockWarps; p->variant = "base";
p->blockWarps = c.blockWarps; p->variant = "base"; p->sparseBlocks = 0;
}
for (size_t i = 1; i < entries.size(); ++i) if (entries[i].mod) c.drv.moduleUnload(entries[i].mod);
p->raceMs = wallMs() - t0;
@ -1000,6 +1108,10 @@ static void prepareRun(Ctx* c, PrepareTask* t) {
struct Options {
bool serve = false, check = false, raceOnly = false;
bool bench = false, memprobe = false; // read-width experiment (5 October 2026)
bool microbench = false; // Counter ASIC 4.0 research (7 October 2026): one kernel per GPU hardware block, sustained
int mbSeconds = 60; // --mb-seconds: the sustained window per probe (the power sampler reads it)
std::string mbOnly; // --mb-only a,b,c: these probes only
bool listRace = false; // --list-race: print the race order --bench would run (card-free), then exit
int batches = 5, warps = 0, probeMib = 0;
int device = 0, batchLog2 = 22, blockWarps = 1;
std::string pack, arch = "auto";
@ -1019,6 +1131,11 @@ static void usage() {
" print the 2^B fingerprint at base nonce 0 (one RESULT line); a variant-5 pack runs --warps persistent warps\n"
" --memprobe [--probe-mib N] no pack: dependent random 4, 16 and 64-byte reads, independent reads, a coalesced stream and an\n"
" integer chain at 4, 64 and 1024 MiB (the same table as igneum-worker-opencl --memprobe)\n"
" --list-race [--pack <dir>] [--variant <name>] [--race ...] card-free: print the race order the run would build (variants N, names) and,\n"
" with a pack, whether the named variant's kernel rewrite applies to its bound kernel; then exit 0, or 1 when a named variant is missing\n"
" --microbench [--mb-seconds 60] [--mb-only a,b] no pack: one sustained kernel per GPU hardware block (ALU families, shuffle,\n"
" byte permute, FP32 and FP16 FMA, tensor tiles per precision, L2-resident chases, texture fetches, a DRAM\n"
" chase and a sleeping-SM floor), each for --mb-seconds with UTC start and end stamps for a power sampler\n"
" --batches N --bench: timed dispatches (default 5)\n"
" --warps N --bench on a variant-5 pack: persistent warps (default: the occupancy capacity, rounded down to a power of two)\n"
" --race --pack <dir> the variant race alone (3 rounds): one line per variant, the race line, exit 0 or 1\n"
@ -1026,7 +1143,8 @@ static void usage() {
" --race-bench-ms N timed window per variant (default 2000)\n"
" --race-budget-s N a race stops compiling and timing after this (default 120; base is kept)\n"
" --race-rounds N interleaved rounds, best per variant (default 1 in --serve, 3 in --race)\n"
" --variant <name> use this variant without a race (also from the tuning file)\n"
" --variant <name> use this variant without a race (also from the tuning file); sp<N> or sp<N>-w<W> is the\n"
" SM-sparse shape (N persistent blocks of W warps, default 32; Counter ASIC 4.0 research)\n"
" --tuning <file> the per-card tuning file (default: IGNEUM_TUNING_FILE from the environment)\n", WORKER_VERSION);
}
@ -1039,6 +1157,10 @@ static Options parseArgs(int argc, char** argv) {
else if (a == "--check") o.check = true;
else if (a == "--bench") o.bench = true;
else if (a == "--memprobe") o.memprobe = true;
else if (a == "--microbench") o.microbench = true;
else if (a == "--mb-seconds") o.mbSeconds = std::atoi(next().c_str());
else if (a == "--mb-only") o.mbOnly = next();
else if (a == "--list-race") o.listRace = true;
else if (a == "--batches") o.batches = std::atoi(next().c_str());
else if (a == "--warps") o.warps = std::atoi(next().c_str());
else if (a == "--probe-mib") o.probeMib = std::atoi(next().c_str());
@ -1060,12 +1182,13 @@ static Options parseArgs(int argc, char** argv) {
}
if (o.batchLog2 < 10 || o.batchLog2 > 28) { std::printf("--batch-log2 must be between 10 and 28\n"); std::exit(2); }
if (o.blockWarps < 1 || o.blockWarps > 32) { std::printf("--block-warps must be between 1 and 32\n"); std::exit(2); }
if (!o.serve && !o.check && !o.raceOnly && !o.bench && !o.memprobe) { usage(); std::exit(2); }
if (!o.serve && !o.check && !o.raceOnly && !o.bench && !o.memprobe && !o.microbench && !o.listRace) { usage(); std::exit(2); }
if (o.mbSeconds < 5 || o.mbSeconds > 600) { std::printf("--mb-seconds must be between 5 and 600\n"); std::exit(2); }
if (o.raceBenchMs < 200 || o.raceBenchMs > 20000) { std::printf("--race-bench-ms must be between 200 and 20000\n"); std::exit(2); }
if (o.raceBudgetS < 5 || o.raceBudgetS > 540) { std::printf("--race-budget-s must be between 5 and 540 (the prepare lead is 600 DAA)\n"); std::exit(2); }
if (o.raceRounds == 0) o.raceRounds = o.raceOnly ? 3 : 1;
if (o.tuningPath.empty()) if (const char* t = std::getenv("IGNEUM_TUNING_FILE")) o.tuningPath = t;
if (o.pack.empty() && !o.memprobe) { std::printf("--pack <dir> is required (igneum-miner export-pack <node> <dir> writes one)\n"); std::exit(2); }
if (o.pack.empty() && !o.memprobe && !o.microbench && !o.listRace) { std::printf("--pack <dir> is required (igneum-miner export-pack <node> <dir> writes one)\n"); std::exit(2); }
while (o.pack.size() > 1 && (o.pack.back() == '/' || o.pack.back() == '\\')) o.pack.pop_back();
return o;
}
@ -1287,7 +1410,7 @@ static uint64_t fnv1a64Bytes(const void* p, size_t n) {
// cuStreamSynchronize (the driver API path loads no event symbols; a 2^24 dispatch is 60 to 900 ms on the cards here,
// so the launch overhead is under 1 percent).
static int runBench(Ctx& c, const Options& o, Pair* p) {
uint32_t nonces = 1u << o.batchLog2, block = 32u * (uint32_t)c.blockWarps;
uint32_t nonces = 1u << o.batchLog2, block = 32u * (uint32_t)p->blockWarps;
if (p->persistent) { uint32_t unit = 32u * (uint32_t)p->warps; nonces = (nonces / unit) * unit; if (nonces == 0) nonces = unit; }
CUdeviceptr dOut = 0;
std::string err;
@ -1310,10 +1433,11 @@ static int runBench(Ctx& c, const Options& o, Pair* p) {
c.drv.memFree(dOut);
std::string dev = c.name; for (char& ch : dev) if (ch == ' ') ch = '_';
std::printf("warm-up dispatch (base 0): %.2f ms; %d timed dispatches of %u nonces: mean %.2f ms\n", warm, o.batches, nonces, sum / o.batches);
std::printf("RESULT pack=%s class=%s device=%s arch=%s regs=%d blocks_per_sm=%d warps=%d resident=%d arena_mib=%llu hot_mib=%u hot_slots=%u hot_fill_ms=%.2f nonces=%u batches=%d check=%s fingerprint=%016llx mhs=%.3f loads=%u bytes=%u scratch_ops=%u time=wall\n",
std::printf("RESULT pack=%s class=%s device=%s arch=%s regs=%d blocks_per_sm=%d warps=%d resident=%d arena_mib=%llu hot_mib=%u hot_slots=%u hot_fill_ms=%.2f nonces=%u batches=%d check=%s fingerprint=%016llx mhs=%.3f loads=%u bytes=%u scratch_ops=%u variant=%s sparse_blocks=%d block_warps=%d time=wall\n",
p->dir.c_str(), p->loadClass.c_str(), dev.c_str(), c.archOpt.c_str(), p->regs, p->blocksPerSM, p->warps, p->residentWarps, (unsigned long long)(p->scratchBytes >> 20), p->hotMb, p->hotSlots, p->hotMs, nonces, o.batches,
p->checked ? (p->checkPass ? "PASS" : "FAIL") : "skipped", (unsigned long long)fp, (double)nonces * (double)o.batches / (sum / 1000.0) / 1e6,
p->loadsPerHash, p->bytesPerHash, p->scratchOps * 8u);
p->loadsPerHash, p->bytesPerHash, p->scratchOps * 8u, p->variant.c_str(), p->sparseBlocks, p->blockWarps);
if (!o.pinned.empty() && p->variant != o.pinned) std::printf("RESULT variant_not_installed requested=%s served=%s race=\"%s\"\n", o.pinned.c_str(), p->variant.c_str(), p->raceLine.c_str());
return 0;
}
@ -1460,14 +1584,267 @@ static int runMemprobe(Ctx& c, const Options& o) {
return 0;
}
// ---------------------------------------------------------------------------------------------
// Counter ASIC 4.0 research, 7 October 2026: --microbench. One kernel per GPU hardware block that gaming and AI
// already paid for, each run sustained for --mb-seconds at full residency so a 1 Hz power sampler reads its watts, with
// the counted operations per second beside it, so the energy per operation on this card is (watts minus the sleeping
// floor) over operations per second. Every probe prints one RESULT line with UTC start and end stamps and a checksum of
// its outputs. Probes compile one at a time, so a form the card or NVRTC refuses (an FP8 tile on a card under sm_89,
// a texture the driver cannot bind) drops that probe alone with its error on the row. Nothing here touches a pack.
struct MicroProbe {
const char* name; // the row's name
const char* unit; // what one counted operation is
double opsPerStep; // counted operations per lane per step
uint32_t steps; // steps per launch (sized so one launch is 50 ms to 2 s on a 5090, approximate)
int tableMib; // a table of uint32 the kernel reads (0 = none); filled by kb_fill mode 0 (or 1 = floats in [0,1))
int tableMode;
int tex; // 0 none; 1 a point-sampled u32 texture over the table; 2 a linearly filtered float texture over it
const char* body; // the kernel body: has steps, seed, out, tbl, mask, tex, g (the lane), x0..x3 (mixed seeds)
};
static const char* MICRO_PRELUDE =
"#include <cstdint>\n"
"__device__ __forceinline__ uint32_t kb_mix(uint32_t x) { x ^= x >> 16; x *= 0x7feb352du; x ^= x >> 15; x *= 0x846ca68bu; x ^= x >> 16; return x; }\n"
"__device__ __forceinline__ uint32_t kb_rotl(uint32_t x, uint32_t r) { return (x << r) | (x >> (32u - r)); }\n"
"extern \"C\" __global__ void kb_fill(uint32_t* t, uint32_t n, uint32_t mode) { uint32_t i = blockIdx.x * blockDim.x + threadIdx.x; if (i >= n) return;\n"
" uint32_t v = kb_mix(i ^ 0x9E3779B9u); if (mode == 1u) { float f = (float)(v >> 8) * (1.0f / 16777216.0f); t[i] = __float_as_uint(f); } else t[i] = v; }\n"
"#define KB_KERNEL(NAME) extern \"C\" __global__ void NAME(uint32_t steps, uint32_t seed, uint32_t* out, const uint32_t* tbl, uint32_t mask, unsigned long long tex) {\\\n"
" uint32_t g = blockIdx.x * blockDim.x + threadIdx.x; uint32_t x0 = kb_mix(g * 4u ^ seed), x1 = kb_mix((g * 4u + 1u) ^ seed), x2 = kb_mix((g * 4u + 2u) ^ seed), x3 = kb_mix((g * 4u + 3u) ^ seed);\n";
// Tensor tiles: the dependency carries the accumulator back into the A fragment so the chain is real; two tiles per step for issue overlap.
#define KB_MMA2(INSTR, NA, NB, NC, ATY) \
" uint32_t a0 = x0, a1 = x1, a2 = x2, a3 = x3, b0 = x1 ^ 0x5bd1e995u, b1 = x2 * 0x27d4eb2fu; " ATY " c0 = 0, c1 = 0, c2 = 0, c3 = 0, e0 = 0, e1 = 0, e2 = 0, e3 = 0;\n" \
" for (uint32_t s = 0u; s < steps; ++s) {\n" \
" asm volatile(\"" INSTR "\" : \"=r\"(c0), \"=r\"(c1), \"=r\"(c2), \"=r\"(c3) : \"r\"(a0), \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(b0), \"r\"(b1), \"r\"(c0), \"r\"(c1), \"r\"(c2), \"r\"(c3));\n" \
" asm volatile(\"" INSTR "\" : \"=r\"(e0), \"=r\"(e1), \"=r\"(e2), \"=r\"(e3) : \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(a0), \"r\"(b1), \"r\"(b0), \"r\"(e0), \"r\"(e1), \"r\"(e2), \"r\"(e3));\n" \
" a0 ^= (uint32_t)c0 + s; a1 ^= (uint32_t)e1; a2 += (uint32_t)c2; a3 ^= (uint32_t)e3 * 0x9E3779B1u;\n" \
" }\n" \
" out[g] = (uint32_t)c0 ^ (uint32_t)c1 ^ (uint32_t)c2 ^ (uint32_t)c3 ^ (uint32_t)e0 ^ (uint32_t)e1 ^ (uint32_t)e2 ^ (uint32_t)e3;\n}\n"
static const MicroProbe MICRO_PROBES[] = {
{ "sleep", "none (the SM-resident floor: full occupancy, __nanosleep, no issue)", 0, 2000, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { __nanosleep(1000); x0 += s; }\n out[g] = x0;\n}\n" },
{ "int_arx", "int32 add, xor or rotate (4 independent chains, 3 ops each per step)", 12, 16384, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = kb_rotl(x0 + x1, 7u) ^ s; x1 = kb_rotl(x1 + x2, 13u) ^ x0; x2 = kb_rotl(x2 + x3, 17u) ^ x1; x3 = kb_rotl(x3 + x0, 23u) ^ x2; }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "int_mul", "int32 multiply-add (4 independent chains)", 4, 16384, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = x0 * 0x9E3779B1u + s; x1 = x1 * 0x85EBCA77u + x0; x2 = x2 * 0xC2B2AE3Du + x1; x3 = x3 * 0x27D4EB2Fu + x2; }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "int_mulhi", "int32 high multiply (4 independent chains)", 4, 16384, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = __umulhi(x0, 0x9E3779B1u) + s; x1 = __umulhi(x1, x0 | 1u) ^ x1; x2 = __umulhi(x2, 0xC2B2AE3Du) + x1; x3 = __umulhi(x3, x2 | 1u) ^ x3; }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "prmt", "byte permute, __byte_perm (4 independent chains)", 4, 16384, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = __byte_perm(x0, x1, 0x2103u ^ (s & 7u)); x1 = __byte_perm(x1, x2, 0x3012u); x2 = __byte_perm(x2, x3, 0x1230u); x3 = __byte_perm(x3, x0, 0x0321u) + s; }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "lop3", "three-input logic (and, or, xor fused to one LOP3; 4 independent chains)", 4, 16384, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = (x0 & x1) ^ (x2 | s); x1 = (x1 & x2) ^ (x3 | x0); x2 = (x2 & x3) ^ (x0 | x1); x3 = (x3 & x0) ^ (x1 | x2); }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "shfl", "warp shuffle, __shfl_xor_sync (4 independent chains, one xor each beside it)", 4, 8192, 0, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = __shfl_xor_sync(0xffffffffu, x0, (int)((s & 31u) | 1u)) ^ x1; x1 = __shfl_xor_sync(0xffffffffu, x1, 2) ^ x2; x2 = __shfl_xor_sync(0xffffffffu, x2, 4) ^ x3; x3 = __shfl_xor_sync(0xffffffffu, x3, 8) ^ x0; }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "fp32_fma", "FP32 fused multiply-add (4 independent chains)", 4, 16384, 0, 0, 0,
" float f0 = __uint_as_float((x0 & 0x007fffffu) | 0x3f800000u), f1 = __uint_as_float((x1 & 0x007fffffu) | 0x3f800000u), f2 = __uint_as_float((x2 & 0x007fffffu) | 0x3f800000u), f3 = __uint_as_float((x3 & 0x007fffffu) | 0x3f800000u);\n"
" for (uint32_t s = 0u; s < steps; ++s) { f0 = fmaf(f0, 0.999f, 0.5f); f1 = fmaf(f1, 1.001f, -0.5f); f2 = fmaf(f2, 0.998f, 0.25f); f3 = fmaf(f3, 1.002f, -0.25f); }\n out[g] = __float_as_uint(f0) ^ __float_as_uint(f1) ^ __float_as_uint(f2) ^ __float_as_uint(f3);\n}\n" },
{ "fp16x2_fma", "FP16 fused multiply-add, two per fma.rn.f16x2 (4 independent chains)", 8, 16384, 0, 0, 0,
" uint32_t h0 = (x0 & 0x03ff03ffu) | 0x3c003c00u, h1 = (x1 & 0x03ff03ffu) | 0x3c003c00u, h2 = (x2 & 0x03ff03ffu) | 0x3c003c00u, h3 = (x3 & 0x03ff03ffu) | 0x3c003c00u;\n"
" const uint32_t m = 0x3bff3bffu, a = 0x38003800u;\n"
" for (uint32_t s = 0u; s < steps; ++s) { asm volatile(\"fma.rn.f16x2 %0, %0, %1, %2;\" : \"+r\"(h0) : \"r\"(m), \"r\"(a)); asm volatile(\"fma.rn.f16x2 %0, %0, %1, %2;\" : \"+r\"(h1) : \"r\"(m), \"r\"(a)); asm volatile(\"fma.rn.f16x2 %0, %0, %1, %2;\" : \"+r\"(h2) : \"r\"(m), \"r\"(a)); asm volatile(\"fma.rn.f16x2 %0, %0, %1, %2;\" : \"+r\"(h3) : \"r\"(m), \"r\"(a)); }\n"
" out[g] = h0 ^ h1 ^ h2 ^ h3;\n}\n" },
{ "mma_u8_m8n8k16", "int8 multiply-add inside mma.sync m8n8k16 u8 (1,024 per tile per warp, 32 per lane; two tiles per step)", 64, 8192, 0, 0, 0,
" uint32_t a0 = x0, b0 = x1, c0 = 0, c1 = 0, a1 = x2, b1 = x3, e0 = 0, e1 = 0;\n"
" for (uint32_t s = 0u; s < steps; ++s) {\n"
" asm volatile(\"mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};\" : \"=r\"(c0), \"=r\"(c1) : \"r\"(a0), \"r\"(b0), \"r\"(c0), \"r\"(c1));\n"
" asm volatile(\"mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};\" : \"=r\"(e0), \"=r\"(e1) : \"r\"(a1), \"r\"(b1), \"r\"(e0), \"r\"(e1));\n"
" a0 ^= c0 + s; b0 = kb_rotl(b0, 7u) ^ c1; a1 ^= e1; b1 = kb_rotl(b1, 5u) ^ e0;\n }\n out[g] = c0 ^ c1 ^ e0 ^ e1;\n}\n" },
{ "mma_s8_m16n8k32", "int8 multiply-add inside mma.sync m16n8k32 s8 (4,096 per tile per warp, 128 per lane; two tiles per step)", 256, 4096, 0, 0, 0,
KB_MMA2("mma.sync.aligned.m16n8k32.row.col.s32.s8.s8.s32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};", 4, 2, 4, "int32_t") },
{ "mma_f16_m16n8k16", "FP16 multiply-add with FP32 accumulate inside mma.sync m16n8k16 (2,048 per tile per warp, 64 per lane; two tiles per step)", 128, 4096, 0, 0, 0,
" uint32_t a0 = (x0 & 0x03ff03ffu) | 0x3c003c00u, a1 = (x1 & 0x03ff03ffu) | 0x3c003c00u, a2 = (x2 & 0x03ff03ffu) | 0x3c003c00u, a3 = (x3 & 0x03ff03ffu) | 0x3c003c00u, b0 = 0x3c003c00u ^ (x1 & 0x00ff00ffu), b1 = 0x3c003c00u ^ (x2 & 0x00ff00ffu);\n"
" float c0 = 0.f, c1 = 0.f, c2 = 0.f, c3 = 0.f, e0 = 0.f, e1 = 0.f, e2 = 0.f, e3 = 0.f;\n"
" for (uint32_t s = 0u; s < steps; ++s) {\n"
" asm volatile(\"mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(c0), \"=f\"(c1), \"=f\"(c2), \"=f\"(c3) : \"r\"(a0), \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(b0), \"r\"(b1), \"f\"(c0), \"f\"(c1), \"f\"(c2), \"f\"(c3));\n"
" asm volatile(\"mma.sync.aligned.m16n8k16.row.col.f32.f16.f16.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(e0), \"=f\"(e1), \"=f\"(e2), \"=f\"(e3) : \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(a0), \"r\"(b1), \"r\"(b0), \"f\"(e0), \"f\"(e1), \"f\"(e2), \"f\"(e3));\n"
" a0 = ((a0 ^ __float_as_uint(c0)) & 0x03ff03ffu) | 0x3c003c00u; a2 = ((a2 ^ __float_as_uint(e2)) & 0x03ff03ffu) | 0x3c003c00u; c0 *= 0.5f; c1 *= 0.5f; c2 *= 0.5f; c3 *= 0.5f; e0 *= 0.5f; e1 *= 0.5f; e2 *= 0.5f; e3 *= 0.5f;\n }\n"
" out[g] = __float_as_uint(c0) ^ __float_as_uint(c1) ^ __float_as_uint(c2) ^ __float_as_uint(c3) ^ __float_as_uint(e0) ^ __float_as_uint(e1) ^ __float_as_uint(e2) ^ __float_as_uint(e3);\n}\n" },
{ "mma_bf16_m16n8k16", "BF16 multiply-add with FP32 accumulate inside mma.sync m16n8k16 (64 per lane; two tiles per step)", 128, 4096, 0, 0, 0,
" uint32_t a0 = (x0 & 0x007f007fu) | 0x3f803f80u, a1 = (x1 & 0x007f007fu) | 0x3f803f80u, a2 = (x2 & 0x007f007fu) | 0x3f803f80u, a3 = (x3 & 0x007f007fu) | 0x3f803f80u, b0 = 0x3f803f80u ^ (x1 & 0x003f003fu), b1 = 0x3f803f80u ^ (x2 & 0x003f003fu);\n"
" float c0 = 0.f, c1 = 0.f, c2 = 0.f, c3 = 0.f, e0 = 0.f, e1 = 0.f, e2 = 0.f, e3 = 0.f;\n"
" for (uint32_t s = 0u; s < steps; ++s) {\n"
" asm volatile(\"mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(c0), \"=f\"(c1), \"=f\"(c2), \"=f\"(c3) : \"r\"(a0), \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(b0), \"r\"(b1), \"f\"(c0), \"f\"(c1), \"f\"(c2), \"f\"(c3));\n"
" asm volatile(\"mma.sync.aligned.m16n8k16.row.col.f32.bf16.bf16.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(e0), \"=f\"(e1), \"=f\"(e2), \"=f\"(e3) : \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(a0), \"r\"(b1), \"r\"(b0), \"f\"(e0), \"f\"(e1), \"f\"(e2), \"f\"(e3));\n"
" a0 = ((a0 ^ __float_as_uint(c0)) & 0x007f007fu) | 0x3f803f80u; a2 = ((a2 ^ __float_as_uint(e2)) & 0x007f007fu) | 0x3f803f80u; c0 *= 0.5f; c1 *= 0.5f; c2 *= 0.5f; c3 *= 0.5f; e0 *= 0.5f; e1 *= 0.5f; e2 *= 0.5f; e3 *= 0.5f;\n }\n"
" out[g] = __float_as_uint(c0) ^ __float_as_uint(c1) ^ __float_as_uint(c2) ^ __float_as_uint(c3) ^ __float_as_uint(e0) ^ __float_as_uint(e1) ^ __float_as_uint(e2) ^ __float_as_uint(e3);\n}\n" },
{ "mma_e4m3_m16n8k32", "FP8 e4m3 multiply-add with FP32 accumulate inside mma.sync m16n8k32 (4,096 per tile per warp, 128 per lane; two tiles per step; sm_89 and later)", 256, 4096, 0, 0, 0,
" uint32_t a0 = x0 & 0x7f7f7f7fu, a1 = x1 & 0x7f7f7f7fu, a2 = x2 & 0x7f7f7f7fu, a3 = x3 & 0x7f7f7f7fu, b0 = (x1 >> 1) & 0x3f3f3f3fu, b1 = (x2 >> 1) & 0x3f3f3f3fu;\n"
" float c0 = 0.f, c1 = 0.f, c2 = 0.f, c3 = 0.f, e0 = 0.f, e1 = 0.f, e2 = 0.f, e3 = 0.f;\n"
" for (uint32_t s = 0u; s < steps; ++s) {\n"
" asm volatile(\"mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(c0), \"=f\"(c1), \"=f\"(c2), \"=f\"(c3) : \"r\"(a0), \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(b0), \"r\"(b1), \"f\"(c0), \"f\"(c1), \"f\"(c2), \"f\"(c3));\n"
" asm volatile(\"mma.sync.aligned.m16n8k32.row.col.f32.e4m3.e4m3.f32 {%0,%1,%2,%3}, {%4,%5,%6,%7}, {%8,%9}, {%10,%11,%12,%13};\" : \"=f\"(e0), \"=f\"(e1), \"=f\"(e2), \"=f\"(e3) : \"r\"(a1), \"r\"(a2), \"r\"(a3), \"r\"(a0), \"r\"(b1), \"r\"(b0), \"f\"(e0), \"f\"(e1), \"f\"(e2), \"f\"(e3));\n"
" a0 = (a0 ^ __float_as_uint(c0)) & 0x7f7f7f7fu; a2 = (a2 ^ __float_as_uint(e2)) & 0x7f7f7f7fu; c0 *= 0.5f; c1 *= 0.5f; c2 *= 0.5f; c3 *= 0.5f; e0 *= 0.5f; e1 *= 0.5f; e2 *= 0.5f; e3 *= 0.5f;\n }\n"
" out[g] = __float_as_uint(c0) ^ __float_as_uint(c1) ^ __float_as_uint(c2) ^ __float_as_uint(c3) ^ __float_as_uint(e0) ^ __float_as_uint(e1) ^ __float_as_uint(e2) ^ __float_as_uint(e3);\n}\n" },
{ "l2_chase_32m", "dependent random 4-byte read in a 32 MiB table (L2-resident on a 5090's 96 MB; one chain per lane)", 1, 2048, 32, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) x0 = tbl[x0 & mask] ^ (x0 * 0x9E3779B1u + s);\n out[g] = x0;\n}\n" },
{ "l2_chase_64m", "dependent random 4-byte read in a 64 MiB table (inside a 5090's L2, outside a 4070's 36 MB)", 1, 2048, 64, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) x0 = tbl[x0 & mask] ^ (x0 * 0x9E3779B1u + s);\n out[g] = x0;\n}\n" },
{ "l2_indep4_32m", "random 4-byte read in a 32 MiB table, 4 independent chains per lane (L2 throughput)", 4, 2048, 32, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) { x0 = tbl[x0 & mask] ^ (x0 * 0x9E3779B1u + s); x1 = tbl[x1 & mask] ^ (x1 * 0x9E3779B1u + s); x2 = tbl[x2 & mask] ^ (x2 * 0x9E3779B1u + s); x3 = tbl[x3 & mask] ^ (x3 * 0x9E3779B1u + s); }\n out[g] = x0 ^ x1 ^ x2 ^ x3;\n}\n" },
{ "dram_chase_1g", "dependent random 4-byte read in a 1 GiB table (the hash's own pattern, the control)", 1, 512, 1024, 0, 0,
" for (uint32_t s = 0u; s < steps; ++s) x0 = tbl[x0 & mask] ^ (x0 * 0x9E3779B1u + s);\n out[g] = x0;\n}\n" },
{ "tex_point_u32_32m", "texture fetch, point sampled, tex.1d.v4.u32.s32 over a 32 MiB u32 table (the sampler's address path; dependent chain)", 1, 2048, 32, 0, 1,
" for (uint32_t s = 0u; s < steps; ++s) { int cx = (int)(x0 & mask); uint32_t t0, t1, t2, t3; asm volatile(\"tex.1d.v4.u32.s32 {%0,%1,%2,%3}, [%4, {%5}];\" : \"=r\"(t0), \"=r\"(t1), \"=r\"(t2), \"=r\"(t3) : \"l\"(tex), \"r\"(cx)); x0 = t0 ^ (x0 * 0x9E3779B1u + s); }\n out[g] = x0;\n}\n" },
{ "tex_linear_f32_256k", "texture fetch, linearly filtered, tex.1d.v4.f32.f32 over a 1 MiB float table (the sampler's interpolation; 4 independent chains)", 4, 4096, 1, 1, 2,
" float p0 = (float)(x0 & 0xffffu), p1 = (float)(x1 & 0xffffu), p2 = (float)(x2 & 0xffffu), p3 = (float)(x3 & 0xffffu);\n"
" for (uint32_t s = 0u; s < steps; ++s) { float t0, t1, t2, t3, u0, u1, u2, u3, v0, v1, v2, v3, w0, w1, w2, w3;\n"
" asm volatile(\"tex.1d.v4.f32.f32 {%0,%1,%2,%3}, [%4, {%5}];\" : \"=f\"(t0), \"=f\"(t1), \"=f\"(t2), \"=f\"(t3) : \"l\"(tex), \"f\"(p0));\n"
" asm volatile(\"tex.1d.v4.f32.f32 {%0,%1,%2,%3}, [%4, {%5}];\" : \"=f\"(u0), \"=f\"(u1), \"=f\"(u2), \"=f\"(u3) : \"l\"(tex), \"f\"(p1));\n"
" asm volatile(\"tex.1d.v4.f32.f32 {%0,%1,%2,%3}, [%4, {%5}];\" : \"=f\"(v0), \"=f\"(v1), \"=f\"(v2), \"=f\"(v3) : \"l\"(tex), \"f\"(p2));\n"
" asm volatile(\"tex.1d.v4.f32.f32 {%0,%1,%2,%3}, [%4, {%5}];\" : \"=f\"(w0), \"=f\"(w1), \"=f\"(w2), \"=f\"(w3) : \"l\"(tex), \"f\"(p3));\n"
" p0 = fmaf(t0, 65535.0f, 0.37f); p1 = fmaf(u0, 65535.0f, 0.61f); p2 = fmaf(v0, 65535.0f, 0.13f); p3 = fmaf(w0, 65535.0f, 0.89f); }\n"
" out[g] = __float_as_uint(p0) ^ __float_as_uint(p1) ^ __float_as_uint(p2) ^ __float_as_uint(p3);\n}\n" },
};
static std::string utcNow() {
std::time_t t = std::time(nullptr); char b[32]; std::strftime(b, sizeof b, "%Y-%m-%dT%H:%M:%SZ", std::gmtime(&t)); return b;
}
static int runMicrobench(Ctx& c, const Options& o) {
std::printf("microbench on %s (sm_%d%d, %d SMs, driver %d.%d, NVRTC %d.%d): %d s per probe, full residency, wall time around cuStreamSynchronize; a 1 Hz power sampler aligns on start_utc and end_utc\n",
c.name.c_str(), c.major, c.minor, c.sms, c.driverVersion / 1000, (c.driverVersion % 100) / 10, c.rtcMajor, c.rtcMinor, o.mbSeconds);
const size_t local = 256;
CUdeviceptr dOut = 0;
const size_t maxLanes = (size_t)(c.sms > 0 ? c.sms : 1) * 2048u;
if (c.drv.memAlloc(&dOut, maxLanes * 4u) != CUDA_SUCCESS) { std::printf("microbench: cuMemAlloc out\n"); return 2; }
std::vector<uint32_t> hOut(maxLanes);
int ran = 0, failed = 0;
for (const MicroProbe& pr : MICRO_PROBES) {
if (!o.mbOnly.empty() && ("," + o.mbOnly + ",").find(std::string(",") + pr.name + ",") == std::string::npos) continue;
std::string src = std::string(MICRO_PRELUDE) + "KB_KERNEL(kb_probe)\n" + pr.body;
Compiled cp; std::string err;
if (!rtcCompile(c, src, (std::string(pr.name) + ".cu").c_str(), "", "", {}, cp, err)) {
std::string e = err; for (char& ch : e) if (ch == '\n') ch = ' ';
std::printf("RESULT microbench probe=%s status=compile_failed error=\"%.300s\"\n", pr.name, e.c_str()); ++failed; std::fflush(stdout); continue;
}
CUmodule mod = nullptr; CUfunction kFill = nullptr, kProbe = nullptr;
if (c.drv.moduleLoadData(&mod, cp.image.data()) != CUDA_SUCCESS || c.drv.moduleGetFunction(&kFill, mod, "kb_fill") != CUDA_SUCCESS || c.drv.moduleGetFunction(&kProbe, mod, "kb_probe") != CUDA_SUCCESS) {
std::printf("RESULT microbench probe=%s status=load_failed\n", pr.name); ++failed; std::fflush(stdout); if (mod) c.drv.moduleUnload(mod); continue;
}
int blocksPerSM = 0; c.drv.occupancy(&blocksPerSM, kProbe, (int)local, 0);
if (blocksPerSM < 1) blocksPerSM = 1;
size_t lanes = (size_t)blocksPerSM * local * (size_t)(c.sms > 0 ? c.sms : 1);
if (lanes > maxLanes) lanes = maxLanes;
int regs = 0; c.drv.funcGetAttribute(&regs, CU_FUNC_ATTRIBUTE_NUM_REGS, kProbe);
CUdeviceptr dTbl = 0; uint32_t mask = 0; unsigned long long tex = 0; CUtexObject texObj = 0; bool ok = true; std::string why;
if (pr.tableMib > 0) {
uint64_t bytes = (uint64_t)pr.tableMib << 20; uint32_t words = (uint32_t)(bytes / 4ull); mask = words - 1u;
if (c.drv.memAlloc(&dTbl, (size_t)bytes) != CUDA_SUCCESS) { ok = false; why = "cuMemAlloc table"; }
else { uint32_t n = words, mode = (uint32_t)pr.tableMode; void* a[3] = { &dTbl, &n, &mode };
if (c.drv.launchKernel(kFill, (unsigned)((words + 255u) / 256u), 1, 1, 256, 1, 1, 0, nullptr, a, nullptr) != CUDA_SUCCESS || c.drv.streamSynchronize(nullptr) != CUDA_SUCCESS) { ok = false; why = "fill"; } }
}
if (ok && pr.tex > 0) {
if (!c.drv.texObjectCreate || !c.drv.texObjectDestroy) { ok = false; why = "the driver has no cuTexObjectCreate"; }
else {
CUDA_RESOURCE_DESC rd; std::memset(&rd, 0, sizeof rd); rd.resType = CU_RESOURCE_TYPE_LINEAR;
rd.res.linear.devPtr = dTbl; rd.res.linear.format = pr.tex == 1 ? CU_AD_FORMAT_UNSIGNED_INT32 : CU_AD_FORMAT_FLOAT; rd.res.linear.numChannels = 1; rd.res.linear.sizeInBytes = (size_t)pr.tableMib << 20;
CUDA_TEXTURE_DESC td; std::memset(&td, 0, sizeof td);
td.addressMode[0] = CU_TR_ADDRESS_MODE_CLAMP; td.addressMode[1] = CU_TR_ADDRESS_MODE_CLAMP; td.addressMode[2] = CU_TR_ADDRESS_MODE_CLAMP;
td.filterMode = pr.tex == 1 ? CU_TR_FILTER_MODE_POINT : CU_TR_FILTER_MODE_LINEAR; td.flags = pr.tex == 1 ? CU_TRSF_READ_AS_INTEGER : 0;
CUresult r = c.drv.texObjectCreate(&texObj, &rd, &td, nullptr);
if (r != CUDA_SUCCESS) { ok = false; why = "cuTexObjectCreate: " + c.err(r); } else tex = (unsigned long long)texObj;
}
}
if (ok) {
uint32_t steps = pr.steps, seed = 0x51ed270bu; void* a[6] = { &steps, &seed, &dOut, &dTbl, &mask, &tex };
// warm-up (also the checksum's launch)
CUresult r = c.drv.launchKernel(kProbe, (unsigned)(lanes / local), 1, 1, (unsigned)local, 1, 1, 0, nullptr, a, nullptr);
if (r == CUDA_SUCCESS) r = c.drv.streamSynchronize(nullptr);
if (r != CUDA_SUCCESS) { ok = false; why = "warm-up: " + c.err(r); }
else {
c.drv.memcpyDtoH(hOut.data(), dOut, lanes * 4u);
uint64_t fp = fnv1a64Bytes(hOut.data(), lanes * 4u);
std::string start = utcNow(); double t0 = wallMs(); uint64_t launches = 0; double last = 0;
while (true) {
double l0 = wallMs();
seed += 0x9E3779B9u;
if (c.drv.launchKernel(kProbe, (unsigned)(lanes / local), 1, 1, (unsigned)local, 1, 1, 0, nullptr, a, nullptr) != CUDA_SUCCESS || c.drv.streamSynchronize(nullptr) != CUDA_SUCCESS) { ok = false; why = "launch"; break; }
last = wallMs() - l0; ++launches;
if (wallMs() - t0 >= o.mbSeconds * 1000.0) break;
}
double secs = (wallMs() - t0) / 1000.0; std::string end = utcNow();
if (ok) {
double stepsPerS = (double)lanes * (double)pr.steps * (double)launches / secs;
std::printf("RESULT microbench probe=%s status=ok unit=\"%s\" ops_per_step=%g lanes=%zu regs=%d blocks_per_sm=%d steps=%u launches=%llu launch_ms=%.1f seconds=%.1f start_utc=%s end_utc=%s G_steps_s=%.3f G_ops_s=%.3f checksum=%016llx\n",
pr.name, pr.unit, pr.opsPerStep, lanes, regs, blocksPerSM, pr.steps, (unsigned long long)launches, last, secs, start.c_str(), end.c_str(), stepsPerS / 1e9, stepsPerS * pr.opsPerStep / 1e9, (unsigned long long)fp);
++ran;
}
}
}
if (!ok) { std::printf("RESULT microbench probe=%s status=skipped why=\"%s\"\n", pr.name, why.c_str()); ++failed; }
std::fflush(stdout);
if (texObj) c.drv.texObjectDestroy(texObj);
if (dTbl) c.drv.memFree(dTbl);
c.drv.moduleUnload(mod);
}
c.drv.memFree(dOut);
std::printf("microbench: done, %d probes ran, %d skipped or failed\n", ran, failed);
return failed > 0 && ran == 0 ? 2 : 0;
}
int main(int argc, char** argv) {
Options o = parseArgs(argc, argv);
Ctx c;
c.blockWarps = o.blockWarps;
c.race = o.race; c.raceBenchMs = o.raceBenchMs; c.raceBudgetS = o.raceBudgetS; c.raceRounds = o.raceRounds; c.batchLog2 = o.batchLog2; c.pinned = o.pinned;
c.warps = o.warps; c.batches = o.batches;
if (o.bench || o.memprobe) c.race = "off";
// --bench runs the pack's base kernel with no race; with --variant <name> (Counter ASIC 4.0 research, 8 October 2026:
// the SM-sparse job of 7 October ran 48 rows on base because --bench turned the race off and buildPair never raced) it
// runs the pinned race instead: base and the named variant only, no timing, the variant installed whatever its speed,
// so the bench reads that kernel; the race line names it
if (benchRaceOff(o.bench || o.memprobe || o.microbench, o.pinned)) c.race = "off";
if (!o.tuningPath.empty()) { bool ok = false; c.tuning = readText(o.tuningPath, ok); if (!ok) c.tuning.clear(); }
if (o.listRace) {
// Counter ASIC 4.0 research (8 October 2026, the third fix of the --bench --variant fault): the race order as the
// bench's own option handling builds it, with no device: "variants 2" with the named variant is the pass line,
// "variants 1 base only" the 02:52Z fault; with a pack the rewrite is applied to the bound kernel and reported
bool raceOff = benchRaceOff(o.bench || o.memprobe || o.microbench, o.pinned);
std::vector<Variant> all = allVariants();
Tuning tu = readTuning(c.tuning, "");
std::string pinned = !o.pinned.empty() ? o.pinned : (tu.found && !tu.race ? tu.variant : "");
std::vector<Variant> order = raceOff ? std::vector<Variant>{ *findVariant(all, "base") } : raceOrder(all, pinned, tu, c.race);
std::string names;
for (const Variant& v : order) names += (names.empty() ? "" : ",") + v.name;
std::printf("RESULT list-race bench=%d race_off=%d pinned=%s variants=%zu names=%s\n", o.bench ? 1 : 0, raceOff ? 1 : 0, pinned.c_str(), order.size(), names.c_str());
bool ok = pinned.empty() || (order.size() >= 2 && order.back().name == pinned);
if (!o.pack.empty() && !pinned.empty()) {
bool rok = true; std::string text = readText(o.pack + "/kernel_bound.cu", rok), dev, err2, src, why;
const Variant* v = findVariant(all, pinned);
bool rewritten = rok && v && deviceOnly(text, dev, err2) && variantSource(dev, *v, v->blockWarps > 0 ? v->blockWarps : o.blockWarps, src, why);
std::printf("RESULT list-race pack=%s variant=%s sparse_blocks=%d block_warps=%d rewrite=%s bytes=%zu nonces_arg=%d unit_fn=%d why=\"%s\"\n", o.pack.c_str(), pinned.c_str(), v ? v->sparseBlocks : 0, v ? (v->blockWarps > 0 ? v->blockWarps : o.blockWarps) : 0,
rewritten ? "applied" : "none", src.size(), rewritten && src.find(", uint32_t nonces) {") != std::string::npos ? 1 : 0, rewritten && src.find("igneum_hash_bound_unit(") != std::string::npos ? 1 : 0, why.empty() ? err2.c_str() : why.c_str());
ok = ok && rewritten;
if (rewritten && v && v->sparseBlocks > 0) {
// the wrapper's call against the unit function's parameters, name by name (the 03:23Z fault: every
// argument one character short), then the whole rewritten text through NVRTC when its library is here
size_t u = src.find("void igneum_hash_bound_unit("), uc = u == std::string::npos ? u : src.find(")", u);
size_t cl = src.rfind("igneum_hash_bound_unit("), cc = cl == std::string::npos ? cl : src.find(")", cl);
std::string params = u == std::string::npos ? "" : src.substr(u + 27, uc - (u + 27)), call = cl == std::string::npos ? "" : src.substr(cl + 23, cc - (cl + 23));
auto names = [](const std::string& list, bool lastToken) { std::vector<std::string> out; size_t i = 0; while (i <= list.size()) { size_t j = list.find(',', i); if (j == std::string::npos) j = list.size(); std::string one = list.substr(i, j - i); size_t e = one.find_last_not_of(" \t"); if (e != std::string::npos) { size_t b = lastToken ? one.find_last_of(" \t*&", e) : std::string::npos; size_t st = b == std::string::npos ? one.find_first_not_of(" \t") : b + 1; out.push_back(one.substr(st, e - st + 1)); } i = j + 1; } return out; };
std::vector<std::string> pn = names(params, true), cn = names(call, false);
bool match = pn.size() == cn.size() && !pn.empty();
for (size_t i = 0; match && i < pn.size(); ++i) if (pn[i] != cn[i]) match = false;
std::printf("RESULT list-race call=\"igneum_hash_bound_unit(%s)\" params=%zu args=%zu names_match=%d\n", call.c_str(), pn.size(), cn.size(), match ? 1 : 0);
ok = ok && match;
std::string rerr, rlib;
if (loadNvrtc(c.rtc, rerr, rlib)) {
c.archOpt = "sm_120"; c.rtcMajor = 12; c.rtcMinor = 8;
Compiled cb; std::string cerr;
bool pr = true; std::string programH = readText(o.pack + "/program.h", pr), memhardH = readText(o.pack + "/memhard.h", pr);
bool compiled = pr && rtcCompile(c, src, "kernel_bound.cu", programH, memhardH, { "igneum_hash_bound" }, cb, cerr);
for (char& ch : cerr) if (ch == '\n') ch = ' ';
std::printf("RESULT list-race nvrtc=%s arch=sm_120 compiled=%d image_bytes=%zu error=\"%.400s\"\n", rlib.c_str(), compiled ? 1 : 0, cb.image.size(), cerr.c_str());
ok = ok && compiled;
} else {
std::printf("RESULT list-race nvrtc=none (%s): the rewritten text was not compiled here\n", rerr.c_str());
}
}
}
return ok ? 0 : 1;
}
std::string err, drvLib, rtcLib;
if (!loadDriver(c.drv, err, drvLib)) { emit("error 0 " + err); return 2; }
if (!loadNvrtc(c.rtc, err, rtcLib)) { emit("error 0 " + err); return 2; }
@ -1476,8 +1853,9 @@ int main(int argc, char** argv) {
WORKER_VERSION, o.device, c.name.c_str(), c.major, c.minor, c.sms, c.driverVersion / 1000, (c.driverVersion % 100) / 10, drvLib.c_str(), c.rtcMajor, c.rtcMinor, rtcLib.c_str(), c.archOpt.c_str(), c.why.c_str()));
if (!c.tuning.empty()) info(fmt("tuning file %s (%zu bytes): %s", o.tuningPath.c_str(), c.tuning.size(), readTuning(c.tuning, c.name).found ? "has an entry for this card" : "no entry for this card"));
if (o.memprobe) { int rc = runMemprobe(c, o); c.drv.primaryCtxRelease(c.dev); return rc; }
if (o.microbench) { int rc = runMicrobench(c, o); c.drv.primaryCtxRelease(c.dev); return rc; }
double t0 = wallMs();
Pair* cur = buildPair(c, o.pack, nullptr, err, !o.check && !o.bench);
Pair* cur = buildPair(c, o.pack, nullptr, err, !o.check && !benchRaceOff(o.bench, o.pinned));
if (!cur) { emit("error 0 " + err); return 1; }
if (o.bench) {
std::printf("pack %s on %s: %s\n", o.pack.c_str(), c.name.c_str(), pairSummary(cur).c_str());

415
proto-cuda/packs-ca4/mx8_mm128/kernel.cl Normal file
View file

@ -0,0 +1,415 @@
// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = sub_group_shuffle((a), (uint)(i))
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = intel_sub_group_shuffle((a), (uint)(i))
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#define IGNEUM_SHFL_IDX(dst, a, i) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u) + (uint)(i)]; xk += 1u; }
#endif
// int8 tile reference (Counter ASIC 4.0 research): 12 index shuffles and 32 byte products per lane; the PTX mma.m8n8k16 u8 layout.
#define IGNEUM_MM8_REF(av, bv, d0, d1) { uint row_ = lane >> 2, col0_ = 2u * (lane & 3u); uint acc0_ = 0u, acc1_ = 0u; for (uint j_ = 0u; j_ < 4u; ++j_) { uint aw_, bw0_, bw1_; IGNEUM_SHFL_IDX(aw_, (av), 4u * row_ + j_); IGNEUM_SHFL_IDX(bw0_, (bv), 4u * col0_ + j_); IGNEUM_SHFL_IDX(bw1_, (bv), 4u * (col0_ + 1u) + j_); for (uint t_ = 0u; t_ < 4u; ++t_) { uint ab_ = (aw_ >> (8u * t_)) & 0xffu; acc0_ += ab_ * ((bw0_ >> (8u * t_)) & 0xffu); acc1_ += ab_ * ((bw1_ >> (8u * t_)) & 0xffu); } } d0 = acc0_; d1 = acc1_; }
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, uint t, uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, t, s);
__global uint* d = ds + ((ulong)t * 16u);
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
uint lane = lid & 31u;
{ uint x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Bit-exact twin of the Metal kernel for the same seed (see proto-cuda/CHECKLIST.md and program.metal).
// Compiled ahead of time by nvcc together with proto-cuda/host.cu. No NVRTC.
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
#include "memhard.h"
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site, so both shift amounts are in 1..31.
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
// n is masked to 0..31; the second shift amount is masked too, so n == 0 gives x.
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__device__ __forceinline__ uint32_t ds_elem(uint32_t i, uint32_t d0, uint32_t d1) {
uint32_t x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset (MEMHARD.md). One thread per cache segment; one thread per 64-byte dataset item.
// The core functions (mh_cache_segment, mh_item) are in memhard.h and are also compiled for the host.
__global__ void igneum_cache_fill(uint32_t* cache, uint32_t nSegments) {
uint32_t seg = blockIdx.x * blockDim.x + threadIdx.x;
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
uint32_t t = blockIdx.x * blockDim.x + threadIdx.x;
if (t < nItems) {
uint32_t s[16];
mh_item(cache, t, s);
uint32_t* d = ds + (size_t)t * 16u;
for (uint32_t i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per thread. blockDim.x is a multiple of 32; lane = threadIdx.x & 31 and every
// __shfl_xor_sync stays inside the lane's own warp, exactly like simd_shuffle_xor inside a
// 32-wide Metal SIMD group. Control flow is uniform, so the full 0xffffffff member mask is valid.
__global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint32_t x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint32_t x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint32_t x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint32_t x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint32_t x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint32_t x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint32_t x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
// Host-side launch wrappers. Declared in program.h, called from host.cu.
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments) {
if (nSegments == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nSegments + block - 1u) / block;
igneum_cache_fill<<<grid, block>>>(cache, nSegments);
return cudaGetLastError();
}
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
if (nItems == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nItems + block - 1u) / block;
igneum_build<<<grid, block>>>(ds, cache, nItems);
return cudaGetLastError();
}
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash<<<nonces / block, block>>>(ds, out, baseNonce, mask);
return cudaGetLastError();
}
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = sub_group_shuffle((a), (uint)(i))
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = intel_sub_group_shuffle((a), (uint)(i))
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#define IGNEUM_SHFL_IDX(dst, a, i) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u) + (uint)(i)]; xk += 1u; }
#endif
// int8 tile reference (Counter ASIC 4.0 research): 12 index shuffles and 32 byte products per lane; the PTX mma.m8n8k16 u8 layout.
#define IGNEUM_MM8_REF(av, bv, d0, d1) { uint row_ = lane >> 2, col0_ = 2u * (lane & 3u); uint acc0_ = 0u, acc1_ = 0u; for (uint j_ = 0u; j_ < 4u; ++j_) { uint aw_, bw0_, bw1_; IGNEUM_SHFL_IDX(aw_, (av), 4u * row_ + j_); IGNEUM_SHFL_IDX(bw0_, (bv), 4u * col0_ + j_); IGNEUM_SHFL_IDX(bw1_, (bv), 4u * (col0_ + 1u) + j_); for (uint t_ = 0u; t_ < 4u; ++t_) { uint ab_ = (aw_ >> (8u * t_)) & 0xffu; acc0_ += ab_ * ((bw0_ >> (8u * t_)) & 0xffu); acc1_ += ab_ * ((bw1_ >> (8u * t_)) & 0xffu); } } d0 = acc0_; d1 = acc1_; }
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, uint t, uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, t, s);
__global uint* d = ds + ((ulong)t * 16u);
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
uint lane = lid & 31u;
{ uint x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif
// Header-bound variant (bind.rs): the init words come from initw, not SEEDW. Same body as igneum_hash.
IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask, __global const uint* initw) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint iw0 = initw[0], iw1 = initw[1], iw2 = initw[2], iw3 = initw[3], iw4 = initw[4], iw5 = initw[5], iw6 = initw[6], iw7 = initw[7];
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
uint lane = lid & 31u;
{ uint x = nonce ^ iw0; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw1; }
{ uint x = nonce ^ iw1; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw2; }
{ uint x = nonce ^ iw2; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw3; }
{ uint x = nonce ^ iw3; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw4; }
{ uint x = nonce ^ iw4; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw5; }
{ uint x = nonce ^ iw5; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw6; }
{ uint x = nonce ^ iw6; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw7; }
{ uint x = nonce ^ iw7; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw0; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
// Host declarations (also in program_bound.h if present):
// struct IgneumInitWords { uint32_t w[8]; };
// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
struct IgneumInitWords { uint32_t w[8]; };
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
return cudaGetLastError();
}
cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Memory-hard dataset core, the same text that the Mac's Metal kernels and CPU verifier were checked against.
// Included by kernel.cu (device), host.cu (host reference) and proto-opencl/host.c (C99 host reference).
// See proto-metal/MEMHARD.md for the construction. kernel.cl carries the same text in OpenCL C.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#if defined(__CUDACC__)
#define IGNEUM_HD __host__ __device__ __forceinline__
#elif defined(_MSC_VER) && !defined(__cplusplus)
#define IGNEUM_HD static __inline
#else
#define IGNEUM_HD static inline
#endif
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
IGNEUM_HD uint32_t mh_rotl(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
IGNEUM_HD void mh_chacha_block(const uint32_t* x, uint32_t* y) {
for (uint32_t i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint32_t r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint32_t i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
IGNEUM_HD void mh_cache_segment(uint32_t* cache, uint32_t seg) {
uint32_t prev[16]; uint32_t x[16]; uint32_t y[16];
for (uint32_t i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint32_t j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
uint32_t* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
IGNEUM_HD void mh_mixer(uint32_t* s, uint32_t rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint32_t r = 0u; r < 8u; ++r) {
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
const uint32_t* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }

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#include <metal_stdlib>
using namespace metal;
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
inline void mh_chacha_block(const thread uint* x, thread uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
inline void mh_cache_segment(device uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
device uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
inline void mh_mixer(thread uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
inline void mh_item(device const uint* cache, uint t, thread uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
device const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// One thread per segment (2^16 threads).
kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) {
mh_cache_segment(cache, gid);
}
// One thread per 64-byte item (dataset words / 16 threads).
kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* dataset [[buffer(1)]],
uint gid [[thread_position_in_grid]]) {
uint s[16];
mh_item(cache, gid, s);
device uint* d = dataset + gid * 16u;
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Program metadata for host.cu plus the launch wrappers defined in kernel.cu.
// Also included by proto-opencl/host.c (C99), which defines IGNEUM_NO_CUDA first and reads only the macros.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#ifndef IGNEUM_NO_CUDA
#include <cuda_runtime.h>
#endif
#define IGNEUM_SEED_STRING "igneum-genesis"
#define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973"
#define IGNEUM_GENERATOR 2
#define IGNEUM_PROGRAM_ATTEMPT 0
#define IGNEUM_PROGRAM_ID 0xd6fc3093180e44f1ull
#define IGNEUM_DAY_STRING "2026-10-03"
#define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033"
#define IGNEUM_DAY0 0x3067619fu
#define IGNEUM_DAY1 0x3c269176u
#define IGNEUM_DATASET_LOG2 28
#define IGNEUM_MASK 0x0fffffffu
#define IGNEUM_LANES 32
#define IGNEUM_ITERATIONS 8
#define IGNEUM_INSTR_COUNT 64
#define IGNEUM_LOADS_PER_HASH 128
#define IGNEUM_WIDE_LOADS_PER_HASH 0
#define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1"
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
#define IGNEUM_LOAD_CLASS "mx8+mm128"
#define IGNEUM_CLASS_MIXER_MULT 8
#define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460))
#define IGNEUM_LOAD_SLOTS 16
#define IGNEUM_LOAD_MIX { 100, 0, 0 }
#define IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 } // loads of 4, 16, 64 bytes per program
#define IGNEUM_BYTES_PER_HASH 512
#define IGNEUM_FOLD_ROT 11
#define IGNEUM_FOLD_MUL 0x9e3779b1u
// Latency-shadow block (Counter ASIC 3.0 item 8, docs/analysis/latency-shadow-2026-10-06.md): NOT the lottery hash. A block of
// IGNEUM_SHADOW_INSTRS ALU instructions (the ten non-load families) runs IGNEUM_SHADOW_REPS times at the end of every
// iteration; the 16 loads, the acceptance rule and the base program are the class's without the shadow.
#define IGNEUM_SHADOW_INSTRS 0
#define IGNEUM_SHADOW_REPS 0
#define IGNEUM_SHADOW_INSTRS_PER_HASH 0
#define IGNEUM_SHADOW_OP_MIX ""
// Counter ASIC 4.0 research (experimental): IGNEUM_MM8_TILES int8 mma.m8n8k16 u8 tiles per iteration after the shadow block.
#define IGNEUM_MM8_TILES 128
#define IGNEUM_MM8_TILES_PER_HASH 1024
// 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h)
#define IGNEUM_DATASET_MODE 1
#define IGNEUM_SEEDW_INIT { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u }
#define IGNEUM_KEY_INIT { 0x3067619fu, 0x3c269176u, 0x84a03b03u, 0xf8c63294u, 0xff977c5bu, 0xe60def3eu, 0x63630141u, 0xb8fbcb58u }
#define IGNEUM_CACHE_LOG2_WORDS 26
#define IGNEUM_CACHE_SEGMENT_LOG2_LINES 6
#define IGNEUM_CACHE_SEGMENTS 65536u
#define IGNEUM_ITEM_ROUNDS 8
#define IGNEUM_MIXER_MULT 8 // mixer applications per round and after the last read (class v3, docs/plans/mixer-x4.md)
#define IGNEUM_MIX_ROT_INIT { 20u, 20u, 19u, 4u, 26u, 3u, 3u, 27u }
#define IGNEUM_MIX_MUL_INIT { 0x42146205u, 0x52cbe0fbu, 0x7ecf4a03u, 0x6728907fu, 0xd81d9751u, 0x132952c3u, 0xf60de277u, 0x05358035u, 0xbaf6499du, 0xe4db9667u, 0x3e98f45du, 0xd0004eddu, 0x2691630du, 0x9beb3bcfu, 0xab310379u, 0x99cfb423u }
#define IGNEUM_MIX_RC_INIT { 0xbab68293u, 0xcc162340u, 0x6ce151ccu, 0xe62b8997u, 0xc9c80297u, 0xf74a1654u, 0x3d704af5u, 0x3cf522b7u, 0x2b9cac04u, 0xa880ac10u, 0x13e5dd1du, 0x6fc3e233u, 0x2d83eeacu, 0x9006e8bfu, 0x2c4b5362u, 0x31b49ee2u }
#ifndef IGNEUM_NO_CUDA
// Defined in kernel.cu. All launch on the default stream and return cudaGetLastError().
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments);
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems);
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps);
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#endif

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{
"format": "igneum-program-pack-3",
"generator": 2,
"attempt": 0,
"program_id": "0xd6fc3093180e44f1",
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
"dataset_mode": "memory-hard",
"seed": "igneum-genesis",
"seed_bytes": "69676e65756d2d67656e65736973",
"seed_words": ["0x67a9a7be", "0x1a155b25", "0xfddfb732", "0x4b5af2e8", "0xc55caf33", "0xa27c13b7", "0x06628a48", "0x03852469"],
"seed_derivation": "seed_words = FNV-1a 64 over seed_bytes (attempt 0) or seed_bytes || attempt_le32 (attempt k >= 1), basis ^ (salt * 0x9E3779B97F4A7C15) for salt 0..3, then h ^= h>>33; h *= 0xff51afd7ed558ccd; h ^= h>>33; words[2*salt] = low 32, words[2*salt+1] = high 32",
"generator_rule": "version 2: exactly 16 load slots drawn first from instructions 1..63 (partial Fisher-Yates), the other 48 ops from the ten non-load weights (sum 75); a load's source is drawn from the registers other than dst written by an earlier instruction and not read by a load since; the candidate must pass the acceptance rule of spec 01 section 1.4.6 (static: no cyclically stale load source, every register has an injecting write; dynamic: 64 units on the seed-keyed closed-form dataset with no constant register bit, no lane-constant load site, under 164 saturated final values, every output bit within 136 of 1024, distinct addresses above 245760), else the next attempt of the seed is tried",
"lanes": 32,
"registers": 8,
"iterations": 8,
"instruction_count": 64,
"loads_per_hash": 128,
"load_class": "mx8+mm128",
"mixer_mult": 8,
"cache_growth": true,
"mixer": "class v3 (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): every mixer application of the item derivation is 8 applications with round keys (r * 8 + j + 1) * 0x9E3779B9, the 8 dependent cache reads per item unchanged; cache growth rule option C: cache words = 2^(26 + doublings(day)), dataset words = 2^(genesis_log2 + doublings(day)), doublings(day) = floor(log2(1 + day / 1460)) for day = days since genesis",
"load_slots": 16,
"load_mix_percent_4_16_64": [100, 0, 0],
"load_width_counts_4_16_64": [16, 0, 0],
"bytes_per_hash": 512,
"wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots",
"op_mix": {"load": 16, "add": 8, "shfl": 8, "xor": 6, "mad": 5, "mul": 5, "mulhi": 5, "sub": 4, "rotl": 3, "rotr": 3, "or": 1},
"register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]",
"splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16",
"iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order",
"output": "lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21); hi = r4 ^ rotl(r5,9) ^ rotl(r6,18) ^ rotl(r7,27); out = (hi << 32) | lo",
"op_semantics": {
"add": "dst = dst + src + (bit `bit` of sel ? imm2 : imm)",
"sub": "dst = dst - src",
"mul": "dst = dst * src (low 32)",
"mulhi": "dst = high 32 bits of dst * src",
"xor": "dst = dst ^ src",
"or": "dst = dst | src",
"rotl": "dst = rotl(dst, rot), rot in 1..31",
"rotr": "dst = rotr(dst, src & 31)",
"mad": "dst = src * src2 + dst",
"shfl": "dst = dst ^ (src of lane (lane ^ mask)), mask in {1,2,4,8,16}, within the 32-lane warp",
"load": "dst = dst ^ dataset[src & dataset.mask]",
"wload": "base = (src of lane 0 & dataset.mask) & ~31; dst = dst ^ dataset[base + lane] (warp-coalesced 128-byte load, lever b, only when --wide-frac > 0)"
},
"dataset": {
"log2_words": 28,
"bytes": 1073741824,
"mask": "0x0fffffff",
"day": "2026-10-03",
"day_bytes": "6461792f323032362d31302d3033",
"day_words_from": "seed_words_from_bytes(day_bytes)",
"d0": "0x3067619f",
"d1": "0x3c269176",
"mode": "memory-hard",
"spec": "proto-metal/MEMHARD.md",
"key": ["0x3067619f", "0x3c269176", "0x84a03b03", "0xf8c63294", "0xff977c5b", "0xe60def3e", "0x63630141", "0xb8fbcb58"],
"key_derivation": "the 8 words of seed_words_from_bytes(day_bytes); d0, d1 are key[0], key[1]",
"cache": {"log2_words": 26, "bytes": 268435456, "line_words": 16, "segment_lines": 64, "segments": 65536, "block": "ChaCha12 core + feed-forward, rotations 16 12 8 7", "sigma": ["0x61707865", "0x3320646e", "0x79622d32", "0x6b206574"], "tag": ["0x49676e65", "0x756d4d48"], "chain": "in_j = prev_line ^ (sigma[0..3] || key[0..7] || seg || j || tag[0..1]); line_j = block(in_j); prev_0 = 0"},
"mixer": {"draw": "SplitMix64 seeded with key[0] | key[1] << 32: rot[0..7] = 1 + next() % 31, mul[0..15] = low32(next()) | 1, rc[0..15] = low32(next())", "rot": [20, 20, 19, 4, 26, 3, 3, 27], "mul": ["0x42146205", "0x52cbe0fb", "0x7ecf4a03", "0x6728907f", "0xd81d9751", "0x132952c3", "0xf60de277", "0x05358035", "0xbaf6499d", "0xe4db9667", "0x3e98f45d", "0xd0004edd", "0x2691630d", "0x9beb3bcf", "0xab310379", "0x99cfb423"], "rc": ["0xbab68293", "0xcc162340", "0x6ce151cc", "0xe62b8997", "0xc9c80297", "0xf74a1654", "0x3d704af5", "0x3cf522b7", "0x2b9cac04", "0xa880ac10", "0x13e5dd1d", "0x6fc3e233", "0x2d83eeac", "0x9006e8bf", "0x2c4b5362", "0x31b49ee2"], "round": "for i in 0..15: s[i] = (s[i] ^ (rc[i] + (r+1) * 0x9E3779B9)) * mul[i]; then quarter rounds on columns (0,4,8,12) (1,5,9,13) (2,6,10,14) (3,7,11,15) with rot[0..3] and diagonals (0,5,10,15) (1,6,11,12) (2,7,8,13) (3,4,9,14) with rot[4..7]", "quarter_round": "a += b; d ^= a; d = rotl(d, r1); c += d; b ^= c; b = rotl(b, r2); a += b; d ^= a; d = rotl(d, r3); c += d; b ^= c; b = rotl(b, r4)"},
"mixer_mult": 8,
"item": "s[0..7] = key; s[8+i] = t * mul[i] + rc[i] for i in 0..7; for r in 0..7: for j in 0..7: s = M(s, rk = (r * 8 + j + 1) * 0x9E3779B9); line = s[0] & 0x003fffff; s[i] ^= cache[line * 16 + i]; then for j in 0..7: s = M(s, rk = (64 + j + 1) * 0x9E3779B9); item(t) = s",
"word": "dataset[w] = item(w >> 4)[w & 15]"
},
"shadow": {"instrs": 0, "reps": 0, "instrs_per_hash": 0, "op_mix": {}, "rule": "Counter ASIC 3.0 item 8 (docs/analysis/latency-shadow-2026-10-06.md): after the 64 base instructions the program stream draws instrs more ALU instructions (the non-load table, nine draws each, the source as on an ALU slot); the block runs reps times at the end of every iteration with the iteration's sel; the acceptance rule interprets the base program only", "program_id_suffix": "'shadow/' || instrs_le16 || reps_le16", "instructions": [
]},
"mm8_tiles": {"tiles": 128, "tiles_per_hash": 1024, "rule": "Counter ASIC 4.0 research (docs/analysis/counter-asic-4-research.md 15.2): after the shadow draws the stream draws tiles descriptors a, b, c (below 8 each) and c2 (below 7, skipping c); each tile is the PTX mma.m8n8k16 u8 product of the 32 lanes' r[a] (8 x 16 bytes) and r[b] (16 x 8), lane l adds C[l >> 2][2 (l & 3)] into r[c] and C[l >> 2][2 (l & 3) + 1] into r[c2] modulo 2^32; the block runs once per iteration after the shadow", "program_id_suffix": "'mm8/' || tiles_le16", "descriptors": [[6,5,2,3],[1,1,4,5],[2,5,0,7],[1,5,2,3],[2,0,2,6],[2,6,7,3],[1,4,1,3],[4,6,0,4],[1,1,1,5],[3,7,4,6],[3,0,0,4],[2,3,0,6],[3,1,6,0],[1,5,2,5],[3,3,3,4],[1,0,5,4],[7,2,0,4],[0,5,1,7],[1,1,2,0],[3,3,2,4],[3,0,6,1],[0,3,6,0],[1,7,6,4],[1,2,0,3],[3,4,0,2],[5,0,3,7],[1,0,7,3],[3,2,0,5],[2,4,6,5],[3,4,1,5],[6,5,6,3],[1,7,4,3],[7,6,3,0],[7,1,4,6],[1,0,5,1],[2,4,1,3],[1,7,7,1],[1,7,0,2],[3,6,2,4],[6,2,2,5],[6,1,4,1],[6,0,6,2],[7,4,5,1],[6,1,6,0],[0,6,4,1],[6,5,6,5],[6,6,1,0],[7,3,3,1],[7,7,6,3],[4,5,1,7],[1,7,4,5],[3,4,0,3],[2,5,7,4],[7,7,1,3],[7,6,6,5],[1,7,3,7],[4,0,7,3],[4,3,6,7],[2,3,6,0],[6,7,5,7],[6,0,2,4],[2,1,2,6],[4,6,1,6],[1,6,0,3],[0,5,5,3],[0,1,2,4],[3,5,1,3],[6,2,3,4],[7,1,1,2],[6,7,5,4],[1,7,1,5],[3,0,1,0],[4,0,3,6],[4,1,0,2],[5,1,3,4],[4,4,7,3],[5,6,1,7],[0,6,3,2],[2,5,0,5],[7,4,4,1],[6,7,3,4],[4,3,1,6],[6,0,1,7],[2,2,1,6],[0,6,0,3],[1,3,4,1],[3,4,2,3],[4,4,3,7],[6,4,5,3],[4,2,2,1],[6,5,3,6],[6,5,5,4],[2,6,2,3],[2,2,5,7],[2,4,7,3],[5,4,1,6],[0,6,3,1],[0,5,1,2],[2,7,3,2],[1,4,0,2],[2,4,2,5],[2,4,6,7],[5,7,6,3],[4,7,4,3],[2,0,3,7],[6,1,0,5],[4,1,0,5],[2,1,4,2],[4,6,1,2],[2,7,5,3],[1,0,0,2],[6,5,4,6],[5,7,4,2],[6,3,4,1],[2,1,7,5],[1,4,1,4],[7,2,5,0],[7,6,7,6],[0,1,2,1],[4,3,5,3],[5,3,7,2],[2,7,2,1],[0,1,3,0],[5,2,3,5],[5,1,2,5],[7,2,7,2],[6,3,3,2],[6,7,5,1]]},
"instructions": [
{"i": 0, "op": "mad", "dst": 2, "src": 3, "src2": 4, "imm": "0xbf7b174d", "imm2": "0x337b762e", "rot": 17, "bit": 2, "mask": 2, "width": 1},
{"i": 1, "op": "mad", "dst": 2, "src": 1, "src2": 1, "imm": "0xdd04a5da", "imm2": "0x42da7657", "rot": 15, "bit": 30, "mask": 16, "width": 1},
{"i": 2, "op": "mad", "dst": 2, "src": 3, "src2": 2, "imm": "0x734003fa", "imm2": "0x5bb67700", "rot": 3, "bit": 20, "mask": 1, "width": 1},
{"i": 3, "op": "xor", "dst": 3, "src": 5, "src2": 5, "imm": "0xc55a1b1c", "imm2": "0xa19720f3", "rot": 7, "bit": 8, "mask": 1, "width": 1},
{"i": 4, "op": "load", "dst": 7, "src": 2, "src2": 5, "imm": "0xad572dd7", "imm2": "0x9ceb3ea7", "rot": 18, "bit": 30, "mask": 2, "width": 1},
{"i": 5, "op": "load", "dst": 5, "src": 7, "src2": 3, "imm": "0x769a53be", "imm2": "0x80f9067e", "rot": 12, "bit": 22, "mask": 1, "width": 1},
{"i": 6, "op": "shfl", "dst": 1, "src": 4, "src2": 0, "imm": "0xd3613d88", "imm2": "0x262fb219", "rot": 10, "bit": 30, "mask": 8, "width": 1},
{"i": 7, "op": "shfl", "dst": 7, "src": 3, "src2": 4, "imm": "0xce38e42f", "imm2": "0xb868b818", "rot": 11, "bit": 8, "mask": 8, "width": 1},
{"i": 8, "op": "mulhi", "dst": 1, "src": 5, "src2": 2, "imm": "0xa5eebca5", "imm2": "0x5703a72b", "rot": 13, "bit": 13, "mask": 16, "width": 1},
{"i": 9, "op": "rotr", "dst": 6, "src": 3, "src2": 4, "imm": "0x17a5a9c7", "imm2": "0xdcfb93a1", "rot": 20, "bit": 27, "mask": 2, "width": 1},
{"i": 10, "op": "or", "dst": 3, "src": 4, "src2": 1, "imm": "0xccb7d785", "imm2": "0xc335364c", "rot": 14, "bit": 12, "mask": 4, "width": 1},
{"i": 11, "op": "load", "dst": 4, "src": 3, "src2": 2, "imm": "0x88cb9af3", "imm2": "0x4e7dc10d", "rot": 24, "bit": 17, "mask": 4, "width": 1},
{"i": 12, "op": "mulhi", "dst": 0, "src": 4, "src2": 4, "imm": "0x45374321", "imm2": "0x3cd91989", "rot": 11, "bit": 4, "mask": 2, "width": 1},
{"i": 13, "op": "add", "dst": 5, "src": 1, "src2": 2, "imm": "0xc7934706", "imm2": "0xd3177981", "rot": 16, "bit": 30, "mask": 2, "width": 1},
{"i": 14, "op": "load", "dst": 0, "src": 4, "src2": 3, "imm": "0xfd7f56bb", "imm2": "0x65e14f52", "rot": 13, "bit": 22, "mask": 2, "width": 1},
{"i": 15, "op": "sub", "dst": 2, "src": 4, "src2": 4, "imm": "0x35a80b49", "imm2": "0x060f2d13", "rot": 16, "bit": 20, "mask": 16, "width": 1},
{"i": 16, "op": "load", "dst": 2, "src": 0, "src2": 2, "imm": "0xae0a32c2", "imm2": "0x4c2a4cfe", "rot": 8, "bit": 31, "mask": 16, "width": 1},
{"i": 17, "op": "load", "dst": 7, "src": 2, "src2": 6, "imm": "0x82a84cc3", "imm2": "0x21a38d68", "rot": 15, "bit": 21, "mask": 2, "width": 1},
{"i": 18, "op": "shfl", "dst": 7, "src": 3, "src2": 3, "imm": "0xa3818806", "imm2": "0x8f66b5c8", "rot": 14, "bit": 6, "mask": 4, "width": 1},
{"i": 19, "op": "mul", "dst": 5, "src": 0, "src2": 1, "imm": "0xa00de107", "imm2": "0x77bfcaa5", "rot": 3, "bit": 10, "mask": 2, "width": 1},
{"i": 20, "op": "shfl", "dst": 3, "src": 4, "src2": 7, "imm": "0x1d2b8cab", "imm2": "0x80b4f9a2", "rot": 14, "bit": 25, "mask": 2, "width": 1},
{"i": 21, "op": "shfl", "dst": 2, "src": 4, "src2": 5, "imm": "0x3ac915d2", "imm2": "0x5fba7bc2", "rot": 16, "bit": 1, "mask": 16, "width": 1},
{"i": 22, "op": "mulhi", "dst": 6, "src": 2, "src2": 0, "imm": "0xdc3ec8fd", "imm2": "0x599e2fa3", "rot": 22, "bit": 3, "mask": 2, "width": 1},
{"i": 23, "op": "load", "dst": 6, "src": 1, "src2": 5, "imm": "0x2a6b16d5", "imm2": "0xd73e396f", "rot": 28, "bit": 29, "mask": 2, "width": 1},
{"i": 24, "op": "mul", "dst": 5, "src": 0, "src2": 7, "imm": "0x376d0223", "imm2": "0xe1c2169a", "rot": 4, "bit": 16, "mask": 16, "width": 1},
{"i": 25, "op": "rotl", "dst": 5, "src": 7, "src2": 3, "imm": "0x78ad8c60", "imm2": "0x6f5b77d5", "rot": 19, "bit": 11, "mask": 16, "width": 1},
{"i": 26, "op": "shfl", "dst": 7, "src": 6, "src2": 5, "imm": "0x93915b9f", "imm2": "0x1e61fb6b", "rot": 28, "bit": 23, "mask": 2, "width": 1},
{"i": 27, "op": "xor", "dst": 0, "src": 5, "src2": 7, "imm": "0x6378fe15", "imm2": "0x66c78f42", "rot": 12, "bit": 31, "mask": 8, "width": 1},
{"i": 28, "op": "xor", "dst": 0, "src": 4, "src2": 7, "imm": "0x20a57fda", "imm2": "0x088c848e", "rot": 16, "bit": 13, "mask": 4, "width": 1},
{"i": 29, "op": "sub", "dst": 3, "src": 0, "src2": 2, "imm": "0x49d95fd5", "imm2": "0x1a5f946a", "rot": 6, "bit": 12, "mask": 1, "width": 1},
{"i": 30, "op": "mul", "dst": 5, "src": 1, "src2": 7, "imm": "0x0a816217", "imm2": "0x405c4f73", "rot": 13, "bit": 27, "mask": 4, "width": 1},
{"i": 31, "op": "load", "dst": 7, "src": 2, "src2": 2, "imm": "0x09ed045e", "imm2": "0xd69c4715", "rot": 5, "bit": 9, "mask": 2, "width": 1},
{"i": 32, "op": "load", "dst": 1, "src": 0, "src2": 6, "imm": "0xeb79ea49", "imm2": "0xcc587f5a", "rot": 6, "bit": 8, "mask": 16, "width": 1},
{"i": 33, "op": "xor", "dst": 5, "src": 6, "src2": 1, "imm": "0x3027401e", "imm2": "0x5f20c27e", "rot": 18, "bit": 9, "mask": 2, "width": 1},
{"i": 34, "op": "load", "dst": 5, "src": 1, "src2": 3, "imm": "0x0e1cab07", "imm2": "0x09356c5b", "rot": 19, "bit": 31, "mask": 1, "width": 1},
{"i": 35, "op": "mulhi", "dst": 0, "src": 5, "src2": 2, "imm": "0x90e31357", "imm2": "0xabd32484", "rot": 26, "bit": 5, "mask": 8, "width": 1},
{"i": 36, "op": "shfl", "dst": 5, "src": 2, "src2": 5, "imm": "0xee9a955f", "imm2": "0x31b3faed", "rot": 8, "bit": 24, "mask": 4, "width": 1},
{"i": 37, "op": "load", "dst": 7, "src": 0, "src2": 7, "imm": "0x3ba2f832", "imm2": "0x1160dcd3", "rot": 4, "bit": 29, "mask": 1, "width": 1},
{"i": 38, "op": "add", "dst": 3, "src": 1, "src2": 7, "imm": "0x75ba2fad", "imm2": "0x230c005c", "rot": 4, "bit": 27, "mask": 1, "width": 1},
{"i": 39, "op": "shfl", "dst": 1, "src": 5, "src2": 3, "imm": "0xdbf37e75", "imm2": "0xb5ac1969", "rot": 30, "bit": 13, "mask": 4, "width": 1},
{"i": 40, "op": "xor", "dst": 2, "src": 5, "src2": 5, "imm": "0x47f136c5", "imm2": "0x06ce9153", "rot": 19, "bit": 10, "mask": 2, "width": 1},
{"i": 41, "op": "mad", "dst": 3, "src": 6, "src2": 3, "imm": "0xce13eff8", "imm2": "0x04cc1d55", "rot": 3, "bit": 1, "mask": 4, "width": 1},
{"i": 42, "op": "sub", "dst": 6, "src": 7, "src2": 1, "imm": "0x6a65ab71", "imm2": "0x8fbc1bcd", "rot": 4, "bit": 1, "mask": 8, "width": 1},
{"i": 43, "op": "xor", "dst": 7, "src": 0, "src2": 7, "imm": "0xdaeb4928", "imm2": "0xc0423027", "rot": 24, "bit": 11, "mask": 8, "width": 1},
{"i": 44, "op": "load", "dst": 1, "src": 7, "src2": 7, "imm": "0x778f01c9", "imm2": "0x28cedcea", "rot": 12, "bit": 4, "mask": 16, "width": 1},
{"i": 45, "op": "mul", "dst": 2, "src": 3, "src2": 2, "imm": "0xf4264f1b", "imm2": "0x0f627d56", "rot": 5, "bit": 28, "mask": 8, "width": 1},
{"i": 46, "op": "mulhi", "dst": 1, "src": 5, "src2": 1, "imm": "0xffb2147a", "imm2": "0xccde9b05", "rot": 13, "bit": 9, "mask": 2, "width": 1},
{"i": 47, "op": "sub", "dst": 4, "src": 3, "src2": 5, "imm": "0x73b36234", "imm2": "0x3f5d5997", "rot": 7, "bit": 18, "mask": 2, "width": 1},
{"i": 48, "op": "rotr", "dst": 2, "src": 6, "src2": 3, "imm": "0x3a4d9aa9", "imm2": "0x212bec7b", "rot": 4, "bit": 29, "mask": 16, "width": 1},
{"i": 49, "op": "load", "dst": 3, "src": 5, "src2": 2, "imm": "0x626f11df", "imm2": "0x56cd5bfd", "rot": 7, "bit": 1, "mask": 1, "width": 1},
{"i": 50, "op": "add", "dst": 1, "src": 5, "src2": 6, "imm": "0x81b8bc2c", "imm2": "0x1907970c", "rot": 28, "bit": 7, "mask": 4, "width": 1},
{"i": 51, "op": "mul", "dst": 0, "src": 2, "src2": 2, "imm": "0xa8848b30", "imm2": "0xef6ac348", "rot": 9, "bit": 15, "mask": 8, "width": 1},
{"i": 52, "op": "add", "dst": 0, "src": 2, "src2": 0, "imm": "0x4f92b968", "imm2": "0x699fd448", "rot": 22, "bit": 6, "mask": 4, "width": 1},
{"i": 53, "op": "add", "dst": 1, "src": 0, "src2": 2, "imm": "0x2bb965af", "imm2": "0x77b1520d", "rot": 2, "bit": 12, "mask": 8, "width": 1},
{"i": 54, "op": "rotl", "dst": 7, "src": 1, "src2": 0, "imm": "0x553e678b", "imm2": "0x3cc8eae0", "rot": 14, "bit": 20, "mask": 2, "width": 1},
{"i": 55, "op": "add", "dst": 3, "src": 7, "src2": 2, "imm": "0x7b0fe07a", "imm2": "0xa54c55a0", "rot": 10, "bit": 1, "mask": 1, "width": 1},
{"i": 56, "op": "load", "dst": 6, "src": 7, "src2": 4, "imm": "0x01eba9aa", "imm2": "0x2758c0f7", "rot": 14, "bit": 15, "mask": 4, "width": 1},
{"i": 57, "op": "rotr", "dst": 1, "src": 5, "src2": 2, "imm": "0x1f5267b3", "imm2": "0x236f5a27", "rot": 2, "bit": 31, "mask": 16, "width": 1},
{"i": 58, "op": "load", "dst": 5, "src": 4, "src2": 3, "imm": "0xa9954a9b", "imm2": "0x6a54d4e8", "rot": 11, "bit": 10, "mask": 16, "width": 1},
{"i": 59, "op": "load", "dst": 6, "src": 2, "src2": 4, "imm": "0x9923ff88", "imm2": "0x9357254e", "rot": 16, "bit": 1, "mask": 16, "width": 1},
{"i": 60, "op": "mad", "dst": 3, "src": 5, "src2": 0, "imm": "0xc0cc51a6", "imm2": "0x3fd7701b", "rot": 20, "bit": 1, "mask": 4, "width": 1},
{"i": 61, "op": "add", "dst": 5, "src": 7, "src2": 7, "imm": "0xaf9dd72d", "imm2": "0xad7493e7", "rot": 7, "bit": 31, "mask": 16, "width": 1},
{"i": 62, "op": "add", "dst": 4, "src": 6, "src2": 2, "imm": "0x89841d87", "imm2": "0x1e07c3d9", "rot": 6, "bit": 27, "mask": 1, "width": 1},
{"i": 63, "op": "rotl", "dst": 5, "src": 4, "src2": 2, "imm": "0xae210f8d", "imm2": "0x8e499ba4", "rot": 19, "bit": 9, "mask": 1, "width": 1}
]
}

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#include <metal_stdlib>
using namespace metal;
// int8 tile reference (Counter ASIC 4.0 research): A = the 32 lanes' av as 8 x 16 bytes (lane l holds row l >> 2, bytes 4 (l & 3)..),
// B = bv as 16 x 8 (lane l holds column l >> 2); lane l gets C[l >> 2][2 (l & 3)] and C[l >> 2][2 (l & 3) + 1]; the PTX mma.m8n8k16 u8 layout.
static inline void mm8_ref(uint av, uint bv, uint lane, thread uint& d0, thread uint& d1) {
uint row = lane >> 2, col0 = 2u * (lane & 3u);
uint acc0 = 0u, acc1 = 0u;
for (uint j = 0u; j < 4u; ++j) {
uint aw = simd_shuffle(av, (ushort)(4u * row + j));
uint bw0 = simd_shuffle(bv, (ushort)(4u * col0 + j));
uint bw1 = simd_shuffle(bv, (ushort)(4u * (col0 + 1u) + j));
for (uint t = 0u; t < 4u; ++t) {
uint ab = (aw >> (8u * t)) & 0xffu;
acc0 += ab * ((bw0 >> (8u * t)) & 0xffu);
acc1 += ab * ((bw1 >> (8u * t)) & 0xffu);
}
}
d0 = acc0; d1 = acc1;
}
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint lane = gid & 31u;
{ uint x = nonce ^ SEEDW[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ SEEDW[1]; }
{ uint x = nonce ^ SEEDW[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ SEEDW[2]; }
{ uint x = nonce ^ SEEDW[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ SEEDW[3]; }
{ uint x = nonce ^ SEEDW[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ SEEDW[4]; }
{ uint x = nonce ^ SEEDW[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ SEEDW[5]; }
{ uint x = nonce ^ SEEDW[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ SEEDW[6]; }
{ uint x = nonce ^ SEEDW[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ SEEDW[7]; }
{ uint x = nonce ^ SEEDW[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ SEEDW[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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#include <metal_stdlib>
using namespace metal;
// int8 tile reference (Counter ASIC 4.0 research): A = the 32 lanes' av as 8 x 16 bytes (lane l holds row l >> 2, bytes 4 (l & 3)..),
// B = bv as 16 x 8 (lane l holds column l >> 2); lane l gets C[l >> 2][2 (l & 3)] and C[l >> 2][2 (l & 3) + 1]; the PTX mma.m8n8k16 u8 layout.
static inline void mm8_ref(uint av, uint bv, uint lane, thread uint& d0, thread uint& d1) {
uint row = lane >> 2, col0 = 2u * (lane & 3u);
uint acc0 = 0u, acc1 = 0u;
for (uint j = 0u; j < 4u; ++j) {
uint aw = simd_shuffle(av, (ushort)(4u * row + j));
uint bw0 = simd_shuffle(bv, (ushort)(4u * col0 + j));
uint bw1 = simd_shuffle(bv, (ushort)(4u * (col0 + 1u) + j));
for (uint t = 0u; t < 4u; ++t) {
uint ab = (aw >> (8u * t)) & 0xffu;
acc0 += ab * ((bw0 >> (8u * t)) & 0xffu);
acc1 += ab * ((bw1 >> (8u * t)) & 0xffu);
}
}
d0 = acc0; d1 = acc1;
}
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Header-bound variant: the init words come from buffer 3 (bind.rs), not from SEEDW.
kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
constant uint* initw [[buffer(3)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint lane = gid & 31u;
{ uint x = nonce ^ initw[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ initw[1]; }
{ uint x = nonce ^ initw[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ initw[2]; }
{ uint x = nonce ^ initw[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ initw[3]; }
{ uint x = nonce ^ initw[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ initw[4]; }
{ uint x = nonce ^ initw[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ initw[5]; }
{ uint x = nonce ^ initw[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ initw[6]; }
{ uint x = nonce ^ initw[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ initw[7]; }
{ uint x = nonce ^ initw[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ initw[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// int8 tile block (Counter ASIC 4.0 research, experimental): 128 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

57
proto-cuda/packs-ca4/mx8_mm128/vectors.h Normal file
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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#define IGNEUM_VEC_WARPS 3
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
{ // base nonce 0
0x25b68ebd0e906b6dull, 0xd5072799aa3388f2ull, 0xcb9ef6af09df1727ull, 0x9640067bd458ba0full, 0xb425a8e6be6ebc66ull, 0xee0337da049776e0ull, 0x575cb409f02fe85cull, 0xf681e6a634ee274dull,
0x6240bea3cd0618a3ull, 0x46542be4215eb40dull, 0xd473cfa0ee990014ull, 0x1edd1dde66d5ed15ull, 0x4e2614069b891edaull, 0xa0177b04b273df1eull, 0x8801079046cd297eull, 0xcbd7d0fc56746f2cull,
0x6dd755062955ea76ull, 0x49c66be7bc453333ull, 0x77b6aa0a2e018a00ull, 0x03cd6c4473aaa4dfull, 0xc22947a71e2df6abull, 0x88dbfa375585588full, 0xee7ad5a0b9fd2cb0ull, 0x32e973e9d4d08f04ull,
0x5216892aa97f054full, 0x0bb544fa1c3164a9ull, 0x287301a65944e03bull, 0x97ff3a15f4be15a1ull, 0x7efb80050078c725ull, 0x466e0db9cdf6cd16ull, 0x3edc67ee6fec9836ull, 0x719475da599c181cull
},
{ // base nonce 4096
0xe8a167c98997e9e4ull, 0x473e97b54279586full, 0xc936941504e34cdaull, 0xcc10b3fb38dbe2b1ull, 0xf5ec50127382b382ull, 0xfed36c8a20572550ull, 0xce2c26f4fc0a3b23ull, 0xbb007d40b8cb148full,
0x828cf96280004a64ull, 0x0be4a5a3a24950faull, 0xa8fe47603236807dull, 0x5126fa0bfc2ff05dull, 0xc1c82fd752965fb2ull, 0xbb03e9a649e56fd6ull, 0x7665244f65ac6f68ull, 0xd7e98be5687212f5ull,
0x158292648b58b97full, 0x17fe5c2db3fa4ffeull, 0xe3fff009c0baabfdull, 0x088db9de945c3641ull, 0xa9b4f2921081e576ull, 0x8e6ff7cd0b306b67ull, 0x3f297f8cd5f05e74ull, 0xcdc25fde19f03490ull,
0x5347a7990e98f475ull, 0x054eaf4ed50cdb55ull, 0x6475d5d6ca0bbe31ull, 0xc49093e12468a24eull, 0x6bf26f2aa7164fc0ull, 0x6016f20b26bec311ull, 0x553d1d640b452da0ull, 0x14a02c647d6fd301ull
},
{ // base nonce 1000000
0x7bdfc082cefc7113ull, 0xbe8d8421159c699bull, 0x79462f47122923a3ull, 0xd8051e3d6c418791ull, 0xad6d08bc7fb8e839ull, 0xd16fe4bbadb350cfull, 0xe52871c076a7b822ull, 0x7caabc8c2924d1b6ull,
0x11f56e922cd78df5ull, 0xdec94f81ca18bfb2ull, 0xfcc2d3a09cab249eull, 0x3d5157679833c75dull, 0xd030fbf56d44a09aull, 0x74d4aad3fdfdea27ull, 0x198020289b4880a4ull, 0x921135a661e458feull,
0x77536f5c70aa1154ull, 0x32ed08793a3819e4ull, 0x316a1ca8cbf71df8ull, 0x01607d5115ba8a6full, 0xcf68787c5b013feaull, 0x8a2189bac924f312ull, 0x5b53bedb0dd0d6aaull, 0x7d1d537591d9394aull,
0x1fe717f8a7c38824ull, 0xcd21f17ea407ab99ull, 0xcf36d53b85d645c7ull, 0x9c4dd4372c8513dcull, 0xe842a34932cf0fa5ull, 0x67d0f83d144c3293ull, 0x12c9e72434886b71ull, 0x6a62329215ace047ull
}
};
// Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455).
static const uint32_t IGNEUM_DS_HEAD[16] = {
0xfdad4319u, 0x1a7b68e1u, 0xde6db608u, 0x13d73892u, 0xd17f447au, 0xb2221ccfu, 0x9db004bdu, 0x57d7d367u,
0xdbc4cf34u, 0x697c009au, 0xc43af1d4u, 0x97f12b2eu, 0x74c37cd0u, 0xc651ea15u, 0x665a6d29u, 0x22330a2du
};
static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u;
static const uint32_t IGNEUM_DS_LAST = 0xa83e7aa6u;
// 64 sampled dataset words (index, value) computed on the Mac.
#define IGNEUM_DS_SAMPLES 64
static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = {
59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u
};
static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = {
0x3230bc7bu, 0x7fbfe2c9u, 0xb2690991u, 0x1745c7c5u, 0x0ab0ccafu, 0x1bf87d6bu, 0x160139fdu, 0x719817acu, 0x0155df4bu, 0xbe1e86c3u, 0x680bcd6cu, 0x79c3dc6cu, 0x181e7e5fu, 0x0713a109u, 0xc705dd9fu, 0x3933b7a8u, 0xdd1c0431u, 0x50522b30u, 0xa0020b38u, 0xbff39e96u, 0x21b67e18u, 0x740f8db3u, 0x2baba568u, 0x2c9bef83u, 0x0ad9b671u, 0xc4327869u, 0x7b4fd7d0u, 0x2c29965fu, 0xec56f15fu, 0x61111746u, 0x303a1d6eu, 0xbddcfd1au, 0xf829a355u, 0x6d5df2a9u, 0x01ab8e44u, 0x06d13507u, 0xda8dcfc6u, 0x01a703e1u, 0xafe7d2c1u, 0xc091c3a2u, 0xac1814feu, 0x6e6ff62au, 0x8fdf01bau, 0xdd3f7159u, 0xdfa0d75cu, 0x26684c35u, 0x7f441e63u, 0x88df2570u, 0x8aa4d5ebu, 0xcc816c05u, 0x434df890u, 0xcd392ad6u, 0x1ab4cb63u, 0x595926fau, 0x7cd76b41u, 0x20cb95c4u, 0x13cf823fu, 0xf9daf901u, 0xff9af40au, 0x2c7dfa51u, 0x871206dbu, 0x938c116cu, 0xb64bf199u, 0x5751f874u
};
// Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words.
static const uint32_t IGNEUM_CACHE_HEAD[16] = {
0x355a86d2u, 0x7957db1cu, 0xd21772afu, 0x6fc1e09bu, 0xd55ce61du, 0x6e6a278bu, 0xd3f543ceu, 0x223d8e82u,
0x143ab337u, 0x2e9f05bdu, 0x2eb389bfu, 0x0c6e449eu, 0x5cfa4222u, 0xba6560feu, 0x8e3e1aa4u, 0xdbcc1d53u
};
static const uint32_t IGNEUM_CACHE_LAST[16] = {
0x41190d91u, 0xbd277957u, 0x22ddbb49u, 0x6986f207u, 0xdf69a4d6u, 0x26401a3au, 0x818230fbu, 0xc417122du,
0x3597b211u, 0xb553ce55u, 0xcf39cc0du, 0x3b7fc43au, 0x3fd43b00u, 0x67e1c80eu, 0xffa7ea7du, 0xca2960abu
};
static const uint64_t IGNEUM_CACHE_FNV64 = 0x48c4f5bf24166b2eull;

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{
"seed": "igneum-genesis",
"day": "2026-10-03",
"dataset_mode": "memory-hard",
"dataset_log2_words": 28,
"mask": "0x0fffffff",
"lanes": 32,
"source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset",
"warps": [
{"base_nonce": 0, "expected": [
"0x25b68ebd0e906b6d", "0xd5072799aa3388f2", "0xcb9ef6af09df1727", "0x9640067bd458ba0f", "0xb425a8e6be6ebc66", "0xee0337da049776e0", "0x575cb409f02fe85c", "0xf681e6a634ee274d",
"0x6240bea3cd0618a3", "0x46542be4215eb40d", "0xd473cfa0ee990014", "0x1edd1dde66d5ed15", "0x4e2614069b891eda", "0xa0177b04b273df1e", "0x8801079046cd297e", "0xcbd7d0fc56746f2c",
"0x6dd755062955ea76", "0x49c66be7bc453333", "0x77b6aa0a2e018a00", "0x03cd6c4473aaa4df", "0xc22947a71e2df6ab", "0x88dbfa375585588f", "0xee7ad5a0b9fd2cb0", "0x32e973e9d4d08f04",
"0x5216892aa97f054f", "0x0bb544fa1c3164a9", "0x287301a65944e03b", "0x97ff3a15f4be15a1", "0x7efb80050078c725", "0x466e0db9cdf6cd16", "0x3edc67ee6fec9836", "0x719475da599c181c"
]},
{"base_nonce": 4096, "expected": [
"0xe8a167c98997e9e4", "0x473e97b54279586f", "0xc936941504e34cda", "0xcc10b3fb38dbe2b1", "0xf5ec50127382b382", "0xfed36c8a20572550", "0xce2c26f4fc0a3b23", "0xbb007d40b8cb148f",
"0x828cf96280004a64", "0x0be4a5a3a24950fa", "0xa8fe47603236807d", "0x5126fa0bfc2ff05d", "0xc1c82fd752965fb2", "0xbb03e9a649e56fd6", "0x7665244f65ac6f68", "0xd7e98be5687212f5",
"0x158292648b58b97f", "0x17fe5c2db3fa4ffe", "0xe3fff009c0baabfd", "0x088db9de945c3641", "0xa9b4f2921081e576", "0x8e6ff7cd0b306b67", "0x3f297f8cd5f05e74", "0xcdc25fde19f03490",
"0x5347a7990e98f475", "0x054eaf4ed50cdb55", "0x6475d5d6ca0bbe31", "0xc49093e12468a24e", "0x6bf26f2aa7164fc0", "0x6016f20b26bec311", "0x553d1d640b452da0", "0x14a02c647d6fd301"
]},
{"base_nonce": 1000000, "expected": [
"0x7bdfc082cefc7113", "0xbe8d8421159c699b", "0x79462f47122923a3", "0xd8051e3d6c418791", "0xad6d08bc7fb8e839", "0xd16fe4bbadb350cf", "0xe52871c076a7b822", "0x7caabc8c2924d1b6",
"0x11f56e922cd78df5", "0xdec94f81ca18bfb2", "0xfcc2d3a09cab249e", "0x3d5157679833c75d", "0xd030fbf56d44a09a", "0x74d4aad3fdfdea27", "0x198020289b4880a4", "0x921135a661e458fe",
"0x77536f5c70aa1154", "0x32ed08793a3819e4", "0x316a1ca8cbf71df8", "0x01607d5115ba8a6f", "0xcf68787c5b013fea", "0x8a2189bac924f312", "0x5b53bedb0dd0d6aa", "0x7d1d537591d9394a",
"0x1fe717f8a7c38824", "0xcd21f17ea407ab99", "0xcf36d53b85d645c7", "0x9c4dd4372c8513dc", "0xe842a34932cf0fa5", "0x67d0f83d144c3293", "0x12c9e72434886b71", "0x6a62329215ace047"
]}
],
"dataset_head": ["0xfdad4319", "0x1a7b68e1", "0xde6db608", "0x13d73892", "0xd17f447a", "0xb2221ccf", "0x9db004bd", "0x57d7d367", "0xdbc4cf34", "0x697c009a", "0xc43af1d4", "0x97f12b2e", "0x74c37cd0", "0xc651ea15", "0x665a6d29", "0x22330a2d"],
"dataset_last_index": 268435455,
"dataset_last": "0xa83e7aa6",
"dataset_samples": [{"index": 59471966, "value": "0x3230bc7b"}, {"index": 217795994, "value": "0x7fbfe2c9"}, {"index": 208353206, "value": "0xb2690991"}, {"index": 42483309, "value": "0x1745c7c5"}, {"index": 172547758, "value": "0x0ab0ccaf"}, {"index": 148076330, "value": "0x1bf87d6b"}, {"index": 183853158, "value": "0x160139fd"}, {"index": 214389424, "value": "0x719817ac"}, {"index": 267488061, "value": "0x0155df4b"}, {"index": 169781097, "value": "0xbe1e86c3"}, {"index": 184093494, "value": "0x680bcd6c"}, {"index": 153880993, "value": "0x79c3dc6c"}, {"index": 84977930, "value": "0x181e7e5f"}, {"index": 46426879, "value": "0x0713a109"}, {"index": 3093825, "value": "0xc705dd9f"}, {"index": 225364072, "value": "0x3933b7a8"}, {"index": 44593546, "value": "0xdd1c0431"}, {"index": 260713159, "value": "0x50522b30"}, {"index": 168250303, "value": "0xa0020b38"}, {"index": 52384140, "value": "0xbff39e96"}, {"index": 223401610, "value": "0x21b67e18"}, {"index": 45554030, "value": "0x740f8db3"}, {"index": 95410555, "value": "0x2baba568"}, {"index": 175039924, "value": "0x2c9bef83"}, {"index": 79171087, "value": "0x0ad9b671"}, {"index": 267580473, "value": "0xc4327869"}, {"index": 24168642, "value": "0x7b4fd7d0"}, {"index": 37981670, "value": "0x2c29965f"}, {"index": 171551130, "value": "0xec56f15f"}, {"index": 195559979, "value": "0x61111746"}, {"index": 204611762, "value": "0x303a1d6e"}, {"index": 140997658, "value": "0xbddcfd1a"}, {"index": 138925853, "value": "0xf829a355"}, {"index": 86637313, "value": "0x6d5df2a9"}, {"index": 20736778, "value": "0x01ab8e44"}, {"index": 219665210, "value": "0x06d13507"}, {"index": 160430336, "value": "0xda8dcfc6"}, {"index": 264654675, "value": "0x01a703e1"}, {"index": 8013395, "value": "0xafe7d2c1"}, {"index": 228945585, "value": "0xc091c3a2"}, {"index": 213884386, "value": "0xac1814fe"}, {"index": 104419827, "value": "0x6e6ff62a"}, {"index": 44185464, "value": "0x8fdf01ba"}, {"index": 142737231, "value": "0xdd3f7159"}, {"index": 99284897, "value": "0xdfa0d75c"}, {"index": 132475900, "value": "0x26684c35"}, {"index": 61861762, "value": "0x7f441e63"}, {"index": 132056166, "value": "0x88df2570"}, {"index": 262388043, "value": "0x8aa4d5eb"}, {"index": 91878046, "value": "0xcc816c05"}, {"index": 117353561, "value": "0x434df890"}, {"index": 124768597, "value": "0xcd392ad6"}, {"index": 71352993, "value": "0x1ab4cb63"}, {"index": 190698941, "value": "0x595926fa"}, {"index": 46055428, "value": "0x7cd76b41"}, {"index": 55281366, "value": "0x20cb95c4"}, {"index": 165145231, "value": "0x13cf823f"}, {"index": 106810753, "value": "0xf9daf901"}, {"index": 171985651, "value": "0xff9af40a"}, {"index": 232085256, "value": "0x2c7dfa51"}, {"index": 159510492, "value": "0x871206db"}, {"index": 40072060, "value": "0x938c116c"}, {"index": 209107596, "value": "0xb64bf199"}, {"index": 39023794, "value": "0x5751f874"}],
"cache_head": ["0x355a86d2", "0x7957db1c", "0xd21772af", "0x6fc1e09b", "0xd55ce61d", "0x6e6a278b", "0xd3f543ce", "0x223d8e82", "0x143ab337", "0x2e9f05bd", "0x2eb389bf", "0x0c6e449e", "0x5cfa4222", "0xba6560fe", "0x8e3e1aa4", "0xdbcc1d53"],
"cache_last_line": ["0x41190d91", "0xbd277957", "0x22ddbb49", "0x6986f207", "0xdf69a4d6", "0x26401a3a", "0x818230fb", "0xc417122d", "0x3597b211", "0xb553ce55", "0xcf39cc0d", "0x3b7fc43a", "0x3fd43b00", "0x67e1c80e", "0xffa7ea7d", "0xca2960ab"],
"cache_fnv1a64": "0x48c4f5bf24166b2e"
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Memory-hard dataset core, the same text that the Mac's Metal kernels and CPU verifier were checked against.
// Included by kernel.cu (device), host.cu (host reference) and proto-opencl/host.c (C99 host reference).
// See proto-metal/MEMHARD.md for the construction. kernel.cl carries the same text in OpenCL C.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#if defined(__CUDACC__)
#define IGNEUM_HD __host__ __device__ __forceinline__
#elif defined(_MSC_VER) && !defined(__cplusplus)
#define IGNEUM_HD static __inline
#else
#define IGNEUM_HD static inline
#endif
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
IGNEUM_HD uint32_t mh_rotl(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
IGNEUM_HD void mh_chacha_block(const uint32_t* x, uint32_t* y) {
for (uint32_t i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint32_t r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint32_t i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
IGNEUM_HD void mh_cache_segment(uint32_t* cache, uint32_t seg) {
uint32_t prev[16]; uint32_t x[16]; uint32_t y[16];
for (uint32_t i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint32_t j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
uint32_t* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
IGNEUM_HD void mh_mixer(uint32_t* s, uint32_t rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint32_t r = 0u; r < 8u; ++r) {
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
const uint32_t* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }

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#include <metal_stdlib>
using namespace metal;
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
inline void mh_chacha_block(const thread uint* x, thread uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
inline void mh_cache_segment(device uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
device uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
inline void mh_mixer(thread uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
inline void mh_item(device const uint* cache, uint t, thread uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
device const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// One thread per segment (2^16 threads).
kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) {
mh_cache_segment(cache, gid);
}
// One thread per 64-byte item (dataset words / 16 threads).
kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* dataset [[buffer(1)]],
uint gid [[thread_position_in_grid]]) {
uint s[16];
mh_item(cache, gid, s);
device uint* d = dataset + gid * 16u;
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Program metadata for host.cu plus the launch wrappers defined in kernel.cu.
// Also included by proto-opencl/host.c (C99), which defines IGNEUM_NO_CUDA first and reads only the macros.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#ifndef IGNEUM_NO_CUDA
#include <cuda_runtime.h>
#endif
#define IGNEUM_SEED_STRING "igneum-genesis"
#define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973"
#define IGNEUM_GENERATOR 2
#define IGNEUM_PROGRAM_ATTEMPT 0
#define IGNEUM_PROGRAM_ID 0xd746ef93184dc1f8ull
#define IGNEUM_DAY_STRING "2026-10-03"
#define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033"
#define IGNEUM_DAY0 0x3067619fu
#define IGNEUM_DAY1 0x3c269176u
#define IGNEUM_DATASET_LOG2 28
#define IGNEUM_MASK 0x0fffffffu
#define IGNEUM_LANES 32
#define IGNEUM_ITERATIONS 8
#define IGNEUM_INSTR_COUNT 64
#define IGNEUM_LOADS_PER_HASH 128
#define IGNEUM_WIDE_LOADS_PER_HASH 0
#define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1"
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
#define IGNEUM_LOAD_CLASS "mx8+mm1430"
#define IGNEUM_CLASS_MIXER_MULT 8
#define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460))
#define IGNEUM_LOAD_SLOTS 16
#define IGNEUM_LOAD_MIX { 100, 0, 0 }
#define IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 } // loads of 4, 16, 64 bytes per program
#define IGNEUM_BYTES_PER_HASH 512
#define IGNEUM_FOLD_ROT 11
#define IGNEUM_FOLD_MUL 0x9e3779b1u
// Latency-shadow block (Counter ASIC 3.0 item 8, docs/analysis/latency-shadow-2026-10-06.md): NOT the lottery hash. A block of
// IGNEUM_SHADOW_INSTRS ALU instructions (the ten non-load families) runs IGNEUM_SHADOW_REPS times at the end of every
// iteration; the 16 loads, the acceptance rule and the base program are the class's without the shadow.
#define IGNEUM_SHADOW_INSTRS 0
#define IGNEUM_SHADOW_REPS 0
#define IGNEUM_SHADOW_INSTRS_PER_HASH 0
#define IGNEUM_SHADOW_OP_MIX ""
// Counter ASIC 4.0 research (experimental): IGNEUM_MM8_TILES int8 mma.m8n8k16 u8 tiles per iteration after the shadow block.
#define IGNEUM_MM8_TILES 1430
#define IGNEUM_MM8_TILES_PER_HASH 11440
// 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h)
#define IGNEUM_DATASET_MODE 1
#define IGNEUM_SEEDW_INIT { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u }
#define IGNEUM_KEY_INIT { 0x3067619fu, 0x3c269176u, 0x84a03b03u, 0xf8c63294u, 0xff977c5bu, 0xe60def3eu, 0x63630141u, 0xb8fbcb58u }
#define IGNEUM_CACHE_LOG2_WORDS 26
#define IGNEUM_CACHE_SEGMENT_LOG2_LINES 6
#define IGNEUM_CACHE_SEGMENTS 65536u
#define IGNEUM_ITEM_ROUNDS 8
#define IGNEUM_MIXER_MULT 8 // mixer applications per round and after the last read (class v3, docs/plans/mixer-x4.md)
#define IGNEUM_MIX_ROT_INIT { 20u, 20u, 19u, 4u, 26u, 3u, 3u, 27u }
#define IGNEUM_MIX_MUL_INIT { 0x42146205u, 0x52cbe0fbu, 0x7ecf4a03u, 0x6728907fu, 0xd81d9751u, 0x132952c3u, 0xf60de277u, 0x05358035u, 0xbaf6499du, 0xe4db9667u, 0x3e98f45du, 0xd0004eddu, 0x2691630du, 0x9beb3bcfu, 0xab310379u, 0x99cfb423u }
#define IGNEUM_MIX_RC_INIT { 0xbab68293u, 0xcc162340u, 0x6ce151ccu, 0xe62b8997u, 0xc9c80297u, 0xf74a1654u, 0x3d704af5u, 0x3cf522b7u, 0x2b9cac04u, 0xa880ac10u, 0x13e5dd1du, 0x6fc3e233u, 0x2d83eeacu, 0x9006e8bfu, 0x2c4b5362u, 0x31b49ee2u }
#ifndef IGNEUM_NO_CUDA
// Defined in kernel.cu. All launch on the default stream and return cudaGetLastError().
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments);
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems);
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps);
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#endif

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#define IGNEUM_VEC_WARPS 3
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
{ // base nonce 0
0xf8bf8814e2416cd8ull, 0xc1df90a403316be4ull, 0xbb787d32f45e15b4ull, 0x422e3ecf86983132ull, 0xaed418273c74197dull, 0x88cbdc6fff914ea9ull, 0x52457b80ae5bfd30ull, 0x5aa82c44125405bbull,
0x241b05accc893061ull, 0x3922a0033166f8a9ull, 0x660fe2c88f23d8b0ull, 0xbdd3700769c59c26ull, 0x13235fa1c27c06a0ull, 0x4a53c774acaca426ull, 0xada3cc0d840d682eull, 0x2e4edea8bc315874ull,
0x2738fcc54c92addbull, 0x3d3ef6d2f89288f1ull, 0x6bf6a8a963b0c773ull, 0x676e254bd1f6fb80ull, 0xb8d118e2cf40064bull, 0x46f197c31d7109adull, 0x69adbeb0148fc4d0ull, 0xee8f6125b98a9c88ull,
0xd4815fd2160b2b85ull, 0xd92ca82baf3e355eull, 0xa944dbf6bb30e11eull, 0x5af3c7e2d33b103full, 0xce9fd26dbee50e2dull, 0xbc25610e53326611ull, 0xf41f1ab121cd52b5ull, 0x64c33325a2b5d43bull
},
{ // base nonce 4096
0xb0bb9c2f786adf4dull, 0x806ba8d31f4e28d6ull, 0x5a2a835b1dc9d4b3ull, 0x6f28eeeea85118b6ull, 0x63e190b78790a6f3ull, 0x04088b6f953938aaull, 0x82eb1f881ce9ddb5ull, 0x9f91e5c7d996c7cfull,
0xbe0355dd8d714908ull, 0x344b05f526076ceeull, 0x81ebf0504e3a9ae2ull, 0x6c522256a53ec4b4ull, 0x1ece11df1618a118ull, 0xb10ded4ba9f77544ull, 0xf8d57b6d96fd61eaull, 0xd114be73fdb26740ull,
0x0be7112c4384a1c2ull, 0xa2f11d4a4c0c302aull, 0xfcd2146ec5fef56dull, 0xb0236e3a4cee2725ull, 0xc4e78111f99ada58ull, 0x9ab2b272ad18b1e7ull, 0x4eb50b5eda7970d0ull, 0x4dda2812d7105002ull,
0xa66f5ff9e123030full, 0x25c689a3d95794ccull, 0xd8264dd83a7e9d0full, 0x13aac7727f2307ccull, 0xd2539ea11d360940ull, 0x80760547b9bf48a6ull, 0xd3a86440129515d8ull, 0xc10a14c2898a6e66ull
},
{ // base nonce 1000000
0x9fa775319d068f6eull, 0xf9053cdb1e27f106ull, 0x55e9096bbe852422ull, 0xbffd11bade2c11f4ull, 0x2c14ec73bdcd0c03ull, 0x2c838a4d3aa8463full, 0x420f94c19067fcc8ull, 0xb33d361bd93e8dbeull,
0x64d4280f4d04ec98ull, 0x105c4e6b978f07d9ull, 0x1545cac655298f62ull, 0x8a2d5c71ec80c66dull, 0x211865bfbaf48819ull, 0x3c8de09457bb16bdull, 0x288d86d556917150ull, 0x44c3655c6cdff067ull,
0x7bc3d9f9785b5ddcull, 0x6b9db79ebdddb1c9ull, 0x7c78589466245632ull, 0x8a958a50a9e482ddull, 0xf283899605afb637ull, 0x9ca6069af0fedd82ull, 0x32adcd4cb7d6129cull, 0xbd99077ff9750508ull,
0xe2cdbb09d4ccb545ull, 0x2f8ca3d3d24f0d64ull, 0xc5293342a005568full, 0xf1427609c2e26234ull, 0x0d942b528f7cde27ull, 0x2f1dde333e26d338ull, 0x53a9d5353b5c71c5ull, 0x05278e408e3529d9ull
}
};
// Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455).
static const uint32_t IGNEUM_DS_HEAD[16] = {
0xfdad4319u, 0x1a7b68e1u, 0xde6db608u, 0x13d73892u, 0xd17f447au, 0xb2221ccfu, 0x9db004bdu, 0x57d7d367u,
0xdbc4cf34u, 0x697c009au, 0xc43af1d4u, 0x97f12b2eu, 0x74c37cd0u, 0xc651ea15u, 0x665a6d29u, 0x22330a2du
};
static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u;
static const uint32_t IGNEUM_DS_LAST = 0xa83e7aa6u;
// 64 sampled dataset words (index, value) computed on the Mac.
#define IGNEUM_DS_SAMPLES 64
static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = {
59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u
};
static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = {
0x3230bc7bu, 0x7fbfe2c9u, 0xb2690991u, 0x1745c7c5u, 0x0ab0ccafu, 0x1bf87d6bu, 0x160139fdu, 0x719817acu, 0x0155df4bu, 0xbe1e86c3u, 0x680bcd6cu, 0x79c3dc6cu, 0x181e7e5fu, 0x0713a109u, 0xc705dd9fu, 0x3933b7a8u, 0xdd1c0431u, 0x50522b30u, 0xa0020b38u, 0xbff39e96u, 0x21b67e18u, 0x740f8db3u, 0x2baba568u, 0x2c9bef83u, 0x0ad9b671u, 0xc4327869u, 0x7b4fd7d0u, 0x2c29965fu, 0xec56f15fu, 0x61111746u, 0x303a1d6eu, 0xbddcfd1au, 0xf829a355u, 0x6d5df2a9u, 0x01ab8e44u, 0x06d13507u, 0xda8dcfc6u, 0x01a703e1u, 0xafe7d2c1u, 0xc091c3a2u, 0xac1814feu, 0x6e6ff62au, 0x8fdf01bau, 0xdd3f7159u, 0xdfa0d75cu, 0x26684c35u, 0x7f441e63u, 0x88df2570u, 0x8aa4d5ebu, 0xcc816c05u, 0x434df890u, 0xcd392ad6u, 0x1ab4cb63u, 0x595926fau, 0x7cd76b41u, 0x20cb95c4u, 0x13cf823fu, 0xf9daf901u, 0xff9af40au, 0x2c7dfa51u, 0x871206dbu, 0x938c116cu, 0xb64bf199u, 0x5751f874u
};
// Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words.
static const uint32_t IGNEUM_CACHE_HEAD[16] = {
0x355a86d2u, 0x7957db1cu, 0xd21772afu, 0x6fc1e09bu, 0xd55ce61du, 0x6e6a278bu, 0xd3f543ceu, 0x223d8e82u,
0x143ab337u, 0x2e9f05bdu, 0x2eb389bfu, 0x0c6e449eu, 0x5cfa4222u, 0xba6560feu, 0x8e3e1aa4u, 0xdbcc1d53u
};
static const uint32_t IGNEUM_CACHE_LAST[16] = {
0x41190d91u, 0xbd277957u, 0x22ddbb49u, 0x6986f207u, 0xdf69a4d6u, 0x26401a3au, 0x818230fbu, 0xc417122du,
0x3597b211u, 0xb553ce55u, 0xcf39cc0du, 0x3b7fc43au, 0x3fd43b00u, 0x67e1c80eu, 0xffa7ea7du, 0xca2960abu
};
static const uint64_t IGNEUM_CACHE_FNV64 = 0x48c4f5bf24166b2eull;

36
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{
"seed": "igneum-genesis",
"day": "2026-10-03",
"dataset_mode": "memory-hard",
"dataset_log2_words": 28,
"mask": "0x0fffffff",
"lanes": 32,
"source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset",
"warps": [
{"base_nonce": 0, "expected": [
"0xf8bf8814e2416cd8", "0xc1df90a403316be4", "0xbb787d32f45e15b4", "0x422e3ecf86983132", "0xaed418273c74197d", "0x88cbdc6fff914ea9", "0x52457b80ae5bfd30", "0x5aa82c44125405bb",
"0x241b05accc893061", "0x3922a0033166f8a9", "0x660fe2c88f23d8b0", "0xbdd3700769c59c26", "0x13235fa1c27c06a0", "0x4a53c774acaca426", "0xada3cc0d840d682e", "0x2e4edea8bc315874",
"0x2738fcc54c92addb", "0x3d3ef6d2f89288f1", "0x6bf6a8a963b0c773", "0x676e254bd1f6fb80", "0xb8d118e2cf40064b", "0x46f197c31d7109ad", "0x69adbeb0148fc4d0", "0xee8f6125b98a9c88",
"0xd4815fd2160b2b85", "0xd92ca82baf3e355e", "0xa944dbf6bb30e11e", "0x5af3c7e2d33b103f", "0xce9fd26dbee50e2d", "0xbc25610e53326611", "0xf41f1ab121cd52b5", "0x64c33325a2b5d43b"
]},
{"base_nonce": 4096, "expected": [
"0xb0bb9c2f786adf4d", "0x806ba8d31f4e28d6", "0x5a2a835b1dc9d4b3", "0x6f28eeeea85118b6", "0x63e190b78790a6f3", "0x04088b6f953938aa", "0x82eb1f881ce9ddb5", "0x9f91e5c7d996c7cf",
"0xbe0355dd8d714908", "0x344b05f526076cee", "0x81ebf0504e3a9ae2", "0x6c522256a53ec4b4", "0x1ece11df1618a118", "0xb10ded4ba9f77544", "0xf8d57b6d96fd61ea", "0xd114be73fdb26740",
"0x0be7112c4384a1c2", "0xa2f11d4a4c0c302a", "0xfcd2146ec5fef56d", "0xb0236e3a4cee2725", "0xc4e78111f99ada58", "0x9ab2b272ad18b1e7", "0x4eb50b5eda7970d0", "0x4dda2812d7105002",
"0xa66f5ff9e123030f", "0x25c689a3d95794cc", "0xd8264dd83a7e9d0f", "0x13aac7727f2307cc", "0xd2539ea11d360940", "0x80760547b9bf48a6", "0xd3a86440129515d8", "0xc10a14c2898a6e66"
]},
{"base_nonce": 1000000, "expected": [
"0x9fa775319d068f6e", "0xf9053cdb1e27f106", "0x55e9096bbe852422", "0xbffd11bade2c11f4", "0x2c14ec73bdcd0c03", "0x2c838a4d3aa8463f", "0x420f94c19067fcc8", "0xb33d361bd93e8dbe",
"0x64d4280f4d04ec98", "0x105c4e6b978f07d9", "0x1545cac655298f62", "0x8a2d5c71ec80c66d", "0x211865bfbaf48819", "0x3c8de09457bb16bd", "0x288d86d556917150", "0x44c3655c6cdff067",
"0x7bc3d9f9785b5ddc", "0x6b9db79ebdddb1c9", "0x7c78589466245632", "0x8a958a50a9e482dd", "0xf283899605afb637", "0x9ca6069af0fedd82", "0x32adcd4cb7d6129c", "0xbd99077ff9750508",
"0xe2cdbb09d4ccb545", "0x2f8ca3d3d24f0d64", "0xc5293342a005568f", "0xf1427609c2e26234", "0x0d942b528f7cde27", "0x2f1dde333e26d338", "0x53a9d5353b5c71c5", "0x05278e408e3529d9"
]}
],
"dataset_head": ["0xfdad4319", "0x1a7b68e1", "0xde6db608", "0x13d73892", "0xd17f447a", "0xb2221ccf", "0x9db004bd", "0x57d7d367", "0xdbc4cf34", "0x697c009a", "0xc43af1d4", "0x97f12b2e", "0x74c37cd0", "0xc651ea15", "0x665a6d29", "0x22330a2d"],
"dataset_last_index": 268435455,
"dataset_last": "0xa83e7aa6",
"dataset_samples": [{"index": 59471966, "value": "0x3230bc7b"}, {"index": 217795994, "value": "0x7fbfe2c9"}, {"index": 208353206, "value": "0xb2690991"}, {"index": 42483309, "value": "0x1745c7c5"}, {"index": 172547758, "value": "0x0ab0ccaf"}, {"index": 148076330, "value": "0x1bf87d6b"}, {"index": 183853158, "value": "0x160139fd"}, {"index": 214389424, "value": "0x719817ac"}, {"index": 267488061, "value": "0x0155df4b"}, {"index": 169781097, "value": "0xbe1e86c3"}, {"index": 184093494, "value": "0x680bcd6c"}, {"index": 153880993, "value": "0x79c3dc6c"}, {"index": 84977930, "value": "0x181e7e5f"}, {"index": 46426879, "value": "0x0713a109"}, {"index": 3093825, "value": "0xc705dd9f"}, {"index": 225364072, "value": "0x3933b7a8"}, {"index": 44593546, "value": "0xdd1c0431"}, {"index": 260713159, "value": "0x50522b30"}, {"index": 168250303, "value": "0xa0020b38"}, {"index": 52384140, "value": "0xbff39e96"}, {"index": 223401610, "value": "0x21b67e18"}, {"index": 45554030, "value": "0x740f8db3"}, {"index": 95410555, "value": "0x2baba568"}, {"index": 175039924, "value": "0x2c9bef83"}, {"index": 79171087, "value": "0x0ad9b671"}, {"index": 267580473, "value": "0xc4327869"}, {"index": 24168642, "value": "0x7b4fd7d0"}, {"index": 37981670, "value": "0x2c29965f"}, {"index": 171551130, "value": "0xec56f15f"}, {"index": 195559979, "value": "0x61111746"}, {"index": 204611762, "value": "0x303a1d6e"}, {"index": 140997658, "value": "0xbddcfd1a"}, {"index": 138925853, "value": "0xf829a355"}, {"index": 86637313, "value": "0x6d5df2a9"}, {"index": 20736778, "value": "0x01ab8e44"}, {"index": 219665210, "value": "0x06d13507"}, {"index": 160430336, "value": "0xda8dcfc6"}, {"index": 264654675, "value": "0x01a703e1"}, {"index": 8013395, "value": "0xafe7d2c1"}, {"index": 228945585, "value": "0xc091c3a2"}, {"index": 213884386, "value": "0xac1814fe"}, {"index": 104419827, "value": "0x6e6ff62a"}, {"index": 44185464, "value": "0x8fdf01ba"}, {"index": 142737231, "value": "0xdd3f7159"}, {"index": 99284897, "value": "0xdfa0d75c"}, {"index": 132475900, "value": "0x26684c35"}, {"index": 61861762, "value": "0x7f441e63"}, {"index": 132056166, "value": "0x88df2570"}, {"index": 262388043, "value": "0x8aa4d5eb"}, {"index": 91878046, "value": "0xcc816c05"}, {"index": 117353561, "value": "0x434df890"}, {"index": 124768597, "value": "0xcd392ad6"}, {"index": 71352993, "value": "0x1ab4cb63"}, {"index": 190698941, "value": "0x595926fa"}, {"index": 46055428, "value": "0x7cd76b41"}, {"index": 55281366, "value": "0x20cb95c4"}, {"index": 165145231, "value": "0x13cf823f"}, {"index": 106810753, "value": "0xf9daf901"}, {"index": 171985651, "value": "0xff9af40a"}, {"index": 232085256, "value": "0x2c7dfa51"}, {"index": 159510492, "value": "0x871206db"}, {"index": 40072060, "value": "0x938c116c"}, {"index": 209107596, "value": "0xb64bf199"}, {"index": 39023794, "value": "0x5751f874"}],
"cache_head": ["0x355a86d2", "0x7957db1c", "0xd21772af", "0x6fc1e09b", "0xd55ce61d", "0x6e6a278b", "0xd3f543ce", "0x223d8e82", "0x143ab337", "0x2e9f05bd", "0x2eb389bf", "0x0c6e449e", "0x5cfa4222", "0xba6560fe", "0x8e3e1aa4", "0xdbcc1d53"],
"cache_last_line": ["0x41190d91", "0xbd277957", "0x22ddbb49", "0x6986f207", "0xdf69a4d6", "0x26401a3a", "0x818230fb", "0xc417122d", "0x3597b211", "0xb553ce55", "0xcf39cc0d", "0x3b7fc43a", "0x3fd43b00", "0x67e1c80e", "0xffa7ea7d", "0xca2960ab"],
"cache_fnv1a64": "0x48c4f5bf24166b2e"
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = sub_group_shuffle((a), (uint)(i))
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#define IGNEUM_SHFL_IDX(dst, a, i) dst = intel_sub_group_shuffle((a), (uint)(i))
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#define IGNEUM_SHFL_IDX(dst, a, i) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u) + (uint)(i)]; xk += 1u; }
#endif
// int8 tile reference (Counter ASIC 4.0 research): 12 index shuffles and 32 byte products per lane; the PTX mma.m8n8k16 u8 layout.
#define IGNEUM_MM8_REF(av, bv, d0, d1) { uint row_ = lane >> 2, col0_ = 2u * (lane & 3u); uint acc0_ = 0u, acc1_ = 0u; for (uint j_ = 0u; j_ < 4u; ++j_) { uint aw_, bw0_, bw1_; IGNEUM_SHFL_IDX(aw_, (av), 4u * row_ + j_); IGNEUM_SHFL_IDX(bw0_, (bv), 4u * col0_ + j_); IGNEUM_SHFL_IDX(bw1_, (bv), 4u * (col0_ + 1u) + j_); for (uint t_ = 0u; t_ < 4u; ++t_) { uint ab_ = (aw_ >> (8u * t_)) & 0xffu; acc0_ += ab_ * ((bw0_ >> (8u * t_)) & 0xffu); acc1_ += ab_ * ((bw1_ >> (8u * t_)) & 0xffu); } } d0 = acc0_; d1 = acc1_; }
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, uint t, uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, t, s);
__global uint* d = ds + ((ulong)t * 16u);
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
uint lane = lid & 31u;
{ uint x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 512 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r4 += d0_; r1 += d1_; } // t128 mm8 a=r6 b=r7 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r6 += d0_; r3 += d1_; } // t129 mm8 a=r3 b=r2 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r4, d0_, d1_); r2 += d0_; r1 += d1_; } // t130 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r3 += d0_; r1 += d1_; } // t131 mm8 a=r3 b=r5 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r0 += d0_; r6 += d1_; } // t132 mm8 a=r0 b=r7 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r0 += d0_; r1 += d1_; } // t133 mm8 a=r2 b=r6 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t134 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r4 += d0_; r5 += d1_; } // t135 mm8 a=r0 b=r2 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t136 mm8 a=r3 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r0, d0_, d1_); r4 += d0_; r6 += d1_; } // t137 mm8 a=r7 b=r0 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r4 += d0_; r2 += d1_; } // t138 mm8 a=r2 b=r2 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r4, d0_, d1_); r2 += d0_; r7 += d1_; } // t139 mm8 a=r0 b=r4 c=r2 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r1 += d0_; r6 += d1_; } // t140 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t141 mm8 a=r5 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r6 += d0_; r2 += d1_; } // t142 mm8 a=r2 b=r2 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r7 += d0_; r1 += d1_; } // t143 mm8 a=r4 b=r3 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t144 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r6 += d0_; r5 += d1_; } // t145 mm8 a=r7 b=r2 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r7 += d1_; } // t146 mm8 a=r2 b=r7 c=r2 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r3 += d0_; r0 += d1_; } // t147 mm8 a=r3 b=r1 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r0 += d0_; r6 += d1_; } // t148 mm8 a=r2 b=r1 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r7 += d0_; r1 += d1_; } // t149 mm8 a=r4 b=r6 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r7 += d0_; r0 += d1_; } // t150 mm8 a=r3 b=r6 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r2 += d0_; r4 += d1_; } // t151 mm8 a=r1 b=r4 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r5 += d0_; r1 += d1_; } // t152 mm8 a=r3 b=r1 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r2 += d0_; r3 += d1_; } // t153 mm8 a=r0 b=r3 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r0 += d0_; r4 += d1_; } // t154 mm8 a=r7 b=r3 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r7 += d0_; r5 += d1_; } // t155 mm8 a=r1 b=r3 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r2 += d0_; r3 += d1_; } // t156 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r4 += d0_; r5 += d1_; } // t157 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r0 += d0_; r4 += d1_; } // t158 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r5 += d0_; r2 += d1_; } // t159 mm8 a=r1 b=r0 c=r5 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r5 += d0_; r7 += d1_; } // t160 mm8 a=r0 b=r1 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r7 += d0_; r0 += d1_; } // t161 mm8 a=r4 b=r0 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r6 += d0_; r1 += d1_; } // t162 mm8 a=r6 b=r6 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r7 += d0_; r3 += d1_; } // t163 mm8 a=r5 b=r3 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t164 mm8 a=r0 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r1 += d0_; r5 += d1_; } // t165 mm8 a=r6 b=r5 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r4 += d0_; r0 += d1_; } // t166 mm8 a=r6 b=r5 c=r4 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r3 += d0_; r7 += d1_; } // t167 mm8 a=r4 b=r5 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r0 += d0_; r7 += d1_; } // t168 mm8 a=r3 b=r6 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r4 += d0_; r3 += d1_; } // t169 mm8 a=r6 b=r2 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r0 += d0_; r4 += d1_; } // t170 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r2 += d0_; r3 += d1_; } // t171 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r5 += d0_; r2 += d1_; } // t172 mm8 a=r7 b=r3 c=r5 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t173 mm8 a=r0 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r5 += d0_; r6 += d1_; } // t174 mm8 a=r6 b=r6 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r3 += d0_; r4 += d1_; } // t175 mm8 a=r1 b=r6 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r5 += d1_; } // t176 mm8 a=r2 b=r4 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r7 += d0_; r2 += d1_; } // t177 mm8 a=r1 b=r7 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r7 += d0_; r3 += d1_; } // t178 mm8 a=r4 b=r2 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r5 += d0_; r1 += d1_; } // t179 mm8 a=r5 b=r2 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r4, d0_, d1_); r2 += d0_; r1 += d1_; } // t180 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r2 += d0_; r4 += d1_; } // t181 mm8 a=r3 b=r5 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r4 += d0_; r3 += d1_; } // t182 mm8 a=r1 b=r1 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r0 += d0_; r7 += d1_; } // t183 mm8 a=r3 b=r1 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r0 += d0_; r7 += d1_; } // t184 mm8 a=r7 b=r4 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r6 += d0_; r3 += d1_; } // t185 mm8 a=r5 b=r0 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r6 += d1_; } // t186 mm8 a=r2 b=r5 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r0 += d0_; r7 += d1_; } // t187 mm8 a=r3 b=r0 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r5 += d0_; r0 += d1_; } // t188 mm8 a=r1 b=r4 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r5 += d0_; r4 += d1_; } // t189 mm8 a=r7 b=r2 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r2 += d0_; r0 += d1_; } // t190 mm8 a=r1 b=r5 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t191 mm8 a=r2 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t192 mm8 a=r5 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t193 mm8 a=r2 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r0 += d0_; r5 += d1_; } // t194 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r2 += d0_; r4 += d1_; } // t195 mm8 a=r2 b=r7 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r2 += d0_; r5 += d1_; } // t196 mm8 a=r5 b=r6 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r6 += d0_; r5 += d1_; } // t197 mm8 a=r5 b=r3 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r1 += d1_; } // t198 mm8 a=r1 b=r0 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r0 += d0_; r4 += d1_; } // t199 mm8 a=r2 b=r5 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t200 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r2 += d0_; r1 += d1_; } // t201 mm8 a=r7 b=r2 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r5 += d0_; r6 += d1_; } // t202 mm8 a=r2 b=r5 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r1 += d0_; r6 += d1_; } // t203 mm8 a=r0 b=r5 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r3 += d0_; r7 += d1_; } // t204 mm8 a=r4 b=r7 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t205 mm8 a=r3 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r7 += d0_; r3 += d1_; } // t206 mm8 a=r0 b=r6 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r4 += d1_; } // t207 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r6 += d0_; r5 += d1_; } // t208 mm8 a=r0 b=r1 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r6 += d0_; r2 += d1_; } // t209 mm8 a=r4 b=r4 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r2 += d0_; r5 += d1_; } // t210 mm8 a=r7 b=r1 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r5 += d0_; r6 += d1_; } // t211 mm8 a=r1 b=r5 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t212 mm8 a=r2 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t213 mm8 a=r2 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r5 += d0_; r7 += d1_; } // t214 mm8 a=r4 b=r6 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r2 += d0_; r6 += d1_; } // t215 mm8 a=r7 b=r3 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t216 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r0 += d0_; r6 += d1_; } // t217 mm8 a=r5 b=r7 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r0 += d1_; } // t218 mm8 a=r7 b=r1 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r3 += d0_; r1 += d1_; } // t219 mm8 a=r2 b=r1 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r4 += d0_; r5 += d1_; } // t220 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t221 mm8 a=r7 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r2 += d0_; r1 += d1_; } // t222 mm8 a=r0 b=r6 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r7 += d0_; r0 += d1_; } // t223 mm8 a=r2 b=r2 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r6 += d0_; r2 += d1_; } // t224 mm8 a=r1 b=r1 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t225 mm8 a=r2 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t226 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r5 += d0_; r6 += d1_; } // t227 mm8 a=r3 b=r5 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r3 += d0_; r1 += d1_; } // t228 mm8 a=r7 b=r1 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t229 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r5 += d0_; r6 += d1_; } // t230 mm8 a=r0 b=r3 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r0 += d1_; } // t231 mm8 a=r1 b=r3 c=r4 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r0 += d0_; r1 += d1_; } // t232 mm8 a=r5 b=r4 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r0 += d0_; r4 += d1_; } // t233 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r2 += d0_; r1 += d1_; } // t234 mm8 a=r2 b=r0 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t235 mm8 a=r3 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r5 += d1_; } // t236 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t237 mm8 a=r3 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r0 += d0_; r2 += d1_; } // t238 mm8 a=r2 b=r0 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r1 += d0_; r0 += d1_; } // t239 mm8 a=r5 b=r7 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r4 += d0_; r6 += d1_; } // t240 mm8 a=r2 b=r7 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r3 += d0_; r7 += d1_; } // t241 mm8 a=r0 b=r1 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r2 += d0_; r7 += d1_; } // t242 mm8 a=r0 b=r2 c=r2 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r1 += d0_; r5 += d1_; } // t243 mm8 a=r4 b=r4 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r0 += d0_; r7 += d1_; } // t244 mm8 a=r7 b=r6 c=r0 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r2 += d0_; r0 += d1_; } // t245 mm8 a=r4 b=r4 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t246 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t247 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r5, d0_, d1_); r7 += d0_; r3 += d1_; } // t248 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r0 += d0_; r5 += d1_; } // t249 mm8 a=r4 b=r4 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r0 += d0_; r1 += d1_; } // t250 mm8 a=r0 b=r6 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t251 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r5 += d0_; r4 += d1_; } // t252 mm8 a=r0 b=r2 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t253 mm8 a=r5 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t254 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r0 += d0_; r3 += d1_; } // t255 mm8 a=r5 b=r0 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r3 += d0_; r4 += d1_; } // t256 mm8 a=r2 b=r1 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r6 += d0_; r0 += d1_; } // t257 mm8 a=r4 b=r3 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r7 += d0_; r3 += d1_; } // t258 mm8 a=r4 b=r1 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r5, d0_, d1_); r3 += d0_; r0 += d1_; } // t259 mm8 a=r5 b=r5 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r3 += d0_; r0 += d1_; } // t260 mm8 a=r3 b=r2 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t261 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r2 += d0_; r5 += d1_; } // t262 mm8 a=r6 b=r4 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r2 += d0_; r1 += d1_; } // t263 mm8 a=r6 b=r4 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r1 += d0_; r4 += d1_; } // t264 mm8 a=r7 b=r2 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r3 += d0_; r1 += d1_; } // t265 mm8 a=r6 b=r1 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r0, d0_, d1_); r7 += d0_; r0 += d1_; } // t266 mm8 a=r0 b=r0 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r4 += d1_; } // t267 mm8 a=r6 b=r3 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r6 += d0_; r5 += d1_; } // t268 mm8 a=r1 b=r0 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r7 += d0_; r3 += d1_; } // t269 mm8 a=r7 b=r7 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r7 += d0_; r0 += d1_; } // t270 mm8 a=r6 b=r2 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r5 += d0_; r3 += d1_; } // t271 mm8 a=r0 b=r3 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r0 += d0_; r3 += d1_; } // t272 mm8 a=r6 b=r0 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t273 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r7 += d0_; r6 += d1_; } // t274 mm8 a=r1 b=r0 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r1 += d0_; r4 += d1_; } // t275 mm8 a=r1 b=r3 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r6 += d0_; r2 += d1_; } // t276 mm8 a=r1 b=r5 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r4 += d0_; r7 += d1_; } // t277 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r0, d0_, d1_); r6 += d0_; r7 += d1_; } // t278 mm8 a=r0 b=r0 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r2 += d0_; r4 += d1_; } // t279 mm8 a=r2 b=r4 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r2, d0_, d1_); r3 += d0_; r5 += d1_; } // t280 mm8 a=r7 b=r2 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r4 += d0_; r2 += d1_; } // t281 mm8 a=r1 b=r0 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r5 += d0_; r1 += d1_; } // t282 mm8 a=r0 b=r1 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t283 mm8 a=r0 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r0 += d0_; r2 += d1_; } // t284 mm8 a=r1 b=r5 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r5 += d0_; r0 += d1_; } // t285 mm8 a=r4 b=r7 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r2 += d0_; r0 += d1_; } // t286 mm8 a=r1 b=r0 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r7 += d0_; r4 += d1_; } // t287 mm8 a=r7 b=r1 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t288 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r4 += d1_; } // t289 mm8 a=r0 b=r5 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r6 += d0_; r7 += d1_; } // t290 mm8 a=r3 b=r2 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r7 += d0_; r1 += d1_; } // t291 mm8 a=r7 b=r4 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r6 += d0_; r3 += d1_; } // t292 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r5, d0_, d1_); r6 += d0_; r4 += d1_; } // t293 mm8 a=r5 b=r5 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r1 += d0_; r6 += d1_; } // t294 mm8 a=r5 b=r7 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r1 += d0_; r3 += d1_; } // t295 mm8 a=r0 b=r7 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r5 += d0_; r6 += d1_; } // t296 mm8 a=r6 b=r1 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r3 += d0_; r5 += d1_; } // t297 mm8 a=r4 b=r5 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r3 += d0_; r1 += d1_; } // t298 mm8 a=r6 b=r0 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r2 += d0_; r3 += d1_; } // t299 mm8 a=r6 b=r0 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r4 += d0_; r2 += d1_; } // t300 mm8 a=r6 b=r4 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r6 += d0_; r3 += d1_; } // t301 mm8 a=r6 b=r4 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r4 += d1_; } // t302 mm8 a=r7 b=r6 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r3 += d0_; r6 += d1_; } // t303 mm8 a=r3 b=r2 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r4 += d1_; } // t304 mm8 a=r6 b=r5 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r0 += d0_; r2 += d1_; } // t305 mm8 a=r4 b=r5 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r0 += d0_; r2 += d1_; } // t306 mm8 a=r3 b=r1 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r5 += d0_; r0 += d1_; } // t307 mm8 a=r4 b=r3 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t308 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r1 += d0_; r4 += d1_; } // t309 mm8 a=r2 b=r1 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r2 += d0_; r3 += d1_; } // t310 mm8 a=r6 b=r1 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r3 += d0_; r2 += d1_; } // t311 mm8 a=r4 b=r6 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t312 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r6, d0_, d1_); r7 += d0_; r1 += d1_; } // t313 mm8 a=r2 b=r6 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r2 += d0_; r1 += d1_; } // t314 mm8 a=r0 b=r3 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r6 += d0_; r2 += d1_; } // t315 mm8 a=r7 b=r1 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r6 += d1_; } // t316 mm8 a=r2 b=r4 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r3 += d0_; r6 += d1_; } // t317 mm8 a=r1 b=r6 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r1, d0_, d1_); r1 += d0_; r0 += d1_; } // t318 mm8 a=r2 b=r1 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r6 += d0_; r3 += d1_; } // t319 mm8 a=r0 b=r2 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r6 += d0_; r2 += d1_; } // t320 mm8 a=r5 b=r2 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t321 mm8 a=r7 b=r4 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r1 += d1_; } // t322 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r3, d0_, d1_); r2 += d0_; r3 += d1_; } // t323 mm8 a=r4 b=r3 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r2 += d0_; r0 += d1_; } // t324 mm8 a=r5 b=r7 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t325 mm8 a=r6 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r7 += d0_; r6 += d1_; } // t326 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r3 += d0_; r0 += d1_; } // t327 mm8 a=r1 b=r5 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r1, d0_, d1_); r1 += d0_; r6 += d1_; } // t328 mm8 a=r0 b=r1 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r7 += d0_; r1 += d1_; } // t329 mm8 a=r0 b=r3 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r4 += d0_; r0 += d1_; } // t330 mm8 a=r6 b=r7 c=r4 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t331 mm8 a=r4 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r6 += d0_; r3 += d1_; } // t332 mm8 a=r4 b=r4 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r4 += d0_; r2 += d1_; } // t333 mm8 a=r4 b=r6 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r0 += d0_; r1 += d1_; } // t334 mm8 a=r2 b=r2 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r2 += d1_; } // t335 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r2 += d0_; r3 += d1_; } // t336 mm8 a=r4 b=r0 c=r2 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r4, d0_, d1_); r0 += d0_; r3 += d1_; } // t337 mm8 a=r1 b=r4 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r2 += d0_; r7 += d1_; } // t338 mm8 a=r3 b=r7 c=r2 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r7 += d0_; r6 += d1_; } // t339 mm8 a=r5 b=r1 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r7 += d0_; r5 += d1_; } // t340 mm8 a=r5 b=r0 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r7 += d0_; r5 += d1_; } // t341 mm8 a=r6 b=r6 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r0 += d0_; r4 += d1_; } // t342 mm8 a=r4 b=r7 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r4, d0_, d1_); r4 += d0_; r6 += d1_; } // t343 mm8 a=r0 b=r4 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r4 += d0_; r6 += d1_; } // t344 mm8 a=r2 b=r5 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r3 += d0_; r1 += d1_; } // t345 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r7 += d0_; r3 += d1_; } // t346 mm8 a=r6 b=r0 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r3 += d0_; r5 += d1_; } // t347 mm8 a=r5 b=r3 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r4, d0_, d1_); r4 += d0_; r5 += d1_; } // t348 mm8 a=r0 b=r4 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r7 += d1_; } // t349 mm8 a=r6 b=r1 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r3 += d0_; r5 += d1_; } // t350 mm8 a=r1 b=r5 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r4 += d0_; r5 += d1_; } // t351 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r6 += d0_; r0 += d1_; } // t352 mm8 a=r4 b=r1 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r1 += d0_; r4 += d1_; } // t353 mm8 a=r7 b=r3 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r1 += d0_; r5 += d1_; } // t354 mm8 a=r4 b=r1 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r5, d0_, d1_); r0 += d0_; r1 += d1_; } // t355 mm8 a=r4 b=r5 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r0 += d0_; r4 += d1_; } // t356 mm8 a=r7 b=r6 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r7 += d0_; r5 += d1_; } // t357 mm8 a=r7 b=r3 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r5 += d0_; r7 += d1_; } // t358 mm8 a=r4 b=r7 c=r5 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r5 += d1_; } // t359 mm8 a=r2 b=r7 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r0 += d0_; r2 += d1_; } // t360 mm8 a=r4 b=r4 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r5 += d0_; r6 += d1_; } // t361 mm8 a=r2 b=r2 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r3 += d0_; r0 += d1_; } // t362 mm8 a=r2 b=r7 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r5 += d0_; r0 += d1_; } // t363 mm8 a=r7 b=r6 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r0 += d0_; r5 += d1_; } // t364 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r5 += d0_; r4 += d1_; } // t365 mm8 a=r6 b=r6 c=r5 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r2 += d0_; r5 += d1_; } // t366 mm8 a=r7 b=r7 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t367 mm8 a=r4 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r0, d0_, d1_); r3 += d0_; r5 += d1_; } // t368 mm8 a=r7 b=r0 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r6 += d0_; r0 += d1_; } // t369 mm8 a=r1 b=r0 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r7 += d0_; r4 += d1_; } // t370 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r2 += d0_; r6 += d1_; } // t371 mm8 a=r5 b=r4 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r6 += d0_; r2 += d1_; } // t372 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r6, d0_, d1_); r2 += d0_; r4 += d1_; } // t373 mm8 a=r4 b=r6 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r5, d0_, d1_); r0 += d0_; r4 += d1_; } // t374 mm8 a=r1 b=r5 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r6 += d0_; r2 += d1_; } // t375 mm8 a=r6 b=r5 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r0 += d0_; r3 += d1_; } // t376 mm8 a=r3 b=r6 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r6 += d0_; r4 += d1_; } // t377 mm8 a=r6 b=r4 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r2 += d0_; r4 += d1_; } // t378 mm8 a=r6 b=r3 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r2 += d0_; r4 += d1_; } // t379 mm8 a=r3 b=r0 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r6 += d0_; r2 += d1_; } // t380 mm8 a=r2 b=r0 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r1 += d0_; r2 += d1_; } // t381 mm8 a=r3 b=r5 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r2 += d0_; r4 += d1_; } // t382 mm8 a=r5 b=r2 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r0 += d0_; r2 += d1_; } // t383 mm8 a=r1 b=r2 c=r0 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r1 += d0_; r0 += d1_; } // t384 mm8 a=r3 b=r1 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r7 += d0_; r5 += d1_; } // t385 mm8 a=r6 b=r0 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r1 += d0_; r7 += d1_; } // t386 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r2 += d0_; r4 += d1_; } // t387 mm8 a=r3 b=r7 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r1 += d0_; r2 += d1_; } // t388 mm8 a=r3 b=r0 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r5 += d0_; r3 += d1_; } // t389 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r1 += d0_; r4 += d1_; } // t390 mm8 a=r5 b=r4 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r4 += d0_; r1 += d1_; } // t391 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r3 += d0_; r0 += d1_; } // t392 mm8 a=r2 b=r3 c=r3 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r6, d0_, d1_); r5 += d0_; r0 += d1_; } // t393 mm8 a=r3 b=r6 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r1 += d0_; r2 += d1_; } // t394 mm8 a=r0 b=r7 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r2 += d0_; r4 += d1_; } // t395 mm8 a=r0 b=r7 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r4 += d1_; } // t396 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t397 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r7 += d0_; r0 += d1_; } // t398 mm8 a=r6 b=r5 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r3, d0_, d1_); r3 += d0_; r5 += d1_; } // t399 mm8 a=r6 b=r3 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r0 += d0_; r4 += d1_; } // t400 mm8 a=r2 b=r7 c=r0 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r2 += d0_; r1 += d1_; } // t401 mm8 a=r7 b=r6 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r0, d0_, d1_); r7 += d0_; r1 += d1_; } // t402 mm8 a=r0 b=r0 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r1 += d0_; r0 += d1_; } // t403 mm8 a=r7 b=r4 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r1, d0_, d1_); r1 += d0_; r4 += d1_; } // t404 mm8 a=r1 b=r1 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r3 += d0_; r6 += d1_; } // t405 mm8 a=r6 b=r6 c=r3 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r4 += d0_; r3 += d1_; } // t406 mm8 a=r6 b=r1 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r2 += d0_; r4 += d1_; } // t407 mm8 a=r5 b=r7 c=r2 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r4 += d0_; r1 += d1_; } // t408 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r4, d0_, d1_); r4 += d0_; r7 += d1_; } // t409 mm8 a=r3 b=r4 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r5, d0_, d1_); r5 += d0_; r2 += d1_; } // t410 mm8 a=r0 b=r5 c=r5 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r5 += d0_; r1 += d1_; } // t411 mm8 a=r2 b=r0 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r4, d0_, d1_); r3 += d0_; r1 += d1_; } // t412 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r6 += d0_; r2 += d1_; } // t413 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r0 += d0_; r3 += d1_; } // t414 mm8 a=r7 b=r1 c=r0 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r5 += d0_; r1 += d1_; } // t415 mm8 a=r4 b=r7 c=r5 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r4, d0_, d1_); r3 += d0_; r5 += d1_; } // t416 mm8 a=r5 b=r4 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t417 mm8 a=r6 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r3, d0_, d1_); r1 += d0_; r5 += d1_; } // t418 mm8 a=r1 b=r3 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r0, d0_, d1_); r0 += d0_; r6 += d1_; } // t419 mm8 a=r5 b=r0 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r2, d0_, d1_); r7 += d0_; r6 += d1_; } // t420 mm8 a=r4 b=r2 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r3 += d0_; r7 += d1_; } // t421 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r4 += d0_; r3 += d1_; } // t422 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r0 += d1_; } // t423 mm8 a=r1 b=r7 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r6 += d0_; r5 += d1_; } // t424 mm8 a=r5 b=r1 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r6 += d0_; r5 += d1_; } // t425 mm8 a=r2 b=r7 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r5 += d0_; r0 += d1_; } // t426 mm8 a=r1 b=r6 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t427 mm8 a=r6 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r2, d0_, d1_); r7 += d0_; r4 += d1_; } // t428 mm8 a=r6 b=r2 c=r7 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r3, d0_, d1_); r7 += d0_; r0 += d1_; } // t429 mm8 a=r3 b=r3 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r3 += d0_; r5 += d1_; } // t430 mm8 a=r7 b=r7 c=r3 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r1 += d0_; r0 += d1_; } // t431 mm8 a=r6 b=r4 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r3 += d0_; r4 += d1_; } // t432 mm8 a=r3 b=r2 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r5 += d0_; r0 += d1_; } // t433 mm8 a=r3 b=r0 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r5 += d0_; r3 += d1_; } // t434 mm8 a=r0 b=r7 c=r5 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r5, d0_, d1_); r6 += d0_; r3 += d1_; } // t435 mm8 a=r7 b=r5 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r0 += d0_; r5 += d1_; } // t436 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r7, d0_, d1_); r3 += d0_; r4 += d1_; } // t437 mm8 a=r0 b=r7 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r4 += d0_; r7 += d1_; } // t438 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r7, d0_, d1_); r3 += d0_; r2 += d1_; } // t439 mm8 a=r4 b=r7 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r3 += d0_; r2 += d1_; } // t440 mm8 a=r3 b=r5 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r1 += d0_; r4 += d1_; } // t441 mm8 a=r5 b=r1 c=r1 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r7 += d0_; r5 += d1_; } // t442 mm8 a=r1 b=r2 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r5 += d0_; r2 += d1_; } // t443 mm8 a=r1 b=r7 c=r5 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r1 += d0_; r0 += d1_; } // t444 mm8 a=r3 b=r7 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r5, d0_, d1_); r7 += d0_; r0 += d1_; } // t445 mm8 a=r7 b=r5 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r2 += d0_; r1 += d1_; } // t446 mm8 a=r3 b=r1 c=r2 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r4 += d0_; r7 += d1_; } // t447 mm8 a=r6 b=r7 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r4 += d0_; r5 += d1_; } // t448 mm8 a=r5 b=r2 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r1 += d0_; r3 += d1_; } // t449 mm8 a=r7 b=r1 c=r1 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r5, d0_, d1_); r7 += d0_; r3 += d1_; } // t450 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r1 += d0_; r7 += d1_; } // t451 mm8 a=r0 b=r3 c=r1 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r7 += d0_; r1 += d1_; } // t452 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t453 mm8 a=r5 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r7 += d0_; r1 += d1_; } // t454 mm8 a=r7 b=r7 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r7 += d0_; r5 += d1_; } // t455 mm8 a=r7 b=r1 c=r7 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r5 += d0_; r6 += d1_; } // t456 mm8 a=r6 b=r5 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r1 += d0_; r5 += d1_; } // t457 mm8 a=r7 b=r7 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r1, d0_, d1_); r4 += d0_; r1 += d1_; } // t458 mm8 a=r5 b=r1 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r7, d0_, d1_); r1 += d0_; r0 += d1_; } // t459 mm8 a=r6 b=r7 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r7, d0_, d1_); r6 += d0_; r5 += d1_; } // t460 mm8 a=r7 b=r7 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r6 += d0_; r2 += d1_; } // t461 mm8 a=r0 b=r6 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r1 += d0_; r2 += d1_; } // t462 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r3 += d0_; r2 += d1_; } // t463 mm8 a=r2 b=r0 c=r3 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r3, d0_, d1_); r0 += d0_; r1 += d1_; } // t464 mm8 a=r0 b=r3 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r0 += d0_; r5 += d1_; } // t465 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r4 += d0_; r1 += d1_; } // t466 mm8 a=r1 b=r2 c=r4 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r0, d0_, d1_); r1 += d0_; r6 += d1_; } // t467 mm8 a=r1 b=r0 c=r1 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r1, d0_, d1_); r6 += d0_; r2 += d1_; } // t468 mm8 a=r4 b=r1 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r0 += d0_; r1 += d1_; } // t469 mm8 a=r2 b=r0 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r2 += d0_; r0 += d1_; } // t470 mm8 a=r3 b=r1 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r7 += d0_; r1 += d1_; } // t471 mm8 a=r2 b=r2 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r7, d0_, d1_); r6 += d0_; r5 += d1_; } // t472 mm8 a=r1 b=r7 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r7, d0_, d1_); r6 += d0_; r1 += d1_; } // t473 mm8 a=r2 b=r7 c=r6 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r3, d0_, d1_); r6 += d0_; r3 += d1_; } // t474 mm8 a=r5 b=r3 c=r6 c2=r3
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r6 += d0_; r0 += d1_; } // t475 mm8 a=r7 b=r6 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r0, d0_, d1_); r5 += d0_; r6 += d1_; } // t476 mm8 a=r3 b=r0 c=r5 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r4 += d0_; r6 += d1_; } // t477 mm8 a=r3 b=r1 c=r4 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r2 += d0_; r5 += d1_; } // t478 mm8 a=r0 b=r6 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r7 += d0_; r1 += d1_; } // t479 mm8 a=r7 b=r6 c=r7 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r0, d0_, d1_); r1 += d0_; r0 += d1_; } // t480 mm8 a=r6 b=r0 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r6 += d0_; r7 += d1_; } // t481 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r3, d0_, d1_); r0 += d0_; r6 += d1_; } // t482 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r0, d0_, d1_); r7 += d0_; r6 += d1_; } // t483 mm8 a=r7 b=r0 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r7, d0_, d1_); r6 += d0_; r4 += d1_; } // t484 mm8 a=r3 b=r7 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r4, d0_, d1_); r1 += d0_; r2 += d1_; } // t485 mm8 a=r6 b=r4 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r5, d0_, d1_); r2 += d0_; r5 += d1_; } // t486 mm8 a=r6 b=r5 c=r2 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r5, d0_, d1_); r4 += d0_; r5 += d1_; } // t487 mm8 a=r2 b=r5 c=r4 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r2, d0_, d1_); r1 += d0_; r2 += d1_; } // t488 mm8 a=r1 b=r2 c=r1 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r2, d0_, d1_); r6 += d0_; r4 += d1_; } // t489 mm8 a=r5 b=r2 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r1, d0_, d1_); r2 += d0_; r6 += d1_; } // t490 mm8 a=r7 b=r1 c=r2 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r0, d0_, d1_); r0 += d0_; r6 += d1_; } // t491 mm8 a=r0 b=r0 c=r0 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r4 += d1_; } // t492 mm8 a=r3 b=r1 c=r6 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r6, r1, d0_, d1_); r7 += d0_; r6 += d1_; } // t493 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r3 += d0_; r1 += d1_; } // t494 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r2, d0_, d1_); r7 += d0_; r2 += d1_; } // t495 mm8 a=r2 b=r2 c=r7 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r5, d0_, d1_); r5 += d0_; r0 += d1_; } // t496 mm8 a=r3 b=r5 c=r5 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r2, d0_, d1_); r2 += d0_; r0 += d1_; } // t497 mm8 a=r3 b=r2 c=r2 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r3, r1, d0_, d1_); r6 += d0_; r2 += d1_; } // t498 mm8 a=r3 b=r1 c=r6 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r1, r6, d0_, d1_); r1 += d0_; r5 += d1_; } // t499 mm8 a=r1 b=r6 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r6, d0_, d1_); r1 += d0_; r5 += d1_; } // t500 mm8 a=r7 b=r6 c=r1 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r1 += d0_; r0 += d1_; } // t501 mm8 a=r4 b=r4 c=r1 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r7, d0_, d1_); r7 += d0_; r6 += d1_; } // t502 mm8 a=r5 b=r7 c=r7 c2=r6
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r5, d0_, d1_); r3 += d0_; r4 += d1_; } // t503 mm8 a=r7 b=r5 c=r3 c2=r4
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r0, d0_, d1_); r4 += d0_; r2 += d1_; } // t504 mm8 a=r2 b=r0 c=r4 c2=r2
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r0, d0_, d1_); r0 += d0_; r1 += d1_; } // t505 mm8 a=r4 b=r0 c=r0 c2=r1
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r2, d0_, d1_); r7 += d0_; r0 += d1_; } // t506 mm8 a=r0 b=r2 c=r7 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r5, r6, d0_, d1_); r4 += d0_; r7 += d1_; } // t507 mm8 a=r5 b=r6 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r7, r3, d0_, d1_); r4 += d0_; r7 += d1_; } // t508 mm8 a=r7 b=r3 c=r4 c2=r7
{ uint d0_, d1_; IGNEUM_MM8_REF(r4, r4, d0_, d1_); r6 += d0_; r0 += d1_; } // t509 mm8 a=r4 b=r4 c=r6 c2=r0
{ uint d0_, d1_; IGNEUM_MM8_REF(r0, r6, d0_, d1_); r6 += d0_; r5 += d1_; } // t510 mm8 a=r0 b=r6 c=r6 c2=r5
{ uint d0_, d1_; IGNEUM_MM8_REF(r2, r4, d0_, d1_); r1 += d0_; r3 += d1_; } // t511 mm8 a=r2 b=r4 c=r1 c2=r3
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Bit-exact twin of the Metal kernel for the same seed (see proto-cuda/CHECKLIST.md and program.metal).
// Compiled ahead of time by nvcc together with proto-cuda/host.cu. No NVRTC.
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
#include "memhard.h"
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site, so both shift amounts are in 1..31.
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
// n is masked to 0..31; the second shift amount is masked too, so n == 0 gives x.
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__device__ __forceinline__ uint32_t ds_elem(uint32_t i, uint32_t d0, uint32_t d1) {
uint32_t x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset (MEMHARD.md). One thread per cache segment; one thread per 64-byte dataset item.
// The core functions (mh_cache_segment, mh_item) are in memhard.h and are also compiled for the host.
__global__ void igneum_cache_fill(uint32_t* cache, uint32_t nSegments) {
uint32_t seg = blockIdx.x * blockDim.x + threadIdx.x;
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
uint32_t t = blockIdx.x * blockDim.x + threadIdx.x;
if (t < nItems) {
uint32_t s[16];
mh_item(cache, t, s);
uint32_t* d = ds + (size_t)t * 16u;
for (uint32_t i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per thread. blockDim.x is a multiple of 32; lane = threadIdx.x & 31 and every
// __shfl_xor_sync stays inside the lane's own warp, exactly like simd_shuffle_xor inside a
// 32-wide Metal SIMD group. Control flow is uniform, so the full 0xffffffff member mask is valid.
__global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint32_t x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint32_t x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint32_t x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint32_t x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint32_t x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint32_t x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint32_t x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 512 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t128 mm8 a=r6 b=r7 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t129 mm8 a=r3 b=r2 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t130 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t131 mm8 a=r3 b=r5 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t132 mm8 a=r0 b=r7 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t133 mm8 a=r2 b=r6 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t134 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t135 mm8 a=r0 b=r2 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t136 mm8 a=r3 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t137 mm8 a=r7 b=r0 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t138 mm8 a=r2 b=r2 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t139 mm8 a=r0 b=r4 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t140 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t141 mm8 a=r5 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t142 mm8 a=r2 b=r2 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t143 mm8 a=r4 b=r3 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t144 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t145 mm8 a=r7 b=r2 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t146 mm8 a=r2 b=r7 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t147 mm8 a=r3 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t148 mm8 a=r2 b=r1 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t149 mm8 a=r4 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t150 mm8 a=r3 b=r6 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t151 mm8 a=r1 b=r4 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t152 mm8 a=r3 b=r1 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t153 mm8 a=r0 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t154 mm8 a=r7 b=r3 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t155 mm8 a=r1 b=r3 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t156 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t157 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t158 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t159 mm8 a=r1 b=r0 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t160 mm8 a=r0 b=r1 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t161 mm8 a=r4 b=r0 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t162 mm8 a=r6 b=r6 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t163 mm8 a=r5 b=r3 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t164 mm8 a=r0 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t165 mm8 a=r6 b=r5 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t166 mm8 a=r6 b=r5 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t167 mm8 a=r4 b=r5 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t168 mm8 a=r3 b=r6 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t169 mm8 a=r6 b=r2 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t170 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t171 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t172 mm8 a=r7 b=r3 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t173 mm8 a=r0 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t174 mm8 a=r6 b=r6 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t175 mm8 a=r1 b=r6 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t176 mm8 a=r2 b=r4 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t177 mm8 a=r1 b=r7 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t178 mm8 a=r4 b=r2 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t179 mm8 a=r5 b=r2 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t180 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t181 mm8 a=r3 b=r5 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t182 mm8 a=r1 b=r1 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t183 mm8 a=r3 b=r1 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t184 mm8 a=r7 b=r4 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t185 mm8 a=r5 b=r0 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t186 mm8 a=r2 b=r5 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t187 mm8 a=r3 b=r0 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t188 mm8 a=r1 b=r4 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t189 mm8 a=r7 b=r2 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t190 mm8 a=r1 b=r5 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t191 mm8 a=r2 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t192 mm8 a=r5 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t193 mm8 a=r2 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t194 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t195 mm8 a=r2 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t196 mm8 a=r5 b=r6 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t197 mm8 a=r5 b=r3 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t198 mm8 a=r1 b=r0 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t199 mm8 a=r2 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t200 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t201 mm8 a=r7 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t202 mm8 a=r2 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t203 mm8 a=r0 b=r5 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t204 mm8 a=r4 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t205 mm8 a=r3 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t206 mm8 a=r0 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t207 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t208 mm8 a=r0 b=r1 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t209 mm8 a=r4 b=r4 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t210 mm8 a=r7 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t211 mm8 a=r1 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t212 mm8 a=r2 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t213 mm8 a=r2 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t214 mm8 a=r4 b=r6 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t215 mm8 a=r7 b=r3 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t216 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t217 mm8 a=r5 b=r7 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t218 mm8 a=r7 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t219 mm8 a=r2 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t220 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t221 mm8 a=r7 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t222 mm8 a=r0 b=r6 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t223 mm8 a=r2 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t224 mm8 a=r1 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t225 mm8 a=r2 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t226 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t227 mm8 a=r3 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t228 mm8 a=r7 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t229 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t230 mm8 a=r0 b=r3 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t231 mm8 a=r1 b=r3 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t232 mm8 a=r5 b=r4 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t233 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t234 mm8 a=r2 b=r0 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t235 mm8 a=r3 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t236 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t237 mm8 a=r3 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t238 mm8 a=r2 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t239 mm8 a=r5 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t240 mm8 a=r2 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t241 mm8 a=r0 b=r1 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t242 mm8 a=r0 b=r2 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t243 mm8 a=r4 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t244 mm8 a=r7 b=r6 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t245 mm8 a=r4 b=r4 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t246 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t247 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t248 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t249 mm8 a=r4 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t250 mm8 a=r0 b=r6 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t251 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t252 mm8 a=r0 b=r2 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t253 mm8 a=r5 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t254 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t255 mm8 a=r5 b=r0 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t256 mm8 a=r2 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t257 mm8 a=r4 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t258 mm8 a=r4 b=r1 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t259 mm8 a=r5 b=r5 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t260 mm8 a=r3 b=r2 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t261 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t262 mm8 a=r6 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t263 mm8 a=r6 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t264 mm8 a=r7 b=r2 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t265 mm8 a=r6 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t266 mm8 a=r0 b=r0 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t267 mm8 a=r6 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t268 mm8 a=r1 b=r0 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t269 mm8 a=r7 b=r7 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t270 mm8 a=r6 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t271 mm8 a=r0 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t272 mm8 a=r6 b=r0 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t273 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t274 mm8 a=r1 b=r0 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t275 mm8 a=r1 b=r3 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t276 mm8 a=r1 b=r5 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t277 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t278 mm8 a=r0 b=r0 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t279 mm8 a=r2 b=r4 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t280 mm8 a=r7 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t281 mm8 a=r1 b=r0 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t282 mm8 a=r0 b=r1 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t283 mm8 a=r0 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t284 mm8 a=r1 b=r5 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t285 mm8 a=r4 b=r7 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t286 mm8 a=r1 b=r0 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t287 mm8 a=r7 b=r1 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t288 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t289 mm8 a=r0 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t290 mm8 a=r3 b=r2 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t291 mm8 a=r7 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t292 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t293 mm8 a=r5 b=r5 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t294 mm8 a=r5 b=r7 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t295 mm8 a=r0 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t296 mm8 a=r6 b=r1 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t297 mm8 a=r4 b=r5 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t298 mm8 a=r6 b=r0 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t299 mm8 a=r6 b=r0 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t300 mm8 a=r6 b=r4 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t301 mm8 a=r6 b=r4 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t302 mm8 a=r7 b=r6 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t303 mm8 a=r3 b=r2 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t304 mm8 a=r6 b=r5 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t305 mm8 a=r4 b=r5 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t306 mm8 a=r3 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t307 mm8 a=r4 b=r3 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t308 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t309 mm8 a=r2 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t310 mm8 a=r6 b=r1 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t311 mm8 a=r4 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t312 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t313 mm8 a=r2 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t314 mm8 a=r0 b=r3 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t315 mm8 a=r7 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t316 mm8 a=r2 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t317 mm8 a=r1 b=r6 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t318 mm8 a=r2 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t319 mm8 a=r0 b=r2 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t320 mm8 a=r5 b=r2 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t321 mm8 a=r7 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t322 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t323 mm8 a=r4 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t324 mm8 a=r5 b=r7 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t325 mm8 a=r6 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t326 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t327 mm8 a=r1 b=r5 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t328 mm8 a=r0 b=r1 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t329 mm8 a=r0 b=r3 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t330 mm8 a=r6 b=r7 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t331 mm8 a=r4 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t332 mm8 a=r4 b=r4 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t333 mm8 a=r4 b=r6 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t334 mm8 a=r2 b=r2 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t335 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t336 mm8 a=r4 b=r0 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t337 mm8 a=r1 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t338 mm8 a=r3 b=r7 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t339 mm8 a=r5 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t340 mm8 a=r5 b=r0 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t341 mm8 a=r6 b=r6 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t342 mm8 a=r4 b=r7 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t343 mm8 a=r0 b=r4 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t344 mm8 a=r2 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t345 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t346 mm8 a=r6 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t347 mm8 a=r5 b=r3 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t348 mm8 a=r0 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t349 mm8 a=r6 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t350 mm8 a=r1 b=r5 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t351 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t352 mm8 a=r4 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t353 mm8 a=r7 b=r3 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t354 mm8 a=r4 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t355 mm8 a=r4 b=r5 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t356 mm8 a=r7 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t357 mm8 a=r7 b=r3 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t358 mm8 a=r4 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t359 mm8 a=r2 b=r7 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t360 mm8 a=r4 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t361 mm8 a=r2 b=r2 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t362 mm8 a=r2 b=r7 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t363 mm8 a=r7 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t364 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t365 mm8 a=r6 b=r6 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t366 mm8 a=r7 b=r7 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t367 mm8 a=r4 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t368 mm8 a=r7 b=r0 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t369 mm8 a=r1 b=r0 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t370 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t371 mm8 a=r5 b=r4 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t372 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t373 mm8 a=r4 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t374 mm8 a=r1 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t375 mm8 a=r6 b=r5 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t376 mm8 a=r3 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t377 mm8 a=r6 b=r4 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t378 mm8 a=r6 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t379 mm8 a=r3 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t380 mm8 a=r2 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t381 mm8 a=r3 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t382 mm8 a=r5 b=r2 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t383 mm8 a=r1 b=r2 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t384 mm8 a=r3 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t385 mm8 a=r6 b=r0 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t386 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t387 mm8 a=r3 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t388 mm8 a=r3 b=r0 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t389 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t390 mm8 a=r5 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t391 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t392 mm8 a=r2 b=r3 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t393 mm8 a=r3 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t394 mm8 a=r0 b=r7 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t395 mm8 a=r0 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t396 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t397 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t398 mm8 a=r6 b=r5 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t399 mm8 a=r6 b=r3 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t400 mm8 a=r2 b=r7 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t401 mm8 a=r7 b=r6 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t402 mm8 a=r0 b=r0 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t403 mm8 a=r7 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t404 mm8 a=r1 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t405 mm8 a=r6 b=r6 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t406 mm8 a=r6 b=r1 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t407 mm8 a=r5 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t408 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t409 mm8 a=r3 b=r4 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t410 mm8 a=r0 b=r5 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t411 mm8 a=r2 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t412 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t413 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t414 mm8 a=r7 b=r1 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t415 mm8 a=r4 b=r7 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t416 mm8 a=r5 b=r4 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t417 mm8 a=r6 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t418 mm8 a=r1 b=r3 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t419 mm8 a=r5 b=r0 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t420 mm8 a=r4 b=r2 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t421 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t422 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t423 mm8 a=r1 b=r7 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t424 mm8 a=r5 b=r1 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t425 mm8 a=r2 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t426 mm8 a=r1 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t427 mm8 a=r6 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t428 mm8 a=r6 b=r2 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t429 mm8 a=r3 b=r3 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t430 mm8 a=r7 b=r7 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t431 mm8 a=r6 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t432 mm8 a=r3 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t433 mm8 a=r3 b=r0 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t434 mm8 a=r0 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t435 mm8 a=r7 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t436 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t437 mm8 a=r0 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t438 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t439 mm8 a=r4 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t440 mm8 a=r3 b=r5 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t441 mm8 a=r5 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t442 mm8 a=r1 b=r2 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t443 mm8 a=r1 b=r7 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t444 mm8 a=r3 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t445 mm8 a=r7 b=r5 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t446 mm8 a=r3 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t447 mm8 a=r6 b=r7 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t448 mm8 a=r5 b=r2 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t449 mm8 a=r7 b=r1 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t450 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t451 mm8 a=r0 b=r3 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t452 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t453 mm8 a=r5 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t454 mm8 a=r7 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t455 mm8 a=r7 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t456 mm8 a=r6 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t457 mm8 a=r7 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t458 mm8 a=r5 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t459 mm8 a=r6 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t460 mm8 a=r7 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t461 mm8 a=r0 b=r6 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t462 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t463 mm8 a=r2 b=r0 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t464 mm8 a=r0 b=r3 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t465 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t466 mm8 a=r1 b=r2 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t467 mm8 a=r1 b=r0 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t468 mm8 a=r4 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t469 mm8 a=r2 b=r0 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t470 mm8 a=r3 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t471 mm8 a=r2 b=r2 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t472 mm8 a=r1 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t473 mm8 a=r2 b=r7 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t474 mm8 a=r5 b=r3 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t475 mm8 a=r7 b=r6 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t476 mm8 a=r3 b=r0 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t477 mm8 a=r3 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t478 mm8 a=r0 b=r6 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t479 mm8 a=r7 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t480 mm8 a=r6 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t481 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t482 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t483 mm8 a=r7 b=r0 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t484 mm8 a=r3 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t485 mm8 a=r6 b=r4 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t486 mm8 a=r6 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t487 mm8 a=r2 b=r5 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t488 mm8 a=r1 b=r2 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t489 mm8 a=r5 b=r2 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t490 mm8 a=r7 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t491 mm8 a=r0 b=r0 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t492 mm8 a=r3 b=r1 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t493 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t494 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t495 mm8 a=r2 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t496 mm8 a=r3 b=r5 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t497 mm8 a=r3 b=r2 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t498 mm8 a=r3 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t499 mm8 a=r1 b=r6 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t500 mm8 a=r7 b=r6 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t501 mm8 a=r4 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t502 mm8 a=r5 b=r7 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t503 mm8 a=r7 b=r5 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t504 mm8 a=r2 b=r0 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t505 mm8 a=r4 b=r0 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t506 mm8 a=r0 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t507 mm8 a=r5 b=r6 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t508 mm8 a=r7 b=r3 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t509 mm8 a=r4 b=r4 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t510 mm8 a=r0 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t511 mm8 a=r2 b=r4 c=r1 c2=r3
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
// Host-side launch wrappers. Declared in program.h, called from host.cu.
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments) {
if (nSegments == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nSegments + block - 1u) / block;
igneum_cache_fill<<<grid, block>>>(cache, nSegments);
return cudaGetLastError();
}
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
if (nItems == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nItems + block - 1u) / block;
igneum_build<<<grid, block>>>(ds, cache, nItems);
return cudaGetLastError();
}
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash<<<nonces / block, block>>>(ds, out, baseNonce, mask);
return cudaGetLastError();
}
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
// Host declarations (also in program_bound.h if present):
// struct IgneumInitWords { uint32_t w[8]; };
// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
struct IgneumInitWords { uint32_t w[8]; };
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// int8 tile block (Counter ASIC 4.0 research, experimental): 512 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t128 mm8 a=r6 b=r7 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t129 mm8 a=r3 b=r2 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t130 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t131 mm8 a=r3 b=r5 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t132 mm8 a=r0 b=r7 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t133 mm8 a=r2 b=r6 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t134 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t135 mm8 a=r0 b=r2 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t136 mm8 a=r3 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t137 mm8 a=r7 b=r0 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t138 mm8 a=r2 b=r2 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t139 mm8 a=r0 b=r4 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t140 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t141 mm8 a=r5 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t142 mm8 a=r2 b=r2 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t143 mm8 a=r4 b=r3 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t144 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t145 mm8 a=r7 b=r2 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t146 mm8 a=r2 b=r7 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t147 mm8 a=r3 b=r1 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t148 mm8 a=r2 b=r1 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t149 mm8 a=r4 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t150 mm8 a=r3 b=r6 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t151 mm8 a=r1 b=r4 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t152 mm8 a=r3 b=r1 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t153 mm8 a=r0 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t154 mm8 a=r7 b=r3 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t155 mm8 a=r1 b=r3 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t156 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t157 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t158 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t159 mm8 a=r1 b=r0 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t160 mm8 a=r0 b=r1 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t161 mm8 a=r4 b=r0 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t162 mm8 a=r6 b=r6 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t163 mm8 a=r5 b=r3 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t164 mm8 a=r0 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t165 mm8 a=r6 b=r5 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t166 mm8 a=r6 b=r5 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t167 mm8 a=r4 b=r5 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t168 mm8 a=r3 b=r6 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t169 mm8 a=r6 b=r2 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t170 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t171 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t172 mm8 a=r7 b=r3 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t173 mm8 a=r0 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t174 mm8 a=r6 b=r6 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t175 mm8 a=r1 b=r6 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t176 mm8 a=r2 b=r4 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t177 mm8 a=r1 b=r7 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t178 mm8 a=r4 b=r2 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t179 mm8 a=r5 b=r2 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t180 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t181 mm8 a=r3 b=r5 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t182 mm8 a=r1 b=r1 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t183 mm8 a=r3 b=r1 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t184 mm8 a=r7 b=r4 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t185 mm8 a=r5 b=r0 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t186 mm8 a=r2 b=r5 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t187 mm8 a=r3 b=r0 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t188 mm8 a=r1 b=r4 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t189 mm8 a=r7 b=r2 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t190 mm8 a=r1 b=r5 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t191 mm8 a=r2 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t192 mm8 a=r5 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t193 mm8 a=r2 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t194 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t195 mm8 a=r2 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t196 mm8 a=r5 b=r6 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t197 mm8 a=r5 b=r3 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t198 mm8 a=r1 b=r0 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t199 mm8 a=r2 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t200 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t201 mm8 a=r7 b=r2 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t202 mm8 a=r2 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t203 mm8 a=r0 b=r5 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t204 mm8 a=r4 b=r7 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t205 mm8 a=r3 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t206 mm8 a=r0 b=r6 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t207 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t208 mm8 a=r0 b=r1 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t209 mm8 a=r4 b=r4 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t210 mm8 a=r7 b=r1 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t211 mm8 a=r1 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t212 mm8 a=r2 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t213 mm8 a=r2 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t214 mm8 a=r4 b=r6 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t215 mm8 a=r7 b=r3 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t216 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t217 mm8 a=r5 b=r7 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t218 mm8 a=r7 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t219 mm8 a=r2 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t220 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t221 mm8 a=r7 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t222 mm8 a=r0 b=r6 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t223 mm8 a=r2 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t224 mm8 a=r1 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t225 mm8 a=r2 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t226 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t227 mm8 a=r3 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t228 mm8 a=r7 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t229 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t230 mm8 a=r0 b=r3 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t231 mm8 a=r1 b=r3 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t232 mm8 a=r5 b=r4 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t233 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t234 mm8 a=r2 b=r0 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t235 mm8 a=r3 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t236 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t237 mm8 a=r3 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t238 mm8 a=r2 b=r0 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t239 mm8 a=r5 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t240 mm8 a=r2 b=r7 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t241 mm8 a=r0 b=r1 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t242 mm8 a=r0 b=r2 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t243 mm8 a=r4 b=r4 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r7 += d1_; } // t244 mm8 a=r7 b=r6 c=r0 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t245 mm8 a=r4 b=r4 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t246 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t247 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t248 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t249 mm8 a=r4 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t250 mm8 a=r0 b=r6 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t251 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t252 mm8 a=r0 b=r2 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t253 mm8 a=r5 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t254 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t255 mm8 a=r5 b=r0 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t256 mm8 a=r2 b=r1 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t257 mm8 a=r4 b=r3 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t258 mm8 a=r4 b=r1 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t259 mm8 a=r5 b=r5 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t260 mm8 a=r3 b=r2 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t261 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t262 mm8 a=r6 b=r4 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t263 mm8 a=r6 b=r4 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t264 mm8 a=r7 b=r2 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t265 mm8 a=r6 b=r1 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t266 mm8 a=r0 b=r0 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t267 mm8 a=r6 b=r3 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t268 mm8 a=r1 b=r0 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t269 mm8 a=r7 b=r7 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t270 mm8 a=r6 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t271 mm8 a=r0 b=r3 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t272 mm8 a=r6 b=r0 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t273 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t274 mm8 a=r1 b=r0 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t275 mm8 a=r1 b=r3 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t276 mm8 a=r1 b=r5 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t277 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t278 mm8 a=r0 b=r0 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t279 mm8 a=r2 b=r4 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t280 mm8 a=r7 b=r2 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t281 mm8 a=r1 b=r0 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t282 mm8 a=r0 b=r1 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t283 mm8 a=r0 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t284 mm8 a=r1 b=r5 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t285 mm8 a=r4 b=r7 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t286 mm8 a=r1 b=r0 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t287 mm8 a=r7 b=r1 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t288 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t289 mm8 a=r0 b=r5 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t290 mm8 a=r3 b=r2 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t291 mm8 a=r7 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t292 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t293 mm8 a=r5 b=r5 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t294 mm8 a=r5 b=r7 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t295 mm8 a=r0 b=r7 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t296 mm8 a=r6 b=r1 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t297 mm8 a=r4 b=r5 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t298 mm8 a=r6 b=r0 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t299 mm8 a=r6 b=r0 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t300 mm8 a=r6 b=r4 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t301 mm8 a=r6 b=r4 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t302 mm8 a=r7 b=r6 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t303 mm8 a=r3 b=r2 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t304 mm8 a=r6 b=r5 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t305 mm8 a=r4 b=r5 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t306 mm8 a=r3 b=r1 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t307 mm8 a=r4 b=r3 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t308 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t309 mm8 a=r2 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t310 mm8 a=r6 b=r1 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t311 mm8 a=r4 b=r6 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t312 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t313 mm8 a=r2 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t314 mm8 a=r0 b=r3 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t315 mm8 a=r7 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t316 mm8 a=r2 b=r4 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t317 mm8 a=r1 b=r6 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t318 mm8 a=r2 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t319 mm8 a=r0 b=r2 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t320 mm8 a=r5 b=r2 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t321 mm8 a=r7 b=r4 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t322 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t323 mm8 a=r4 b=r3 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t324 mm8 a=r5 b=r7 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t325 mm8 a=r6 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t326 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t327 mm8 a=r1 b=r5 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t328 mm8 a=r0 b=r1 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t329 mm8 a=r0 b=r3 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r0 += d1_; } // t330 mm8 a=r6 b=r7 c=r4 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t331 mm8 a=r4 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t332 mm8 a=r4 b=r4 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t333 mm8 a=r4 b=r6 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t334 mm8 a=r2 b=r2 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t335 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r3 += d1_; } // t336 mm8 a=r4 b=r0 c=r2 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t337 mm8 a=r1 b=r4 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r7 += d1_; } // t338 mm8 a=r3 b=r7 c=r2 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t339 mm8 a=r5 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t340 mm8 a=r5 b=r0 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t341 mm8 a=r6 b=r6 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t342 mm8 a=r4 b=r7 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t343 mm8 a=r0 b=r4 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t344 mm8 a=r2 b=r5 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t345 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t346 mm8 a=r6 b=r0 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t347 mm8 a=r5 b=r3 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t348 mm8 a=r0 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t349 mm8 a=r6 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t350 mm8 a=r1 b=r5 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t351 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t352 mm8 a=r4 b=r1 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t353 mm8 a=r7 b=r3 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t354 mm8 a=r4 b=r1 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t355 mm8 a=r4 b=r5 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t356 mm8 a=r7 b=r6 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t357 mm8 a=r7 b=r3 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r7 += d1_; } // t358 mm8 a=r4 b=r7 c=r5 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t359 mm8 a=r2 b=r7 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t360 mm8 a=r4 b=r4 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t361 mm8 a=r2 b=r2 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t362 mm8 a=r2 b=r7 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t363 mm8 a=r7 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t364 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r4 += d1_; } // t365 mm8 a=r6 b=r6 c=r5 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t366 mm8 a=r7 b=r7 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t367 mm8 a=r4 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t368 mm8 a=r7 b=r0 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t369 mm8 a=r1 b=r0 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t370 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t371 mm8 a=r5 b=r4 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t372 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t373 mm8 a=r4 b=r6 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r5), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t374 mm8 a=r1 b=r5 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t375 mm8 a=r6 b=r5 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t376 mm8 a=r3 b=r6 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t377 mm8 a=r6 b=r4 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t378 mm8 a=r6 b=r3 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t379 mm8 a=r3 b=r0 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t380 mm8 a=r2 b=r0 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t381 mm8 a=r3 b=r5 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t382 mm8 a=r5 b=r2 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r0 += d0_; r2 += d1_; } // t383 mm8 a=r1 b=r2 c=r0 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t384 mm8 a=r3 b=r1 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t385 mm8 a=r6 b=r0 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t386 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t387 mm8 a=r3 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t388 mm8 a=r3 b=r0 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t389 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t390 mm8 a=r5 b=r4 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t391 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r0 += d1_; } // t392 mm8 a=r2 b=r3 c=r3 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t393 mm8 a=r3 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t394 mm8 a=r0 b=r7 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t395 mm8 a=r0 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t396 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t397 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t398 mm8 a=r6 b=r5 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r3), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t399 mm8 a=r6 b=r3 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r4 += d1_; } // t400 mm8 a=r2 b=r7 c=r0 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t401 mm8 a=r7 b=r6 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t402 mm8 a=r0 b=r0 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t403 mm8 a=r7 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t404 mm8 a=r1 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r6 += d1_; } // t405 mm8 a=r6 b=r6 c=r3 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t406 mm8 a=r6 b=r1 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r2 += d0_; r4 += d1_; } // t407 mm8 a=r5 b=r7 c=r2 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t408 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r4), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t409 mm8 a=r3 b=r4 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t410 mm8 a=r0 b=r5 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t411 mm8 a=r2 b=r0 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t412 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t413 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r0 += d0_; r3 += d1_; } // t414 mm8 a=r7 b=r1 c=r0 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r1 += d1_; } // t415 mm8 a=r4 b=r7 c=r5 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t416 mm8 a=r5 b=r4 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t417 mm8 a=r6 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t418 mm8 a=r1 b=r3 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t419 mm8 a=r5 b=r0 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t420 mm8 a=r4 b=r2 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r3 += d0_; r7 += d1_; } // t421 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r3 += d1_; } // t422 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t423 mm8 a=r1 b=r7 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t424 mm8 a=r5 b=r1 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t425 mm8 a=r2 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t426 mm8 a=r1 b=r6 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t427 mm8 a=r6 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r4 += d1_; } // t428 mm8 a=r6 b=r2 c=r7 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r3), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t429 mm8 a=r3 b=r3 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r5 += d1_; } // t430 mm8 a=r7 b=r7 c=r3 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t431 mm8 a=r6 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t432 mm8 a=r3 b=r2 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t433 mm8 a=r3 b=r0 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r3 += d1_; } // t434 mm8 a=r0 b=r7 c=r5 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t435 mm8 a=r7 b=r5 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t436 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t437 mm8 a=r0 b=r7 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t438 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r7), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t439 mm8 a=r4 b=r7 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t440 mm8 a=r3 b=r5 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r4 += d1_; } // t441 mm8 a=r5 b=r1 c=r1 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t442 mm8 a=r1 b=r2 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r5 += d0_; r2 += d1_; } // t443 mm8 a=r1 b=r7 c=r5 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t444 mm8 a=r3 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t445 mm8 a=r7 b=r5 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r1 += d1_; } // t446 mm8 a=r3 b=r1 c=r2 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t447 mm8 a=r6 b=r7 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t448 mm8 a=r5 b=r2 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t449 mm8 a=r7 b=r1 c=r1 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r7 += d0_; r3 += d1_; } // t450 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r1 += d0_; r7 += d1_; } // t451 mm8 a=r0 b=r3 c=r1 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t452 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t453 mm8 a=r5 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t454 mm8 a=r7 b=r7 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r5 += d1_; } // t455 mm8 a=r7 b=r1 c=r7 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t456 mm8 a=r6 b=r5 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t457 mm8 a=r7 b=r7 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t458 mm8 a=r5 b=r1 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r7), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t459 mm8 a=r6 b=r7 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t460 mm8 a=r7 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t461 mm8 a=r0 b=r6 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t462 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r3 += d0_; r2 += d1_; } // t463 mm8 a=r2 b=r0 c=r3 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t464 mm8 a=r0 b=r3 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r0 += d0_; r5 += d1_; } // t465 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r4 += d0_; r1 += d1_; } // t466 mm8 a=r1 b=r2 c=r4 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r6 += d1_; } // t467 mm8 a=r1 b=r0 c=r1 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t468 mm8 a=r4 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t469 mm8 a=r2 b=r0 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t470 mm8 a=r3 b=r1 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t471 mm8 a=r2 b=r2 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t472 mm8 a=r1 b=r7 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r1 += d1_; } // t473 mm8 a=r2 b=r7 c=r6 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r3), "r"(0u), "r"(0u)); r6 += d0_; r3 += d1_; } // t474 mm8 a=r5 b=r3 c=r6 c2=r3
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t475 mm8 a=r7 b=r6 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r0), "r"(0u), "r"(0u)); r5 += d0_; r6 += d1_; } // t476 mm8 a=r3 b=r0 c=r5 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r4 += d0_; r6 += d1_; } // t477 mm8 a=r3 b=r1 c=r4 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t478 mm8 a=r0 b=r6 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r7 += d0_; r1 += d1_; } // t479 mm8 a=r7 b=r6 c=r7 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r0), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t480 mm8 a=r6 b=r0 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r7 += d1_; } // t481 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r3), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t482 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r0), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t483 mm8 a=r7 b=r0 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r7), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t484 mm8 a=r3 b=r7 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t485 mm8 a=r6 b=r4 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r5), "r"(0u), "r"(0u)); r2 += d0_; r5 += d1_; } // t486 mm8 a=r6 b=r5 c=r2 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r5), "r"(0u), "r"(0u)); r4 += d0_; r5 += d1_; } // t487 mm8 a=r2 b=r5 c=r4 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r2), "r"(0u), "r"(0u)); r1 += d0_; r2 += d1_; } // t488 mm8 a=r1 b=r2 c=r1 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r2), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t489 mm8 a=r5 b=r2 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r1), "r"(0u), "r"(0u)); r2 += d0_; r6 += d1_; } // t490 mm8 a=r7 b=r1 c=r2 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r6 += d1_; } // t491 mm8 a=r0 b=r0 c=r0 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r4 += d1_; } // t492 mm8 a=r3 b=r1 c=r6 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r6), "r"(r1), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t493 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r3 += d0_; r1 += d1_; } // t494 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r2 += d1_; } // t495 mm8 a=r2 b=r2 c=r7 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r5), "r"(0u), "r"(0u)); r5 += d0_; r0 += d1_; } // t496 mm8 a=r3 b=r5 c=r5 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r2), "r"(0u), "r"(0u)); r2 += d0_; r0 += d1_; } // t497 mm8 a=r3 b=r2 c=r2 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r3), "r"(r1), "r"(0u), "r"(0u)); r6 += d0_; r2 += d1_; } // t498 mm8 a=r3 b=r1 c=r6 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r1), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t499 mm8 a=r1 b=r6 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r6), "r"(0u), "r"(0u)); r1 += d0_; r5 += d1_; } // t500 mm8 a=r7 b=r6 c=r1 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r0 += d1_; } // t501 mm8 a=r4 b=r4 c=r1 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r7), "r"(0u), "r"(0u)); r7 += d0_; r6 += d1_; } // t502 mm8 a=r5 b=r7 c=r7 c2=r6
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r5), "r"(0u), "r"(0u)); r3 += d0_; r4 += d1_; } // t503 mm8 a=r7 b=r5 c=r3 c2=r4
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r0), "r"(0u), "r"(0u)); r4 += d0_; r2 += d1_; } // t504 mm8 a=r2 b=r0 c=r4 c2=r2
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r0), "r"(0u), "r"(0u)); r0 += d0_; r1 += d1_; } // t505 mm8 a=r4 b=r0 c=r0 c2=r1
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r2), "r"(0u), "r"(0u)); r7 += d0_; r0 += d1_; } // t506 mm8 a=r0 b=r2 c=r7 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r5), "r"(r6), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t507 mm8 a=r5 b=r6 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r7), "r"(r3), "r"(0u), "r"(0u)); r4 += d0_; r7 += d1_; } // t508 mm8 a=r7 b=r3 c=r4 c2=r7
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r4), "r"(r4), "r"(0u), "r"(0u)); r6 += d0_; r0 += d1_; } // t509 mm8 a=r4 b=r4 c=r6 c2=r0
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r0), "r"(r6), "r"(0u), "r"(0u)); r6 += d0_; r5 += d1_; } // t510 mm8 a=r0 b=r6 c=r6 c2=r5
{ uint32_t d0_, d1_; asm volatile("mma.sync.aligned.m8n8k16.row.col.s32.u8.u8.s32 {%0,%1}, {%2}, {%3}, {%4,%5};" : "=r"(d0_), "=r"(d1_) : "r"(r2), "r"(r4), "r"(0u), "r"(0u)); r1 += d0_; r3 += d1_; } // t511 mm8 a=r2 b=r4 c=r1 c2=r3
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
return cudaGetLastError();
}
cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Memory-hard dataset core, the same text that the Mac's Metal kernels and CPU verifier were checked against.
// Included by kernel.cu (device), host.cu (host reference) and proto-opencl/host.c (C99 host reference).
// See proto-metal/MEMHARD.md for the construction. kernel.cl carries the same text in OpenCL C.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#if defined(__CUDACC__)
#define IGNEUM_HD __host__ __device__ __forceinline__
#elif defined(_MSC_VER) && !defined(__cplusplus)
#define IGNEUM_HD static __inline
#else
#define IGNEUM_HD static inline
#endif
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
IGNEUM_HD uint32_t mh_rotl(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
IGNEUM_HD void mh_chacha_block(const uint32_t* x, uint32_t* y) {
for (uint32_t i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint32_t r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint32_t i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
IGNEUM_HD void mh_cache_segment(uint32_t* cache, uint32_t seg) {
uint32_t prev[16]; uint32_t x[16]; uint32_t y[16];
for (uint32_t i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint32_t j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
uint32_t* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
IGNEUM_HD void mh_mixer(uint32_t* s, uint32_t rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint32_t r = 0u; r < 8u; ++r) {
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
const uint32_t* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }

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#include <metal_stdlib>
using namespace metal;
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
inline void mh_chacha_block(const thread uint* x, thread uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
inline void mh_cache_segment(device uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
device uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
inline void mh_mixer(thread uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
inline void mh_item(device const uint* cache, uint t, thread uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
device const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// One thread per segment (2^16 threads).
kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) {
mh_cache_segment(cache, gid);
}
// One thread per 64-byte item (dataset words / 16 threads).
kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* dataset [[buffer(1)]],
uint gid [[thread_position_in_grid]]) {
uint s[16];
mh_item(cache, gid, s);
device uint* d = dataset + gid * 16u;
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Program metadata for host.cu plus the launch wrappers defined in kernel.cu.
// Also included by proto-opencl/host.c (C99), which defines IGNEUM_NO_CUDA first and reads only the macros.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#ifndef IGNEUM_NO_CUDA
#include <cuda_runtime.h>
#endif
#define IGNEUM_SEED_STRING "igneum-genesis"
#define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973"
#define IGNEUM_GENERATOR 2
#define IGNEUM_PROGRAM_ATTEMPT 0
#define IGNEUM_PROGRAM_ID 0xd5492e93169cad0bull
#define IGNEUM_DAY_STRING "2026-10-03"
#define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033"
#define IGNEUM_DAY0 0x3067619fu
#define IGNEUM_DAY1 0x3c269176u
#define IGNEUM_DATASET_LOG2 28
#define IGNEUM_MASK 0x0fffffffu
#define IGNEUM_LANES 32
#define IGNEUM_ITERATIONS 8
#define IGNEUM_INSTR_COUNT 64
#define IGNEUM_LOADS_PER_HASH 128
#define IGNEUM_WIDE_LOADS_PER_HASH 0
#define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1"
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
#define IGNEUM_LOAD_CLASS "mx8+mm512"
#define IGNEUM_CLASS_MIXER_MULT 8
#define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460))
#define IGNEUM_LOAD_SLOTS 16
#define IGNEUM_LOAD_MIX { 100, 0, 0 }
#define IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 } // loads of 4, 16, 64 bytes per program
#define IGNEUM_BYTES_PER_HASH 512
#define IGNEUM_FOLD_ROT 11
#define IGNEUM_FOLD_MUL 0x9e3779b1u
// Latency-shadow block (Counter ASIC 3.0 item 8, docs/analysis/latency-shadow-2026-10-06.md): NOT the lottery hash. A block of
// IGNEUM_SHADOW_INSTRS ALU instructions (the ten non-load families) runs IGNEUM_SHADOW_REPS times at the end of every
// iteration; the 16 loads, the acceptance rule and the base program are the class's without the shadow.
#define IGNEUM_SHADOW_INSTRS 0
#define IGNEUM_SHADOW_REPS 0
#define IGNEUM_SHADOW_INSTRS_PER_HASH 0
#define IGNEUM_SHADOW_OP_MIX ""
// Counter ASIC 4.0 research (experimental): IGNEUM_MM8_TILES int8 mma.m8n8k16 u8 tiles per iteration after the shadow block.
#define IGNEUM_MM8_TILES 512
#define IGNEUM_MM8_TILES_PER_HASH 4096
// 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h)
#define IGNEUM_DATASET_MODE 1
#define IGNEUM_SEEDW_INIT { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u }
#define IGNEUM_KEY_INIT { 0x3067619fu, 0x3c269176u, 0x84a03b03u, 0xf8c63294u, 0xff977c5bu, 0xe60def3eu, 0x63630141u, 0xb8fbcb58u }
#define IGNEUM_CACHE_LOG2_WORDS 26
#define IGNEUM_CACHE_SEGMENT_LOG2_LINES 6
#define IGNEUM_CACHE_SEGMENTS 65536u
#define IGNEUM_ITEM_ROUNDS 8
#define IGNEUM_MIXER_MULT 8 // mixer applications per round and after the last read (class v3, docs/plans/mixer-x4.md)
#define IGNEUM_MIX_ROT_INIT { 20u, 20u, 19u, 4u, 26u, 3u, 3u, 27u }
#define IGNEUM_MIX_MUL_INIT { 0x42146205u, 0x52cbe0fbu, 0x7ecf4a03u, 0x6728907fu, 0xd81d9751u, 0x132952c3u, 0xf60de277u, 0x05358035u, 0xbaf6499du, 0xe4db9667u, 0x3e98f45du, 0xd0004eddu, 0x2691630du, 0x9beb3bcfu, 0xab310379u, 0x99cfb423u }
#define IGNEUM_MIX_RC_INIT { 0xbab68293u, 0xcc162340u, 0x6ce151ccu, 0xe62b8997u, 0xc9c80297u, 0xf74a1654u, 0x3d704af5u, 0x3cf522b7u, 0x2b9cac04u, 0xa880ac10u, 0x13e5dd1du, 0x6fc3e233u, 0x2d83eeacu, 0x9006e8bfu, 0x2c4b5362u, 0x31b49ee2u }
#ifndef IGNEUM_NO_CUDA
// Defined in kernel.cu. All launch on the default stream and return cudaGetLastError().
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments);
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems);
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps);
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#endif

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#include <metal_stdlib>
using namespace metal;
// int8 tile reference (Counter ASIC 4.0 research): A = the 32 lanes' av as 8 x 16 bytes (lane l holds row l >> 2, bytes 4 (l & 3)..),
// B = bv as 16 x 8 (lane l holds column l >> 2); lane l gets C[l >> 2][2 (l & 3)] and C[l >> 2][2 (l & 3) + 1]; the PTX mma.m8n8k16 u8 layout.
static inline void mm8_ref(uint av, uint bv, uint lane, thread uint& d0, thread uint& d1) {
uint row = lane >> 2, col0 = 2u * (lane & 3u);
uint acc0 = 0u, acc1 = 0u;
for (uint j = 0u; j < 4u; ++j) {
uint aw = simd_shuffle(av, (ushort)(4u * row + j));
uint bw0 = simd_shuffle(bv, (ushort)(4u * col0 + j));
uint bw1 = simd_shuffle(bv, (ushort)(4u * (col0 + 1u) + j));
for (uint t = 0u; t < 4u; ++t) {
uint ab = (aw >> (8u * t)) & 0xffu;
acc0 += ab * ((bw0 >> (8u * t)) & 0xffu);
acc1 += ab * ((bw1 >> (8u * t)) & 0xffu);
}
}
d0 = acc0; d1 = acc1;
}
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint lane = gid & 31u;
{ uint x = nonce ^ SEEDW[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ SEEDW[1]; }
{ uint x = nonce ^ SEEDW[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ SEEDW[2]; }
{ uint x = nonce ^ SEEDW[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ SEEDW[3]; }
{ uint x = nonce ^ SEEDW[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ SEEDW[4]; }
{ uint x = nonce ^ SEEDW[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ SEEDW[5]; }
{ uint x = nonce ^ SEEDW[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ SEEDW[6]; }
{ uint x = nonce ^ SEEDW[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ SEEDW[7]; }
{ uint x = nonce ^ SEEDW[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ SEEDW[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// int8 tile block (Counter ASIC 4.0 research, experimental): 512 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t128 mm8 a=r6 b=r7 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t129 mm8 a=r3 b=r2 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t130 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t131 mm8 a=r3 b=r5 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t132 mm8 a=r0 b=r7 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t133 mm8 a=r2 b=r6 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t134 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t135 mm8 a=r0 b=r2 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t136 mm8 a=r3 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t137 mm8 a=r7 b=r0 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t138 mm8 a=r2 b=r2 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t139 mm8 a=r0 b=r4 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t140 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t141 mm8 a=r5 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t142 mm8 a=r2 b=r2 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t143 mm8 a=r4 b=r3 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t144 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t145 mm8 a=r7 b=r2 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t146 mm8 a=r2 b=r7 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t147 mm8 a=r3 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t148 mm8 a=r2 b=r1 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t149 mm8 a=r4 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t150 mm8 a=r3 b=r6 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t151 mm8 a=r1 b=r4 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t152 mm8 a=r3 b=r1 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t153 mm8 a=r0 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t154 mm8 a=r7 b=r3 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t155 mm8 a=r1 b=r3 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t156 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t157 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t158 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t159 mm8 a=r1 b=r0 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t160 mm8 a=r0 b=r1 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t161 mm8 a=r4 b=r0 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t162 mm8 a=r6 b=r6 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t163 mm8 a=r5 b=r3 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t164 mm8 a=r0 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t165 mm8 a=r6 b=r5 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t166 mm8 a=r6 b=r5 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t167 mm8 a=r4 b=r5 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t168 mm8 a=r3 b=r6 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t169 mm8 a=r6 b=r2 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t170 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t171 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t172 mm8 a=r7 b=r3 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t173 mm8 a=r0 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t174 mm8 a=r6 b=r6 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t175 mm8 a=r1 b=r6 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t176 mm8 a=r2 b=r4 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t177 mm8 a=r1 b=r7 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t178 mm8 a=r4 b=r2 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t179 mm8 a=r5 b=r2 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t180 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t181 mm8 a=r3 b=r5 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t182 mm8 a=r1 b=r1 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t183 mm8 a=r3 b=r1 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t184 mm8 a=r7 b=r4 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t185 mm8 a=r5 b=r0 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t186 mm8 a=r2 b=r5 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t187 mm8 a=r3 b=r0 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t188 mm8 a=r1 b=r4 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t189 mm8 a=r7 b=r2 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t190 mm8 a=r1 b=r5 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t191 mm8 a=r2 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t192 mm8 a=r5 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t193 mm8 a=r2 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t194 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t195 mm8 a=r2 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t196 mm8 a=r5 b=r6 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t197 mm8 a=r5 b=r3 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t198 mm8 a=r1 b=r0 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t199 mm8 a=r2 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t200 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t201 mm8 a=r7 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t202 mm8 a=r2 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t203 mm8 a=r0 b=r5 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t204 mm8 a=r4 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t205 mm8 a=r3 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t206 mm8 a=r0 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t207 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t208 mm8 a=r0 b=r1 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t209 mm8 a=r4 b=r4 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t210 mm8 a=r7 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t211 mm8 a=r1 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t212 mm8 a=r2 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t213 mm8 a=r2 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t214 mm8 a=r4 b=r6 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t215 mm8 a=r7 b=r3 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t216 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t217 mm8 a=r5 b=r7 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t218 mm8 a=r7 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t219 mm8 a=r2 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t220 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t221 mm8 a=r7 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t222 mm8 a=r0 b=r6 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t223 mm8 a=r2 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t224 mm8 a=r1 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t225 mm8 a=r2 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t226 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t227 mm8 a=r3 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t228 mm8 a=r7 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t229 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t230 mm8 a=r0 b=r3 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t231 mm8 a=r1 b=r3 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t232 mm8 a=r5 b=r4 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t233 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t234 mm8 a=r2 b=r0 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t235 mm8 a=r3 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t236 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t237 mm8 a=r3 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t238 mm8 a=r2 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t239 mm8 a=r5 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t240 mm8 a=r2 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t241 mm8 a=r0 b=r1 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t242 mm8 a=r0 b=r2 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t243 mm8 a=r4 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t244 mm8 a=r7 b=r6 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t245 mm8 a=r4 b=r4 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t246 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t247 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t248 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t249 mm8 a=r4 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t250 mm8 a=r0 b=r6 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t251 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t252 mm8 a=r0 b=r2 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t253 mm8 a=r5 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t254 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t255 mm8 a=r5 b=r0 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t256 mm8 a=r2 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t257 mm8 a=r4 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t258 mm8 a=r4 b=r1 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t259 mm8 a=r5 b=r5 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t260 mm8 a=r3 b=r2 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t261 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t262 mm8 a=r6 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t263 mm8 a=r6 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t264 mm8 a=r7 b=r2 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t265 mm8 a=r6 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t266 mm8 a=r0 b=r0 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t267 mm8 a=r6 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t268 mm8 a=r1 b=r0 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t269 mm8 a=r7 b=r7 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t270 mm8 a=r6 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t271 mm8 a=r0 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t272 mm8 a=r6 b=r0 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t273 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t274 mm8 a=r1 b=r0 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t275 mm8 a=r1 b=r3 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t276 mm8 a=r1 b=r5 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t277 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t278 mm8 a=r0 b=r0 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t279 mm8 a=r2 b=r4 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t280 mm8 a=r7 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t281 mm8 a=r1 b=r0 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t282 mm8 a=r0 b=r1 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t283 mm8 a=r0 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t284 mm8 a=r1 b=r5 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t285 mm8 a=r4 b=r7 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t286 mm8 a=r1 b=r0 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t287 mm8 a=r7 b=r1 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t288 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t289 mm8 a=r0 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t290 mm8 a=r3 b=r2 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t291 mm8 a=r7 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t292 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t293 mm8 a=r5 b=r5 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t294 mm8 a=r5 b=r7 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t295 mm8 a=r0 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t296 mm8 a=r6 b=r1 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t297 mm8 a=r4 b=r5 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t298 mm8 a=r6 b=r0 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t299 mm8 a=r6 b=r0 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t300 mm8 a=r6 b=r4 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t301 mm8 a=r6 b=r4 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t302 mm8 a=r7 b=r6 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t303 mm8 a=r3 b=r2 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t304 mm8 a=r6 b=r5 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t305 mm8 a=r4 b=r5 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t306 mm8 a=r3 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t307 mm8 a=r4 b=r3 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t308 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t309 mm8 a=r2 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t310 mm8 a=r6 b=r1 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t311 mm8 a=r4 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t312 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t313 mm8 a=r2 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t314 mm8 a=r0 b=r3 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t315 mm8 a=r7 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t316 mm8 a=r2 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t317 mm8 a=r1 b=r6 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t318 mm8 a=r2 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t319 mm8 a=r0 b=r2 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t320 mm8 a=r5 b=r2 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t321 mm8 a=r7 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t322 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t323 mm8 a=r4 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t324 mm8 a=r5 b=r7 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t325 mm8 a=r6 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t326 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t327 mm8 a=r1 b=r5 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t328 mm8 a=r0 b=r1 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t329 mm8 a=r0 b=r3 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t330 mm8 a=r6 b=r7 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t331 mm8 a=r4 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t332 mm8 a=r4 b=r4 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t333 mm8 a=r4 b=r6 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t334 mm8 a=r2 b=r2 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t335 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t336 mm8 a=r4 b=r0 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t337 mm8 a=r1 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t338 mm8 a=r3 b=r7 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t339 mm8 a=r5 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t340 mm8 a=r5 b=r0 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t341 mm8 a=r6 b=r6 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t342 mm8 a=r4 b=r7 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t343 mm8 a=r0 b=r4 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t344 mm8 a=r2 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t345 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t346 mm8 a=r6 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t347 mm8 a=r5 b=r3 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t348 mm8 a=r0 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t349 mm8 a=r6 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t350 mm8 a=r1 b=r5 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t351 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t352 mm8 a=r4 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t353 mm8 a=r7 b=r3 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t354 mm8 a=r4 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t355 mm8 a=r4 b=r5 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t356 mm8 a=r7 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t357 mm8 a=r7 b=r3 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t358 mm8 a=r4 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t359 mm8 a=r2 b=r7 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t360 mm8 a=r4 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t361 mm8 a=r2 b=r2 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t362 mm8 a=r2 b=r7 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t363 mm8 a=r7 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t364 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t365 mm8 a=r6 b=r6 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t366 mm8 a=r7 b=r7 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t367 mm8 a=r4 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t368 mm8 a=r7 b=r0 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t369 mm8 a=r1 b=r0 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t370 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t371 mm8 a=r5 b=r4 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t372 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t373 mm8 a=r4 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t374 mm8 a=r1 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t375 mm8 a=r6 b=r5 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t376 mm8 a=r3 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t377 mm8 a=r6 b=r4 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t378 mm8 a=r6 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t379 mm8 a=r3 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t380 mm8 a=r2 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t381 mm8 a=r3 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t382 mm8 a=r5 b=r2 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t383 mm8 a=r1 b=r2 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t384 mm8 a=r3 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t385 mm8 a=r6 b=r0 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t386 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t387 mm8 a=r3 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t388 mm8 a=r3 b=r0 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t389 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t390 mm8 a=r5 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t391 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t392 mm8 a=r2 b=r3 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t393 mm8 a=r3 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t394 mm8 a=r0 b=r7 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t395 mm8 a=r0 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t396 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t397 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t398 mm8 a=r6 b=r5 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t399 mm8 a=r6 b=r3 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t400 mm8 a=r2 b=r7 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t401 mm8 a=r7 b=r6 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t402 mm8 a=r0 b=r0 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t403 mm8 a=r7 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t404 mm8 a=r1 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t405 mm8 a=r6 b=r6 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t406 mm8 a=r6 b=r1 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t407 mm8 a=r5 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t408 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t409 mm8 a=r3 b=r4 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t410 mm8 a=r0 b=r5 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t411 mm8 a=r2 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t412 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t413 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t414 mm8 a=r7 b=r1 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t415 mm8 a=r4 b=r7 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t416 mm8 a=r5 b=r4 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t417 mm8 a=r6 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t418 mm8 a=r1 b=r3 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t419 mm8 a=r5 b=r0 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t420 mm8 a=r4 b=r2 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t421 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t422 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t423 mm8 a=r1 b=r7 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t424 mm8 a=r5 b=r1 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t425 mm8 a=r2 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t426 mm8 a=r1 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t427 mm8 a=r6 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t428 mm8 a=r6 b=r2 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t429 mm8 a=r3 b=r3 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t430 mm8 a=r7 b=r7 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t431 mm8 a=r6 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t432 mm8 a=r3 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t433 mm8 a=r3 b=r0 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t434 mm8 a=r0 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t435 mm8 a=r7 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t436 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t437 mm8 a=r0 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t438 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t439 mm8 a=r4 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t440 mm8 a=r3 b=r5 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t441 mm8 a=r5 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t442 mm8 a=r1 b=r2 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t443 mm8 a=r1 b=r7 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t444 mm8 a=r3 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t445 mm8 a=r7 b=r5 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t446 mm8 a=r3 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t447 mm8 a=r6 b=r7 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t448 mm8 a=r5 b=r2 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t449 mm8 a=r7 b=r1 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t450 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t451 mm8 a=r0 b=r3 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t452 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t453 mm8 a=r5 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t454 mm8 a=r7 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t455 mm8 a=r7 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t456 mm8 a=r6 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t457 mm8 a=r7 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t458 mm8 a=r5 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t459 mm8 a=r6 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t460 mm8 a=r7 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t461 mm8 a=r0 b=r6 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t462 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t463 mm8 a=r2 b=r0 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t464 mm8 a=r0 b=r3 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t465 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t466 mm8 a=r1 b=r2 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t467 mm8 a=r1 b=r0 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t468 mm8 a=r4 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t469 mm8 a=r2 b=r0 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t470 mm8 a=r3 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t471 mm8 a=r2 b=r2 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t472 mm8 a=r1 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t473 mm8 a=r2 b=r7 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t474 mm8 a=r5 b=r3 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t475 mm8 a=r7 b=r6 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t476 mm8 a=r3 b=r0 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t477 mm8 a=r3 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t478 mm8 a=r0 b=r6 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t479 mm8 a=r7 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t480 mm8 a=r6 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t481 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t482 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t483 mm8 a=r7 b=r0 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t484 mm8 a=r3 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t485 mm8 a=r6 b=r4 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t486 mm8 a=r6 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t487 mm8 a=r2 b=r5 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t488 mm8 a=r1 b=r2 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t489 mm8 a=r5 b=r2 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t490 mm8 a=r7 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t491 mm8 a=r0 b=r0 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t492 mm8 a=r3 b=r1 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t493 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t494 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t495 mm8 a=r2 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t496 mm8 a=r3 b=r5 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t497 mm8 a=r3 b=r2 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t498 mm8 a=r3 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t499 mm8 a=r1 b=r6 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t500 mm8 a=r7 b=r6 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t501 mm8 a=r4 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t502 mm8 a=r5 b=r7 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t503 mm8 a=r7 b=r5 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t504 mm8 a=r2 b=r0 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t505 mm8 a=r4 b=r0 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t506 mm8 a=r0 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t507 mm8 a=r5 b=r6 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t508 mm8 a=r7 b=r3 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t509 mm8 a=r4 b=r4 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t510 mm8 a=r0 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t511 mm8 a=r2 b=r4 c=r1 c2=r3
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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proto-cuda/packs-ca4/mx8_mm512/program_bound.metal Normal file
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#include <metal_stdlib>
using namespace metal;
// int8 tile reference (Counter ASIC 4.0 research): A = the 32 lanes' av as 8 x 16 bytes (lane l holds row l >> 2, bytes 4 (l & 3)..),
// B = bv as 16 x 8 (lane l holds column l >> 2); lane l gets C[l >> 2][2 (l & 3)] and C[l >> 2][2 (l & 3) + 1]; the PTX mma.m8n8k16 u8 layout.
static inline void mm8_ref(uint av, uint bv, uint lane, thread uint& d0, thread uint& d1) {
uint row = lane >> 2, col0 = 2u * (lane & 3u);
uint acc0 = 0u, acc1 = 0u;
for (uint j = 0u; j < 4u; ++j) {
uint aw = simd_shuffle(av, (ushort)(4u * row + j));
uint bw0 = simd_shuffle(bv, (ushort)(4u * col0 + j));
uint bw1 = simd_shuffle(bv, (ushort)(4u * (col0 + 1u) + j));
for (uint t = 0u; t < 4u; ++t) {
uint ab = (aw >> (8u * t)) & 0xffu;
acc0 += ab * ((bw0 >> (8u * t)) & 0xffu);
acc1 += ab * ((bw1 >> (8u * t)) & 0xffu);
}
}
d0 = acc0; d1 = acc1;
}
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Header-bound variant: the init words come from buffer 3 (bind.rs), not from SEEDW.
kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
constant uint* initw [[buffer(3)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint lane = gid & 31u;
{ uint x = nonce ^ initw[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ initw[1]; }
{ uint x = nonce ^ initw[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ initw[2]; }
{ uint x = nonce ^ initw[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ initw[3]; }
{ uint x = nonce ^ initw[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ initw[4]; }
{ uint x = nonce ^ initw[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ initw[5]; }
{ uint x = nonce ^ initw[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ initw[6]; }
{ uint x = nonce ^ initw[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ initw[7]; }
{ uint x = nonce ^ initw[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ initw[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// int8 tile block (Counter ASIC 4.0 research, experimental): 512 mma.m8n8k16 u8 tiles per iteration, both outputs consumed
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t0 mm8 a=r6 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t1 mm8 a=r1 b=r1 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t2 mm8 a=r2 b=r5 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t3 mm8 a=r1 b=r5 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t4 mm8 a=r2 b=r0 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t5 mm8 a=r2 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t6 mm8 a=r1 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t7 mm8 a=r4 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t8 mm8 a=r1 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t9 mm8 a=r3 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t10 mm8 a=r3 b=r0 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t11 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t12 mm8 a=r3 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t13 mm8 a=r1 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t14 mm8 a=r3 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t15 mm8 a=r1 b=r0 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t16 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t17 mm8 a=r0 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t18 mm8 a=r1 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t19 mm8 a=r3 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t20 mm8 a=r3 b=r0 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t21 mm8 a=r0 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t22 mm8 a=r1 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t23 mm8 a=r1 b=r2 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t24 mm8 a=r3 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t25 mm8 a=r5 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t26 mm8 a=r1 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t27 mm8 a=r3 b=r2 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t28 mm8 a=r2 b=r4 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t29 mm8 a=r3 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t30 mm8 a=r6 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t31 mm8 a=r1 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t32 mm8 a=r7 b=r6 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t33 mm8 a=r7 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t34 mm8 a=r1 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t35 mm8 a=r2 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t36 mm8 a=r1 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t37 mm8 a=r1 b=r7 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t38 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t39 mm8 a=r6 b=r2 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t40 mm8 a=r6 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t41 mm8 a=r6 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t42 mm8 a=r7 b=r4 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t43 mm8 a=r6 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t44 mm8 a=r0 b=r6 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t45 mm8 a=r6 b=r5 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t46 mm8 a=r6 b=r6 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t47 mm8 a=r7 b=r3 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t48 mm8 a=r7 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t49 mm8 a=r4 b=r5 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t50 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t51 mm8 a=r3 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t52 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t53 mm8 a=r7 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t54 mm8 a=r7 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t55 mm8 a=r1 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t56 mm8 a=r4 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t57 mm8 a=r4 b=r3 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t58 mm8 a=r2 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t59 mm8 a=r6 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t60 mm8 a=r6 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t61 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t62 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t63 mm8 a=r1 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t64 mm8 a=r0 b=r5 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t65 mm8 a=r0 b=r1 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t66 mm8 a=r3 b=r5 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t67 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t68 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t69 mm8 a=r6 b=r7 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t70 mm8 a=r1 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t71 mm8 a=r3 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t72 mm8 a=r4 b=r0 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t73 mm8 a=r4 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t74 mm8 a=r5 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t75 mm8 a=r4 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t76 mm8 a=r5 b=r6 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t77 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t78 mm8 a=r2 b=r5 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t79 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t80 mm8 a=r6 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t81 mm8 a=r4 b=r3 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t82 mm8 a=r6 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t83 mm8 a=r2 b=r2 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t84 mm8 a=r0 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t85 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t86 mm8 a=r3 b=r4 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t87 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t88 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t89 mm8 a=r4 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t90 mm8 a=r6 b=r5 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t91 mm8 a=r6 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t92 mm8 a=r2 b=r6 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t93 mm8 a=r2 b=r2 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t94 mm8 a=r2 b=r4 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t95 mm8 a=r5 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t96 mm8 a=r0 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t97 mm8 a=r0 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t98 mm8 a=r2 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t99 mm8 a=r1 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t100 mm8 a=r2 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t101 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t102 mm8 a=r5 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t103 mm8 a=r4 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t104 mm8 a=r2 b=r0 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t105 mm8 a=r6 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t106 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t107 mm8 a=r2 b=r1 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t108 mm8 a=r4 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t109 mm8 a=r2 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t110 mm8 a=r1 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t111 mm8 a=r6 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t112 mm8 a=r5 b=r7 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t113 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t114 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t115 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t116 mm8 a=r7 b=r2 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t117 mm8 a=r7 b=r6 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t118 mm8 a=r0 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t119 mm8 a=r4 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t120 mm8 a=r5 b=r3 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t121 mm8 a=r2 b=r7 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t122 mm8 a=r0 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t123 mm8 a=r5 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t124 mm8 a=r5 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t125 mm8 a=r7 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t126 mm8 a=r6 b=r3 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t127 mm8 a=r6 b=r7 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t128 mm8 a=r6 b=r7 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t129 mm8 a=r3 b=r2 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t130 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t131 mm8 a=r3 b=r5 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t132 mm8 a=r0 b=r7 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t133 mm8 a=r2 b=r6 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t134 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t135 mm8 a=r0 b=r2 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t136 mm8 a=r3 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t137 mm8 a=r7 b=r0 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t138 mm8 a=r2 b=r2 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t139 mm8 a=r0 b=r4 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t140 mm8 a=r4 b=r6 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t141 mm8 a=r5 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t142 mm8 a=r2 b=r2 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t143 mm8 a=r4 b=r3 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t144 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t145 mm8 a=r7 b=r2 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t146 mm8 a=r2 b=r7 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t147 mm8 a=r3 b=r1 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t148 mm8 a=r2 b=r1 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t149 mm8 a=r4 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t150 mm8 a=r3 b=r6 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t151 mm8 a=r1 b=r4 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t152 mm8 a=r3 b=r1 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t153 mm8 a=r0 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t154 mm8 a=r7 b=r3 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t155 mm8 a=r1 b=r3 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t156 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t157 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t158 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t159 mm8 a=r1 b=r0 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t160 mm8 a=r0 b=r1 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t161 mm8 a=r4 b=r0 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t162 mm8 a=r6 b=r6 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t163 mm8 a=r5 b=r3 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t164 mm8 a=r0 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t165 mm8 a=r6 b=r5 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t166 mm8 a=r6 b=r5 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t167 mm8 a=r4 b=r5 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t168 mm8 a=r3 b=r6 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t169 mm8 a=r6 b=r2 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t170 mm8 a=r6 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t171 mm8 a=r6 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t172 mm8 a=r7 b=r3 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t173 mm8 a=r0 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t174 mm8 a=r6 b=r6 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t175 mm8 a=r1 b=r6 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t176 mm8 a=r2 b=r4 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t177 mm8 a=r1 b=r7 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t178 mm8 a=r4 b=r2 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t179 mm8 a=r5 b=r2 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t180 mm8 a=r0 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t181 mm8 a=r3 b=r5 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t182 mm8 a=r1 b=r1 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t183 mm8 a=r3 b=r1 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t184 mm8 a=r7 b=r4 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t185 mm8 a=r5 b=r0 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t186 mm8 a=r2 b=r5 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t187 mm8 a=r3 b=r0 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t188 mm8 a=r1 b=r4 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t189 mm8 a=r7 b=r2 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t190 mm8 a=r1 b=r5 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t191 mm8 a=r2 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t192 mm8 a=r5 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t193 mm8 a=r2 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t194 mm8 a=r4 b=r1 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t195 mm8 a=r2 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t196 mm8 a=r5 b=r6 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t197 mm8 a=r5 b=r3 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t198 mm8 a=r1 b=r0 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t199 mm8 a=r2 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t200 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t201 mm8 a=r7 b=r2 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t202 mm8 a=r2 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t203 mm8 a=r0 b=r5 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t204 mm8 a=r4 b=r7 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t205 mm8 a=r3 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t206 mm8 a=r0 b=r6 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t207 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t208 mm8 a=r0 b=r1 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t209 mm8 a=r4 b=r4 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t210 mm8 a=r7 b=r1 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t211 mm8 a=r1 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t212 mm8 a=r2 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t213 mm8 a=r2 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t214 mm8 a=r4 b=r6 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t215 mm8 a=r7 b=r3 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t216 mm8 a=r6 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t217 mm8 a=r5 b=r7 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t218 mm8 a=r7 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t219 mm8 a=r2 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t220 mm8 a=r1 b=r7 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t221 mm8 a=r7 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t222 mm8 a=r0 b=r6 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t223 mm8 a=r2 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t224 mm8 a=r1 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t225 mm8 a=r2 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t226 mm8 a=r2 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t227 mm8 a=r3 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t228 mm8 a=r7 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t229 mm8 a=r1 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t230 mm8 a=r0 b=r3 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t231 mm8 a=r1 b=r3 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t232 mm8 a=r5 b=r4 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t233 mm8 a=r7 b=r2 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t234 mm8 a=r2 b=r0 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t235 mm8 a=r3 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t236 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t237 mm8 a=r3 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t238 mm8 a=r2 b=r0 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t239 mm8 a=r5 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t240 mm8 a=r2 b=r7 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t241 mm8 a=r0 b=r1 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t242 mm8 a=r0 b=r2 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t243 mm8 a=r4 b=r4 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r0 += d0_; r7 += d1_; } // t244 mm8 a=r7 b=r6 c=r0 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t245 mm8 a=r4 b=r4 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t246 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t247 mm8 a=r3 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t248 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t249 mm8 a=r4 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t250 mm8 a=r0 b=r6 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t251 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t252 mm8 a=r0 b=r2 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t253 mm8 a=r5 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t254 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t255 mm8 a=r5 b=r0 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t256 mm8 a=r2 b=r1 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t257 mm8 a=r4 b=r3 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t258 mm8 a=r4 b=r1 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t259 mm8 a=r5 b=r5 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t260 mm8 a=r3 b=r2 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t261 mm8 a=r0 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t262 mm8 a=r6 b=r4 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t263 mm8 a=r6 b=r4 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t264 mm8 a=r7 b=r2 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t265 mm8 a=r6 b=r1 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t266 mm8 a=r0 b=r0 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t267 mm8 a=r6 b=r3 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t268 mm8 a=r1 b=r0 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t269 mm8 a=r7 b=r7 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t270 mm8 a=r6 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t271 mm8 a=r0 b=r3 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t272 mm8 a=r6 b=r0 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t273 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t274 mm8 a=r1 b=r0 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t275 mm8 a=r1 b=r3 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t276 mm8 a=r1 b=r5 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t277 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t278 mm8 a=r0 b=r0 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t279 mm8 a=r2 b=r4 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r2, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t280 mm8 a=r7 b=r2 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t281 mm8 a=r1 b=r0 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t282 mm8 a=r0 b=r1 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t283 mm8 a=r0 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t284 mm8 a=r1 b=r5 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t285 mm8 a=r4 b=r7 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t286 mm8 a=r1 b=r0 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t287 mm8 a=r7 b=r1 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t288 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t289 mm8 a=r0 b=r5 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t290 mm8 a=r3 b=r2 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t291 mm8 a=r7 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t292 mm8 a=r6 b=r7 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r5, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t293 mm8 a=r5 b=r5 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t294 mm8 a=r5 b=r7 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t295 mm8 a=r0 b=r7 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t296 mm8 a=r6 b=r1 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t297 mm8 a=r4 b=r5 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t298 mm8 a=r6 b=r0 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t299 mm8 a=r6 b=r0 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t300 mm8 a=r6 b=r4 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t301 mm8 a=r6 b=r4 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t302 mm8 a=r7 b=r6 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t303 mm8 a=r3 b=r2 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t304 mm8 a=r6 b=r5 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t305 mm8 a=r4 b=r5 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t306 mm8 a=r3 b=r1 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t307 mm8 a=r4 b=r3 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t308 mm8 a=r2 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t309 mm8 a=r2 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t310 mm8 a=r6 b=r1 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t311 mm8 a=r4 b=r6 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t312 mm8 a=r1 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t313 mm8 a=r2 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t314 mm8 a=r0 b=r3 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t315 mm8 a=r7 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t316 mm8 a=r2 b=r4 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t317 mm8 a=r1 b=r6 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t318 mm8 a=r2 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t319 mm8 a=r0 b=r2 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t320 mm8 a=r5 b=r2 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t321 mm8 a=r7 b=r4 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t322 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r3, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t323 mm8 a=r4 b=r3 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t324 mm8 a=r5 b=r7 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t325 mm8 a=r6 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t326 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t327 mm8 a=r1 b=r5 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r1, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t328 mm8 a=r0 b=r1 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t329 mm8 a=r0 b=r3 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r0 += d1_; } // t330 mm8 a=r6 b=r7 c=r4 c2=r0
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t331 mm8 a=r4 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t332 mm8 a=r4 b=r4 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t333 mm8 a=r4 b=r6 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t334 mm8 a=r2 b=r2 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t335 mm8 a=r7 b=r1 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r2 += d0_; r3 += d1_; } // t336 mm8 a=r4 b=r0 c=r2 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r4, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t337 mm8 a=r1 b=r4 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r2 += d0_; r7 += d1_; } // t338 mm8 a=r3 b=r7 c=r2 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t339 mm8 a=r5 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t340 mm8 a=r5 b=r0 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t341 mm8 a=r6 b=r6 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t342 mm8 a=r4 b=r7 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t343 mm8 a=r0 b=r4 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t344 mm8 a=r2 b=r5 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t345 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t346 mm8 a=r6 b=r0 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t347 mm8 a=r5 b=r3 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t348 mm8 a=r0 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t349 mm8 a=r6 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t350 mm8 a=r1 b=r5 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t351 mm8 a=r6 b=r4 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t352 mm8 a=r4 b=r1 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t353 mm8 a=r7 b=r3 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t354 mm8 a=r4 b=r1 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r5, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t355 mm8 a=r4 b=r5 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t356 mm8 a=r7 b=r6 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t357 mm8 a=r7 b=r3 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r7 += d1_; } // t358 mm8 a=r4 b=r7 c=r5 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t359 mm8 a=r2 b=r7 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t360 mm8 a=r4 b=r4 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t361 mm8 a=r2 b=r2 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t362 mm8 a=r2 b=r7 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t363 mm8 a=r7 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t364 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r5 += d0_; r4 += d1_; } // t365 mm8 a=r6 b=r6 c=r5 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t366 mm8 a=r7 b=r7 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t367 mm8 a=r4 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t368 mm8 a=r7 b=r0 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t369 mm8 a=r1 b=r0 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t370 mm8 a=r2 b=r5 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t371 mm8 a=r5 b=r4 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t372 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r6, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t373 mm8 a=r4 b=r6 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r5, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t374 mm8 a=r1 b=r5 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t375 mm8 a=r6 b=r5 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t376 mm8 a=r3 b=r6 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t377 mm8 a=r6 b=r4 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t378 mm8 a=r6 b=r3 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t379 mm8 a=r3 b=r0 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t380 mm8 a=r2 b=r0 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t381 mm8 a=r3 b=r5 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t382 mm8 a=r5 b=r2 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r0 += d0_; r2 += d1_; } // t383 mm8 a=r1 b=r2 c=r0 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t384 mm8 a=r3 b=r1 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t385 mm8 a=r6 b=r0 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t386 mm8 a=r2 b=r0 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t387 mm8 a=r3 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t388 mm8 a=r3 b=r0 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t389 mm8 a=r6 b=r4 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t390 mm8 a=r5 b=r4 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t391 mm8 a=r6 b=r3 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r3 += d0_; r0 += d1_; } // t392 mm8 a=r2 b=r3 c=r3 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t393 mm8 a=r3 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t394 mm8 a=r0 b=r7 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t395 mm8 a=r0 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t396 mm8 a=r7 b=r7 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t397 mm8 a=r5 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t398 mm8 a=r6 b=r5 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r3, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t399 mm8 a=r6 b=r3 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r0 += d0_; r4 += d1_; } // t400 mm8 a=r2 b=r7 c=r0 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t401 mm8 a=r7 b=r6 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t402 mm8 a=r0 b=r0 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t403 mm8 a=r7 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r1, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t404 mm8 a=r1 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r3 += d0_; r6 += d1_; } // t405 mm8 a=r6 b=r6 c=r3 c2=r6
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t406 mm8 a=r6 b=r1 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r2 += d0_; r4 += d1_; } // t407 mm8 a=r5 b=r7 c=r2 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t408 mm8 a=r7 b=r4 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r4, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t409 mm8 a=r3 b=r4 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r5, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t410 mm8 a=r0 b=r5 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t411 mm8 a=r2 b=r0 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r4, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t412 mm8 a=r7 b=r4 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t413 mm8 a=r2 b=r7 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r0 += d0_; r3 += d1_; } // t414 mm8 a=r7 b=r1 c=r0 c2=r3
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r5 += d0_; r1 += d1_; } // t415 mm8 a=r4 b=r7 c=r5 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r4, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t416 mm8 a=r5 b=r4 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t417 mm8 a=r6 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r3, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t418 mm8 a=r1 b=r3 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r0, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t419 mm8 a=r5 b=r0 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r2, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t420 mm8 a=r4 b=r2 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r3 += d0_; r7 += d1_; } // t421 mm8 a=r4 b=r4 c=r3 c2=r7
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r4 += d0_; r3 += d1_; } // t422 mm8 a=r0 b=r7 c=r4 c2=r3
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t423 mm8 a=r1 b=r7 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t424 mm8 a=r5 b=r1 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t425 mm8 a=r2 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t426 mm8 a=r1 b=r6 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r6, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t427 mm8 a=r6 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r2, lane, d0_, d1_); r7 += d0_; r4 += d1_; } // t428 mm8 a=r6 b=r2 c=r7 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r3, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t429 mm8 a=r3 b=r3 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r3 += d0_; r5 += d1_; } // t430 mm8 a=r7 b=r7 c=r3 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t431 mm8 a=r6 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t432 mm8 a=r3 b=r2 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t433 mm8 a=r3 b=r0 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r5 += d0_; r3 += d1_; } // t434 mm8 a=r0 b=r7 c=r5 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t435 mm8 a=r7 b=r5 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t436 mm8 a=r6 b=r4 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r7, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t437 mm8 a=r0 b=r7 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t438 mm8 a=r5 b=r1 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r7, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t439 mm8 a=r4 b=r7 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t440 mm8 a=r3 b=r5 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r1 += d0_; r4 += d1_; } // t441 mm8 a=r5 b=r1 c=r1 c2=r4
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t442 mm8 a=r1 b=r2 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r5 += d0_; r2 += d1_; } // t443 mm8 a=r1 b=r7 c=r5 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t444 mm8 a=r3 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t445 mm8 a=r7 b=r5 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r2 += d0_; r1 += d1_; } // t446 mm8 a=r3 b=r1 c=r2 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t447 mm8 a=r6 b=r7 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t448 mm8 a=r5 b=r2 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t449 mm8 a=r7 b=r1 c=r1 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r7 += d0_; r3 += d1_; } // t450 mm8 a=r7 b=r5 c=r7 c2=r3
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r1 += d0_; r7 += d1_; } // t451 mm8 a=r0 b=r3 c=r1 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t452 mm8 a=r2 b=r4 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t453 mm8 a=r5 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t454 mm8 a=r7 b=r7 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r7 += d0_; r5 += d1_; } // t455 mm8 a=r7 b=r1 c=r7 c2=r5
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t456 mm8 a=r6 b=r5 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t457 mm8 a=r7 b=r7 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r5, r1, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t458 mm8 a=r5 b=r1 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r7, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t459 mm8 a=r6 b=r7 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r7, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t460 mm8 a=r7 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t461 mm8 a=r0 b=r6 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t462 mm8 a=r0 b=r6 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r3 += d0_; r2 += d1_; } // t463 mm8 a=r2 b=r0 c=r3 c2=r2
{ uint d0_, d1_; mm8_ref(r0, r3, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t464 mm8 a=r0 b=r3 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r0 += d0_; r5 += d1_; } // t465 mm8 a=r1 b=r7 c=r0 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r4 += d0_; r1 += d1_; } // t466 mm8 a=r1 b=r2 c=r4 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r0, lane, d0_, d1_); r1 += d0_; r6 += d1_; } // t467 mm8 a=r1 b=r0 c=r1 c2=r6
{ uint d0_, d1_; mm8_ref(r4, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t468 mm8 a=r4 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t469 mm8 a=r2 b=r0 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t470 mm8 a=r3 b=r1 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t471 mm8 a=r2 b=r2 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r1, r7, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t472 mm8 a=r1 b=r7 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r7, lane, d0_, d1_); r6 += d0_; r1 += d1_; } // t473 mm8 a=r2 b=r7 c=r6 c2=r1
{ uint d0_, d1_; mm8_ref(r5, r3, lane, d0_, d1_); r6 += d0_; r3 += d1_; } // t474 mm8 a=r5 b=r3 c=r6 c2=r3
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t475 mm8 a=r7 b=r6 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r0, lane, d0_, d1_); r5 += d0_; r6 += d1_; } // t476 mm8 a=r3 b=r0 c=r5 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r4 += d0_; r6 += d1_; } // t477 mm8 a=r3 b=r1 c=r4 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t478 mm8 a=r0 b=r6 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r7 += d0_; r1 += d1_; } // t479 mm8 a=r7 b=r6 c=r7 c2=r1
{ uint d0_, d1_; mm8_ref(r6, r0, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t480 mm8 a=r6 b=r0 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r6 += d0_; r7 += d1_; } // t481 mm8 a=r2 b=r4 c=r6 c2=r7
{ uint d0_, d1_; mm8_ref(r2, r3, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t482 mm8 a=r2 b=r3 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r0, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t483 mm8 a=r7 b=r0 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r7, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t484 mm8 a=r3 b=r7 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r4, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t485 mm8 a=r6 b=r4 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r6, r5, lane, d0_, d1_); r2 += d0_; r5 += d1_; } // t486 mm8 a=r6 b=r5 c=r2 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r5, lane, d0_, d1_); r4 += d0_; r5 += d1_; } // t487 mm8 a=r2 b=r5 c=r4 c2=r5
{ uint d0_, d1_; mm8_ref(r1, r2, lane, d0_, d1_); r1 += d0_; r2 += d1_; } // t488 mm8 a=r1 b=r2 c=r1 c2=r2
{ uint d0_, d1_; mm8_ref(r5, r2, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t489 mm8 a=r5 b=r2 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r7, r1, lane, d0_, d1_); r2 += d0_; r6 += d1_; } // t490 mm8 a=r7 b=r1 c=r2 c2=r6
{ uint d0_, d1_; mm8_ref(r0, r0, lane, d0_, d1_); r0 += d0_; r6 += d1_; } // t491 mm8 a=r0 b=r0 c=r0 c2=r6
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r4 += d1_; } // t492 mm8 a=r3 b=r1 c=r6 c2=r4
{ uint d0_, d1_; mm8_ref(r6, r1, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t493 mm8 a=r6 b=r1 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r3 += d0_; r1 += d1_; } // t494 mm8 a=r5 b=r6 c=r3 c2=r1
{ uint d0_, d1_; mm8_ref(r2, r2, lane, d0_, d1_); r7 += d0_; r2 += d1_; } // t495 mm8 a=r2 b=r2 c=r7 c2=r2
{ uint d0_, d1_; mm8_ref(r3, r5, lane, d0_, d1_); r5 += d0_; r0 += d1_; } // t496 mm8 a=r3 b=r5 c=r5 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r2, lane, d0_, d1_); r2 += d0_; r0 += d1_; } // t497 mm8 a=r3 b=r2 c=r2 c2=r0
{ uint d0_, d1_; mm8_ref(r3, r1, lane, d0_, d1_); r6 += d0_; r2 += d1_; } // t498 mm8 a=r3 b=r1 c=r6 c2=r2
{ uint d0_, d1_; mm8_ref(r1, r6, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t499 mm8 a=r1 b=r6 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r7, r6, lane, d0_, d1_); r1 += d0_; r5 += d1_; } // t500 mm8 a=r7 b=r6 c=r1 c2=r5
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r1 += d0_; r0 += d1_; } // t501 mm8 a=r4 b=r4 c=r1 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r7, lane, d0_, d1_); r7 += d0_; r6 += d1_; } // t502 mm8 a=r5 b=r7 c=r7 c2=r6
{ uint d0_, d1_; mm8_ref(r7, r5, lane, d0_, d1_); r3 += d0_; r4 += d1_; } // t503 mm8 a=r7 b=r5 c=r3 c2=r4
{ uint d0_, d1_; mm8_ref(r2, r0, lane, d0_, d1_); r4 += d0_; r2 += d1_; } // t504 mm8 a=r2 b=r0 c=r4 c2=r2
{ uint d0_, d1_; mm8_ref(r4, r0, lane, d0_, d1_); r0 += d0_; r1 += d1_; } // t505 mm8 a=r4 b=r0 c=r0 c2=r1
{ uint d0_, d1_; mm8_ref(r0, r2, lane, d0_, d1_); r7 += d0_; r0 += d1_; } // t506 mm8 a=r0 b=r2 c=r7 c2=r0
{ uint d0_, d1_; mm8_ref(r5, r6, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t507 mm8 a=r5 b=r6 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r7, r3, lane, d0_, d1_); r4 += d0_; r7 += d1_; } // t508 mm8 a=r7 b=r3 c=r4 c2=r7
{ uint d0_, d1_; mm8_ref(r4, r4, lane, d0_, d1_); r6 += d0_; r0 += d1_; } // t509 mm8 a=r4 b=r4 c=r6 c2=r0
{ uint d0_, d1_; mm8_ref(r0, r6, lane, d0_, d1_); r6 += d0_; r5 += d1_; } // t510 mm8 a=r0 b=r6 c=r6 c2=r5
{ uint d0_, d1_; mm8_ref(r2, r4, lane, d0_, d1_); r1 += d0_; r3 += d1_; } // t511 mm8 a=r2 b=r4 c=r1 c2=r3
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Expected outputs: igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#define IGNEUM_VEC_WARPS 3
static const uint32_t IGNEUM_VEC_BASE[IGNEUM_VEC_WARPS] = { 0u, 4096u, 1000000u };
static const uint64_t IGNEUM_VEC_OUT[IGNEUM_VEC_WARPS][32] = {
{ // base nonce 0
0x9fb618fc7b6228c3ull, 0x7213e619e80bff2eull, 0x8908e869fc64e236ull, 0x53853d142eaa1e6cull, 0x8d5808d85bd32eaeull, 0xe4f65ecf58bac2a9ull, 0x4ea054f4156f4c70ull, 0xa1f08a2b3a1892e0ull,
0xf44e93176c787eefull, 0xfb9c55a11549b45bull, 0x10b7acceda07b5d6ull, 0x4474ce4799a31f83ull, 0x197eb259ca50e2acull, 0x96e4dfb43bf258a8ull, 0x12c83c8e53a92bf9ull, 0x83ecf8570f5f1dc2ull,
0xb946e6cd2443717bull, 0x60a888be09b52c72ull, 0x3b763ae6046e85a7ull, 0x6b93ec061ac325e3ull, 0x60db0f498f330cd0ull, 0xf522f6d924097107ull, 0x38b94f8f4453d839ull, 0x517d41d209a5ddebull,
0x4858f3b1f2d71b82ull, 0x787a16b5e58c3fd9ull, 0xe78b4de4e009ec91ull, 0x0b8198730d366171ull, 0x9397dc5c1d63fa72ull, 0x15ca5f6540b987a3ull, 0x83a24efeb6311fb7ull, 0x714a3e83fec4a2beull
},
{ // base nonce 4096
0xeba4e6729f0e97b7ull, 0x74af8ebe7886a1caull, 0x7b92eb7acdaede21ull, 0x2b4909c0c88ffb31ull, 0xcd5a3d7fc34eab6full, 0x928be2f89abd8307ull, 0x1ee3a56655f8e701ull, 0xd2f307a6599e90feull,
0x624b2ea35003d63cull, 0x831b70652ed75475ull, 0xc7130ca2e331789aull, 0xf2ea9c7c896c794bull, 0x360d08611e11f090ull, 0xc86b79a26ce04221ull, 0xc800bf3fd30e8091ull, 0x3cd7a142317a4fc7ull,
0x5020b46b67593caeull, 0xf569cf2ad3352bd6ull, 0xcdd040840753678dull, 0x7f91ccac56ed6baaull, 0xf844b8e0342f813bull, 0xd7ccc48b5c99ea75ull, 0x3f801464920736cfull, 0x2cd1c9fcb4868010ull,
0x8aeffc12d4739525ull, 0x42ca83cca80b44c3ull, 0x6148286c39ecf6dbull, 0xd5db07f58d639b0dull, 0x813dcc14cf534f42ull, 0xcba5207abd54f712ull, 0xbe48e582f2f5cb2aull, 0x09d56ce806b90b55ull
},
{ // base nonce 1000000
0xe73c99aacc6c825cull, 0xda827d89d90359f9ull, 0x4d224a3c6f1147e7ull, 0x6748b5fd24e70062ull, 0x9053e40978e90a50ull, 0x7347ab5b612bb430ull, 0xd7371fb2cdfea057ull, 0xbc24275fd6f92ff3ull,
0x57daadd306115c53ull, 0xd5571774c6de8831ull, 0xce515d8d9a249a47ull, 0x1ec0e9dac751c9d2ull, 0xc35a8fa80881fdafull, 0x9bb227f408b1e2c4ull, 0xb11818ebab6cf5a4ull, 0x212b46a1bf67e747ull,
0x96bd3432a7384a4full, 0x006c173b6f4854efull, 0x59c23df13369f803ull, 0x01528a936a9a0776ull, 0xcb38ceab8f869d43ull, 0x67a9b4af9ac66df2ull, 0x63b3dc84e4485cf8ull, 0xbfc1a38632fd9d2full,
0xd2854da6e088992eull, 0xc755fd06911b0a51ull, 0x01a2c5a460546176ull, 0x0710d4a963fee5f6ull, 0x3ddbebf9a8d3fe7eull, 0xaf55162589b7f13cull, 0xb25f45be4e6bbeaaull, 0x88fb9a4c59780da2ull
}
};
// Dataset self-test: dataset[0..15] and dataset[IGNEUM_MASK] (268435455).
static const uint32_t IGNEUM_DS_HEAD[16] = {
0xfdad4319u, 0x1a7b68e1u, 0xde6db608u, 0x13d73892u, 0xd17f447au, 0xb2221ccfu, 0x9db004bdu, 0x57d7d367u,
0xdbc4cf34u, 0x697c009au, 0xc43af1d4u, 0x97f12b2eu, 0x74c37cd0u, 0xc651ea15u, 0x665a6d29u, 0x22330a2du
};
static const uint32_t IGNEUM_DS_LAST_INDEX = 268435455u;
static const uint32_t IGNEUM_DS_LAST = 0xa83e7aa6u;
// 64 sampled dataset words (index, value) computed on the Mac.
#define IGNEUM_DS_SAMPLES 64
static const uint32_t IGNEUM_DS_SAMPLE_INDEX[IGNEUM_DS_SAMPLES] = {
59471966u, 217795994u, 208353206u, 42483309u, 172547758u, 148076330u, 183853158u, 214389424u, 267488061u, 169781097u, 184093494u, 153880993u, 84977930u, 46426879u, 3093825u, 225364072u, 44593546u, 260713159u, 168250303u, 52384140u, 223401610u, 45554030u, 95410555u, 175039924u, 79171087u, 267580473u, 24168642u, 37981670u, 171551130u, 195559979u, 204611762u, 140997658u, 138925853u, 86637313u, 20736778u, 219665210u, 160430336u, 264654675u, 8013395u, 228945585u, 213884386u, 104419827u, 44185464u, 142737231u, 99284897u, 132475900u, 61861762u, 132056166u, 262388043u, 91878046u, 117353561u, 124768597u, 71352993u, 190698941u, 46055428u, 55281366u, 165145231u, 106810753u, 171985651u, 232085256u, 159510492u, 40072060u, 209107596u, 39023794u
};
static const uint32_t IGNEUM_DS_SAMPLE_VALUE[IGNEUM_DS_SAMPLES] = {
0x3230bc7bu, 0x7fbfe2c9u, 0xb2690991u, 0x1745c7c5u, 0x0ab0ccafu, 0x1bf87d6bu, 0x160139fdu, 0x719817acu, 0x0155df4bu, 0xbe1e86c3u, 0x680bcd6cu, 0x79c3dc6cu, 0x181e7e5fu, 0x0713a109u, 0xc705dd9fu, 0x3933b7a8u, 0xdd1c0431u, 0x50522b30u, 0xa0020b38u, 0xbff39e96u, 0x21b67e18u, 0x740f8db3u, 0x2baba568u, 0x2c9bef83u, 0x0ad9b671u, 0xc4327869u, 0x7b4fd7d0u, 0x2c29965fu, 0xec56f15fu, 0x61111746u, 0x303a1d6eu, 0xbddcfd1au, 0xf829a355u, 0x6d5df2a9u, 0x01ab8e44u, 0x06d13507u, 0xda8dcfc6u, 0x01a703e1u, 0xafe7d2c1u, 0xc091c3a2u, 0xac1814feu, 0x6e6ff62au, 0x8fdf01bau, 0xdd3f7159u, 0xdfa0d75cu, 0x26684c35u, 0x7f441e63u, 0x88df2570u, 0x8aa4d5ebu, 0xcc816c05u, 0x434df890u, 0xcd392ad6u, 0x1ab4cb63u, 0x595926fau, 0x7cd76b41u, 0x20cb95c4u, 0x13cf823fu, 0xf9daf901u, 0xff9af40au, 0x2c7dfa51u, 0x871206dbu, 0x938c116cu, 0xb64bf199u, 0x5751f874u
};
// Cache self-test (memory-hard mode): cache[0..15], the last 16 words, and FNV-1a 64 over all 2^26 words.
static const uint32_t IGNEUM_CACHE_HEAD[16] = {
0x355a86d2u, 0x7957db1cu, 0xd21772afu, 0x6fc1e09bu, 0xd55ce61du, 0x6e6a278bu, 0xd3f543ceu, 0x223d8e82u,
0x143ab337u, 0x2e9f05bdu, 0x2eb389bfu, 0x0c6e449eu, 0x5cfa4222u, 0xba6560feu, 0x8e3e1aa4u, 0xdbcc1d53u
};
static const uint32_t IGNEUM_CACHE_LAST[16] = {
0x41190d91u, 0xbd277957u, 0x22ddbb49u, 0x6986f207u, 0xdf69a4d6u, 0x26401a3au, 0x818230fbu, 0xc417122du,
0x3597b211u, 0xb553ce55u, 0xcf39cc0du, 0x3b7fc43au, 0x3fd43b00u, 0x67e1c80eu, 0xffa7ea7du, 0xca2960abu
};
static const uint64_t IGNEUM_CACHE_FNV64 = 0x48c4f5bf24166b2eull;

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{
"seed": "igneum-genesis",
"day": "2026-10-03",
"dataset_mode": "memory-hard",
"dataset_log2_words": 28,
"mask": "0x0fffffff",
"lanes": 32,
"source": "igneum-pow (Rust) CPU interpreter, generator v2, memory-hard dataset",
"warps": [
{"base_nonce": 0, "expected": [
"0x9fb618fc7b6228c3", "0x7213e619e80bff2e", "0x8908e869fc64e236", "0x53853d142eaa1e6c", "0x8d5808d85bd32eae", "0xe4f65ecf58bac2a9", "0x4ea054f4156f4c70", "0xa1f08a2b3a1892e0",
"0xf44e93176c787eef", "0xfb9c55a11549b45b", "0x10b7acceda07b5d6", "0x4474ce4799a31f83", "0x197eb259ca50e2ac", "0x96e4dfb43bf258a8", "0x12c83c8e53a92bf9", "0x83ecf8570f5f1dc2",
"0xb946e6cd2443717b", "0x60a888be09b52c72", "0x3b763ae6046e85a7", "0x6b93ec061ac325e3", "0x60db0f498f330cd0", "0xf522f6d924097107", "0x38b94f8f4453d839", "0x517d41d209a5ddeb",
"0x4858f3b1f2d71b82", "0x787a16b5e58c3fd9", "0xe78b4de4e009ec91", "0x0b8198730d366171", "0x9397dc5c1d63fa72", "0x15ca5f6540b987a3", "0x83a24efeb6311fb7", "0x714a3e83fec4a2be"
]},
{"base_nonce": 4096, "expected": [
"0xeba4e6729f0e97b7", "0x74af8ebe7886a1ca", "0x7b92eb7acdaede21", "0x2b4909c0c88ffb31", "0xcd5a3d7fc34eab6f", "0x928be2f89abd8307", "0x1ee3a56655f8e701", "0xd2f307a6599e90fe",
"0x624b2ea35003d63c", "0x831b70652ed75475", "0xc7130ca2e331789a", "0xf2ea9c7c896c794b", "0x360d08611e11f090", "0xc86b79a26ce04221", "0xc800bf3fd30e8091", "0x3cd7a142317a4fc7",
"0x5020b46b67593cae", "0xf569cf2ad3352bd6", "0xcdd040840753678d", "0x7f91ccac56ed6baa", "0xf844b8e0342f813b", "0xd7ccc48b5c99ea75", "0x3f801464920736cf", "0x2cd1c9fcb4868010",
"0x8aeffc12d4739525", "0x42ca83cca80b44c3", "0x6148286c39ecf6db", "0xd5db07f58d639b0d", "0x813dcc14cf534f42", "0xcba5207abd54f712", "0xbe48e582f2f5cb2a", "0x09d56ce806b90b55"
]},
{"base_nonce": 1000000, "expected": [
"0xe73c99aacc6c825c", "0xda827d89d90359f9", "0x4d224a3c6f1147e7", "0x6748b5fd24e70062", "0x9053e40978e90a50", "0x7347ab5b612bb430", "0xd7371fb2cdfea057", "0xbc24275fd6f92ff3",
"0x57daadd306115c53", "0xd5571774c6de8831", "0xce515d8d9a249a47", "0x1ec0e9dac751c9d2", "0xc35a8fa80881fdaf", "0x9bb227f408b1e2c4", "0xb11818ebab6cf5a4", "0x212b46a1bf67e747",
"0x96bd3432a7384a4f", "0x006c173b6f4854ef", "0x59c23df13369f803", "0x01528a936a9a0776", "0xcb38ceab8f869d43", "0x67a9b4af9ac66df2", "0x63b3dc84e4485cf8", "0xbfc1a38632fd9d2f",
"0xd2854da6e088992e", "0xc755fd06911b0a51", "0x01a2c5a460546176", "0x0710d4a963fee5f6", "0x3ddbebf9a8d3fe7e", "0xaf55162589b7f13c", "0xb25f45be4e6bbeaa", "0x88fb9a4c59780da2"
]}
],
"dataset_head": ["0xfdad4319", "0x1a7b68e1", "0xde6db608", "0x13d73892", "0xd17f447a", "0xb2221ccf", "0x9db004bd", "0x57d7d367", "0xdbc4cf34", "0x697c009a", "0xc43af1d4", "0x97f12b2e", "0x74c37cd0", "0xc651ea15", "0x665a6d29", "0x22330a2d"],
"dataset_last_index": 268435455,
"dataset_last": "0xa83e7aa6",
"dataset_samples": [{"index": 59471966, "value": "0x3230bc7b"}, {"index": 217795994, "value": "0x7fbfe2c9"}, {"index": 208353206, "value": "0xb2690991"}, {"index": 42483309, "value": "0x1745c7c5"}, {"index": 172547758, "value": "0x0ab0ccaf"}, {"index": 148076330, "value": "0x1bf87d6b"}, {"index": 183853158, "value": "0x160139fd"}, {"index": 214389424, "value": "0x719817ac"}, {"index": 267488061, "value": "0x0155df4b"}, {"index": 169781097, "value": "0xbe1e86c3"}, {"index": 184093494, "value": "0x680bcd6c"}, {"index": 153880993, "value": "0x79c3dc6c"}, {"index": 84977930, "value": "0x181e7e5f"}, {"index": 46426879, "value": "0x0713a109"}, {"index": 3093825, "value": "0xc705dd9f"}, {"index": 225364072, "value": "0x3933b7a8"}, {"index": 44593546, "value": "0xdd1c0431"}, {"index": 260713159, "value": "0x50522b30"}, {"index": 168250303, "value": "0xa0020b38"}, {"index": 52384140, "value": "0xbff39e96"}, {"index": 223401610, "value": "0x21b67e18"}, {"index": 45554030, "value": "0x740f8db3"}, {"index": 95410555, "value": "0x2baba568"}, {"index": 175039924, "value": "0x2c9bef83"}, {"index": 79171087, "value": "0x0ad9b671"}, {"index": 267580473, "value": "0xc4327869"}, {"index": 24168642, "value": "0x7b4fd7d0"}, {"index": 37981670, "value": "0x2c29965f"}, {"index": 171551130, "value": "0xec56f15f"}, {"index": 195559979, "value": "0x61111746"}, {"index": 204611762, "value": "0x303a1d6e"}, {"index": 140997658, "value": "0xbddcfd1a"}, {"index": 138925853, "value": "0xf829a355"}, {"index": 86637313, "value": "0x6d5df2a9"}, {"index": 20736778, "value": "0x01ab8e44"}, {"index": 219665210, "value": "0x06d13507"}, {"index": 160430336, "value": "0xda8dcfc6"}, {"index": 264654675, "value": "0x01a703e1"}, {"index": 8013395, "value": "0xafe7d2c1"}, {"index": 228945585, "value": "0xc091c3a2"}, {"index": 213884386, "value": "0xac1814fe"}, {"index": 104419827, "value": "0x6e6ff62a"}, {"index": 44185464, "value": "0x8fdf01ba"}, {"index": 142737231, "value": "0xdd3f7159"}, {"index": 99284897, "value": "0xdfa0d75c"}, {"index": 132475900, "value": "0x26684c35"}, {"index": 61861762, "value": "0x7f441e63"}, {"index": 132056166, "value": "0x88df2570"}, {"index": 262388043, "value": "0x8aa4d5eb"}, {"index": 91878046, "value": "0xcc816c05"}, {"index": 117353561, "value": "0x434df890"}, {"index": 124768597, "value": "0xcd392ad6"}, {"index": 71352993, "value": "0x1ab4cb63"}, {"index": 190698941, "value": "0x595926fa"}, {"index": 46055428, "value": "0x7cd76b41"}, {"index": 55281366, "value": "0x20cb95c4"}, {"index": 165145231, "value": "0x13cf823f"}, {"index": 106810753, "value": "0xf9daf901"}, {"index": 171985651, "value": "0xff9af40a"}, {"index": 232085256, "value": "0x2c7dfa51"}, {"index": 159510492, "value": "0x871206db"}, {"index": 40072060, "value": "0x938c116c"}, {"index": 209107596, "value": "0xb64bf199"}, {"index": 39023794, "value": "0x5751f874"}],
"cache_head": ["0x355a86d2", "0x7957db1c", "0xd21772af", "0x6fc1e09b", "0xd55ce61d", "0x6e6a278b", "0xd3f543ce", "0x223d8e82", "0x143ab337", "0x2e9f05bd", "0x2eb389bf", "0x0c6e449e", "0x5cfa4222", "0xba6560fe", "0x8e3e1aa4", "0xdbcc1d53"],
"cache_last_line": ["0x41190d91", "0xbd277957", "0x22ddbb49", "0x6986f207", "0xdf69a4d6", "0x26401a3a", "0x818230fb", "0xc417122d", "0x3597b211", "0xb553ce55", "0xcf39cc0d", "0x3b7fc43a", "0x3fd43b00", "0x67e1c80e", "0xffa7ea7d", "0xca2960ab"],
"cache_fnv1a64": "0x48c4f5bf24166b2e"
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#endif
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, uint t, uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, t, s);
__global uint* d = ds + ((ulong)t * 16u);
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x8bc12da9u : 0x92199f99u); // s0 add
r0 = r0 + r7 + ((((sel >> 26u) & 1u) != 0u) ? 0x63079e5au : 0x8d72d3adu); // s1 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r6 = r6 ^ t_; } // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + ((((sel >> 31u) & 1u) != 0u) ? 0x5d4c7a60u : 0xb21b4babu); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + ((((sel >> 16u) & 1u) != 0u) ? 0xc88e2942u : 0x2fe0e98bu); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r6 = r6 ^ t_; } // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 4u); r2 = r2 ^ t_; } // s12 shfl
r1 = r1 + r5 + ((((sel >> 25u) & 1u) != 0u) ? 0xbc48c63eu : 0xbdf8f9a5u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r2 = r2 ^ t_; } // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x96e8f127u : 0x45c37cecu); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = mul_hi(r6, r0); // s28 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r2 = r2 ^ t_; } // s29 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r1 = r1 ^ t_; } // s30 shfl
r1 = r1 + r6 + ((((sel >> 1u) & 1u) != 0u) ? 0xb1cdb2abu : 0x37985632u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // s33 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r0 = r0 ^ t_; } // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x856e0180u : 0x804e777eu); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xe9bd0cc4u : 0x0b06c8a7u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = mul_hi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = mul_hi(r4, r3); // s44 mulhi
r6 = r6 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0xcdcb63f6u : 0xee822e17u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r4 = r4 ^ t_; } // s47 shfl
r6 = mul_hi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0xd4758987u : 0x3dfad1b6u); // s56 add
r4 = r4 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x0602d6beu : 0xfca75bc2u); // s57 add
r5 = mul_hi(r5, r6); // s58 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r2 = r2 ^ t_; } // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8596687au : 0xd71c02ffu); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 2u); r7 = r7 ^ t_; } // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0x08ac5733u : 0x3c6fe15du); // s72 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + ((((sel >> 1u) & 1u) != 0u) ? 0xc100b495u : 0x295d5faeu); // s77 add
r3 = mul_hi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x5cc59530u : 0x274a9221u); // s81 add
r7 = r7 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x141479ecu : 0xc8651f8eu); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r2 = r2 ^ t_; } // s85 shfl
r3 = r3 ^ r2; // s86 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x883c0c92u : 0x53f915c2u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + ((((sel >> 31u) & 1u) != 0u) ? 0x3cc5bd20u : 0xe2be00a5u); // s91 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r7 = r7 ^ t_; } // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0xbfd646cbu : 0x423fd9c9u); // s101 add
r7 = r7 + r6 + ((((sel >> 11u) & 1u) != 0u) ? 0x19b74a43u : 0x8d3c011du); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + ((((sel >> 15u) & 1u) != 0u) ? 0x7dcb7e18u : 0x8ce14721u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = mul_hi(r2, r0); // s109 mulhi
r1 = mul_hi(r1, r0); // s110 mulhi
r0 = r0 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x3c179ad8u : 0x2d9fc6b9u); // s111 add
r2 = mul_hi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x47359729u : 0x502138e2u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = mul_hi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 2u); r4 = r4 ^ t_; } // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r7 = r7 ^ t_; } // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x6c57e4e7u : 0x33dff776u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + ((((sel >> 30u) & 1u) != 0u) ? 0xe8212c0cu : 0x5db25b34u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = mul_hi(r0, r5); // s138 mulhi
r2 = r2 + r7 + ((((sel >> 10u) & 1u) != 0u) ? 0xd44ff710u : 0x218d4090u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + ((((sel >> 29u) & 1u) != 0u) ? 0xb98942fau : 0xf4b1a8deu); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + ((((sel >> 17u) & 1u) != 0u) ? 0x0d48ba42u : 0x2bef10f2u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + ((((sel >> 30u) & 1u) != 0u) ? 0xc98dea9cu : 0xdc5cc080u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0x6c752dcbu : 0x18197438u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + ((((sel >> 3u) & 1u) != 0u) ? 0x8e481727u : 0xf1c46574u); // s163 add
r0 = mul_hi(r0, r4); // s164 mulhi
r2 = r2 + r6 + ((((sel >> 20u) & 1u) != 0u) ? 0x550ab406u : 0xac578137u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xaebb5966u : 0xa33e6706u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 8u); r7 = r7 ^ t_; } // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5bb7550fu : 0xd94d55acu); // s184 add
r3 = r3 | r5; // s185 or
r6 = mul_hi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s188 shfl
r6 = r6 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x2a354e2du : 0x89e747feu); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = mul_hi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r4 = r4 ^ t_; } // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + ((((sel >> 7u) & 1u) != 0u) ? 0x10cfdc71u : 0xea03e8e7u); // s197 add
r7 = r7 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x66e148d3u : 0xa7ee0102u); // s198 add
r5 = r5 - r2; // s199 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r5 = r5 ^ t_; } // s200 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 8u); r7 = r7 ^ t_; } // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x8558b619u : 0x8379a4deu); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = mul_hi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s209 shfl
r7 = r7 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0xf4049c4cu : 0xaa8cb14eu); // s210 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r3 = r3 ^ t_; } // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = mul_hi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r5 = r5 ^ t_; } // s222 shfl
r5 = mul_hi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0x2a7fecb2u : 0x1d176220u); // s230 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r1 = r1 ^ t_; } // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + ((((sel >> 25u) & 1u) != 0u) ? 0xadce39f3u : 0x17dafb4du); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + ((((sel >> 29u) & 1u) != 0u) ? 0x0e7033b6u : 0xf2f77d26u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x7b2ff6b7u : 0xfed2da4eu); // s247 add
r0 = r0 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb5fad7b1u : 0x03b2891cu); // s248 add
r5 = mul_hi(r5, r4); // s249 mulhi
r5 = r5 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0xa7e71c2fu : 0x042cd6e3u); // s250 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0xb83d78deu : 0x784a302bu); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Bit-exact twin of the Metal kernel for the same seed (see proto-cuda/CHECKLIST.md and program.metal).
// Compiled ahead of time by nvcc together with proto-cuda/host.cu. No NVRTC.
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
#include "memhard.h"
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site, so both shift amounts are in 1..31.
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
// n is masked to 0..31; the second shift amount is masked too, so n == 0 gives x.
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__device__ __forceinline__ uint32_t ds_elem(uint32_t i, uint32_t d0, uint32_t d1) {
uint32_t x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset (MEMHARD.md). One thread per cache segment; one thread per 64-byte dataset item.
// The core functions (mh_cache_segment, mh_item) are in memhard.h and are also compiled for the host.
__global__ void igneum_cache_fill(uint32_t* cache, uint32_t nSegments) {
uint32_t seg = blockIdx.x * blockDim.x + threadIdx.x;
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__global__ void igneum_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
uint32_t t = blockIdx.x * blockDim.x + threadIdx.x;
if (t < nItems) {
uint32_t s[16];
mh_item(cache, t, s);
uint32_t* d = ds + (size_t)t * 16u;
for (uint32_t i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per thread. blockDim.x is a multiple of 32; lane = threadIdx.x & 31 and every
// __shfl_xor_sync stays inside the lane's own warp, exactly like simd_shuffle_xor inside a
// 32-wide Metal SIMD group. Control flow is uniform, so the full 0xffffffff member mask is valid.
__global__ void igneum_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint32_t x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint32_t x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint32_t x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint32_t x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint32_t x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint32_t x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint32_t x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint32_t sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x8bc12da9u : 0x92199f99u); // s0 add
r0 = r0 + r7 + ((((sel >> 26u) & 1u) != 0u) ? 0x63079e5au : 0x8d72d3adu); // s1 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 2); // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + ((((sel >> 31u) & 1u) != 0u) ? 0x5d4c7a60u : 0xb21b4babu); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + ((((sel >> 16u) & 1u) != 0u) ? 0xc88e2942u : 0x2fe0e98bu); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 4); // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r6, 4); // s12 shfl
r1 = r1 + r5 + ((((sel >> 25u) & 1u) != 0u) ? 0xbc48c63eu : 0xbdf8f9a5u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x96e8f127u : 0x45c37cecu); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = __umulhi(r6, r0); // s28 mulhi
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // s29 shfl
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // s30 shfl
r1 = r1 + r6 + ((((sel >> 1u) & 1u) != 0u) ? 0xb1cdb2abu : 0x37985632u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // s33 shfl
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x856e0180u : 0x804e777eu); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xe9bd0cc4u : 0x0b06c8a7u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = __umulhi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = __umulhi(r4, r3); // s44 mulhi
r6 = r6 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0xcdcb63f6u : 0xee822e17u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // s47 shfl
r6 = __umulhi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0xd4758987u : 0x3dfad1b6u); // s56 add
r4 = r4 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x0602d6beu : 0xfca75bc2u); // s57 add
r5 = __umulhi(r5, r6); // s58 mulhi
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8596687au : 0xd71c02ffu); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 2); // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0x08ac5733u : 0x3c6fe15du); // s72 add
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + ((((sel >> 1u) & 1u) != 0u) ? 0xc100b495u : 0x295d5faeu); // s77 add
r3 = __umulhi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x5cc59530u : 0x274a9221u); // s81 add
r7 = r7 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x141479ecu : 0xc8651f8eu); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s85 shfl
r3 = r3 ^ r2; // s86 xor
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x883c0c92u : 0x53f915c2u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + ((((sel >> 31u) & 1u) != 0u) ? 0x3cc5bd20u : 0xe2be00a5u); // s91 add
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0xbfd646cbu : 0x423fd9c9u); // s101 add
r7 = r7 + r6 + ((((sel >> 11u) & 1u) != 0u) ? 0x19b74a43u : 0x8d3c011du); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + ((((sel >> 15u) & 1u) != 0u) ? 0x7dcb7e18u : 0x8ce14721u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = __umulhi(r2, r0); // s109 mulhi
r1 = __umulhi(r1, r0); // s110 mulhi
r0 = r0 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x3c179ad8u : 0x2d9fc6b9u); // s111 add
r2 = __umulhi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x47359729u : 0x502138e2u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = __umulhi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r2, 2); // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x6c57e4e7u : 0x33dff776u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + ((((sel >> 30u) & 1u) != 0u) ? 0xe8212c0cu : 0x5db25b34u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = __umulhi(r0, r5); // s138 mulhi
r2 = r2 + r7 + ((((sel >> 10u) & 1u) != 0u) ? 0xd44ff710u : 0x218d4090u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + ((((sel >> 29u) & 1u) != 0u) ? 0xb98942fau : 0xf4b1a8deu); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + ((((sel >> 17u) & 1u) != 0u) ? 0x0d48ba42u : 0x2bef10f2u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + ((((sel >> 30u) & 1u) != 0u) ? 0xc98dea9cu : 0xdc5cc080u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0x6c752dcbu : 0x18197438u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + ((((sel >> 3u) & 1u) != 0u) ? 0x8e481727u : 0xf1c46574u); // s163 add
r0 = __umulhi(r0, r4); // s164 mulhi
r2 = r2 + r6 + ((((sel >> 20u) & 1u) != 0u) ? 0x550ab406u : 0xac578137u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xaebb5966u : 0xa33e6706u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r0, 8); // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5bb7550fu : 0xd94d55acu); // s184 add
r3 = r3 | r5; // s185 or
r6 = __umulhi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s188 shfl
r6 = r6 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x2a354e2du : 0x89e747feu); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = __umulhi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + ((((sel >> 7u) & 1u) != 0u) ? 0x10cfdc71u : 0xea03e8e7u); // s197 add
r7 = r7 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x66e148d3u : 0xa7ee0102u); // s198 add
r5 = r5 - r2; // s199 sub
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s200 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 8); // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x8558b619u : 0x8379a4deu); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = __umulhi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s209 shfl
r7 = r7 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0xf4049c4cu : 0xaa8cb14eu); // s210 add
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = __umulhi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s222 shfl
r5 = __umulhi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0x2a7fecb2u : 0x1d176220u); // s230 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + ((((sel >> 25u) & 1u) != 0u) ? 0xadce39f3u : 0x17dafb4du); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + ((((sel >> 29u) & 1u) != 0u) ? 0x0e7033b6u : 0xf2f77d26u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x7b2ff6b7u : 0xfed2da4eu); // s247 add
r0 = r0 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb5fad7b1u : 0x03b2891cu); // s248 add
r5 = __umulhi(r5, r4); // s249 mulhi
r5 = r5 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0xa7e71c2fu : 0x042cd6e3u); // s250 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 1); // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0xb83d78deu : 0x784a302bu); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
// Host-side launch wrappers. Declared in program.h, called from host.cu.
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments) {
if (nSegments == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nSegments + block - 1u) / block;
igneum_cache_fill<<<grid, block>>>(cache, nSegments);
return cudaGetLastError();
}
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems) {
if (nItems == 0u) return cudaErrorInvalidValue;
uint32_t block = 256u;
uint32_t grid = (nItems + block - 1u) / block;
igneum_build<<<grid, block>>>(ds, cache, nItems);
return cudaGetLastError();
}
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash<<<nonces / block, block>>>(ds, out, baseNonce, mask);
return cudaGetLastError();
}
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// OpenCL C twin of the Metal kernel for the same seed (see proto-opencl/README.md, WAVEFRONT.md and program.metal).
// Built from source at runtime by proto-opencl/host.c, which passes these defines:
// IGNEUM_GROUP work-group size of igneum_hash, a multiple of 32 (default 32: one work-group = one 32-lane unit)
// IGNEUM_EXCHANGE 0 = local-memory exchange with a barrier (any device, any wave width; the default)
// 1 = sub_group_shuffle_xor (cl_khr_subgroup_shuffle), only with IGNEUM_GROUP 32 and a sub-group size of exactly 32
// 2 = intel_sub_group_shuffle_xor (cl_intel_subgroups), same condition
// The verification unit is always 32 lanes. A 64-wide hardware wave (AMD GCN/CDNA, RDNA in wave64) runs two units;
// the exchange masks are 1, 2, 4, 8, 16, so every partner lane lies inside the lane's own aligned run of 32.
#ifndef IGNEUM_GROUP
#define IGNEUM_GROUP 32
#endif
#ifndef IGNEUM_EXCHANGE
#define IGNEUM_EXCHANGE 0
#endif
#ifdef __OPENCL_VERSION__
#define IGNEUM_KERNEL_HASH __kernel __attribute__((reqd_work_group_size(IGNEUM_GROUP, 1, 1)))
#define IGNEUM_LOCAL_WORDS(name, n) __local uint name[n]
#if IGNEUM_EXCHANGE == 1
#ifdef cl_khr_subgroups
#pragma OPENCL EXTENSION cl_khr_subgroups : enable
#endif
#ifdef cl_khr_subgroup_shuffle
#pragma OPENCL EXTENSION cl_khr_subgroup_shuffle : enable
#endif
#elif IGNEUM_EXCHANGE == 2
#pragma OPENCL EXTENSION cl_intel_subgroups : enable
#endif
#else
// Not an OpenCL compiler: proto-opencl/emu compiles this file as C++ and supplies the built-ins and these two macros.
#include "emu_opencl.h"
#endif
#if IGNEUM_EXCHANGE == 1
#define IGNEUM_SHFL_XOR(dst, a, m) dst = sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#elif IGNEUM_EXCHANGE == 2
#define IGNEUM_SHFL_XOR(dst, a, m) dst = intel_sub_group_shuffle_xor((a), (uint)(m))
#define IGNEUM_BCAST0(dst, a) dst = sub_group_broadcast((a), 0u)
#else
// Local-memory exchange. Two buffers of IGNEUM_GROUP words alternate (xk counts exchanges), so one barrier per
// exchange is enough: a lane can only overwrite buffer b at exchange k+2 after passing barrier k+1, and every lane
// reaches barrier k+1 only after its read of buffer b at exchange k. The partner lid ^ m stays inside the lane's
// aligned run of 32 because m < 32. Control flow is uniform, so every work-item reaches every barrier.
#define IGNEUM_SHFL_XOR(dst, a, m) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid ^ (uint)(m))]; xk += 1u; }
#define IGNEUM_BCAST0(dst, a) { xch[(xk & 1u) * IGNEUM_GROUP + lid] = (a); barrier(CLK_LOCAL_MEM_FENCE); dst = xch[(xk & 1u) * IGNEUM_GROUP + (lid & ~31u)]; xk += 1u; }
#endif
static inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
// n is a literal in 1..31 at every call site. OpenCL rotate() rotates left by n modulo 32.
static inline uint rotl_imm(uint x, uint n) { return rotate(x, n); }
// Right rotation by n modulo 32 as a left rotation by (32 - n) modulo 32; n == 0 gives x.
static inline uint rotr_var(uint x, uint n) { return rotate(x, (0u - n) & 31u); }
static inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
static inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
static inline void mh_chacha_block(const uint* x, uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
static inline void mh_cache_segment(__global uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
__global uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
static inline void mh_mixer(uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
static inline void mh_item(__global const uint* cache, uint t, uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
__global const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
static inline uint mh_word(__global const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// Memory-hard dataset (MEMHARD.md). One work-item per cache segment; one work-item per 64-byte dataset item.
// The same constants as memhard.h in this pack (one emitter, three dialects).
__kernel void igneum_cache_fill(__global uint* cache, uint nSegments) {
uint seg = (uint)get_global_id(0);
if (seg < nSegments) mh_cache_segment(cache, seg);
}
__kernel void igneum_build(__global uint* ds, __global const uint* cache, uint nItems) {
uint t = (uint)get_global_id(0);
if (t < nItems) {
uint s[16];
mh_item(cache, t, s);
__global uint* d = ds + ((ulong)t * 16u);
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}
}
// One hash per work-item. IGNEUM_GROUP is a multiple of 32; lane = lid & 31 and every exchange stays inside the
// lane's own aligned run of 32 work-items, exactly like simd_shuffle_xor inside a 32-wide Metal SIMD group and
// __shfl_xor_sync inside a CUDA warp. Control flow is uniform (no branches at all).
IGNEUM_KERNEL_HASH void igneum_hash(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ 0x67a9a7beu; x += 0x9e3779b9u; x = splitmix32(x); r0 = x ^ 0x1a155b25u; } // SEEDW[0], 0x9e3779b9u * 1u, SEEDW[1]
{ uint x = nonce ^ 0x1a155b25u; x += 0x3c6ef372u; x = splitmix32(x); r1 = x ^ 0xfddfb732u; } // SEEDW[1], 0x9e3779b9u * 2u, SEEDW[2]
{ uint x = nonce ^ 0xfddfb732u; x += 0xdaa66d2bu; x = splitmix32(x); r2 = x ^ 0x4b5af2e8u; } // SEEDW[2], 0x9e3779b9u * 3u, SEEDW[3]
{ uint x = nonce ^ 0x4b5af2e8u; x += 0x78dde6e4u; x = splitmix32(x); r3 = x ^ 0xc55caf33u; } // SEEDW[3], 0x9e3779b9u * 4u, SEEDW[4]
{ uint x = nonce ^ 0xc55caf33u; x += 0x1715609du; x = splitmix32(x); r4 = x ^ 0xa27c13b7u; } // SEEDW[4], 0x9e3779b9u * 5u, SEEDW[5]
{ uint x = nonce ^ 0xa27c13b7u; x += 0xb54cda56u; x = splitmix32(x); r5 = x ^ 0x06628a48u; } // SEEDW[5], 0x9e3779b9u * 6u, SEEDW[6]
{ uint x = nonce ^ 0x06628a48u; x += 0x5384540fu; x = splitmix32(x); r6 = x ^ 0x03852469u; } // SEEDW[6], 0x9e3779b9u * 7u, SEEDW[7]
{ uint x = nonce ^ 0x03852469u; x += 0xf1bbcdc8u; x = splitmix32(x); r7 = x ^ 0x67a9a7beu; } // SEEDW[7], 0x9e3779b9u * 8u, SEEDW[0]
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x8bc12da9u : 0x92199f99u); // s0 add
r0 = r0 + r7 + ((((sel >> 26u) & 1u) != 0u) ? 0x63079e5au : 0x8d72d3adu); // s1 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r6 = r6 ^ t_; } // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + ((((sel >> 31u) & 1u) != 0u) ? 0x5d4c7a60u : 0xb21b4babu); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + ((((sel >> 16u) & 1u) != 0u) ? 0xc88e2942u : 0x2fe0e98bu); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r6 = r6 ^ t_; } // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 4u); r2 = r2 ^ t_; } // s12 shfl
r1 = r1 + r5 + ((((sel >> 25u) & 1u) != 0u) ? 0xbc48c63eu : 0xbdf8f9a5u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r2 = r2 ^ t_; } // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x96e8f127u : 0x45c37cecu); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = mul_hi(r6, r0); // s28 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r2 = r2 ^ t_; } // s29 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r1 = r1 ^ t_; } // s30 shfl
r1 = r1 + r6 + ((((sel >> 1u) & 1u) != 0u) ? 0xb1cdb2abu : 0x37985632u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // s33 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r0 = r0 ^ t_; } // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x856e0180u : 0x804e777eu); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xe9bd0cc4u : 0x0b06c8a7u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = mul_hi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = mul_hi(r4, r3); // s44 mulhi
r6 = r6 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0xcdcb63f6u : 0xee822e17u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r4 = r4 ^ t_; } // s47 shfl
r6 = mul_hi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0xd4758987u : 0x3dfad1b6u); // s56 add
r4 = r4 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x0602d6beu : 0xfca75bc2u); // s57 add
r5 = mul_hi(r5, r6); // s58 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r2 = r2 ^ t_; } // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8596687au : 0xd71c02ffu); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 2u); r7 = r7 ^ t_; } // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0x08ac5733u : 0x3c6fe15du); // s72 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + ((((sel >> 1u) & 1u) != 0u) ? 0xc100b495u : 0x295d5faeu); // s77 add
r3 = mul_hi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x5cc59530u : 0x274a9221u); // s81 add
r7 = r7 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x141479ecu : 0xc8651f8eu); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r2 = r2 ^ t_; } // s85 shfl
r3 = r3 ^ r2; // s86 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x883c0c92u : 0x53f915c2u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + ((((sel >> 31u) & 1u) != 0u) ? 0x3cc5bd20u : 0xe2be00a5u); // s91 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r7 = r7 ^ t_; } // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0xbfd646cbu : 0x423fd9c9u); // s101 add
r7 = r7 + r6 + ((((sel >> 11u) & 1u) != 0u) ? 0x19b74a43u : 0x8d3c011du); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + ((((sel >> 15u) & 1u) != 0u) ? 0x7dcb7e18u : 0x8ce14721u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = mul_hi(r2, r0); // s109 mulhi
r1 = mul_hi(r1, r0); // s110 mulhi
r0 = r0 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x3c179ad8u : 0x2d9fc6b9u); // s111 add
r2 = mul_hi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x47359729u : 0x502138e2u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = mul_hi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 2u); r4 = r4 ^ t_; } // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r7 = r7 ^ t_; } // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x6c57e4e7u : 0x33dff776u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + ((((sel >> 30u) & 1u) != 0u) ? 0xe8212c0cu : 0x5db25b34u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = mul_hi(r0, r5); // s138 mulhi
r2 = r2 + r7 + ((((sel >> 10u) & 1u) != 0u) ? 0xd44ff710u : 0x218d4090u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + ((((sel >> 29u) & 1u) != 0u) ? 0xb98942fau : 0xf4b1a8deu); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + ((((sel >> 17u) & 1u) != 0u) ? 0x0d48ba42u : 0x2bef10f2u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + ((((sel >> 30u) & 1u) != 0u) ? 0xc98dea9cu : 0xdc5cc080u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0x6c752dcbu : 0x18197438u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + ((((sel >> 3u) & 1u) != 0u) ? 0x8e481727u : 0xf1c46574u); // s163 add
r0 = mul_hi(r0, r4); // s164 mulhi
r2 = r2 + r6 + ((((sel >> 20u) & 1u) != 0u) ? 0x550ab406u : 0xac578137u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xaebb5966u : 0xa33e6706u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 8u); r7 = r7 ^ t_; } // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5bb7550fu : 0xd94d55acu); // s184 add
r3 = r3 | r5; // s185 or
r6 = mul_hi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s188 shfl
r6 = r6 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x2a354e2du : 0x89e747feu); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = mul_hi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r4 = r4 ^ t_; } // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + ((((sel >> 7u) & 1u) != 0u) ? 0x10cfdc71u : 0xea03e8e7u); // s197 add
r7 = r7 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x66e148d3u : 0xa7ee0102u); // s198 add
r5 = r5 - r2; // s199 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r5 = r5 ^ t_; } // s200 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 8u); r7 = r7 ^ t_; } // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x8558b619u : 0x8379a4deu); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = mul_hi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s209 shfl
r7 = r7 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0xf4049c4cu : 0xaa8cb14eu); // s210 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r3 = r3 ^ t_; } // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = mul_hi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r5 = r5 ^ t_; } // s222 shfl
r5 = mul_hi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0x2a7fecb2u : 0x1d176220u); // s230 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r1 = r1 ^ t_; } // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + ((((sel >> 25u) & 1u) != 0u) ? 0xadce39f3u : 0x17dafb4du); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + ((((sel >> 29u) & 1u) != 0u) ? 0x0e7033b6u : 0xf2f77d26u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x7b2ff6b7u : 0xfed2da4eu); // s247 add
r0 = r0 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb5fad7b1u : 0x03b2891cu); // s248 add
r5 = mul_hi(r5, r4); // s249 mulhi
r5 = r5 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0xa7e71c2fu : 0x042cd6e3u); // s250 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0xb83d78deu : 0x784a302bu); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}
#if IGNEUM_EXCHANGE != 0
// Reports the sub-group size this device uses for a work-group of IGNEUM_GROUP items. host.c runs it only when the
// per-kernel query (clGetKernelSubGroupInfoKHR on igneum_hash) is unavailable; that query is preferred because a
// compiler may pick a different wave width per kernel (RDNA: wave32 or wave64). See WAVEFRONT.md.
IGNEUM_KERNEL_HASH void igneum_probe_subgroup(__global uint* out) {
if (get_local_id(0) == 0u) { out[0] = get_sub_group_size(); out[1] = get_num_sub_groups(); }
}
#endif
// Header-bound variant (bind.rs): the init words come from initw, not SEEDW. Same body as igneum_hash.
IGNEUM_KERNEL_HASH void igneum_hash_bound(__global const uint* ds, __global ulong* out, uint baseNonce, uint mask, __global const uint* initw) {
uint gid = (uint)get_global_id(0);
uint lid = (uint)get_local_id(0);
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
uint iw0 = initw[0], iw1 = initw[1], iw2 = initw[2], iw3 = initw[3], iw4 = initw[4], iw5 = initw[5], iw6 = initw[6], iw7 = initw[7];
#if IGNEUM_EXCHANGE == 0
IGNEUM_LOCAL_WORDS(xch, 2 * IGNEUM_GROUP);
uint xk = 0u;
#else
(void)lid;
#endif
{ uint x = nonce ^ iw0; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw1; }
{ uint x = nonce ^ iw1; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw2; }
{ uint x = nonce ^ iw2; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw3; }
{ uint x = nonce ^ iw3; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw4; }
{ uint x = nonce ^ iw4; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw5; }
{ uint x = nonce ^ iw5; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw6; }
{ uint x = nonce ^ iw6; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw7; }
{ uint x = nonce ^ iw7; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw0; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r1 = r1 ^ t_; } // 6 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r7 = r7 ^ t_; } // 7 shfl
r1 = mul_hi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = mul_hi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r7 = r7 ^ t_; } // 18 shfl
r5 = r5 * r0; // 19 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // 20 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 16u); r2 = r2 ^ t_; } // 21 shfl
r6 = mul_hi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 2u); r7 = r7 ^ t_; } // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = mul_hi(r0, r5); // 35 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r5 = r5 ^ t_; } // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 4u); r1 = r1 ^ t_; } // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = mul_hi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x8bc12da9u : 0x92199f99u); // s0 add
r0 = r0 + r7 + ((((sel >> 26u) & 1u) != 0u) ? 0x63079e5au : 0x8d72d3adu); // s1 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 2u); r6 = r6 ^ t_; } // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + ((((sel >> 31u) & 1u) != 0u) ? 0x5d4c7a60u : 0xb21b4babu); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + ((((sel >> 16u) & 1u) != 0u) ? 0xc88e2942u : 0x2fe0e98bu); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 4u); r6 = r6 ^ t_; } // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 4u); r2 = r2 ^ t_; } // s12 shfl
r1 = r1 + r5 + ((((sel >> 25u) & 1u) != 0u) ? 0xbc48c63eu : 0xbdf8f9a5u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 8u); r2 = r2 ^ t_; } // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x96e8f127u : 0x45c37cecu); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = mul_hi(r6, r0); // s28 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r2 = r2 ^ t_; } // s29 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r1 = r1 ^ t_; } // s30 shfl
r1 = r1 + r6 + ((((sel >> 1u) & 1u) != 0u) ? 0xb1cdb2abu : 0x37985632u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r4, 2u); r3 = r3 ^ t_; } // s33 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 4u); r0 = r0 ^ t_; } // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x856e0180u : 0x804e777eu); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xe9bd0cc4u : 0x0b06c8a7u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = mul_hi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = mul_hi(r4, r3); // s44 mulhi
r6 = r6 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0xcdcb63f6u : 0xee822e17u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r3, 8u); r4 = r4 ^ t_; } // s47 shfl
r6 = mul_hi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0xd4758987u : 0x3dfad1b6u); // s56 add
r4 = r4 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x0602d6beu : 0xfca75bc2u); // s57 add
r5 = mul_hi(r5, r6); // s58 mulhi
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r2 = r2 ^ t_; } // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8596687au : 0xd71c02ffu); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 2u); r7 = r7 ^ t_; } // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0x08ac5733u : 0x3c6fe15du); // s72 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r3 = r3 ^ t_; } // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + ((((sel >> 1u) & 1u) != 0u) ? 0xc100b495u : 0x295d5faeu); // s77 add
r3 = mul_hi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x5cc59530u : 0x274a9221u); // s81 add
r7 = r7 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x141479ecu : 0xc8651f8eu); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r2 = r2 ^ t_; } // s85 shfl
r3 = r3 ^ r2; // s86 xor
{ uint t_; IGNEUM_SHFL_XOR(t_, r7, 2u); r5 = r5 ^ t_; } // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x883c0c92u : 0x53f915c2u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + ((((sel >> 31u) & 1u) != 0u) ? 0x3cc5bd20u : 0xe2be00a5u); // s91 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 1u); r7 = r7 ^ t_; } // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0xbfd646cbu : 0x423fd9c9u); // s101 add
r7 = r7 + r6 + ((((sel >> 11u) & 1u) != 0u) ? 0x19b74a43u : 0x8d3c011du); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + ((((sel >> 15u) & 1u) != 0u) ? 0x7dcb7e18u : 0x8ce14721u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = mul_hi(r2, r0); // s109 mulhi
r1 = mul_hi(r1, r0); // s110 mulhi
r0 = r0 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x3c179ad8u : 0x2d9fc6b9u); // s111 add
r2 = mul_hi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x47359729u : 0x502138e2u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = mul_hi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 2u); r4 = r4 ^ t_; } // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r7 = r7 ^ t_; } // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x6c57e4e7u : 0x33dff776u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + ((((sel >> 30u) & 1u) != 0u) ? 0xe8212c0cu : 0x5db25b34u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = mul_hi(r0, r5); // s138 mulhi
r2 = r2 + r7 + ((((sel >> 10u) & 1u) != 0u) ? 0xd44ff710u : 0x218d4090u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r6, 1u); r3 = r3 ^ t_; } // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + ((((sel >> 29u) & 1u) != 0u) ? 0xb98942fau : 0xf4b1a8deu); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + ((((sel >> 17u) & 1u) != 0u) ? 0x0d48ba42u : 0x2bef10f2u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + ((((sel >> 30u) & 1u) != 0u) ? 0xc98dea9cu : 0xdc5cc080u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0x6c752dcbu : 0x18197438u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + ((((sel >> 3u) & 1u) != 0u) ? 0x8e481727u : 0xf1c46574u); // s163 add
r0 = mul_hi(r0, r4); // s164 mulhi
r2 = r2 + r6 + ((((sel >> 20u) & 1u) != 0u) ? 0x550ab406u : 0xac578137u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xaebb5966u : 0xa33e6706u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 8u); r7 = r7 ^ t_; } // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5bb7550fu : 0xd94d55acu); // s184 add
r3 = r3 | r5; // s185 or
r6 = mul_hi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r7 = r7 ^ t_; } // s188 shfl
r6 = r6 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x2a354e2du : 0x89e747feu); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = mul_hi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
{ uint t_; IGNEUM_SHFL_XOR(t_, r5, 16u); r4 = r4 ^ t_; } // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + ((((sel >> 7u) & 1u) != 0u) ? 0x10cfdc71u : 0xea03e8e7u); // s197 add
r7 = r7 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x66e148d3u : 0xa7ee0102u); // s198 add
r5 = r5 - r2; // s199 sub
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 2u); r5 = r5 ^ t_; } // s200 shfl
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 8u); r7 = r7 ^ t_; } // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x8558b619u : 0x8379a4deu); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = mul_hi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
{ uint t_; IGNEUM_SHFL_XOR(t_, r0, 4u); r2 = r2 ^ t_; } // s209 shfl
r7 = r7 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0xf4049c4cu : 0xaa8cb14eu); // s210 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 16u); r7 = r7 ^ t_; } // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 16u); r3 = r3 ^ t_; } // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = mul_hi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 8u); r5 = r5 ^ t_; } // s222 shfl
r5 = mul_hi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0x2a7fecb2u : 0x1d176220u); // s230 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r2, 4u); r1 = r1 ^ t_; } // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + ((((sel >> 25u) & 1u) != 0u) ? 0xadce39f3u : 0x17dafb4du); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + ((((sel >> 29u) & 1u) != 0u) ? 0x0e7033b6u : 0xf2f77d26u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x7b2ff6b7u : 0xfed2da4eu); // s247 add
r0 = r0 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb5fad7b1u : 0x03b2891cu); // s248 add
r5 = mul_hi(r5, r4); // s249 mulhi
r5 = r5 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0xa7e71c2fu : 0x042cd6e3u); // s250 add
{ uint t_; IGNEUM_SHFL_XOR(t_, r1, 1u); r6 = r6 ^ t_; } // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0xb83d78deu : 0x784a302bu); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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proto-cuda/packs-ca4/mx8_sh256x27/kernel_bound.cu Normal file
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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Header-bound twin of igneum_hash in kernel.cu: the init words come from a kernel argument, not SEEDW.
// Host declarations (also in program_bound.h if present):
// struct IgneumInitWords { uint32_t w[8]; };
// cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
// IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps);
// cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#include <cuda_runtime.h>
#include <cstdint>
#include "program.h"
struct IgneumInitWords { uint32_t w[8]; };
__device__ __forceinline__ uint32_t splitmix32(uint32_t x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
__device__ __forceinline__ uint32_t rotl_imm(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); }
__device__ __forceinline__ uint32_t rotr_var(uint32_t x, uint32_t n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
__global__ void igneum_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask, IgneumInitWords iw) {
uint32_t gid = blockIdx.x * blockDim.x + threadIdx.x;
uint32_t nonce = baseNonce + gid;
uint32_t r0, r1, r2, r3, r4, r5, r6, r7;
{ uint32_t x = nonce ^ iw.w[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ iw.w[1]; }
{ uint32_t x = nonce ^ iw.w[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ iw.w[2]; }
{ uint32_t x = nonce ^ iw.w[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ iw.w[3]; }
{ uint32_t x = nonce ^ iw.w[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ iw.w[4]; }
{ uint32_t x = nonce ^ iw.w[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ iw.w[5]; }
{ uint32_t x = nonce ^ iw.w[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ iw.w[6]; }
{ uint32_t x = nonce ^ iw.w[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ iw.w[7]; }
{ uint32_t x = nonce ^ iw.w[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ iw.w[0]; }
for (uint32_t it = 0u; it < 8u; ++it) {
uint32_t sel = r0;
r2 = r3 * r4 + r2; // 0 mad
r2 = r1 * r1 + r2; // 1 mad
r2 = r3 * r2 + r2; // 2 mad
r3 = r3 ^ r5; // 3 xor
r7 = r7 ^ ds[r2 & mask]; // 4 load
r5 = r5 ^ ds[r7 & mask]; // 5 load
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // 6 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // 7 shfl
r1 = __umulhi(r1, r5); // 8 mulhi
r6 = rotr_var(r6, r3); // 9 rotr
r3 = r3 | r4; // 10 or
r4 = r4 ^ ds[r3 & mask]; // 11 load
r0 = __umulhi(r0, r4); // 12 mulhi
r5 = r5 + r1 + ((((sel >> 30u) & 1u) != 0u) ? 0xd3177981u : 0xc7934706u); // 13 add
r0 = r0 ^ ds[r4 & mask]; // 14 load
r2 = r2 - r4; // 15 sub
r2 = r2 ^ ds[r0 & mask]; // 16 load
r7 = r7 ^ ds[r2 & mask]; // 17 load
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // 18 shfl
r5 = r5 * r0; // 19 mul
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // 20 shfl
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 16); // 21 shfl
r6 = __umulhi(r6, r2); // 22 mulhi
r6 = r6 ^ ds[r1 & mask]; // 23 load
r5 = r5 * r0; // 24 mul
r5 = rotl_imm(r5, 19u); // 25 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r6, 2); // 26 shfl
r0 = r0 ^ r5; // 27 xor
r0 = r0 ^ r4; // 28 xor
r3 = r3 - r0; // 29 sub
r5 = r5 * r1; // 30 mul
r7 = r7 ^ ds[r2 & mask]; // 31 load
r1 = r1 ^ ds[r0 & mask]; // 32 load
r5 = r5 ^ r6; // 33 xor
r5 = r5 ^ ds[r1 & mask]; // 34 load
r0 = __umulhi(r0, r5); // 35 mulhi
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // 36 shfl
r7 = r7 ^ ds[r0 & mask]; // 37 load
r3 = r3 + r1 + ((((sel >> 27u) & 1u) != 0u) ? 0x230c005cu : 0x75ba2fadu); // 38 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r5, 4); // 39 shfl
r2 = r2 ^ r5; // 40 xor
r3 = r6 * r3 + r3; // 41 mad
r6 = r6 - r7; // 42 sub
r7 = r7 ^ r0; // 43 xor
r1 = r1 ^ ds[r7 & mask]; // 44 load
r2 = r2 * r3; // 45 mul
r1 = __umulhi(r1, r5); // 46 mulhi
r4 = r4 - r3; // 47 sub
r2 = rotr_var(r2, r6); // 48 rotr
r3 = r3 ^ ds[r5 & mask]; // 49 load
r1 = r1 + r5 + ((((sel >> 7u) & 1u) != 0u) ? 0x1907970cu : 0x81b8bc2cu); // 50 add
r0 = r0 * r2; // 51 mul
r0 = r0 + r2 + ((((sel >> 6u) & 1u) != 0u) ? 0x699fd448u : 0x4f92b968u); // 52 add
r1 = r1 + r0 + ((((sel >> 12u) & 1u) != 0u) ? 0x77b1520du : 0x2bb965afu); // 53 add
r7 = rotl_imm(r7, 14u); // 54 rotl
r3 = r3 + r7 + ((((sel >> 1u) & 1u) != 0u) ? 0xa54c55a0u : 0x7b0fe07au); // 55 add
r6 = r6 ^ ds[r7 & mask]; // 56 load
r1 = rotr_var(r1, r5); // 57 rotr
r5 = r5 ^ ds[r4 & mask]; // 58 load
r6 = r6 ^ ds[r2 & mask]; // 59 load
r3 = r5 * r0 + r3; // 60 mad
r5 = r5 + r7 + ((((sel >> 31u) & 1u) != 0u) ? 0xad7493e7u : 0xaf9dd72du); // 61 add
r4 = r4 + r6 + ((((sel >> 27u) & 1u) != 0u) ? 0x1e07c3d9u : 0x89841d87u); // 62 add
r5 = rotl_imm(r5, 19u); // 63 rotl
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint32_t sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x8bc12da9u : 0x92199f99u); // s0 add
r0 = r0 + r7 + ((((sel >> 26u) & 1u) != 0u) ? 0x63079e5au : 0x8d72d3adu); // s1 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r3, 2); // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + ((((sel >> 31u) & 1u) != 0u) ? 0x5d4c7a60u : 0xb21b4babu); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + ((((sel >> 16u) & 1u) != 0u) ? 0xc88e2942u : 0x2fe0e98bu); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 4); // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r6, 4); // s12 shfl
r1 = r1 + r5 + ((((sel >> 25u) & 1u) != 0u) ? 0xbc48c63eu : 0xbdf8f9a5u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 8); // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + ((((sel >> 1u) & 1u) != 0u) ? 0x96e8f127u : 0x45c37cecu); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = __umulhi(r6, r0); // s28 mulhi
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // s29 shfl
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // s30 shfl
r1 = r1 + r6 + ((((sel >> 1u) & 1u) != 0u) ? 0xb1cdb2abu : 0x37985632u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r4, 2); // s33 shfl
r0 = r0 ^ __shfl_xor_sync(0xffffffffu, r3, 4); // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x856e0180u : 0x804e777eu); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + ((((sel >> 2u) & 1u) != 0u) ? 0xe9bd0cc4u : 0x0b06c8a7u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = __umulhi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = __umulhi(r4, r3); // s44 mulhi
r6 = r6 + r7 + ((((sel >> 12u) & 1u) != 0u) ? 0xcdcb63f6u : 0xee822e17u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r3, 8); // s47 shfl
r6 = __umulhi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0xd4758987u : 0x3dfad1b6u); // s56 add
r4 = r4 + r1 + ((((sel >> 0u) & 1u) != 0u) ? 0x0602d6beu : 0xfca75bc2u); // s57 add
r5 = __umulhi(r5, r6); // s58 mulhi
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + ((((sel >> 6u) & 1u) != 0u) ? 0x8596687au : 0xd71c02ffu); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r5, 2); // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0x08ac5733u : 0x3c6fe15du); // s72 add
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + ((((sel >> 1u) & 1u) != 0u) ? 0xc100b495u : 0x295d5faeu); // s77 add
r3 = __umulhi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + ((((sel >> 15u) & 1u) != 0u) ? 0x5cc59530u : 0x274a9221u); // s81 add
r7 = r7 + r3 + ((((sel >> 5u) & 1u) != 0u) ? 0x141479ecu : 0xc8651f8eu); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s85 shfl
r3 = r3 ^ r2; // s86 xor
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r7, 2); // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + ((((sel >> 18u) & 1u) != 0u) ? 0x883c0c92u : 0x53f915c2u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + ((((sel >> 31u) & 1u) != 0u) ? 0x3cc5bd20u : 0xe2be00a5u); // s91 add
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r2, 1); // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + ((((sel >> 17u) & 1u) != 0u) ? 0xbfd646cbu : 0x423fd9c9u); // s101 add
r7 = r7 + r6 + ((((sel >> 11u) & 1u) != 0u) ? 0x19b74a43u : 0x8d3c011du); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + ((((sel >> 15u) & 1u) != 0u) ? 0x7dcb7e18u : 0x8ce14721u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = __umulhi(r2, r0); // s109 mulhi
r1 = __umulhi(r1, r0); // s110 mulhi
r0 = r0 + r2 + ((((sel >> 28u) & 1u) != 0u) ? 0x3c179ad8u : 0x2d9fc6b9u); // s111 add
r2 = __umulhi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + ((((sel >> 22u) & 1u) != 0u) ? 0x47359729u : 0x502138e2u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = __umulhi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r2, 2); // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x6c57e4e7u : 0x33dff776u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + ((((sel >> 30u) & 1u) != 0u) ? 0xe8212c0cu : 0x5db25b34u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = __umulhi(r0, r5); // s138 mulhi
r2 = r2 + r7 + ((((sel >> 10u) & 1u) != 0u) ? 0xd44ff710u : 0x218d4090u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r6, 1); // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + ((((sel >> 29u) & 1u) != 0u) ? 0xb98942fau : 0xf4b1a8deu); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + ((((sel >> 17u) & 1u) != 0u) ? 0x0d48ba42u : 0x2bef10f2u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + ((((sel >> 30u) & 1u) != 0u) ? 0xc98dea9cu : 0xdc5cc080u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0x6c752dcbu : 0x18197438u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + ((((sel >> 3u) & 1u) != 0u) ? 0x8e481727u : 0xf1c46574u); // s163 add
r0 = __umulhi(r0, r4); // s164 mulhi
r2 = r2 + r6 + ((((sel >> 20u) & 1u) != 0u) ? 0x550ab406u : 0xac578137u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + ((((sel >> 14u) & 1u) != 0u) ? 0xaebb5966u : 0xa33e6706u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r0, 8); // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + ((((sel >> 21u) & 1u) != 0u) ? 0x5bb7550fu : 0xd94d55acu); // s184 add
r3 = r3 | r5; // s185 or
r6 = __umulhi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s188 shfl
r6 = r6 + r5 + ((((sel >> 6u) & 1u) != 0u) ? 0x2a354e2du : 0x89e747feu); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = __umulhi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
r4 = r4 ^ __shfl_xor_sync(0xffffffffu, r5, 16); // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + ((((sel >> 7u) & 1u) != 0u) ? 0x10cfdc71u : 0xea03e8e7u); // s197 add
r7 = r7 + r5 + ((((sel >> 15u) & 1u) != 0u) ? 0x66e148d3u : 0xa7ee0102u); // s198 add
r5 = r5 - r2; // s199 sub
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r1, 2); // s200 shfl
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 8); // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + ((((sel >> 10u) & 1u) != 0u) ? 0x8558b619u : 0x8379a4deu); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = __umulhi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
r2 = r2 ^ __shfl_xor_sync(0xffffffffu, r0, 4); // s209 shfl
r7 = r7 + r0 + ((((sel >> 11u) & 1u) != 0u) ? 0xf4049c4cu : 0xaa8cb14eu); // s210 add
r7 = r7 ^ __shfl_xor_sync(0xffffffffu, r1, 16); // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
r3 = r3 ^ __shfl_xor_sync(0xffffffffu, r2, 16); // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = __umulhi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
r5 = r5 ^ __shfl_xor_sync(0xffffffffu, r2, 8); // s222 shfl
r5 = __umulhi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0x2a7fecb2u : 0x1d176220u); // s230 add
r1 = r1 ^ __shfl_xor_sync(0xffffffffu, r2, 4); // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + ((((sel >> 25u) & 1u) != 0u) ? 0xadce39f3u : 0x17dafb4du); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + ((((sel >> 29u) & 1u) != 0u) ? 0x0e7033b6u : 0xf2f77d26u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + ((((sel >> 31u) & 1u) != 0u) ? 0x7b2ff6b7u : 0xfed2da4eu); // s247 add
r0 = r0 + r7 + ((((sel >> 0u) & 1u) != 0u) ? 0xb5fad7b1u : 0x03b2891cu); // s248 add
r5 = __umulhi(r5, r4); // s249 mulhi
r5 = r5 + r2 + ((((sel >> 11u) & 1u) != 0u) ? 0xa7e71c2fu : 0x042cd6e3u); // s250 add
r6 = r6 ^ __shfl_xor_sync(0xffffffffu, r1, 1); // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + ((((sel >> 16u) & 1u) != 0u) ? 0xb83d78deu : 0x784a302bu); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint32_t lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint32_t hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((uint64_t)hi << 32) | (uint64_t)lo;
}
cudaError_t igneum_launch_hash_bound(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
IgneumInitWords iw, uint32_t nonces, uint32_t blockWarps) {
if (blockWarps == 0u || blockWarps > 32u) return cudaErrorInvalidValue;
uint32_t block = 32u * blockWarps;
if (nonces == 0u || (nonces % block) != 0u) return cudaErrorInvalidValue;
igneum_hash_bound<<<nonces / block, block>>>(ds, out, baseNonce, mask, iw);
return cudaGetLastError();
}
cudaError_t igneum_hash_bound_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps) {
cudaFuncAttributes attr;
cudaError_t e = cudaFuncGetAttributes(&attr, igneum_hash_bound);
if (e != cudaSuccess) return e;
*numRegs = attr.numRegs;
return cudaOccupancyMaxActiveBlocksPerMultiprocessor(blocksPerSM, igneum_hash_bound, (int)(32u * blockWarps), 0);
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Memory-hard dataset core, the same text that the Mac's Metal kernels and CPU verifier were checked against.
// Included by kernel.cu (device), host.cu (host reference) and proto-opencl/host.c (C99 host reference).
// See proto-metal/MEMHARD.md for the construction. kernel.cl carries the same text in OpenCL C.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#if defined(__CUDACC__)
#define IGNEUM_HD __host__ __device__ __forceinline__
#elif defined(_MSC_VER) && !defined(__cplusplus)
#define IGNEUM_HD static __inline
#else
#define IGNEUM_HD static inline
#endif
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
IGNEUM_HD uint32_t mh_rotl(uint32_t x, uint32_t n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
IGNEUM_HD void mh_chacha_block(const uint32_t* x, uint32_t* y) {
for (uint32_t i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint32_t r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint32_t i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
IGNEUM_HD void mh_cache_segment(uint32_t* cache, uint32_t seg) {
uint32_t prev[16]; uint32_t x[16]; uint32_t y[16];
for (uint32_t i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint32_t j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
uint32_t* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
IGNEUM_HD void mh_mixer(uint32_t* s, uint32_t rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
IGNEUM_HD void mh_item(const uint32_t* cache, uint32_t t, uint32_t* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint32_t r = 0u; r < 8u; ++r) {
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
const uint32_t* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint32_t i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint32_t j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
IGNEUM_HD uint32_t mh_word(const uint32_t* cache, uint32_t w) { uint32_t s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }

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#include <metal_stdlib>
using namespace metal;
// Memory-hard dataset core (MEMHARD.md). Cache: 2^26 words in 2^16 segments of 64 chained ChaCha12 lines.
// Item: 8 rounds of 8 x seed-parameterised mixer + one 64-byte cache read, then 8 x final mixer (class v3, mixer multiplier 8,
// docs/plans/mixer-x4.md: the round key of application j of round r is 0x9E3779B9 * (r * m + j + 1)). All parameters are literals.
#define MH_CACHE_LINE_MASK 0x003fffffu
#define MH_SEGMENT_LINES 64u
#define MH_QR(a, b, c, d, r1, r2, r3, r4) { a += b; d ^= a; d = mh_rotl(d, r1); c += d; b ^= c; b = mh_rotl(b, r2); a += b; d ^= a; d = mh_rotl(d, r3); c += d; b ^= c; b = mh_rotl(b, r4); }
inline uint mh_rotl(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31 at every call site
// y = ChaCha12 core(x) + x
inline void mh_chacha_block(const thread uint* x, thread uint* y) {
for (uint i = 0u; i < 16u; ++i) y[i] = x[i];
for (uint r = 0u; r < 6u; ++r) {
MH_QR(y[0], y[4], y[8], y[12], 16u, 12u, 8u, 7u) MH_QR(y[1], y[5], y[9], y[13], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[6], y[10], y[14], 16u, 12u, 8u, 7u) MH_QR(y[3], y[7], y[11], y[15], 16u, 12u, 8u, 7u)
MH_QR(y[0], y[5], y[10], y[15], 16u, 12u, 8u, 7u) MH_QR(y[1], y[6], y[11], y[12], 16u, 12u, 8u, 7u)
MH_QR(y[2], y[7], y[8], y[13], 16u, 12u, 8u, 7u) MH_QR(y[3], y[4], y[9], y[14], 16u, 12u, 8u, 7u)
}
for (uint i = 0u; i < 16u; ++i) y[i] += x[i];
}
// One cache segment: 64 chained lines written at cache[seg * 1024]. in_j = prev ^ (sigma || K || seg || j || tag), prev_0 = 0.
inline void mh_cache_segment(device uint* cache, uint seg) {
uint prev[16]; uint x[16]; uint y[16];
for (uint i = 0u; i < 16u; ++i) prev[i] = 0u;
for (uint j = 0u; j < MH_SEGMENT_LINES; ++j) {
x[0] = 0x61707865u ^ prev[0]; x[1] = 0x3320646eu ^ prev[1]; x[2] = 0x79622d32u ^ prev[2]; x[3] = 0x6b206574u ^ prev[3];
x[4] = 0x3067619fu ^ prev[4];
x[5] = 0x3c269176u ^ prev[5];
x[6] = 0x84a03b03u ^ prev[6];
x[7] = 0xf8c63294u ^ prev[7];
x[8] = 0xff977c5bu ^ prev[8];
x[9] = 0xe60def3eu ^ prev[9];
x[10] = 0x63630141u ^ prev[10];
x[11] = 0xb8fbcb58u ^ prev[11];
x[12] = seg ^ prev[12]; x[13] = j ^ prev[13]; x[14] = 0x49676e65u ^ prev[14]; x[15] = 0x756d4d48u ^ prev[15];
mh_chacha_block(x, y);
device uint* line = cache + ((seg * MH_SEGMENT_LINES + j) * 16u);
for (uint i = 0u; i < 16u; ++i) { line[i] = y[i]; prev[i] = y[i]; }
}
}
// M_r: per word (s ^ (RC + rk)) * MUL, then a column round and a diagonal round with the seed-drawn rotations.
inline void mh_mixer(thread uint* s, uint rk) {
s[0] = (s[0] ^ (0xbab68293u + rk)) * 0x42146205u;
s[1] = (s[1] ^ (0xcc162340u + rk)) * 0x52cbe0fbu;
s[2] = (s[2] ^ (0x6ce151ccu + rk)) * 0x7ecf4a03u;
s[3] = (s[3] ^ (0xe62b8997u + rk)) * 0x6728907fu;
s[4] = (s[4] ^ (0xc9c80297u + rk)) * 0xd81d9751u;
s[5] = (s[5] ^ (0xf74a1654u + rk)) * 0x132952c3u;
s[6] = (s[6] ^ (0x3d704af5u + rk)) * 0xf60de277u;
s[7] = (s[7] ^ (0x3cf522b7u + rk)) * 0x05358035u;
s[8] = (s[8] ^ (0x2b9cac04u + rk)) * 0xbaf6499du;
s[9] = (s[9] ^ (0xa880ac10u + rk)) * 0xe4db9667u;
s[10] = (s[10] ^ (0x13e5dd1du + rk)) * 0x3e98f45du;
s[11] = (s[11] ^ (0x6fc3e233u + rk)) * 0xd0004eddu;
s[12] = (s[12] ^ (0x2d83eeacu + rk)) * 0x2691630du;
s[13] = (s[13] ^ (0x9006e8bfu + rk)) * 0x9beb3bcfu;
s[14] = (s[14] ^ (0x2c4b5362u + rk)) * 0xab310379u;
s[15] = (s[15] ^ (0x31b49ee2u + rk)) * 0x99cfb423u;
MH_QR(s[0], s[4], s[8], s[12], 20u, 20u, 19u, 4u) MH_QR(s[1], s[5], s[9], s[13], 20u, 20u, 19u, 4u)
MH_QR(s[2], s[6], s[10], s[14], 20u, 20u, 19u, 4u) MH_QR(s[3], s[7], s[11], s[15], 20u, 20u, 19u, 4u)
MH_QR(s[0], s[5], s[10], s[15], 26u, 3u, 3u, 27u) MH_QR(s[1], s[6], s[11], s[12], 26u, 3u, 3u, 27u)
MH_QR(s[2], s[7], s[8], s[13], 26u, 3u, 3u, 27u) MH_QR(s[3], s[4], s[9], s[14], 26u, 3u, 3u, 27u)
}
// Item t: 16 words. s = (K, t * MUL[i] + RC[i]); 8 rounds of 8 x mixer + cache line s[0] & mask; 8 x final mixer.
inline void mh_item(device const uint* cache, uint t, thread uint* s) {
s[0] = 0x3067619fu;
s[1] = 0x3c269176u;
s[2] = 0x84a03b03u;
s[3] = 0xf8c63294u;
s[4] = 0xff977c5bu;
s[5] = 0xe60def3eu;
s[6] = 0x63630141u;
s[7] = 0xb8fbcb58u;
s[8] = t * 0x42146205u + 0xbab68293u;
s[9] = t * 0x52cbe0fbu + 0xcc162340u;
s[10] = t * 0x7ecf4a03u + 0x6ce151ccu;
s[11] = t * 0x6728907fu + 0xe62b8997u;
s[12] = t * 0xd81d9751u + 0xc9c80297u;
s[13] = t * 0x132952c3u + 0xf74a1654u;
s[14] = t * 0xf60de277u + 0x3d704af5u;
s[15] = t * 0x05358035u + 0x3cf522b7u;
for (uint r = 0u; r < 8u; ++r) {
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (r * 8u + j + 1u));
device const uint* line = cache + ((s[0] & MH_CACHE_LINE_MASK) * 16u);
for (uint i = 0u; i < 16u; ++i) s[i] ^= line[i];
}
for (uint j = 0u; j < 8u; ++j) mh_mixer(s, 0x9E3779B9u * (64u + j + 1u));
}
// dataset[w] without the dataset: derive item w >> 4 and take word w & 15.
inline uint mh_word(device const uint* cache, uint w) { uint s[16]; mh_item(cache, w >> 4u, s); return s[w & 15u]; }
// One thread per segment (2^16 threads).
kernel void igneum_cache_fill(device uint* cache [[buffer(0)]], uint gid [[thread_position_in_grid]]) {
mh_cache_segment(cache, gid);
}
// One thread per 64-byte item (dataset words / 16 threads).
kernel void igneum_build(device const uint* cache [[buffer(0)]], device uint* dataset [[buffer(1)]],
uint gid [[thread_position_in_grid]]) {
uint s[16];
mh_item(cache, gid, s);
device uint* d = dataset + gid * 16u;
for (uint i = 0u; i < 16u; ++i) d[i] = s[i];
}

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// Generated by igneum-pow export (generator v2) for seed "igneum-genesis". Do not edit by hand.
// Program metadata for host.cu plus the launch wrappers defined in kernel.cu.
// Also included by proto-opencl/host.c (C99), which defines IGNEUM_NO_CUDA first and reads only the macros.
#pragma once
#ifdef __cplusplus
#include <cstdint>
#else
#include <stdint.h>
#endif
#ifndef IGNEUM_NO_CUDA
#include <cuda_runtime.h>
#endif
#define IGNEUM_SEED_STRING "igneum-genesis"
#define IGNEUM_SEED_BYTES_HEX "69676e65756d2d67656e65736973"
#define IGNEUM_GENERATOR 2
#define IGNEUM_PROGRAM_ATTEMPT 0
#define IGNEUM_PROGRAM_ID 0x9a8b77853b298baaull
#define IGNEUM_DAY_STRING "2026-10-03"
#define IGNEUM_DAY_BYTES_HEX "6461792f323032362d31302d3033"
#define IGNEUM_DAY0 0x3067619fu
#define IGNEUM_DAY1 0x3c269176u
#define IGNEUM_DATASET_LOG2 28
#define IGNEUM_MASK 0x0fffffffu
#define IGNEUM_LANES 32
#define IGNEUM_ITERATIONS 8
#define IGNEUM_INSTR_COUNT 64
#define IGNEUM_LOADS_PER_HASH 128
#define IGNEUM_WIDE_LOADS_PER_HASH 0
#define IGNEUM_OP_MIX "load=16 add=8 shfl=8 xor=6 mad=5 mul=5 mulhi=5 sub=4 rotl=3 rotr=3 or=1"
// Class v3 construction (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): version 2 loads; the dataset item
// derivation applies the mixer IGNEUM_MIXER_MULT times per round (memhard.h), and the cache follows the growth rule.
#define IGNEUM_LOAD_CLASS "mx8+sh256x27"
#define IGNEUM_CLASS_MIXER_MULT 8
#define IGNEUM_CACHE_GROWTH 1 // 1: cache words = 2^(26 + doublings(day)), doublings = floor(log2(1 + day / 1460))
#define IGNEUM_LOAD_SLOTS 16
#define IGNEUM_LOAD_MIX { 100, 0, 0 }
#define IGNEUM_LOAD_WIDTH_COUNTS { 16, 0, 0 } // loads of 4, 16, 64 bytes per program
#define IGNEUM_BYTES_PER_HASH 512
#define IGNEUM_FOLD_ROT 11
#define IGNEUM_FOLD_MUL 0x9e3779b1u
// Latency-shadow block (Counter ASIC 3.0 item 8, docs/analysis/latency-shadow-2026-10-06.md): NOT the lottery hash. A block of
// IGNEUM_SHADOW_INSTRS ALU instructions (the ten non-load families) runs IGNEUM_SHADOW_REPS times at the end of every
// iteration; the 16 loads, the acceptance rule and the base program are the class's without the shadow.
#define IGNEUM_SHADOW_INSTRS 256
#define IGNEUM_SHADOW_REPS 27
#define IGNEUM_SHADOW_INSTRS_PER_HASH 55296
#define IGNEUM_SHADOW_OP_MIX "add=47 rotl=30 xor=30 shfl=29 mad=27 mul=22 sub=21 rotr=20 mulhi=18 or=12"
// 0 = closed-form dataset (ds_elem), 1 = memory-hard cache construction (MEMHARD.md, memhard.h)
#define IGNEUM_DATASET_MODE 1
#define IGNEUM_SEEDW_INIT { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u }
#define IGNEUM_KEY_INIT { 0x3067619fu, 0x3c269176u, 0x84a03b03u, 0xf8c63294u, 0xff977c5bu, 0xe60def3eu, 0x63630141u, 0xb8fbcb58u }
#define IGNEUM_CACHE_LOG2_WORDS 26
#define IGNEUM_CACHE_SEGMENT_LOG2_LINES 6
#define IGNEUM_CACHE_SEGMENTS 65536u
#define IGNEUM_ITEM_ROUNDS 8
#define IGNEUM_MIXER_MULT 8 // mixer applications per round and after the last read (class v3, docs/plans/mixer-x4.md)
#define IGNEUM_MIX_ROT_INIT { 20u, 20u, 19u, 4u, 26u, 3u, 3u, 27u }
#define IGNEUM_MIX_MUL_INIT { 0x42146205u, 0x52cbe0fbu, 0x7ecf4a03u, 0x6728907fu, 0xd81d9751u, 0x132952c3u, 0xf60de277u, 0x05358035u, 0xbaf6499du, 0xe4db9667u, 0x3e98f45du, 0xd0004eddu, 0x2691630du, 0x9beb3bcfu, 0xab310379u, 0x99cfb423u }
#define IGNEUM_MIX_RC_INIT { 0xbab68293u, 0xcc162340u, 0x6ce151ccu, 0xe62b8997u, 0xc9c80297u, 0xf74a1654u, 0x3d704af5u, 0x3cf522b7u, 0x2b9cac04u, 0xa880ac10u, 0x13e5dd1du, 0x6fc3e233u, 0x2d83eeacu, 0x9006e8bfu, 0x2c4b5362u, 0x31b49ee2u }
#ifndef IGNEUM_NO_CUDA
// Defined in kernel.cu. All launch on the default stream and return cudaGetLastError().
cudaError_t igneum_launch_cache_fill(uint32_t* cache, uint32_t nSegments);
cudaError_t igneum_launch_build(uint32_t* ds, const uint32_t* cache, uint32_t nItems);
cudaError_t igneum_launch_hash(const uint32_t* ds, uint64_t* out, uint32_t baseNonce, uint32_t mask,
uint32_t nonces, uint32_t blockWarps);
cudaError_t igneum_hash_info(int* numRegs, int* blocksPerSM, uint32_t blockWarps);
#endif

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{
"format": "igneum-program-pack-3",
"generator": 2,
"attempt": 0,
"program_id": "0x9a8b77853b298baa",
"program_id_derivation": "FNV-1a 64 over 'igneum-program/' || generator_le32 || seed_words as little-endian bytes || attempt_le32",
"dataset_mode": "memory-hard",
"seed": "igneum-genesis",
"seed_bytes": "69676e65756d2d67656e65736973",
"seed_words": ["0x67a9a7be", "0x1a155b25", "0xfddfb732", "0x4b5af2e8", "0xc55caf33", "0xa27c13b7", "0x06628a48", "0x03852469"],
"seed_derivation": "seed_words = FNV-1a 64 over seed_bytes (attempt 0) or seed_bytes || attempt_le32 (attempt k >= 1), basis ^ (salt * 0x9E3779B97F4A7C15) for salt 0..3, then h ^= h>>33; h *= 0xff51afd7ed558ccd; h ^= h>>33; words[2*salt] = low 32, words[2*salt+1] = high 32",
"generator_rule": "version 2: exactly 16 load slots drawn first from instructions 1..63 (partial Fisher-Yates), the other 48 ops from the ten non-load weights (sum 75); a load's source is drawn from the registers other than dst written by an earlier instruction and not read by a load since; the candidate must pass the acceptance rule of spec 01 section 1.4.6 (static: no cyclically stale load source, every register has an injecting write; dynamic: 64 units on the seed-keyed closed-form dataset with no constant register bit, no lane-constant load site, under 164 saturated final values, every output bit within 136 of 1024, distinct addresses above 245760), else the next attempt of the seed is tried",
"lanes": 32,
"registers": 8,
"iterations": 8,
"instruction_count": 64,
"loads_per_hash": 128,
"load_class": "mx8+sh256x27",
"mixer_mult": 8,
"cache_growth": true,
"mixer": "class v3 (Counter ASIC 2.0, 5 October 2026, docs/plans/mixer-x4.md): every mixer application of the item derivation is 8 applications with round keys (r * 8 + j + 1) * 0x9E3779B9, the 8 dependent cache reads per item unchanged; cache growth rule option C: cache words = 2^(26 + doublings(day)), dataset words = 2^(genesis_log2 + doublings(day)), doublings(day) = floor(log2(1 + day / 1460)) for day = days since genesis",
"load_slots": 16,
"load_mix_percent_4_16_64": [100, 0, 0],
"load_width_counts_4_16_64": [16, 0, 0],
"bytes_per_hash": 512,
"wide_load": "read-width experiment (5 October 2026, docs/plans/read-width.md), NOT the lottery hash: a load of W words (width field, 4 or 16) reads dataset[b .. b + W) with b = (src & mask) & ~(W - 1) and folds every word into dst: x = dst ^ w[0]; for j in 1..W: x = (rotl(x, 11) * 0x9e3779b1) ^ w[j]; dst = x; width 1 is the plain load; the width is drawn per instruction from the class mix with one extra below(100) draw after the nine of version 2, and the program id is FNV-1a 64 over 'igneum-program-rw/' || generator_le32 || seed words || attempt_le32 || mix[3] || load_slots",
"op_mix": {"load": 16, "add": 8, "shfl": 8, "xor": 6, "mad": 5, "mul": 5, "mulhi": 5, "sub": 4, "rotl": 3, "rotr": 3, "or": 1},
"register_init": "for i in 0..7: x = nonce ^ seed_words[i]; x += 0x9e3779b9 * (i+1) (mod 2^32); x = splitmix32(x); r[i] = x ^ seed_words[(i+1) & 7]",
"splitmix32": "x ^= x>>16; x *= 0x7feb352d; x ^= x>>15; x *= 0x846ca68b; x ^= x>>16",
"iteration": "sel = r0 sampled once at the top of each iteration, then all instructions in order",
"output": "lo = r0 ^ rotl(r1,7) ^ rotl(r2,14) ^ rotl(r3,21); hi = r4 ^ rotl(r5,9) ^ rotl(r6,18) ^ rotl(r7,27); out = (hi << 32) | lo",
"op_semantics": {
"add": "dst = dst + src + (bit `bit` of sel ? imm2 : imm)",
"sub": "dst = dst - src",
"mul": "dst = dst * src (low 32)",
"mulhi": "dst = high 32 bits of dst * src",
"xor": "dst = dst ^ src",
"or": "dst = dst | src",
"rotl": "dst = rotl(dst, rot), rot in 1..31",
"rotr": "dst = rotr(dst, src & 31)",
"mad": "dst = src * src2 + dst",
"shfl": "dst = dst ^ (src of lane (lane ^ mask)), mask in {1,2,4,8,16}, within the 32-lane warp",
"load": "dst = dst ^ dataset[src & dataset.mask]",
"wload": "base = (src of lane 0 & dataset.mask) & ~31; dst = dst ^ dataset[base + lane] (warp-coalesced 128-byte load, lever b, only when --wide-frac > 0)"
},
"dataset": {
"log2_words": 28,
"bytes": 1073741824,
"mask": "0x0fffffff",
"day": "2026-10-03",
"day_bytes": "6461792f323032362d31302d3033",
"day_words_from": "seed_words_from_bytes(day_bytes)",
"d0": "0x3067619f",
"d1": "0x3c269176",
"mode": "memory-hard",
"spec": "proto-metal/MEMHARD.md",
"key": ["0x3067619f", "0x3c269176", "0x84a03b03", "0xf8c63294", "0xff977c5b", "0xe60def3e", "0x63630141", "0xb8fbcb58"],
"key_derivation": "the 8 words of seed_words_from_bytes(day_bytes); d0, d1 are key[0], key[1]",
"cache": {"log2_words": 26, "bytes": 268435456, "line_words": 16, "segment_lines": 64, "segments": 65536, "block": "ChaCha12 core + feed-forward, rotations 16 12 8 7", "sigma": ["0x61707865", "0x3320646e", "0x79622d32", "0x6b206574"], "tag": ["0x49676e65", "0x756d4d48"], "chain": "in_j = prev_line ^ (sigma[0..3] || key[0..7] || seg || j || tag[0..1]); line_j = block(in_j); prev_0 = 0"},
"mixer": {"draw": "SplitMix64 seeded with key[0] | key[1] << 32: rot[0..7] = 1 + next() % 31, mul[0..15] = low32(next()) | 1, rc[0..15] = low32(next())", "rot": [20, 20, 19, 4, 26, 3, 3, 27], "mul": ["0x42146205", "0x52cbe0fb", "0x7ecf4a03", "0x6728907f", "0xd81d9751", "0x132952c3", "0xf60de277", "0x05358035", "0xbaf6499d", "0xe4db9667", "0x3e98f45d", "0xd0004edd", "0x2691630d", "0x9beb3bcf", "0xab310379", "0x99cfb423"], "rc": ["0xbab68293", "0xcc162340", "0x6ce151cc", "0xe62b8997", "0xc9c80297", "0xf74a1654", "0x3d704af5", "0x3cf522b7", "0x2b9cac04", "0xa880ac10", "0x13e5dd1d", "0x6fc3e233", "0x2d83eeac", "0x9006e8bf", "0x2c4b5362", "0x31b49ee2"], "round": "for i in 0..15: s[i] = (s[i] ^ (rc[i] + (r+1) * 0x9E3779B9)) * mul[i]; then quarter rounds on columns (0,4,8,12) (1,5,9,13) (2,6,10,14) (3,7,11,15) with rot[0..3] and diagonals (0,5,10,15) (1,6,11,12) (2,7,8,13) (3,4,9,14) with rot[4..7]", "quarter_round": "a += b; d ^= a; d = rotl(d, r1); c += d; b ^= c; b = rotl(b, r2); a += b; d ^= a; d = rotl(d, r3); c += d; b ^= c; b = rotl(b, r4)"},
"mixer_mult": 8,
"item": "s[0..7] = key; s[8+i] = t * mul[i] + rc[i] for i in 0..7; for r in 0..7: for j in 0..7: s = M(s, rk = (r * 8 + j + 1) * 0x9E3779B9); line = s[0] & 0x003fffff; s[i] ^= cache[line * 16 + i]; then for j in 0..7: s = M(s, rk = (64 + j + 1) * 0x9E3779B9); item(t) = s",
"word": "dataset[w] = item(w >> 4)[w & 15]"
},
"shadow": {"instrs": 256, "reps": 27, "instrs_per_hash": 55296, "op_mix": {"add": 47, "rotl": 30, "xor": 30, "shfl": 29, "mad": 27, "mul": 22, "sub": 21, "rotr": 20, "mulhi": 18, "or": 12}, "rule": "Counter ASIC 3.0 item 8 (docs/analysis/latency-shadow-2026-10-06.md): after the 64 base instructions the program stream draws instrs more ALU instructions (the non-load table, nine draws each, the source as on an ALU slot); the block runs reps times at the end of every iteration with the iteration's sel; the acceptance rule interprets the base program only", "program_id_suffix": "'shadow/' || instrs_le16 || reps_le16", "instructions": [
{"i": 0, "op": "add", "dst": 5, "src": 2, "src2": 1, "imm": "0x92199f99", "imm2": "0x8bc12da9", "rot": 9, "bit": 18, "mask": 4},
{"i": 1, "op": "add", "dst": 0, "src": 7, "src2": 1, "imm": "0x8d72d3ad", "imm2": "0x63079e5a", "rot": 20, "bit": 26, "mask": 4},
{"i": 2, "op": "shfl", "dst": 6, "src": 3, "src2": 6, "imm": "0x9beaeddf", "imm2": "0x744ecb00", "rot": 10, "bit": 4, "mask": 2},
{"i": 3, "op": "sub", "dst": 4, "src": 2, "src2": 0, "imm": "0x2a3ddc67", "imm2": "0x72c80241", "rot": 30, "bit": 1, "mask": 16},
{"i": 4, "op": "add", "dst": 7, "src": 0, "src2": 5, "imm": "0xb21b4bab", "imm2": "0x5d4c7a60", "rot": 17, "bit": 31, "mask": 4},
{"i": 5, "op": "rotl", "dst": 0, "src": 6, "src2": 3, "imm": "0xe69d7919", "imm2": "0xa048c61e", "rot": 11, "bit": 1, "mask": 8},
{"i": 6, "op": "add", "dst": 0, "src": 1, "src2": 3, "imm": "0x2fe0e98b", "imm2": "0xc88e2942", "rot": 5, "bit": 16, "mask": 16},
{"i": 7, "op": "xor", "dst": 7, "src": 1, "src2": 0, "imm": "0xc16efe98", "imm2": "0x01a638c8", "rot": 8, "bit": 17, "mask": 1},
{"i": 8, "op": "mad", "dst": 1, "src": 6, "src2": 5, "imm": "0x76ec7b8b", "imm2": "0x25663feb", "rot": 29, "bit": 30, "mask": 2},
{"i": 9, "op": "shfl", "dst": 6, "src": 1, "src2": 0, "imm": "0x6c8ee3cb", "imm2": "0xea93237e", "rot": 27, "bit": 1, "mask": 4},
{"i": 10, "op": "mad", "dst": 1, "src": 2, "src2": 2, "imm": "0x6dc4ea18", "imm2": "0x6efde6f5", "rot": 3, "bit": 20, "mask": 2},
{"i": 11, "op": "mad", "dst": 5, "src": 0, "src2": 3, "imm": "0x023613fc", "imm2": "0x18c51939", "rot": 19, "bit": 31, "mask": 1},
{"i": 12, "op": "shfl", "dst": 2, "src": 6, "src2": 1, "imm": "0x74aec8d2", "imm2": "0x7f7ad29c", "rot": 7, "bit": 8, "mask": 4},
{"i": 13, "op": "add", "dst": 1, "src": 5, "src2": 6, "imm": "0xbdf8f9a5", "imm2": "0xbc48c63e", "rot": 6, "bit": 25, "mask": 2},
{"i": 14, "op": "rotl", "dst": 1, "src": 2, "src2": 6, "imm": "0x7ad8ca8b", "imm2": "0x14c712ad", "rot": 29, "bit": 25, "mask": 8},
{"i": 15, "op": "sub", "dst": 1, "src": 4, "src2": 5, "imm": "0xd3349f69", "imm2": "0x70aac45a", "rot": 29, "bit": 9, "mask": 16},
{"i": 16, "op": "or", "dst": 7, "src": 1, "src2": 2, "imm": "0x08168ed1", "imm2": "0x28964037", "rot": 26, "bit": 0, "mask": 2},
{"i": 17, "op": "shfl", "dst": 2, "src": 4, "src2": 6, "imm": "0x98d85f72", "imm2": "0x3dc87042", "rot": 29, "bit": 22, "mask": 8},
{"i": 18, "op": "xor", "dst": 7, "src": 4, "src2": 0, "imm": "0x651d4a0e", "imm2": "0x93c198bd", "rot": 26, "bit": 12, "mask": 8},
{"i": 19, "op": "mul", "dst": 6, "src": 1, "src2": 6, "imm": "0xd38ce89d", "imm2": "0x3dfad388", "rot": 5, "bit": 28, "mask": 8},
{"i": 20, "op": "mad", "dst": 5, "src": 6, "src2": 0, "imm": "0x59d78b36", "imm2": "0xc4db274e", "rot": 25, "bit": 24, "mask": 1},
{"i": 21, "op": "sub", "dst": 3, "src": 1, "src2": 7, "imm": "0xf6c6a6c7", "imm2": "0x8536f4e6", "rot": 6, "bit": 12, "mask": 4},
{"i": 22, "op": "mul", "dst": 6, "src": 0, "src2": 7, "imm": "0x599445b4", "imm2": "0x632f8c32", "rot": 19, "bit": 4, "mask": 8},
{"i": 23, "op": "add", "dst": 2, "src": 0, "src2": 7, "imm": "0x45c37cec", "imm2": "0x96e8f127", "rot": 15, "bit": 1, "mask": 4},
{"i": 24, "op": "sub", "dst": 6, "src": 4, "src2": 3, "imm": "0xc1c44491", "imm2": "0x92e3ce57", "rot": 20, "bit": 25, "mask": 4},
{"i": 25, "op": "mad", "dst": 7, "src": 3, "src2": 4, "imm": "0x89bfb8d3", "imm2": "0x19b5455e", "rot": 22, "bit": 2, "mask": 16},
{"i": 26, "op": "rotl", "dst": 3, "src": 5, "src2": 7, "imm": "0x2f47ce8d", "imm2": "0x8b458ec5", "rot": 9, "bit": 0, "mask": 4},
{"i": 27, "op": "sub", "dst": 2, "src": 1, "src2": 2, "imm": "0x9f0dce23", "imm2": "0x3cdca814", "rot": 25, "bit": 1, "mask": 2},
{"i": 28, "op": "mulhi", "dst": 6, "src": 0, "src2": 3, "imm": "0x61fc9eb8", "imm2": "0x23202e9d", "rot": 30, "bit": 16, "mask": 16},
{"i": 29, "op": "shfl", "dst": 2, "src": 4, "src2": 3, "imm": "0x339dbd65", "imm2": "0xc175f639", "rot": 15, "bit": 22, "mask": 2},
{"i": 30, "op": "shfl", "dst": 1, "src": 6, "src2": 1, "imm": "0x5bd14589", "imm2": "0xa68a2bed", "rot": 31, "bit": 31, "mask": 1},
{"i": 31, "op": "add", "dst": 1, "src": 6, "src2": 1, "imm": "0x37985632", "imm2": "0xb1cdb2ab", "rot": 29, "bit": 1, "mask": 8},
{"i": 32, "op": "rotr", "dst": 0, "src": 1, "src2": 6, "imm": "0x4b2058f4", "imm2": "0xf06d8ac9", "rot": 9, "bit": 15, "mask": 16},
{"i": 33, "op": "shfl", "dst": 3, "src": 4, "src2": 4, "imm": "0x2081626c", "imm2": "0x08d1bb87", "rot": 24, "bit": 29, "mask": 2},
{"i": 34, "op": "shfl", "dst": 0, "src": 3, "src2": 6, "imm": "0xe4fcfe03", "imm2": "0x78a46b13", "rot": 15, "bit": 29, "mask": 4},
{"i": 35, "op": "mul", "dst": 7, "src": 0, "src2": 4, "imm": "0x33148d30", "imm2": "0x5780a3d6", "rot": 6, "bit": 11, "mask": 2},
{"i": 36, "op": "add", "dst": 3, "src": 1, "src2": 1, "imm": "0x804e777e", "imm2": "0x856e0180", "rot": 22, "bit": 0, "mask": 16},
{"i": 37, "op": "xor", "dst": 1, "src": 6, "src2": 0, "imm": "0xc69aa2f6", "imm2": "0xafebe3e8", "rot": 15, "bit": 9, "mask": 16},
{"i": 38, "op": "mul", "dst": 2, "src": 7, "src2": 4, "imm": "0xeb4c4082", "imm2": "0x3f1e0da7", "rot": 25, "bit": 20, "mask": 16},
{"i": 39, "op": "add", "dst": 6, "src": 5, "src2": 5, "imm": "0x0b06c8a7", "imm2": "0xe9bd0cc4", "rot": 6, "bit": 2, "mask": 4},
{"i": 40, "op": "mul", "dst": 5, "src": 7, "src2": 7, "imm": "0x070af1b6", "imm2": "0x6b648e75", "rot": 10, "bit": 6, "mask": 16},
{"i": 41, "op": "mulhi", "dst": 2, "src": 3, "src2": 2, "imm": "0x389753b2", "imm2": "0x9e657305", "rot": 30, "bit": 2, "mask": 4},
{"i": 42, "op": "xor", "dst": 2, "src": 0, "src2": 4, "imm": "0x0960e5b9", "imm2": "0xa925a406", "rot": 4, "bit": 6, "mask": 16},
{"i": 43, "op": "rotl", "dst": 0, "src": 1, "src2": 1, "imm": "0x8eabe09f", "imm2": "0x76ef71e2", "rot": 4, "bit": 19, "mask": 8},
{"i": 44, "op": "mulhi", "dst": 4, "src": 3, "src2": 7, "imm": "0x6a34768a", "imm2": "0x2e427c64", "rot": 21, "bit": 5, "mask": 4},
{"i": 45, "op": "add", "dst": 6, "src": 7, "src2": 5, "imm": "0xee822e17", "imm2": "0xcdcb63f6", "rot": 27, "bit": 12, "mask": 16},
{"i": 46, "op": "mad", "dst": 3, "src": 2, "src2": 0, "imm": "0xc89ead43", "imm2": "0x4d3108b2", "rot": 26, "bit": 17, "mask": 1},
{"i": 47, "op": "shfl", "dst": 4, "src": 3, "src2": 0, "imm": "0xdd62be9e", "imm2": "0xf243f6f2", "rot": 8, "bit": 4, "mask": 8},
{"i": 48, "op": "mulhi", "dst": 6, "src": 5, "src2": 0, "imm": "0xd3f7fa72", "imm2": "0x0debc83f", "rot": 25, "bit": 5, "mask": 2},
{"i": 49, "op": "sub", "dst": 0, "src": 2, "src2": 6, "imm": "0x7afadd15", "imm2": "0xc07fc39c", "rot": 30, "bit": 29, "mask": 8},
{"i": 50, "op": "sub", "dst": 3, "src": 5, "src2": 3, "imm": "0x179b78ec", "imm2": "0xaeccde37", "rot": 30, "bit": 17, "mask": 1},
{"i": 51, "op": "rotr", "dst": 1, "src": 4, "src2": 1, "imm": "0xa4bfcea6", "imm2": "0xbf63bb2f", "rot": 2, "bit": 21, "mask": 2},
{"i": 52, "op": "mad", "dst": 6, "src": 7, "src2": 7, "imm": "0xabf5ed10", "imm2": "0x8a285f51", "rot": 3, "bit": 23, "mask": 2},
{"i": 53, "op": "xor", "dst": 5, "src": 3, "src2": 5, "imm": "0x88b416eb", "imm2": "0x36271d87", "rot": 19, "bit": 10, "mask": 2},
{"i": 54, "op": "sub", "dst": 1, "src": 0, "src2": 1, "imm": "0xa3417dd3", "imm2": "0xcd98f620", "rot": 28, "bit": 2, "mask": 1},
{"i": 55, "op": "sub", "dst": 5, "src": 6, "src2": 2, "imm": "0x45996c6f", "imm2": "0xe3d41087", "rot": 4, "bit": 31, "mask": 1},
{"i": 56, "op": "add", "dst": 3, "src": 2, "src2": 0, "imm": "0x3dfad1b6", "imm2": "0xd4758987", "rot": 27, "bit": 10, "mask": 2},
{"i": 57, "op": "add", "dst": 4, "src": 1, "src2": 3, "imm": "0xfca75bc2", "imm2": "0x0602d6be", "rot": 19, "bit": 0, "mask": 16},
{"i": 58, "op": "mulhi", "dst": 5, "src": 6, "src2": 5, "imm": "0x83250a7b", "imm2": "0x2f93d53b", "rot": 25, "bit": 7, "mask": 2},
{"i": 59, "op": "shfl", "dst": 2, "src": 1, "src2": 0, "imm": "0x13f4a089", "imm2": "0x145ea125", "rot": 12, "bit": 3, "mask": 2},
{"i": 60, "op": "rotl", "dst": 2, "src": 5, "src2": 6, "imm": "0xad3170e3", "imm2": "0x15db04d1", "rot": 9, "bit": 13, "mask": 2},
{"i": 61, "op": "or", "dst": 4, "src": 6, "src2": 2, "imm": "0x4b6305b2", "imm2": "0x6e7b2e9c", "rot": 27, "bit": 16, "mask": 4},
{"i": 62, "op": "rotr", "dst": 6, "src": 4, "src2": 6, "imm": "0xfcd4b1c9", "imm2": "0xaf5c733b", "rot": 6, "bit": 21, "mask": 16},
{"i": 63, "op": "mul", "dst": 2, "src": 4, "src2": 6, "imm": "0x95cebb3e", "imm2": "0xbba9cdfc", "rot": 19, "bit": 23, "mask": 1},
{"i": 64, "op": "xor", "dst": 0, "src": 5, "src2": 7, "imm": "0x5f7579ff", "imm2": "0xb104e01a", "rot": 25, "bit": 12, "mask": 8},
{"i": 65, "op": "xor", "dst": 2, "src": 7, "src2": 3, "imm": "0x749c7611", "imm2": "0xf17df3bb", "rot": 27, "bit": 26, "mask": 2},
{"i": 66, "op": "add", "dst": 2, "src": 1, "src2": 6, "imm": "0xd71c02ff", "imm2": "0x8596687a", "rot": 4, "bit": 6, "mask": 2},
{"i": 67, "op": "rotl", "dst": 1, "src": 3, "src2": 2, "imm": "0xd2864071", "imm2": "0xaa644ef3", "rot": 21, "bit": 5, "mask": 1},
{"i": 68, "op": "mul", "dst": 3, "src": 2, "src2": 1, "imm": "0xd0689a5f", "imm2": "0xa3a1f063", "rot": 13, "bit": 28, "mask": 2},
{"i": 69, "op": "shfl", "dst": 7, "src": 5, "src2": 6, "imm": "0xd01476eb", "imm2": "0x76abb5c2", "rot": 7, "bit": 30, "mask": 2},
{"i": 70, "op": "mul", "dst": 3, "src": 2, "src2": 5, "imm": "0x59a75c10", "imm2": "0x1e1fbb72", "rot": 20, "bit": 16, "mask": 1},
{"i": 71, "op": "mad", "dst": 0, "src": 2, "src2": 5, "imm": "0x39cca1df", "imm2": "0x22c057ac", "rot": 5, "bit": 23, "mask": 16},
{"i": 72, "op": "add", "dst": 6, "src": 7, "src2": 3, "imm": "0x3c6fe15d", "imm2": "0x08ac5733", "rot": 14, "bit": 0, "mask": 4},
{"i": 73, "op": "shfl", "dst": 3, "src": 2, "src2": 6, "imm": "0x2098627d", "imm2": "0xf4fecc81", "rot": 20, "bit": 30, "mask": 8},
{"i": 74, "op": "mul", "dst": 3, "src": 6, "src2": 5, "imm": "0xf82e9e23", "imm2": "0x3ad62132", "rot": 10, "bit": 14, "mask": 16},
{"i": 75, "op": "xor", "dst": 6, "src": 7, "src2": 4, "imm": "0x70548a91", "imm2": "0xa9715d2e", "rot": 6, "bit": 24, "mask": 1},
{"i": 76, "op": "or", "dst": 3, "src": 0, "src2": 7, "imm": "0xa164325f", "imm2": "0xf300838b", "rot": 23, "bit": 23, "mask": 16},
{"i": 77, "op": "add", "dst": 2, "src": 4, "src2": 6, "imm": "0x295d5fae", "imm2": "0xc100b495", "rot": 7, "bit": 1, "mask": 2},
{"i": 78, "op": "mulhi", "dst": 3, "src": 7, "src2": 4, "imm": "0xb62cca87", "imm2": "0x2ebde415", "rot": 14, "bit": 7, "mask": 2},
{"i": 79, "op": "or", "dst": 4, "src": 1, "src2": 7, "imm": "0xfcbc482d", "imm2": "0x8876e6cd", "rot": 29, "bit": 5, "mask": 2},
{"i": 80, "op": "rotr", "dst": 4, "src": 3, "src2": 0, "imm": "0x6d64013b", "imm2": "0x675f4a8d", "rot": 26, "bit": 18, "mask": 8},
{"i": 81, "op": "add", "dst": 4, "src": 3, "src2": 3, "imm": "0x274a9221", "imm2": "0x5cc59530", "rot": 15, "bit": 15, "mask": 2},
{"i": 82, "op": "add", "dst": 7, "src": 3, "src2": 0, "imm": "0xc8651f8e", "imm2": "0x141479ec", "rot": 18, "bit": 5, "mask": 1},
{"i": 83, "op": "rotr", "dst": 3, "src": 6, "src2": 0, "imm": "0xcc8a7766", "imm2": "0xc2eb5161", "rot": 4, "bit": 29, "mask": 2},
{"i": 84, "op": "mad", "dst": 2, "src": 4, "src2": 7, "imm": "0xbc507d51", "imm2": "0x0b1196fd", "rot": 9, "bit": 7, "mask": 8},
{"i": 85, "op": "shfl", "dst": 2, "src": 5, "src2": 5, "imm": "0x5a156c90", "imm2": "0xa6b3fbfa", "rot": 11, "bit": 2, "mask": 16},
{"i": 86, "op": "xor", "dst": 3, "src": 2, "src2": 1, "imm": "0x8b042658", "imm2": "0xacf37a8f", "rot": 12, "bit": 23, "mask": 16},
{"i": 87, "op": "shfl", "dst": 5, "src": 7, "src2": 2, "imm": "0x1a214238", "imm2": "0x017fdf5d", "rot": 29, "bit": 14, "mask": 2},
{"i": 88, "op": "xor", "dst": 0, "src": 4, "src2": 2, "imm": "0xd523e612", "imm2": "0x2158c2ed", "rot": 30, "bit": 14, "mask": 4},
{"i": 89, "op": "add", "dst": 3, "src": 2, "src2": 7, "imm": "0x53f915c2", "imm2": "0x883c0c92", "rot": 9, "bit": 18, "mask": 8},
{"i": 90, "op": "rotr", "dst": 7, "src": 5, "src2": 5, "imm": "0xbd633b21", "imm2": "0xcf8c356c", "rot": 25, "bit": 31, "mask": 4},
{"i": 91, "op": "add", "dst": 3, "src": 1, "src2": 1, "imm": "0xe2be00a5", "imm2": "0x3cc5bd20", "rot": 10, "bit": 31, "mask": 1},
{"i": 92, "op": "shfl", "dst": 7, "src": 2, "src2": 4, "imm": "0x3d3da600", "imm2": "0x1f22df89", "rot": 4, "bit": 24, "mask": 1},
{"i": 93, "op": "rotr", "dst": 6, "src": 2, "src2": 7, "imm": "0xb0f57471", "imm2": "0x8f2a7eca", "rot": 16, "bit": 25, "mask": 1},
{"i": 94, "op": "rotl", "dst": 7, "src": 0, "src2": 4, "imm": "0x00a21815", "imm2": "0xeb4d7218", "rot": 14, "bit": 18, "mask": 16},
{"i": 95, "op": "mad", "dst": 4, "src": 5, "src2": 5, "imm": "0xc4c3828e", "imm2": "0xfb7bba17", "rot": 16, "bit": 10, "mask": 16},
{"i": 96, "op": "mad", "dst": 2, "src": 4, "src2": 5, "imm": "0xfc5bbc75", "imm2": "0xfc43468f", "rot": 31, "bit": 20, "mask": 16},
{"i": 97, "op": "xor", "dst": 1, "src": 0, "src2": 2, "imm": "0x1fe9c249", "imm2": "0x164bb16b", "rot": 15, "bit": 9, "mask": 4},
{"i": 98, "op": "mul", "dst": 5, "src": 4, "src2": 1, "imm": "0xeda725fa", "imm2": "0x66f7e9a2", "rot": 21, "bit": 6, "mask": 2},
{"i": 99, "op": "sub", "dst": 2, "src": 0, "src2": 7, "imm": "0x8fb29f7d", "imm2": "0xf530eda1", "rot": 27, "bit": 30, "mask": 4},
{"i": 100, "op": "rotl", "dst": 7, "src": 2, "src2": 0, "imm": "0x9f4de742", "imm2": "0x9b5ff871", "rot": 30, "bit": 21, "mask": 16},
{"i": 101, "op": "add", "dst": 5, "src": 6, "src2": 7, "imm": "0x423fd9c9", "imm2": "0xbfd646cb", "rot": 17, "bit": 17, "mask": 2},
{"i": 102, "op": "add", "dst": 7, "src": 6, "src2": 3, "imm": "0x8d3c011d", "imm2": "0x19b74a43", "rot": 12, "bit": 11, "mask": 4},
{"i": 103, "op": "rotl", "dst": 5, "src": 6, "src2": 0, "imm": "0xcfc70303", "imm2": "0xf2b3e8ef", "rot": 6, "bit": 24, "mask": 1},
{"i": 104, "op": "mul", "dst": 0, "src": 4, "src2": 5, "imm": "0x650475eb", "imm2": "0x11dcbd94", "rot": 15, "bit": 10, "mask": 1},
{"i": 105, "op": "or", "dst": 0, "src": 5, "src2": 3, "imm": "0xaacaa145", "imm2": "0x9139d3fe", "rot": 4, "bit": 18, "mask": 2},
{"i": 106, "op": "add", "dst": 0, "src": 1, "src2": 7, "imm": "0x8ce14721", "imm2": "0x7dcb7e18", "rot": 24, "bit": 15, "mask": 8},
{"i": 107, "op": "rotl", "dst": 0, "src": 3, "src2": 3, "imm": "0xb36d6d98", "imm2": "0x2c3390c8", "rot": 15, "bit": 10, "mask": 16},
{"i": 108, "op": "sub", "dst": 4, "src": 2, "src2": 5, "imm": "0xf6bbdaef", "imm2": "0x9db6f65e", "rot": 25, "bit": 10, "mask": 1},
{"i": 109, "op": "mulhi", "dst": 2, "src": 0, "src2": 0, "imm": "0xb1721fd6", "imm2": "0xd96d52c9", "rot": 1, "bit": 27, "mask": 8},
{"i": 110, "op": "mulhi", "dst": 1, "src": 0, "src2": 5, "imm": "0xfb4ca37f", "imm2": "0xb6ec7dbe", "rot": 27, "bit": 12, "mask": 8},
{"i": 111, "op": "add", "dst": 0, "src": 2, "src2": 0, "imm": "0x2d9fc6b9", "imm2": "0x3c179ad8", "rot": 9, "bit": 28, "mask": 16},
{"i": 112, "op": "mulhi", "dst": 2, "src": 0, "src2": 6, "imm": "0x71a9f6bd", "imm2": "0xd3417bf5", "rot": 2, "bit": 14, "mask": 8},
{"i": 113, "op": "sub", "dst": 6, "src": 3, "src2": 5, "imm": "0xa3d19400", "imm2": "0x15df7330", "rot": 5, "bit": 2, "mask": 8},
{"i": 114, "op": "mad", "dst": 7, "src": 6, "src2": 3, "imm": "0x1400d92e", "imm2": "0xfa4a158e", "rot": 16, "bit": 9, "mask": 1},
{"i": 115, "op": "rotr", "dst": 5, "src": 1, "src2": 3, "imm": "0xd01684c3", "imm2": "0x6367febb", "rot": 23, "bit": 19, "mask": 2},
{"i": 116, "op": "rotr", "dst": 6, "src": 4, "src2": 2, "imm": "0x8cd9eb96", "imm2": "0x98f33b24", "rot": 25, "bit": 1, "mask": 2},
{"i": 117, "op": "add", "dst": 2, "src": 1, "src2": 7, "imm": "0x502138e2", "imm2": "0x47359729", "rot": 5, "bit": 22, "mask": 4},
{"i": 118, "op": "mad", "dst": 3, "src": 2, "src2": 0, "imm": "0xd94a35c7", "imm2": "0xb83416c3", "rot": 11, "bit": 3, "mask": 4},
{"i": 119, "op": "mul", "dst": 1, "src": 3, "src2": 6, "imm": "0x09b30cf7", "imm2": "0xef3b98e7", "rot": 17, "bit": 23, "mask": 8},
{"i": 120, "op": "mad", "dst": 2, "src": 0, "src2": 4, "imm": "0x56416fe0", "imm2": "0x5e1dc8f3", "rot": 17, "bit": 14, "mask": 2},
{"i": 121, "op": "mul", "dst": 0, "src": 3, "src2": 2, "imm": "0x2892697c", "imm2": "0x9cb3b14e", "rot": 29, "bit": 25, "mask": 2},
{"i": 122, "op": "mulhi", "dst": 2, "src": 0, "src2": 3, "imm": "0xc33089a1", "imm2": "0xd6c5b530", "rot": 27, "bit": 13, "mask": 8},
{"i": 123, "op": "mul", "dst": 5, "src": 6, "src2": 4, "imm": "0xdfe04e4a", "imm2": "0x3cc40160", "rot": 3, "bit": 14, "mask": 2},
{"i": 124, "op": "mad", "dst": 4, "src": 2, "src2": 4, "imm": "0xb33dc1b7", "imm2": "0xab97743a", "rot": 7, "bit": 21, "mask": 4},
{"i": 125, "op": "shfl", "dst": 4, "src": 2, "src2": 0, "imm": "0xfd469909", "imm2": "0xfc85dc55", "rot": 28, "bit": 24, "mask": 2},
{"i": 126, "op": "xor", "dst": 2, "src": 0, "src2": 5, "imm": "0xa0094578", "imm2": "0xf1bee474", "rot": 31, "bit": 7, "mask": 2},
{"i": 127, "op": "rotl", "dst": 1, "src": 7, "src2": 2, "imm": "0xb7ae00a0", "imm2": "0x86cce297", "rot": 7, "bit": 31, "mask": 8},
{"i": 128, "op": "shfl", "dst": 7, "src": 2, "src2": 7, "imm": "0x019d1940", "imm2": "0x3fe9e7dd", "rot": 14, "bit": 4, "mask": 4},
{"i": 129, "op": "rotl", "dst": 6, "src": 7, "src2": 7, "imm": "0x40a74cc4", "imm2": "0x09eb4adf", "rot": 17, "bit": 30, "mask": 1},
{"i": 130, "op": "add", "dst": 2, "src": 5, "src2": 5, "imm": "0x33dff776", "imm2": "0x6c57e4e7", "rot": 27, "bit": 15, "mask": 4},
{"i": 131, "op": "or", "dst": 0, "src": 3, "src2": 1, "imm": "0xe0c53bb9", "imm2": "0x124404f6", "rot": 4, "bit": 21, "mask": 16},
{"i": 132, "op": "rotr", "dst": 5, "src": 0, "src2": 1, "imm": "0xe4353fce", "imm2": "0x559d0118", "rot": 2, "bit": 29, "mask": 4},
{"i": 133, "op": "add", "dst": 2, "src": 3, "src2": 6, "imm": "0x5db25b34", "imm2": "0xe8212c0c", "rot": 21, "bit": 30, "mask": 1},
{"i": 134, "op": "xor", "dst": 4, "src": 3, "src2": 6, "imm": "0x7366e50e", "imm2": "0x7cc1ffbd", "rot": 19, "bit": 18, "mask": 16},
{"i": 135, "op": "xor", "dst": 6, "src": 1, "src2": 2, "imm": "0xa36decb7", "imm2": "0x79291734", "rot": 26, "bit": 0, "mask": 8},
{"i": 136, "op": "sub", "dst": 1, "src": 7, "src2": 0, "imm": "0x225b03e4", "imm2": "0x7183e193", "rot": 16, "bit": 6, "mask": 2},
{"i": 137, "op": "mad", "dst": 2, "src": 6, "src2": 2, "imm": "0x6f620d51", "imm2": "0x4e814e19", "rot": 6, "bit": 6, "mask": 2},
{"i": 138, "op": "mulhi", "dst": 0, "src": 5, "src2": 6, "imm": "0x919d6bf3", "imm2": "0xc6240638", "rot": 17, "bit": 11, "mask": 16},
{"i": 139, "op": "add", "dst": 2, "src": 7, "src2": 7, "imm": "0x218d4090", "imm2": "0xd44ff710", "rot": 1, "bit": 10, "mask": 16},
{"i": 140, "op": "rotr", "dst": 1, "src": 4, "src2": 4, "imm": "0x4cbfa722", "imm2": "0x114e9564", "rot": 28, "bit": 9, "mask": 16},
{"i": 141, "op": "shfl", "dst": 3, "src": 6, "src2": 2, "imm": "0xf702c6a1", "imm2": "0xf8f3c5d9", "rot": 7, "bit": 24, "mask": 1},
{"i": 142, "op": "mad", "dst": 7, "src": 6, "src2": 2, "imm": "0xa2d285be", "imm2": "0x9cc94532", "rot": 15, "bit": 20, "mask": 8},
{"i": 143, "op": "mul", "dst": 2, "src": 3, "src2": 7, "imm": "0x08b7ed80", "imm2": "0xa8abced4", "rot": 18, "bit": 10, "mask": 4},
{"i": 144, "op": "add", "dst": 7, "src": 4, "src2": 2, "imm": "0xf4b1a8de", "imm2": "0xb98942fa", "rot": 18, "bit": 29, "mask": 8},
{"i": 145, "op": "rotl", "dst": 7, "src": 6, "src2": 1, "imm": "0x64b6ba2d", "imm2": "0xf9e86793", "rot": 15, "bit": 24, "mask": 8},
{"i": 146, "op": "xor", "dst": 7, "src": 5, "src2": 3, "imm": "0x41c42b5f", "imm2": "0x7c7e0e39", "rot": 8, "bit": 23, "mask": 2},
{"i": 147, "op": "mad", "dst": 4, "src": 7, "src2": 4, "imm": "0x3caa807a", "imm2": "0x553a0cec", "rot": 11, "bit": 22, "mask": 8},
{"i": 148, "op": "rotr", "dst": 6, "src": 5, "src2": 3, "imm": "0x3cb1289a", "imm2": "0x6b36f78a", "rot": 1, "bit": 9, "mask": 16},
{"i": 149, "op": "mad", "dst": 1, "src": 2, "src2": 4, "imm": "0x95310ea8", "imm2": "0xc533aa6a", "rot": 16, "bit": 17, "mask": 1},
{"i": 150, "op": "add", "dst": 1, "src": 7, "src2": 7, "imm": "0x2bef10f2", "imm2": "0x0d48ba42", "rot": 8, "bit": 17, "mask": 4},
{"i": 151, "op": "xor", "dst": 5, "src": 4, "src2": 7, "imm": "0xda997ab2", "imm2": "0xae31d69e", "rot": 11, "bit": 31, "mask": 2},
{"i": 152, "op": "add", "dst": 7, "src": 0, "src2": 6, "imm": "0xdc5cc080", "imm2": "0xc98dea9c", "rot": 16, "bit": 30, "mask": 2},
{"i": 153, "op": "mul", "dst": 4, "src": 6, "src2": 7, "imm": "0xbfbf5f6c", "imm2": "0x61f611bb", "rot": 14, "bit": 22, "mask": 2},
{"i": 154, "op": "mul", "dst": 0, "src": 2, "src2": 3, "imm": "0xa78008c3", "imm2": "0xbad5eeb1", "rot": 10, "bit": 28, "mask": 8},
{"i": 155, "op": "xor", "dst": 6, "src": 5, "src2": 4, "imm": "0x1a73b866", "imm2": "0x1f5a62c9", "rot": 9, "bit": 27, "mask": 8},
{"i": 156, "op": "rotr", "dst": 4, "src": 2, "src2": 0, "imm": "0x9c88500c", "imm2": "0xe25dccf9", "rot": 11, "bit": 2, "mask": 16},
{"i": 157, "op": "rotl", "dst": 1, "src": 4, "src2": 4, "imm": "0xb05e7669", "imm2": "0x9db704b1", "rot": 11, "bit": 28, "mask": 4},
{"i": 158, "op": "add", "dst": 5, "src": 0, "src2": 6, "imm": "0x18197438", "imm2": "0x6c752dcb", "rot": 11, "bit": 11, "mask": 2},
{"i": 159, "op": "mad", "dst": 4, "src": 1, "src2": 5, "imm": "0x4796a65e", "imm2": "0x00e08c7a", "rot": 8, "bit": 19, "mask": 4},
{"i": 160, "op": "rotl", "dst": 4, "src": 7, "src2": 5, "imm": "0x08a03052", "imm2": "0x0204f0ba", "rot": 26, "bit": 5, "mask": 2},
{"i": 161, "op": "mad", "dst": 3, "src": 0, "src2": 7, "imm": "0xa0603b0e", "imm2": "0x7eee83d5", "rot": 28, "bit": 22, "mask": 16},
{"i": 162, "op": "rotr", "dst": 3, "src": 1, "src2": 6, "imm": "0x78a3c69d", "imm2": "0x684693a0", "rot": 21, "bit": 23, "mask": 4},
{"i": 163, "op": "add", "dst": 4, "src": 0, "src2": 7, "imm": "0xf1c46574", "imm2": "0x8e481727", "rot": 9, "bit": 3, "mask": 4},
{"i": 164, "op": "mulhi", "dst": 0, "src": 4, "src2": 3, "imm": "0x04644afa", "imm2": "0x64bda2b5", "rot": 26, "bit": 16, "mask": 16},
{"i": 165, "op": "add", "dst": 2, "src": 6, "src2": 2, "imm": "0xac578137", "imm2": "0x550ab406", "rot": 13, "bit": 20, "mask": 16},
{"i": 166, "op": "rotl", "dst": 0, "src": 4, "src2": 5, "imm": "0x7f564760", "imm2": "0xb9a8b4f8", "rot": 13, "bit": 29, "mask": 1},
{"i": 167, "op": "add", "dst": 3, "src": 1, "src2": 0, "imm": "0xa33e6706", "imm2": "0xaebb5966", "rot": 12, "bit": 14, "mask": 16},
{"i": 168, "op": "or", "dst": 3, "src": 5, "src2": 3, "imm": "0x65b2f3eb", "imm2": "0xb1d00d20", "rot": 12, "bit": 2, "mask": 8},
{"i": 169, "op": "rotr", "dst": 6, "src": 2, "src2": 3, "imm": "0x7f21faf5", "imm2": "0xbbf0d3f9", "rot": 17, "bit": 13, "mask": 8},
{"i": 170, "op": "xor", "dst": 4, "src": 6, "src2": 2, "imm": "0x162c7140", "imm2": "0x90d404ad", "rot": 26, "bit": 1, "mask": 4},
{"i": 171, "op": "sub", "dst": 6, "src": 1, "src2": 7, "imm": "0x6ef9c76e", "imm2": "0xfb7ba272", "rot": 31, "bit": 25, "mask": 1},
{"i": 172, "op": "rotl", "dst": 7, "src": 5, "src2": 4, "imm": "0xde04eb3b", "imm2": "0xd56caa00", "rot": 22, "bit": 21, "mask": 4},
{"i": 173, "op": "rotl", "dst": 5, "src": 3, "src2": 5, "imm": "0xa9eac934", "imm2": "0x2c338e51", "rot": 15, "bit": 22, "mask": 2},
{"i": 174, "op": "shfl", "dst": 7, "src": 0, "src2": 3, "imm": "0x700be4e3", "imm2": "0x4bcfc732", "rot": 19, "bit": 6, "mask": 8},
{"i": 175, "op": "xor", "dst": 0, "src": 5, "src2": 1, "imm": "0x02ccdba9", "imm2": "0xd0915be0", "rot": 15, "bit": 2, "mask": 16},
{"i": 176, "op": "rotl", "dst": 7, "src": 4, "src2": 1, "imm": "0x489c8165", "imm2": "0xf24b5a4f", "rot": 6, "bit": 22, "mask": 1},
{"i": 177, "op": "sub", "dst": 7, "src": 0, "src2": 6, "imm": "0x23ad9693", "imm2": "0x9a8c2f7b", "rot": 24, "bit": 2, "mask": 2},
{"i": 178, "op": "rotl", "dst": 3, "src": 0, "src2": 6, "imm": "0xafa72a42", "imm2": "0x371d74ee", "rot": 30, "bit": 16, "mask": 1},
{"i": 179, "op": "mad", "dst": 7, "src": 6, "src2": 1, "imm": "0x18a2a3f3", "imm2": "0xb811b951", "rot": 2, "bit": 9, "mask": 2},
{"i": 180, "op": "rotl", "dst": 6, "src": 4, "src2": 1, "imm": "0xe6c69c0e", "imm2": "0xfc46a951", "rot": 9, "bit": 31, "mask": 4},
{"i": 181, "op": "xor", "dst": 2, "src": 4, "src2": 7, "imm": "0xbd1b89e4", "imm2": "0xdf4bce5c", "rot": 15, "bit": 19, "mask": 4},
{"i": 182, "op": "xor", "dst": 2, "src": 7, "src2": 5, "imm": "0x3dd12aed", "imm2": "0xd0756a69", "rot": 13, "bit": 16, "mask": 4},
{"i": 183, "op": "xor", "dst": 7, "src": 2, "src2": 3, "imm": "0x77ce69d6", "imm2": "0x2b39bdf2", "rot": 8, "bit": 22, "mask": 16},
{"i": 184, "op": "add", "dst": 1, "src": 2, "src2": 4, "imm": "0xd94d55ac", "imm2": "0x5bb7550f", "rot": 31, "bit": 21, "mask": 1},
{"i": 185, "op": "or", "dst": 3, "src": 5, "src2": 6, "imm": "0x7b1ce846", "imm2": "0xcc3b8509", "rot": 28, "bit": 9, "mask": 4},
{"i": 186, "op": "mulhi", "dst": 6, "src": 3, "src2": 0, "imm": "0xa5e24690", "imm2": "0x2200ba81", "rot": 26, "bit": 10, "mask": 16},
{"i": 187, "op": "or", "dst": 4, "src": 0, "src2": 3, "imm": "0xf6efe759", "imm2": "0xae1f7118", "rot": 19, "bit": 20, "mask": 4},
{"i": 188, "op": "shfl", "dst": 7, "src": 1, "src2": 5, "imm": "0xdb318b45", "imm2": "0xcec459c9", "rot": 20, "bit": 11, "mask": 2},
{"i": 189, "op": "add", "dst": 6, "src": 5, "src2": 1, "imm": "0x89e747fe", "imm2": "0x2a354e2d", "rot": 22, "bit": 6, "mask": 1},
{"i": 190, "op": "xor", "dst": 1, "src": 4, "src2": 2, "imm": "0xc379e617", "imm2": "0x75e9d63b", "rot": 23, "bit": 3, "mask": 2},
{"i": 191, "op": "mulhi", "dst": 7, "src": 4, "src2": 3, "imm": "0x5a710287", "imm2": "0x7fe4ead6", "rot": 10, "bit": 25, "mask": 4},
{"i": 192, "op": "rotl", "dst": 2, "src": 1, "src2": 2, "imm": "0x4d5e59a3", "imm2": "0x1e4fef28", "rot": 26, "bit": 0, "mask": 1},
{"i": 193, "op": "rotl", "dst": 5, "src": 3, "src2": 7, "imm": "0x7444c47d", "imm2": "0xdad5f8be", "rot": 8, "bit": 30, "mask": 2},
{"i": 194, "op": "shfl", "dst": 4, "src": 5, "src2": 7, "imm": "0x6a225bbb", "imm2": "0xd6532cd7", "rot": 13, "bit": 17, "mask": 16},
{"i": 195, "op": "xor", "dst": 4, "src": 5, "src2": 3, "imm": "0x68344b9a", "imm2": "0xcb46a38b", "rot": 1, "bit": 27, "mask": 16},
{"i": 196, "op": "mul", "dst": 1, "src": 3, "src2": 4, "imm": "0xbebf7359", "imm2": "0x3f0890ba", "rot": 18, "bit": 12, "mask": 4},
{"i": 197, "op": "add", "dst": 5, "src": 2, "src2": 3, "imm": "0xea03e8e7", "imm2": "0x10cfdc71", "rot": 31, "bit": 7, "mask": 8},
{"i": 198, "op": "add", "dst": 7, "src": 5, "src2": 1, "imm": "0xa7ee0102", "imm2": "0x66e148d3", "rot": 12, "bit": 15, "mask": 1},
{"i": 199, "op": "sub", "dst": 5, "src": 2, "src2": 4, "imm": "0xc215584e", "imm2": "0x55fce30f", "rot": 30, "bit": 9, "mask": 2},
{"i": 200, "op": "shfl", "dst": 5, "src": 1, "src2": 1, "imm": "0x308f8358", "imm2": "0x489f1f93", "rot": 13, "bit": 13, "mask": 2},
{"i": 201, "op": "shfl", "dst": 7, "src": 1, "src2": 5, "imm": "0x713f1957", "imm2": "0x2239f757", "rot": 15, "bit": 7, "mask": 8},
{"i": 202, "op": "rotr", "dst": 4, "src": 5, "src2": 1, "imm": "0xb037b6e7", "imm2": "0x49a8b528", "rot": 27, "bit": 13, "mask": 16},
{"i": 203, "op": "xor", "dst": 7, "src": 5, "src2": 1, "imm": "0x56110241", "imm2": "0xefc8386d", "rot": 22, "bit": 20, "mask": 1},
{"i": 204, "op": "xor", "dst": 7, "src": 0, "src2": 0, "imm": "0x0827fcc7", "imm2": "0xf4f5dd07", "rot": 13, "bit": 7, "mask": 2},
{"i": 205, "op": "add", "dst": 6, "src": 2, "src2": 0, "imm": "0x8379a4de", "imm2": "0x8558b619", "rot": 26, "bit": 10, "mask": 1},
{"i": 206, "op": "rotl", "dst": 4, "src": 3, "src2": 3, "imm": "0x091ceef0", "imm2": "0x69b0f72f", "rot": 13, "bit": 7, "mask": 1},
{"i": 207, "op": "mulhi", "dst": 1, "src": 3, "src2": 4, "imm": "0x758edac1", "imm2": "0x98dd2f21", "rot": 15, "bit": 9, "mask": 1},
{"i": 208, "op": "mad", "dst": 1, "src": 4, "src2": 4, "imm": "0x78871a1a", "imm2": "0x5e14e1c8", "rot": 19, "bit": 6, "mask": 2},
{"i": 209, "op": "shfl", "dst": 2, "src": 0, "src2": 2, "imm": "0xf7e0b9aa", "imm2": "0xaecfd347", "rot": 21, "bit": 9, "mask": 4},
{"i": 210, "op": "add", "dst": 7, "src": 0, "src2": 7, "imm": "0xaa8cb14e", "imm2": "0xf4049c4c", "rot": 24, "bit": 11, "mask": 8},
{"i": 211, "op": "shfl", "dst": 7, "src": 1, "src2": 6, "imm": "0xc230d919", "imm2": "0xf76d08fb", "rot": 21, "bit": 13, "mask": 16},
{"i": 212, "op": "xor", "dst": 1, "src": 0, "src2": 2, "imm": "0x31a5af90", "imm2": "0x7eef58ee", "rot": 9, "bit": 12, "mask": 4},
{"i": 213, "op": "rotl", "dst": 7, "src": 1, "src2": 6, "imm": "0x0db26138", "imm2": "0x8e3c31f9", "rot": 3, "bit": 26, "mask": 2},
{"i": 214, "op": "rotr", "dst": 4, "src": 7, "src2": 3, "imm": "0x29558100", "imm2": "0xe4b13ad6", "rot": 29, "bit": 24, "mask": 8},
{"i": 215, "op": "shfl", "dst": 3, "src": 2, "src2": 6, "imm": "0x1b48c3d0", "imm2": "0x5c674ff6", "rot": 5, "bit": 9, "mask": 16},
{"i": 216, "op": "or", "dst": 5, "src": 1, "src2": 0, "imm": "0xef768632", "imm2": "0x6de9d10d", "rot": 10, "bit": 4, "mask": 4},
{"i": 217, "op": "sub", "dst": 1, "src": 2, "src2": 5, "imm": "0x88ca7f5a", "imm2": "0x24718a36", "rot": 18, "bit": 31, "mask": 1},
{"i": 218, "op": "sub", "dst": 6, "src": 5, "src2": 0, "imm": "0xc4a06728", "imm2": "0xdc2a4fd8", "rot": 9, "bit": 9, "mask": 2},
{"i": 219, "op": "rotl", "dst": 6, "src": 5, "src2": 7, "imm": "0xb7489e47", "imm2": "0xf13795c5", "rot": 4, "bit": 3, "mask": 8},
{"i": 220, "op": "mulhi", "dst": 2, "src": 0, "src2": 2, "imm": "0x873cd31b", "imm2": "0x3dfbc55d", "rot": 12, "bit": 23, "mask": 8},
{"i": 221, "op": "or", "dst": 2, "src": 0, "src2": 3, "imm": "0xdc21f099", "imm2": "0xee06f01e", "rot": 2, "bit": 17, "mask": 8},
{"i": 222, "op": "shfl", "dst": 5, "src": 2, "src2": 6, "imm": "0x36def499", "imm2": "0xa2849d59", "rot": 23, "bit": 4, "mask": 8},
{"i": 223, "op": "mulhi", "dst": 5, "src": 6, "src2": 7, "imm": "0xfb95fbca", "imm2": "0xc1aac427", "rot": 14, "bit": 11, "mask": 2},
{"i": 224, "op": "sub", "dst": 0, "src": 6, "src2": 7, "imm": "0x3d9d29c4", "imm2": "0x34d0dcc0", "rot": 17, "bit": 6, "mask": 4},
{"i": 225, "op": "rotl", "dst": 7, "src": 0, "src2": 5, "imm": "0x93b01b8e", "imm2": "0xfe1d75ac", "rot": 23, "bit": 15, "mask": 1},
{"i": 226, "op": "or", "dst": 4, "src": 2, "src2": 4, "imm": "0xfed76e8e", "imm2": "0x1c24ecd8", "rot": 2, "bit": 6, "mask": 16},
{"i": 227, "op": "mul", "dst": 2, "src": 4, "src2": 1, "imm": "0x5795f5b0", "imm2": "0x0566ea2a", "rot": 6, "bit": 28, "mask": 4},
{"i": 228, "op": "rotl", "dst": 3, "src": 0, "src2": 2, "imm": "0x8c8486de", "imm2": "0xd066aa8f", "rot": 12, "bit": 20, "mask": 1},
{"i": 229, "op": "rotr", "dst": 0, "src": 4, "src2": 0, "imm": "0x23a3e882", "imm2": "0xaca23902", "rot": 5, "bit": 22, "mask": 16},
{"i": 230, "op": "add", "dst": 0, "src": 6, "src2": 4, "imm": "0x1d176220", "imm2": "0x2a7fecb2", "rot": 20, "bit": 16, "mask": 2},
{"i": 231, "op": "shfl", "dst": 1, "src": 2, "src2": 0, "imm": "0x91172787", "imm2": "0xc5d7af28", "rot": 3, "bit": 24, "mask": 4},
{"i": 232, "op": "mul", "dst": 2, "src": 1, "src2": 2, "imm": "0x0be68835", "imm2": "0xde692bdb", "rot": 30, "bit": 17, "mask": 1},
{"i": 233, "op": "mad", "dst": 7, "src": 0, "src2": 1, "imm": "0xf90d2db5", "imm2": "0x96c4c175", "rot": 28, "bit": 7, "mask": 4},
{"i": 234, "op": "rotl", "dst": 5, "src": 2, "src2": 1, "imm": "0x16379736", "imm2": "0x6973b905", "rot": 22, "bit": 17, "mask": 4},
{"i": 235, "op": "rotr", "dst": 4, "src": 6, "src2": 2, "imm": "0x84292a13", "imm2": "0x0f897740", "rot": 12, "bit": 6, "mask": 8},
{"i": 236, "op": "mad", "dst": 0, "src": 5, "src2": 1, "imm": "0xeb7de837", "imm2": "0x64f0c302", "rot": 4, "bit": 19, "mask": 1},
{"i": 237, "op": "xor", "dst": 6, "src": 4, "src2": 4, "imm": "0x6ab4b683", "imm2": "0x20f17adb", "rot": 1, "bit": 0, "mask": 16},
{"i": 238, "op": "xor", "dst": 4, "src": 6, "src2": 1, "imm": "0x5836b35c", "imm2": "0x3293cc4a", "rot": 16, "bit": 22, "mask": 16},
{"i": 239, "op": "rotl", "dst": 6, "src": 1, "src2": 6, "imm": "0x769d8bc0", "imm2": "0xdc86c9cc", "rot": 18, "bit": 27, "mask": 16},
{"i": 240, "op": "add", "dst": 4, "src": 7, "src2": 1, "imm": "0x17dafb4d", "imm2": "0xadce39f3", "rot": 12, "bit": 25, "mask": 8},
{"i": 241, "op": "sub", "dst": 0, "src": 7, "src2": 4, "imm": "0xd4690bda", "imm2": "0xdab9b27b", "rot": 30, "bit": 21, "mask": 1},
{"i": 242, "op": "rotr", "dst": 1, "src": 6, "src2": 2, "imm": "0x670a2d0a", "imm2": "0x0612e33c", "rot": 31, "bit": 25, "mask": 2},
{"i": 243, "op": "add", "dst": 3, "src": 0, "src2": 2, "imm": "0xf2f77d26", "imm2": "0x0e7033b6", "rot": 27, "bit": 29, "mask": 1},
{"i": 244, "op": "mad", "dst": 2, "src": 7, "src2": 4, "imm": "0xa9eefc9d", "imm2": "0x16166c85", "rot": 18, "bit": 23, "mask": 16},
{"i": 245, "op": "mad", "dst": 4, "src": 0, "src2": 6, "imm": "0xb26f6c0f", "imm2": "0x0630e821", "rot": 23, "bit": 30, "mask": 4},
{"i": 246, "op": "mul", "dst": 5, "src": 7, "src2": 2, "imm": "0x269ce4bf", "imm2": "0x1ce28d32", "rot": 30, "bit": 15, "mask": 16},
{"i": 247, "op": "add", "dst": 3, "src": 5, "src2": 0, "imm": "0xfed2da4e", "imm2": "0x7b2ff6b7", "rot": 25, "bit": 31, "mask": 2},
{"i": 248, "op": "add", "dst": 0, "src": 7, "src2": 5, "imm": "0x03b2891c", "imm2": "0xb5fad7b1", "rot": 2, "bit": 0, "mask": 4},
{"i": 249, "op": "mulhi", "dst": 5, "src": 4, "src2": 6, "imm": "0xa69a1e71", "imm2": "0x15f0c0ea", "rot": 4, "bit": 1, "mask": 4},
{"i": 250, "op": "add", "dst": 5, "src": 2, "src2": 3, "imm": "0x042cd6e3", "imm2": "0xa7e71c2f", "rot": 24, "bit": 11, "mask": 8},
{"i": 251, "op": "shfl", "dst": 6, "src": 1, "src2": 2, "imm": "0x89c6b683", "imm2": "0x10bbf661", "rot": 24, "bit": 5, "mask": 1},
{"i": 252, "op": "xor", "dst": 6, "src": 1, "src2": 3, "imm": "0x265c66d6", "imm2": "0xd4a689ed", "rot": 6, "bit": 14, "mask": 8},
{"i": 253, "op": "mul", "dst": 2, "src": 5, "src2": 5, "imm": "0x890b8201", "imm2": "0x97c36bf3", "rot": 17, "bit": 22, "mask": 4},
{"i": 254, "op": "add", "dst": 0, "src": 6, "src2": 0, "imm": "0x784a302b", "imm2": "0xb83d78de", "rot": 27, "bit": 16, "mask": 4},
{"i": 255, "op": "sub", "dst": 2, "src": 4, "src2": 0, "imm": "0x817adb38", "imm2": "0xf3a3534b", "rot": 7, "bit": 22, "mask": 4}
]},
"instructions": [
{"i": 0, "op": "mad", "dst": 2, "src": 3, "src2": 4, "imm": "0xbf7b174d", "imm2": "0x337b762e", "rot": 17, "bit": 2, "mask": 2, "width": 1},
{"i": 1, "op": "mad", "dst": 2, "src": 1, "src2": 1, "imm": "0xdd04a5da", "imm2": "0x42da7657", "rot": 15, "bit": 30, "mask": 16, "width": 1},
{"i": 2, "op": "mad", "dst": 2, "src": 3, "src2": 2, "imm": "0x734003fa", "imm2": "0x5bb67700", "rot": 3, "bit": 20, "mask": 1, "width": 1},
{"i": 3, "op": "xor", "dst": 3, "src": 5, "src2": 5, "imm": "0xc55a1b1c", "imm2": "0xa19720f3", "rot": 7, "bit": 8, "mask": 1, "width": 1},
{"i": 4, "op": "load", "dst": 7, "src": 2, "src2": 5, "imm": "0xad572dd7", "imm2": "0x9ceb3ea7", "rot": 18, "bit": 30, "mask": 2, "width": 1},
{"i": 5, "op": "load", "dst": 5, "src": 7, "src2": 3, "imm": "0x769a53be", "imm2": "0x80f9067e", "rot": 12, "bit": 22, "mask": 1, "width": 1},
{"i": 6, "op": "shfl", "dst": 1, "src": 4, "src2": 0, "imm": "0xd3613d88", "imm2": "0x262fb219", "rot": 10, "bit": 30, "mask": 8, "width": 1},
{"i": 7, "op": "shfl", "dst": 7, "src": 3, "src2": 4, "imm": "0xce38e42f", "imm2": "0xb868b818", "rot": 11, "bit": 8, "mask": 8, "width": 1},
{"i": 8, "op": "mulhi", "dst": 1, "src": 5, "src2": 2, "imm": "0xa5eebca5", "imm2": "0x5703a72b", "rot": 13, "bit": 13, "mask": 16, "width": 1},
{"i": 9, "op": "rotr", "dst": 6, "src": 3, "src2": 4, "imm": "0x17a5a9c7", "imm2": "0xdcfb93a1", "rot": 20, "bit": 27, "mask": 2, "width": 1},
{"i": 10, "op": "or", "dst": 3, "src": 4, "src2": 1, "imm": "0xccb7d785", "imm2": "0xc335364c", "rot": 14, "bit": 12, "mask": 4, "width": 1},
{"i": 11, "op": "load", "dst": 4, "src": 3, "src2": 2, "imm": "0x88cb9af3", "imm2": "0x4e7dc10d", "rot": 24, "bit": 17, "mask": 4, "width": 1},
{"i": 12, "op": "mulhi", "dst": 0, "src": 4, "src2": 4, "imm": "0x45374321", "imm2": "0x3cd91989", "rot": 11, "bit": 4, "mask": 2, "width": 1},
{"i": 13, "op": "add", "dst": 5, "src": 1, "src2": 2, "imm": "0xc7934706", "imm2": "0xd3177981", "rot": 16, "bit": 30, "mask": 2, "width": 1},
{"i": 14, "op": "load", "dst": 0, "src": 4, "src2": 3, "imm": "0xfd7f56bb", "imm2": "0x65e14f52", "rot": 13, "bit": 22, "mask": 2, "width": 1},
{"i": 15, "op": "sub", "dst": 2, "src": 4, "src2": 4, "imm": "0x35a80b49", "imm2": "0x060f2d13", "rot": 16, "bit": 20, "mask": 16, "width": 1},
{"i": 16, "op": "load", "dst": 2, "src": 0, "src2": 2, "imm": "0xae0a32c2", "imm2": "0x4c2a4cfe", "rot": 8, "bit": 31, "mask": 16, "width": 1},
{"i": 17, "op": "load", "dst": 7, "src": 2, "src2": 6, "imm": "0x82a84cc3", "imm2": "0x21a38d68", "rot": 15, "bit": 21, "mask": 2, "width": 1},
{"i": 18, "op": "shfl", "dst": 7, "src": 3, "src2": 3, "imm": "0xa3818806", "imm2": "0x8f66b5c8", "rot": 14, "bit": 6, "mask": 4, "width": 1},
{"i": 19, "op": "mul", "dst": 5, "src": 0, "src2": 1, "imm": "0xa00de107", "imm2": "0x77bfcaa5", "rot": 3, "bit": 10, "mask": 2, "width": 1},
{"i": 20, "op": "shfl", "dst": 3, "src": 4, "src2": 7, "imm": "0x1d2b8cab", "imm2": "0x80b4f9a2", "rot": 14, "bit": 25, "mask": 2, "width": 1},
{"i": 21, "op": "shfl", "dst": 2, "src": 4, "src2": 5, "imm": "0x3ac915d2", "imm2": "0x5fba7bc2", "rot": 16, "bit": 1, "mask": 16, "width": 1},
{"i": 22, "op": "mulhi", "dst": 6, "src": 2, "src2": 0, "imm": "0xdc3ec8fd", "imm2": "0x599e2fa3", "rot": 22, "bit": 3, "mask": 2, "width": 1},
{"i": 23, "op": "load", "dst": 6, "src": 1, "src2": 5, "imm": "0x2a6b16d5", "imm2": "0xd73e396f", "rot": 28, "bit": 29, "mask": 2, "width": 1},
{"i": 24, "op": "mul", "dst": 5, "src": 0, "src2": 7, "imm": "0x376d0223", "imm2": "0xe1c2169a", "rot": 4, "bit": 16, "mask": 16, "width": 1},
{"i": 25, "op": "rotl", "dst": 5, "src": 7, "src2": 3, "imm": "0x78ad8c60", "imm2": "0x6f5b77d5", "rot": 19, "bit": 11, "mask": 16, "width": 1},
{"i": 26, "op": "shfl", "dst": 7, "src": 6, "src2": 5, "imm": "0x93915b9f", "imm2": "0x1e61fb6b", "rot": 28, "bit": 23, "mask": 2, "width": 1},
{"i": 27, "op": "xor", "dst": 0, "src": 5, "src2": 7, "imm": "0x6378fe15", "imm2": "0x66c78f42", "rot": 12, "bit": 31, "mask": 8, "width": 1},
{"i": 28, "op": "xor", "dst": 0, "src": 4, "src2": 7, "imm": "0x20a57fda", "imm2": "0x088c848e", "rot": 16, "bit": 13, "mask": 4, "width": 1},
{"i": 29, "op": "sub", "dst": 3, "src": 0, "src2": 2, "imm": "0x49d95fd5", "imm2": "0x1a5f946a", "rot": 6, "bit": 12, "mask": 1, "width": 1},
{"i": 30, "op": "mul", "dst": 5, "src": 1, "src2": 7, "imm": "0x0a816217", "imm2": "0x405c4f73", "rot": 13, "bit": 27, "mask": 4, "width": 1},
{"i": 31, "op": "load", "dst": 7, "src": 2, "src2": 2, "imm": "0x09ed045e", "imm2": "0xd69c4715", "rot": 5, "bit": 9, "mask": 2, "width": 1},
{"i": 32, "op": "load", "dst": 1, "src": 0, "src2": 6, "imm": "0xeb79ea49", "imm2": "0xcc587f5a", "rot": 6, "bit": 8, "mask": 16, "width": 1},
{"i": 33, "op": "xor", "dst": 5, "src": 6, "src2": 1, "imm": "0x3027401e", "imm2": "0x5f20c27e", "rot": 18, "bit": 9, "mask": 2, "width": 1},
{"i": 34, "op": "load", "dst": 5, "src": 1, "src2": 3, "imm": "0x0e1cab07", "imm2": "0x09356c5b", "rot": 19, "bit": 31, "mask": 1, "width": 1},
{"i": 35, "op": "mulhi", "dst": 0, "src": 5, "src2": 2, "imm": "0x90e31357", "imm2": "0xabd32484", "rot": 26, "bit": 5, "mask": 8, "width": 1},
{"i": 36, "op": "shfl", "dst": 5, "src": 2, "src2": 5, "imm": "0xee9a955f", "imm2": "0x31b3faed", "rot": 8, "bit": 24, "mask": 4, "width": 1},
{"i": 37, "op": "load", "dst": 7, "src": 0, "src2": 7, "imm": "0x3ba2f832", "imm2": "0x1160dcd3", "rot": 4, "bit": 29, "mask": 1, "width": 1},
{"i": 38, "op": "add", "dst": 3, "src": 1, "src2": 7, "imm": "0x75ba2fad", "imm2": "0x230c005c", "rot": 4, "bit": 27, "mask": 1, "width": 1},
{"i": 39, "op": "shfl", "dst": 1, "src": 5, "src2": 3, "imm": "0xdbf37e75", "imm2": "0xb5ac1969", "rot": 30, "bit": 13, "mask": 4, "width": 1},
{"i": 40, "op": "xor", "dst": 2, "src": 5, "src2": 5, "imm": "0x47f136c5", "imm2": "0x06ce9153", "rot": 19, "bit": 10, "mask": 2, "width": 1},
{"i": 41, "op": "mad", "dst": 3, "src": 6, "src2": 3, "imm": "0xce13eff8", "imm2": "0x04cc1d55", "rot": 3, "bit": 1, "mask": 4, "width": 1},
{"i": 42, "op": "sub", "dst": 6, "src": 7, "src2": 1, "imm": "0x6a65ab71", "imm2": "0x8fbc1bcd", "rot": 4, "bit": 1, "mask": 8, "width": 1},
{"i": 43, "op": "xor", "dst": 7, "src": 0, "src2": 7, "imm": "0xdaeb4928", "imm2": "0xc0423027", "rot": 24, "bit": 11, "mask": 8, "width": 1},
{"i": 44, "op": "load", "dst": 1, "src": 7, "src2": 7, "imm": "0x778f01c9", "imm2": "0x28cedcea", "rot": 12, "bit": 4, "mask": 16, "width": 1},
{"i": 45, "op": "mul", "dst": 2, "src": 3, "src2": 2, "imm": "0xf4264f1b", "imm2": "0x0f627d56", "rot": 5, "bit": 28, "mask": 8, "width": 1},
{"i": 46, "op": "mulhi", "dst": 1, "src": 5, "src2": 1, "imm": "0xffb2147a", "imm2": "0xccde9b05", "rot": 13, "bit": 9, "mask": 2, "width": 1},
{"i": 47, "op": "sub", "dst": 4, "src": 3, "src2": 5, "imm": "0x73b36234", "imm2": "0x3f5d5997", "rot": 7, "bit": 18, "mask": 2, "width": 1},
{"i": 48, "op": "rotr", "dst": 2, "src": 6, "src2": 3, "imm": "0x3a4d9aa9", "imm2": "0x212bec7b", "rot": 4, "bit": 29, "mask": 16, "width": 1},
{"i": 49, "op": "load", "dst": 3, "src": 5, "src2": 2, "imm": "0x626f11df", "imm2": "0x56cd5bfd", "rot": 7, "bit": 1, "mask": 1, "width": 1},
{"i": 50, "op": "add", "dst": 1, "src": 5, "src2": 6, "imm": "0x81b8bc2c", "imm2": "0x1907970c", "rot": 28, "bit": 7, "mask": 4, "width": 1},
{"i": 51, "op": "mul", "dst": 0, "src": 2, "src2": 2, "imm": "0xa8848b30", "imm2": "0xef6ac348", "rot": 9, "bit": 15, "mask": 8, "width": 1},
{"i": 52, "op": "add", "dst": 0, "src": 2, "src2": 0, "imm": "0x4f92b968", "imm2": "0x699fd448", "rot": 22, "bit": 6, "mask": 4, "width": 1},
{"i": 53, "op": "add", "dst": 1, "src": 0, "src2": 2, "imm": "0x2bb965af", "imm2": "0x77b1520d", "rot": 2, "bit": 12, "mask": 8, "width": 1},
{"i": 54, "op": "rotl", "dst": 7, "src": 1, "src2": 0, "imm": "0x553e678b", "imm2": "0x3cc8eae0", "rot": 14, "bit": 20, "mask": 2, "width": 1},
{"i": 55, "op": "add", "dst": 3, "src": 7, "src2": 2, "imm": "0x7b0fe07a", "imm2": "0xa54c55a0", "rot": 10, "bit": 1, "mask": 1, "width": 1},
{"i": 56, "op": "load", "dst": 6, "src": 7, "src2": 4, "imm": "0x01eba9aa", "imm2": "0x2758c0f7", "rot": 14, "bit": 15, "mask": 4, "width": 1},
{"i": 57, "op": "rotr", "dst": 1, "src": 5, "src2": 2, "imm": "0x1f5267b3", "imm2": "0x236f5a27", "rot": 2, "bit": 31, "mask": 16, "width": 1},
{"i": 58, "op": "load", "dst": 5, "src": 4, "src2": 3, "imm": "0xa9954a9b", "imm2": "0x6a54d4e8", "rot": 11, "bit": 10, "mask": 16, "width": 1},
{"i": 59, "op": "load", "dst": 6, "src": 2, "src2": 4, "imm": "0x9923ff88", "imm2": "0x9357254e", "rot": 16, "bit": 1, "mask": 16, "width": 1},
{"i": 60, "op": "mad", "dst": 3, "src": 5, "src2": 0, "imm": "0xc0cc51a6", "imm2": "0x3fd7701b", "rot": 20, "bit": 1, "mask": 4, "width": 1},
{"i": 61, "op": "add", "dst": 5, "src": 7, "src2": 7, "imm": "0xaf9dd72d", "imm2": "0xad7493e7", "rot": 7, "bit": 31, "mask": 16, "width": 1},
{"i": 62, "op": "add", "dst": 4, "src": 6, "src2": 2, "imm": "0x89841d87", "imm2": "0x1e07c3d9", "rot": 6, "bit": 27, "mask": 1, "width": 1},
{"i": 63, "op": "rotl", "dst": 5, "src": 4, "src2": 2, "imm": "0xae210f8d", "imm2": "0x8e499ba4", "rot": 19, "bit": 9, "mask": 1, "width": 1}
]
}

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#include <metal_stdlib>
using namespace metal;
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
kernel void igneum_hash(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
{ uint x = nonce ^ SEEDW[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ SEEDW[1]; }
{ uint x = nonce ^ SEEDW[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ SEEDW[2]; }
{ uint x = nonce ^ SEEDW[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ SEEDW[3]; }
{ uint x = nonce ^ SEEDW[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ SEEDW[4]; }
{ uint x = nonce ^ SEEDW[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ SEEDW[5]; }
{ uint x = nonce ^ SEEDW[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ SEEDW[6]; }
{ uint x = nonce ^ SEEDW[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ SEEDW[7]; }
{ uint x = nonce ^ SEEDW[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ SEEDW[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + select(0x92199f99u, 0x8bc12da9u, ((sel >> 18u) & 1u) != 0u); // s0 add
r0 = r0 + r7 + select(0x8d72d3adu, 0x63079e5au, ((sel >> 26u) & 1u) != 0u); // s1 add
r6 = r6 ^ simd_shuffle_xor(r3, (ushort)2); // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + select(0xb21b4babu, 0x5d4c7a60u, ((sel >> 31u) & 1u) != 0u); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + select(0x2fe0e98bu, 0xc88e2942u, ((sel >> 16u) & 1u) != 0u); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)4); // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
r2 = r2 ^ simd_shuffle_xor(r6, (ushort)4); // s12 shfl
r1 = r1 + r5 + select(0xbdf8f9a5u, 0xbc48c63eu, ((sel >> 25u) & 1u) != 0u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)8); // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + select(0x45c37cecu, 0x96e8f127u, ((sel >> 1u) & 1u) != 0u); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = mulhi(r6, r0); // s28 mulhi
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)2); // s29 shfl
r1 = r1 ^ simd_shuffle_xor(r6, (ushort)1); // s30 shfl
r1 = r1 + r6 + select(0x37985632u, 0xb1cdb2abu, ((sel >> 1u) & 1u) != 0u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // s33 shfl
r0 = r0 ^ simd_shuffle_xor(r3, (ushort)4); // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + select(0x804e777eu, 0x856e0180u, ((sel >> 0u) & 1u) != 0u); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + select(0x0b06c8a7u, 0xe9bd0cc4u, ((sel >> 2u) & 1u) != 0u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = mulhi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = mulhi(r4, r3); // s44 mulhi
r6 = r6 + r7 + select(0xee822e17u, 0xcdcb63f6u, ((sel >> 12u) & 1u) != 0u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
r4 = r4 ^ simd_shuffle_xor(r3, (ushort)8); // s47 shfl
r6 = mulhi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + select(0x3dfad1b6u, 0xd4758987u, ((sel >> 10u) & 1u) != 0u); // s56 add
r4 = r4 + r1 + select(0xfca75bc2u, 0x0602d6beu, ((sel >> 0u) & 1u) != 0u); // s57 add
r5 = mulhi(r5, r6); // s58 mulhi
r2 = r2 ^ simd_shuffle_xor(r1, (ushort)2); // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + select(0xd71c02ffu, 0x8596687au, ((sel >> 6u) & 1u) != 0u); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)2); // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + select(0x3c6fe15du, 0x08ac5733u, ((sel >> 0u) & 1u) != 0u); // s72 add
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)8); // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + select(0x295d5faeu, 0xc100b495u, ((sel >> 1u) & 1u) != 0u); // s77 add
r3 = mulhi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + select(0x274a9221u, 0x5cc59530u, ((sel >> 15u) & 1u) != 0u); // s81 add
r7 = r7 + r3 + select(0xc8651f8eu, 0x141479ecu, ((sel >> 5u) & 1u) != 0u); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
r2 = r2 ^ simd_shuffle_xor(r5, (ushort)16); // s85 shfl
r3 = r3 ^ r2; // s86 xor
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)2); // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + select(0x53f915c2u, 0x883c0c92u, ((sel >> 18u) & 1u) != 0u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + select(0xe2be00a5u, 0x3cc5bd20u, ((sel >> 31u) & 1u) != 0u); // s91 add
r7 = r7 ^ simd_shuffle_xor(r2, (ushort)1); // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + select(0x423fd9c9u, 0xbfd646cbu, ((sel >> 17u) & 1u) != 0u); // s101 add
r7 = r7 + r6 + select(0x8d3c011du, 0x19b74a43u, ((sel >> 11u) & 1u) != 0u); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + select(0x8ce14721u, 0x7dcb7e18u, ((sel >> 15u) & 1u) != 0u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = mulhi(r2, r0); // s109 mulhi
r1 = mulhi(r1, r0); // s110 mulhi
r0 = r0 + r2 + select(0x2d9fc6b9u, 0x3c179ad8u, ((sel >> 28u) & 1u) != 0u); // s111 add
r2 = mulhi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + select(0x502138e2u, 0x47359729u, ((sel >> 22u) & 1u) != 0u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = mulhi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
r4 = r4 ^ simd_shuffle_xor(r2, (ushort)2); // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
r7 = r7 ^ simd_shuffle_xor(r2, (ushort)4); // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + select(0x33dff776u, 0x6c57e4e7u, ((sel >> 15u) & 1u) != 0u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + select(0x5db25b34u, 0xe8212c0cu, ((sel >> 30u) & 1u) != 0u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = mulhi(r0, r5); // s138 mulhi
r2 = r2 + r7 + select(0x218d4090u, 0xd44ff710u, ((sel >> 10u) & 1u) != 0u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + select(0xf4b1a8deu, 0xb98942fau, ((sel >> 29u) & 1u) != 0u); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + select(0x2bef10f2u, 0x0d48ba42u, ((sel >> 17u) & 1u) != 0u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + select(0xdc5cc080u, 0xc98dea9cu, ((sel >> 30u) & 1u) != 0u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + select(0x18197438u, 0x6c752dcbu, ((sel >> 11u) & 1u) != 0u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + select(0xf1c46574u, 0x8e481727u, ((sel >> 3u) & 1u) != 0u); // s163 add
r0 = mulhi(r0, r4); // s164 mulhi
r2 = r2 + r6 + select(0xac578137u, 0x550ab406u, ((sel >> 20u) & 1u) != 0u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + select(0xa33e6706u, 0xaebb5966u, ((sel >> 14u) & 1u) != 0u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
r7 = r7 ^ simd_shuffle_xor(r0, (ushort)8); // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + select(0xd94d55acu, 0x5bb7550fu, ((sel >> 21u) & 1u) != 0u); // s184 add
r3 = r3 | r5; // s185 or
r6 = mulhi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)2); // s188 shfl
r6 = r6 + r5 + select(0x89e747feu, 0x2a354e2du, ((sel >> 6u) & 1u) != 0u); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = mulhi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
r4 = r4 ^ simd_shuffle_xor(r5, (ushort)16); // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + select(0xea03e8e7u, 0x10cfdc71u, ((sel >> 7u) & 1u) != 0u); // s197 add
r7 = r7 + r5 + select(0xa7ee0102u, 0x66e148d3u, ((sel >> 15u) & 1u) != 0u); // s198 add
r5 = r5 - r2; // s199 sub
r5 = r5 ^ simd_shuffle_xor(r1, (ushort)2); // s200 shfl
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)8); // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + select(0x8379a4deu, 0x8558b619u, ((sel >> 10u) & 1u) != 0u); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = mulhi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // s209 shfl
r7 = r7 + r0 + select(0xaa8cb14eu, 0xf4049c4cu, ((sel >> 11u) & 1u) != 0u); // s210 add
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)16); // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)16); // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = mulhi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)8); // s222 shfl
r5 = mulhi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + select(0x1d176220u, 0x2a7fecb2u, ((sel >> 16u) & 1u) != 0u); // s230 add
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)4); // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + select(0x17dafb4du, 0xadce39f3u, ((sel >> 25u) & 1u) != 0u); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + select(0xf2f77d26u, 0x0e7033b6u, ((sel >> 29u) & 1u) != 0u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + select(0xfed2da4eu, 0x7b2ff6b7u, ((sel >> 31u) & 1u) != 0u); // s247 add
r0 = r0 + r7 + select(0x03b2891cu, 0xb5fad7b1u, ((sel >> 0u) & 1u) != 0u); // s248 add
r5 = mulhi(r5, r4); // s249 mulhi
r5 = r5 + r2 + select(0x042cd6e3u, 0xa7e71c2fu, ((sel >> 11u) & 1u) != 0u); // s250 add
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)1); // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + select(0x784a302bu, 0xb83d78deu, ((sel >> 16u) & 1u) != 0u); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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#include <metal_stdlib>
using namespace metal;
#define MASK 0x0fffffffu
constant uint SEEDW[8] = { 0x67a9a7beu, 0x1a155b25u, 0xfddfb732u, 0x4b5af2e8u, 0xc55caf33u, 0xa27c13b7u, 0x06628a48u, 0x03852469u };
inline uint splitmix32(uint x) {
x ^= x >> 16; x *= 0x7feb352du;
x ^= x >> 15; x *= 0x846ca68bu;
x ^= x >> 16;
return x;
}
inline uint rotl_imm(uint x, uint n) { return (x << n) | (x >> (32u - n)); } // n in 1..31
inline uint rotr_var(uint x, uint n) { n &= 31u; return (x >> n) | (x << ((32u - n) & 31u)); }
inline uint ds_elem(uint i, uint d0, uint d1) {
uint x = i ^ d0;
x *= 0x9E3779B1u; x ^= x >> 15;
x += d1;
x *= 0x85EBCA77u; x ^= x >> 13;
x *= 0xC2B2AE3Du; x ^= x >> 16;
return x;
}
// Header-bound variant: the init words come from buffer 3 (bind.rs), not from SEEDW.
kernel void igneum_hash_bound(device const uint* dataset [[buffer(0)]],
device ulong* out [[buffer(1)]],
constant uint& baseNonce [[buffer(2)]],
constant uint* initw [[buffer(3)]],
uint gid [[thread_position_in_grid]]) {
uint nonce = baseNonce + gid;
uint r0, r1, r2, r3, r4, r5, r6, r7;
{ uint x = nonce ^ initw[0]; x += 0x9e3779b9u * 1u; x = splitmix32(x); r0 = x ^ initw[1]; }
{ uint x = nonce ^ initw[1]; x += 0x9e3779b9u * 2u; x = splitmix32(x); r1 = x ^ initw[2]; }
{ uint x = nonce ^ initw[2]; x += 0x9e3779b9u * 3u; x = splitmix32(x); r2 = x ^ initw[3]; }
{ uint x = nonce ^ initw[3]; x += 0x9e3779b9u * 4u; x = splitmix32(x); r3 = x ^ initw[4]; }
{ uint x = nonce ^ initw[4]; x += 0x9e3779b9u * 5u; x = splitmix32(x); r4 = x ^ initw[5]; }
{ uint x = nonce ^ initw[5]; x += 0x9e3779b9u * 6u; x = splitmix32(x); r5 = x ^ initw[6]; }
{ uint x = nonce ^ initw[6]; x += 0x9e3779b9u * 7u; x = splitmix32(x); r6 = x ^ initw[7]; }
{ uint x = nonce ^ initw[7]; x += 0x9e3779b9u * 8u; x = splitmix32(x); r7 = x ^ initw[0]; }
for (uint it = 0u; it < 8u; ++it) {
uint sel = r0;
r2 = r3 * r4 + r2; // 0
r2 = r1 * r1 + r2; // 1
r2 = r3 * r2 + r2; // 2
r3 = r3 ^ r5; // 3
r7 = r7 ^ dataset[r2 & MASK]; // 4
r5 = r5 ^ dataset[r7 & MASK]; // 5
r1 = r1 ^ simd_shuffle_xor(r4, (ushort)8); // 6
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)8); // 7
r1 = mulhi(r1, r5); // 8
r6 = rotr_var(r6, r3); // 9
r3 = r3 | r4; // 10
r4 = r4 ^ dataset[r3 & MASK]; // 11
r0 = mulhi(r0, r4); // 12
r5 = r5 + r1 + select(0xc7934706u, 0xd3177981u, ((sel >> 30u) & 1u) != 0u); // 13
r0 = r0 ^ dataset[r4 & MASK]; // 14
r2 = r2 - r4; // 15
r2 = r2 ^ dataset[r0 & MASK]; // 16
r7 = r7 ^ dataset[r2 & MASK]; // 17
r7 = r7 ^ simd_shuffle_xor(r3, (ushort)4); // 18
r5 = r5 * r0; // 19
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // 20
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)16); // 21
r6 = mulhi(r6, r2); // 22
r6 = r6 ^ dataset[r1 & MASK]; // 23
r5 = r5 * r0; // 24
r5 = rotl_imm(r5, 19u); // 25
r7 = r7 ^ simd_shuffle_xor(r6, (ushort)2); // 26
r0 = r0 ^ r5; // 27
r0 = r0 ^ r4; // 28
r3 = r3 - r0; // 29
r5 = r5 * r1; // 30
r7 = r7 ^ dataset[r2 & MASK]; // 31
r1 = r1 ^ dataset[r0 & MASK]; // 32
r5 = r5 ^ r6; // 33
r5 = r5 ^ dataset[r1 & MASK]; // 34
r0 = mulhi(r0, r5); // 35
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)4); // 36
r7 = r7 ^ dataset[r0 & MASK]; // 37
r3 = r3 + r1 + select(0x75ba2fadu, 0x230c005cu, ((sel >> 27u) & 1u) != 0u); // 38
r1 = r1 ^ simd_shuffle_xor(r5, (ushort)4); // 39
r2 = r2 ^ r5; // 40
r3 = r6 * r3 + r3; // 41
r6 = r6 - r7; // 42
r7 = r7 ^ r0; // 43
r1 = r1 ^ dataset[r7 & MASK]; // 44
r2 = r2 * r3; // 45
r1 = mulhi(r1, r5); // 46
r4 = r4 - r3; // 47
r2 = rotr_var(r2, r6); // 48
r3 = r3 ^ dataset[r5 & MASK]; // 49
r1 = r1 + r5 + select(0x81b8bc2cu, 0x1907970cu, ((sel >> 7u) & 1u) != 0u); // 50
r0 = r0 * r2; // 51
r0 = r0 + r2 + select(0x4f92b968u, 0x699fd448u, ((sel >> 6u) & 1u) != 0u); // 52
r1 = r1 + r0 + select(0x2bb965afu, 0x77b1520du, ((sel >> 12u) & 1u) != 0u); // 53
r7 = rotl_imm(r7, 14u); // 54
r3 = r3 + r7 + select(0x7b0fe07au, 0xa54c55a0u, ((sel >> 1u) & 1u) != 0u); // 55
r6 = r6 ^ dataset[r7 & MASK]; // 56
r1 = rotr_var(r1, r5); // 57
r5 = r5 ^ dataset[r4 & MASK]; // 58
r6 = r6 ^ dataset[r2 & MASK]; // 59
r3 = r5 * r0 + r3; // 60
r5 = r5 + r7 + select(0xaf9dd72du, 0xad7493e7u, ((sel >> 31u) & 1u) != 0u); // 61
r4 = r4 + r6 + select(0x89841d87u, 0x1e07c3d9u, ((sel >> 27u) & 1u) != 0u); // 62
r5 = rotl_imm(r5, 19u); // 63
// latency-shadow block (Counter ASIC 3.0 item 8): 256 ALU instructions x 27 passes after instruction 63, no load
for (uint sh = 0u; sh < 27u; ++sh) {
r5 = r5 + r2 + select(0x92199f99u, 0x8bc12da9u, ((sel >> 18u) & 1u) != 0u); // s0 add
r0 = r0 + r7 + select(0x8d72d3adu, 0x63079e5au, ((sel >> 26u) & 1u) != 0u); // s1 add
r6 = r6 ^ simd_shuffle_xor(r3, (ushort)2); // s2 shfl
r4 = r4 - r2; // s3 sub
r7 = r7 + r0 + select(0xb21b4babu, 0x5d4c7a60u, ((sel >> 31u) & 1u) != 0u); // s4 add
r0 = rotl_imm(r0, 11u); // s5 rotl
r0 = r0 + r1 + select(0x2fe0e98bu, 0xc88e2942u, ((sel >> 16u) & 1u) != 0u); // s6 add
r7 = r7 ^ r1; // s7 xor
r1 = r6 * r5 + r1; // s8 mad
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)4); // s9 shfl
r1 = r2 * r2 + r1; // s10 mad
r5 = r0 * r3 + r5; // s11 mad
r2 = r2 ^ simd_shuffle_xor(r6, (ushort)4); // s12 shfl
r1 = r1 + r5 + select(0xbdf8f9a5u, 0xbc48c63eu, ((sel >> 25u) & 1u) != 0u); // s13 add
r1 = rotl_imm(r1, 29u); // s14 rotl
r1 = r1 - r4; // s15 sub
r7 = r7 | r1; // s16 or
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)8); // s17 shfl
r7 = r7 ^ r4; // s18 xor
r6 = r6 * r1; // s19 mul
r5 = r6 * r0 + r5; // s20 mad
r3 = r3 - r1; // s21 sub
r6 = r6 * r0; // s22 mul
r2 = r2 + r0 + select(0x45c37cecu, 0x96e8f127u, ((sel >> 1u) & 1u) != 0u); // s23 add
r6 = r6 - r4; // s24 sub
r7 = r3 * r4 + r7; // s25 mad
r3 = rotl_imm(r3, 9u); // s26 rotl
r2 = r2 - r1; // s27 sub
r6 = mulhi(r6, r0); // s28 mulhi
r2 = r2 ^ simd_shuffle_xor(r4, (ushort)2); // s29 shfl
r1 = r1 ^ simd_shuffle_xor(r6, (ushort)1); // s30 shfl
r1 = r1 + r6 + select(0x37985632u, 0xb1cdb2abu, ((sel >> 1u) & 1u) != 0u); // s31 add
r0 = rotr_var(r0, r1); // s32 rotr
r3 = r3 ^ simd_shuffle_xor(r4, (ushort)2); // s33 shfl
r0 = r0 ^ simd_shuffle_xor(r3, (ushort)4); // s34 shfl
r7 = r7 * r0; // s35 mul
r3 = r3 + r1 + select(0x804e777eu, 0x856e0180u, ((sel >> 0u) & 1u) != 0u); // s36 add
r1 = r1 ^ r6; // s37 xor
r2 = r2 * r7; // s38 mul
r6 = r6 + r5 + select(0x0b06c8a7u, 0xe9bd0cc4u, ((sel >> 2u) & 1u) != 0u); // s39 add
r5 = r5 * r7; // s40 mul
r2 = mulhi(r2, r3); // s41 mulhi
r2 = r2 ^ r0; // s42 xor
r0 = rotl_imm(r0, 4u); // s43 rotl
r4 = mulhi(r4, r3); // s44 mulhi
r6 = r6 + r7 + select(0xee822e17u, 0xcdcb63f6u, ((sel >> 12u) & 1u) != 0u); // s45 add
r3 = r2 * r0 + r3; // s46 mad
r4 = r4 ^ simd_shuffle_xor(r3, (ushort)8); // s47 shfl
r6 = mulhi(r6, r5); // s48 mulhi
r0 = r0 - r2; // s49 sub
r3 = r3 - r5; // s50 sub
r1 = rotr_var(r1, r4); // s51 rotr
r6 = r7 * r7 + r6; // s52 mad
r5 = r5 ^ r3; // s53 xor
r1 = r1 - r0; // s54 sub
r5 = r5 - r6; // s55 sub
r3 = r3 + r2 + select(0x3dfad1b6u, 0xd4758987u, ((sel >> 10u) & 1u) != 0u); // s56 add
r4 = r4 + r1 + select(0xfca75bc2u, 0x0602d6beu, ((sel >> 0u) & 1u) != 0u); // s57 add
r5 = mulhi(r5, r6); // s58 mulhi
r2 = r2 ^ simd_shuffle_xor(r1, (ushort)2); // s59 shfl
r2 = rotl_imm(r2, 9u); // s60 rotl
r4 = r4 | r6; // s61 or
r6 = rotr_var(r6, r4); // s62 rotr
r2 = r2 * r4; // s63 mul
r0 = r0 ^ r5; // s64 xor
r2 = r2 ^ r7; // s65 xor
r2 = r2 + r1 + select(0xd71c02ffu, 0x8596687au, ((sel >> 6u) & 1u) != 0u); // s66 add
r1 = rotl_imm(r1, 21u); // s67 rotl
r3 = r3 * r2; // s68 mul
r7 = r7 ^ simd_shuffle_xor(r5, (ushort)2); // s69 shfl
r3 = r3 * r2; // s70 mul
r0 = r2 * r5 + r0; // s71 mad
r6 = r6 + r7 + select(0x3c6fe15du, 0x08ac5733u, ((sel >> 0u) & 1u) != 0u); // s72 add
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)8); // s73 shfl
r3 = r3 * r6; // s74 mul
r6 = r6 ^ r7; // s75 xor
r3 = r3 | r0; // s76 or
r2 = r2 + r4 + select(0x295d5faeu, 0xc100b495u, ((sel >> 1u) & 1u) != 0u); // s77 add
r3 = mulhi(r3, r7); // s78 mulhi
r4 = r4 | r1; // s79 or
r4 = rotr_var(r4, r3); // s80 rotr
r4 = r4 + r3 + select(0x274a9221u, 0x5cc59530u, ((sel >> 15u) & 1u) != 0u); // s81 add
r7 = r7 + r3 + select(0xc8651f8eu, 0x141479ecu, ((sel >> 5u) & 1u) != 0u); // s82 add
r3 = rotr_var(r3, r6); // s83 rotr
r2 = r4 * r7 + r2; // s84 mad
r2 = r2 ^ simd_shuffle_xor(r5, (ushort)16); // s85 shfl
r3 = r3 ^ r2; // s86 xor
r5 = r5 ^ simd_shuffle_xor(r7, (ushort)2); // s87 shfl
r0 = r0 ^ r4; // s88 xor
r3 = r3 + r2 + select(0x53f915c2u, 0x883c0c92u, ((sel >> 18u) & 1u) != 0u); // s89 add
r7 = rotr_var(r7, r5); // s90 rotr
r3 = r3 + r1 + select(0xe2be00a5u, 0x3cc5bd20u, ((sel >> 31u) & 1u) != 0u); // s91 add
r7 = r7 ^ simd_shuffle_xor(r2, (ushort)1); // s92 shfl
r6 = rotr_var(r6, r2); // s93 rotr
r7 = rotl_imm(r7, 14u); // s94 rotl
r4 = r5 * r5 + r4; // s95 mad
r2 = r4 * r5 + r2; // s96 mad
r1 = r1 ^ r0; // s97 xor
r5 = r5 * r4; // s98 mul
r2 = r2 - r0; // s99 sub
r7 = rotl_imm(r7, 30u); // s100 rotl
r5 = r5 + r6 + select(0x423fd9c9u, 0xbfd646cbu, ((sel >> 17u) & 1u) != 0u); // s101 add
r7 = r7 + r6 + select(0x8d3c011du, 0x19b74a43u, ((sel >> 11u) & 1u) != 0u); // s102 add
r5 = rotl_imm(r5, 6u); // s103 rotl
r0 = r0 * r4; // s104 mul
r0 = r0 | r5; // s105 or
r0 = r0 + r1 + select(0x8ce14721u, 0x7dcb7e18u, ((sel >> 15u) & 1u) != 0u); // s106 add
r0 = rotl_imm(r0, 15u); // s107 rotl
r4 = r4 - r2; // s108 sub
r2 = mulhi(r2, r0); // s109 mulhi
r1 = mulhi(r1, r0); // s110 mulhi
r0 = r0 + r2 + select(0x2d9fc6b9u, 0x3c179ad8u, ((sel >> 28u) & 1u) != 0u); // s111 add
r2 = mulhi(r2, r0); // s112 mulhi
r6 = r6 - r3; // s113 sub
r7 = r6 * r3 + r7; // s114 mad
r5 = rotr_var(r5, r1); // s115 rotr
r6 = rotr_var(r6, r4); // s116 rotr
r2 = r2 + r1 + select(0x502138e2u, 0x47359729u, ((sel >> 22u) & 1u) != 0u); // s117 add
r3 = r2 * r0 + r3; // s118 mad
r1 = r1 * r3; // s119 mul
r2 = r0 * r4 + r2; // s120 mad
r0 = r0 * r3; // s121 mul
r2 = mulhi(r2, r0); // s122 mulhi
r5 = r5 * r6; // s123 mul
r4 = r2 * r4 + r4; // s124 mad
r4 = r4 ^ simd_shuffle_xor(r2, (ushort)2); // s125 shfl
r2 = r2 ^ r0; // s126 xor
r1 = rotl_imm(r1, 7u); // s127 rotl
r7 = r7 ^ simd_shuffle_xor(r2, (ushort)4); // s128 shfl
r6 = rotl_imm(r6, 17u); // s129 rotl
r2 = r2 + r5 + select(0x33dff776u, 0x6c57e4e7u, ((sel >> 15u) & 1u) != 0u); // s130 add
r0 = r0 | r3; // s131 or
r5 = rotr_var(r5, r0); // s132 rotr
r2 = r2 + r3 + select(0x5db25b34u, 0xe8212c0cu, ((sel >> 30u) & 1u) != 0u); // s133 add
r4 = r4 ^ r3; // s134 xor
r6 = r6 ^ r1; // s135 xor
r1 = r1 - r7; // s136 sub
r2 = r6 * r2 + r2; // s137 mad
r0 = mulhi(r0, r5); // s138 mulhi
r2 = r2 + r7 + select(0x218d4090u, 0xd44ff710u, ((sel >> 10u) & 1u) != 0u); // s139 add
r1 = rotr_var(r1, r4); // s140 rotr
r3 = r3 ^ simd_shuffle_xor(r6, (ushort)1); // s141 shfl
r7 = r6 * r2 + r7; // s142 mad
r2 = r2 * r3; // s143 mul
r7 = r7 + r4 + select(0xf4b1a8deu, 0xb98942fau, ((sel >> 29u) & 1u) != 0u); // s144 add
r7 = rotl_imm(r7, 15u); // s145 rotl
r7 = r7 ^ r5; // s146 xor
r4 = r7 * r4 + r4; // s147 mad
r6 = rotr_var(r6, r5); // s148 rotr
r1 = r2 * r4 + r1; // s149 mad
r1 = r1 + r7 + select(0x2bef10f2u, 0x0d48ba42u, ((sel >> 17u) & 1u) != 0u); // s150 add
r5 = r5 ^ r4; // s151 xor
r7 = r7 + r0 + select(0xdc5cc080u, 0xc98dea9cu, ((sel >> 30u) & 1u) != 0u); // s152 add
r4 = r4 * r6; // s153 mul
r0 = r0 * r2; // s154 mul
r6 = r6 ^ r5; // s155 xor
r4 = rotr_var(r4, r2); // s156 rotr
r1 = rotl_imm(r1, 11u); // s157 rotl
r5 = r5 + r0 + select(0x18197438u, 0x6c752dcbu, ((sel >> 11u) & 1u) != 0u); // s158 add
r4 = r1 * r5 + r4; // s159 mad
r4 = rotl_imm(r4, 26u); // s160 rotl
r3 = r0 * r7 + r3; // s161 mad
r3 = rotr_var(r3, r1); // s162 rotr
r4 = r4 + r0 + select(0xf1c46574u, 0x8e481727u, ((sel >> 3u) & 1u) != 0u); // s163 add
r0 = mulhi(r0, r4); // s164 mulhi
r2 = r2 + r6 + select(0xac578137u, 0x550ab406u, ((sel >> 20u) & 1u) != 0u); // s165 add
r0 = rotl_imm(r0, 13u); // s166 rotl
r3 = r3 + r1 + select(0xa33e6706u, 0xaebb5966u, ((sel >> 14u) & 1u) != 0u); // s167 add
r3 = r3 | r5; // s168 or
r6 = rotr_var(r6, r2); // s169 rotr
r4 = r4 ^ r6; // s170 xor
r6 = r6 - r1; // s171 sub
r7 = rotl_imm(r7, 22u); // s172 rotl
r5 = rotl_imm(r5, 15u); // s173 rotl
r7 = r7 ^ simd_shuffle_xor(r0, (ushort)8); // s174 shfl
r0 = r0 ^ r5; // s175 xor
r7 = rotl_imm(r7, 6u); // s176 rotl
r7 = r7 - r0; // s177 sub
r3 = rotl_imm(r3, 30u); // s178 rotl
r7 = r6 * r1 + r7; // s179 mad
r6 = rotl_imm(r6, 9u); // s180 rotl
r2 = r2 ^ r4; // s181 xor
r2 = r2 ^ r7; // s182 xor
r7 = r7 ^ r2; // s183 xor
r1 = r1 + r2 + select(0xd94d55acu, 0x5bb7550fu, ((sel >> 21u) & 1u) != 0u); // s184 add
r3 = r3 | r5; // s185 or
r6 = mulhi(r6, r3); // s186 mulhi
r4 = r4 | r0; // s187 or
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)2); // s188 shfl
r6 = r6 + r5 + select(0x89e747feu, 0x2a354e2du, ((sel >> 6u) & 1u) != 0u); // s189 add
r1 = r1 ^ r4; // s190 xor
r7 = mulhi(r7, r4); // s191 mulhi
r2 = rotl_imm(r2, 26u); // s192 rotl
r5 = rotl_imm(r5, 8u); // s193 rotl
r4 = r4 ^ simd_shuffle_xor(r5, (ushort)16); // s194 shfl
r4 = r4 ^ r5; // s195 xor
r1 = r1 * r3; // s196 mul
r5 = r5 + r2 + select(0xea03e8e7u, 0x10cfdc71u, ((sel >> 7u) & 1u) != 0u); // s197 add
r7 = r7 + r5 + select(0xa7ee0102u, 0x66e148d3u, ((sel >> 15u) & 1u) != 0u); // s198 add
r5 = r5 - r2; // s199 sub
r5 = r5 ^ simd_shuffle_xor(r1, (ushort)2); // s200 shfl
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)8); // s201 shfl
r4 = rotr_var(r4, r5); // s202 rotr
r7 = r7 ^ r5; // s203 xor
r7 = r7 ^ r0; // s204 xor
r6 = r6 + r2 + select(0x8379a4deu, 0x8558b619u, ((sel >> 10u) & 1u) != 0u); // s205 add
r4 = rotl_imm(r4, 13u); // s206 rotl
r1 = mulhi(r1, r3); // s207 mulhi
r1 = r4 * r4 + r1; // s208 mad
r2 = r2 ^ simd_shuffle_xor(r0, (ushort)4); // s209 shfl
r7 = r7 + r0 + select(0xaa8cb14eu, 0xf4049c4cu, ((sel >> 11u) & 1u) != 0u); // s210 add
r7 = r7 ^ simd_shuffle_xor(r1, (ushort)16); // s211 shfl
r1 = r1 ^ r0; // s212 xor
r7 = rotl_imm(r7, 3u); // s213 rotl
r4 = rotr_var(r4, r7); // s214 rotr
r3 = r3 ^ simd_shuffle_xor(r2, (ushort)16); // s215 shfl
r5 = r5 | r1; // s216 or
r1 = r1 - r2; // s217 sub
r6 = r6 - r5; // s218 sub
r6 = rotl_imm(r6, 4u); // s219 rotl
r2 = mulhi(r2, r0); // s220 mulhi
r2 = r2 | r0; // s221 or
r5 = r5 ^ simd_shuffle_xor(r2, (ushort)8); // s222 shfl
r5 = mulhi(r5, r6); // s223 mulhi
r0 = r0 - r6; // s224 sub
r7 = rotl_imm(r7, 23u); // s225 rotl
r4 = r4 | r2; // s226 or
r2 = r2 * r4; // s227 mul
r3 = rotl_imm(r3, 12u); // s228 rotl
r0 = rotr_var(r0, r4); // s229 rotr
r0 = r0 + r6 + select(0x1d176220u, 0x2a7fecb2u, ((sel >> 16u) & 1u) != 0u); // s230 add
r1 = r1 ^ simd_shuffle_xor(r2, (ushort)4); // s231 shfl
r2 = r2 * r1; // s232 mul
r7 = r0 * r1 + r7; // s233 mad
r5 = rotl_imm(r5, 22u); // s234 rotl
r4 = rotr_var(r4, r6); // s235 rotr
r0 = r5 * r1 + r0; // s236 mad
r6 = r6 ^ r4; // s237 xor
r4 = r4 ^ r6; // s238 xor
r6 = rotl_imm(r6, 18u); // s239 rotl
r4 = r4 + r7 + select(0x17dafb4du, 0xadce39f3u, ((sel >> 25u) & 1u) != 0u); // s240 add
r0 = r0 - r7; // s241 sub
r1 = rotr_var(r1, r6); // s242 rotr
r3 = r3 + r0 + select(0xf2f77d26u, 0x0e7033b6u, ((sel >> 29u) & 1u) != 0u); // s243 add
r2 = r7 * r4 + r2; // s244 mad
r4 = r0 * r6 + r4; // s245 mad
r5 = r5 * r7; // s246 mul
r3 = r3 + r5 + select(0xfed2da4eu, 0x7b2ff6b7u, ((sel >> 31u) & 1u) != 0u); // s247 add
r0 = r0 + r7 + select(0x03b2891cu, 0xb5fad7b1u, ((sel >> 0u) & 1u) != 0u); // s248 add
r5 = mulhi(r5, r4); // s249 mulhi
r5 = r5 + r2 + select(0x042cd6e3u, 0xa7e71c2fu, ((sel >> 11u) & 1u) != 0u); // s250 add
r6 = r6 ^ simd_shuffle_xor(r1, (ushort)1); // s251 shfl
r6 = r6 ^ r1; // s252 xor
r2 = r2 * r5; // s253 mul
r0 = r0 + r6 + select(0x784a302bu, 0xb83d78deu, ((sel >> 16u) & 1u) != 0u); // s254 add
r2 = r2 - r4; // s255 sub
}
}
uint lo = r0 ^ rotl_imm(r1, 7u) ^ rotl_imm(r2, 14u) ^ rotl_imm(r3, 21u);
uint hi = r4 ^ rotl_imm(r5, 9u) ^ rotl_imm(r6, 18u) ^ rotl_imm(r7, 27u);
out[gid] = ((ulong)hi << 32) | (ulong)lo;
}

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