Chip text: the served sentence opens "adopts the 64-register window and retains it across every rotation" (the close's 10.0h after the site audit read); the card's cost of the window labelled measured (rented 5090 and 4090 at stock, 8 October 2026); the X35 pin follows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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@ -2335,7 +2335,7 @@ Evidence: `docs/design/latency-ladder.md` (the k column, the rung table at k = 0
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Status: Fixed, stated; restated (7 October 2026, evening, by order of the coordinator; the chip-text rewrite e57da45a, on master at 25f38035): the served texts give the floor and the premium at the 5090's measured knee: 2.1x per joule with a core as good as a GPU lane (k = 1), 3.4x with one three times better (k about 0.33), no core below about 1.8 pJ per op in the model's range, the premium 81.8 W at the best points, Ember Tune named as how a user gets there; the ledger pin for X35 moved to the new sentence; `site/litepaper.html#chip-model` and the home line.
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Status: Fixed, stated; restated (8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; `docs/design/class-v6-rotating-family.md` 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026, the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (`tools/ci/ledger-text-check.mjs`). Was: the 2.1x to 3.4x range at the 5090's knee, below.
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Status: Fixed, stated; restated (8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; `docs/design/class-v6-rotating-family.md` 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026 and the card's measured cost of the window (a rented 5090 and 4090 at stock, within 5 percent per load), the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (`tools/ci/ledger-text-check.mjs`). Was: the 2.1x to 3.4x range at the 5090's knee, below.
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### X36. The X9 described as a shipping chip
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"X34 and X35 said Bitmain's Antminer X9 'ships from July 2026' and called it 'the shipping RandomX chip'. It never shipped: Bitmain opened pre-orders on 26 December 2025 for July 2026 delivery, resellers told buyers in mid-May 2026 that Bitmain had discontinued it and refunded them, no unit was delivered and none was independently benchmarked."
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@ -186,7 +186,7 @@ Generated by `tools/ledger/export-public.mjs` from `docs/fud-ledger.md`; a gate
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| X32 | The roadmap carried calendar months beside a testnet that is weeks away | Fixed, stated | Every calendar month is out of the roadmap. | [site/litepaper.html](../site/litepaper.html) |
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| X33 | The public benchmark dated "January 2027" | Fixed, stated | Both sentences read "The public benchmark with a leaderboard ships with the public testnet." (`site/litepaper.html`, For miners and Questions miners ask). | [site/litepaper.html](../site/litepaper.html) |
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| X34 | RandomX described as chip-free | Fixed, stated | Four sentences corrected, each with the X9 as the stated fact and its date; every sentence that only names the technique stands. | [site/index.html](../site/index.html) |
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| X35 | The class v4 chip headline stated as one number, 2.1x | Fixed, stated; restated | The served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. | [docs/design/latency-ladder.md](../docs/design/latency-ladder.md) |
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| X35 | The class v4 chip headline stated as one number, 2.1x | Fixed, stated; restated | The served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every… | [docs/design/latency-ladder.md](../docs/design/latency-ladder.md) |
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| X36 | The X9 described as a shipping chip | Fixed, stated; restated | The X9 appears on the served pages only as a precedent (the pre-order, the withdrawal, no benchmark) and no served sentence uses its claimed core as a chip core against the model; the Antminer X5 is served as an… | [site/index.html](../site/index.html) |
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| X37 | The class v4 energy premium is a cost the user pays, not a line in a model | Answered with evidence | Measured on the RTX 5090, 145 W of premium unlocked and 82 W at the knee; the RTX 5080 at stock 84 W, its grid running; the team identity says the premium needed for 2x at k = 1 is 103 W at the lock and a premium of… | [docs/plans/counter-asic-3-status.md](../docs/plans/counter-asic-3-status.md) |
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| N1 | A 0.3.15 node on the live file wrote blocks every 0.3.14 node rejected | Fixed | The class v4 signal (PROPOSED, `docs/plans/counter-asic-3-node.md` section 6) is the producer's object version in the high byte of the header version; the first 0.3.15 build stamped it from the binary alone, so on the… | [infra/fast-time/node-compat.mjs](../infra/fast-time/node-compat.mjs) |
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@ -243,7 +243,7 @@
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<div class="derived"><p>Here are the limits, stated before anyone else states them.</p>
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<ul>
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<li><strong>A proof in seconds.</strong> Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.</li>
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<li><strong>A chip is impossible.</strong> No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
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<li><strong>A chip is impossible.</strong> No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
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<li><strong>A guaranteed income floor.</strong> No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.</li>
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<li><strong>A memory-hard prototype on every vendor.</strong> Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.</li>
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<li><strong>Finality in the first month.</strong> No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.</li>
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@ -257,7 +257,7 @@
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<div class="home-three rows">
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<div class="home-row"><span class="n">01</span><div><b>The same card finds the block and proves it.</b><p>Both jobs pay. When you stop, the card still games.</p></div></div>
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<div class="home-row"><span class="n">02</span><div><b>A fair start.</b><p>Nobody holds a coin before block one. The protocol carries no fee. The one payment to the project is the Ember software’s optional 1% dev fee, like other GPU miners, off with one flag.</p></div></div>
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<div class="home-row"><span class="n">03</span><div><b>Built for graphics cards.</b><p>Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. Modelled on measured cards (8 October 2026), the chip core synthesised and claimed; a 5090 locked at its knee pays 82 W for the class v4 shadow work (measured, 7 October 2026). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules.</a></p></div></div>
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<div class="home-row"><span class="n">03</span><div><b>Built for graphics cards.</b><p>Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. Modelled on measured cards (8 October 2026), the chip core synthesised and claimed; a 5090 locked at its knee pays 82 W for the class v4 shadow work (measured, 7 October 2026). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules.</a></p></div></div>
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</div>
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</div>
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</section>
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@ -1377,7 +1377,7 @@ blockquote{margin:10px 0;padding:10px 14px;border-left:3px solid var(--line-2);c
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<article class="entry" id="X35" data-bucket="Fixed or built">
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<div class="head"><span class="id">X35</span><h3>The class v4 chip headline stated as one number, 2.1x</h3><span class="date">8 October 2026</span></div>
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<blockquote>The home page said the strongest chip reaches 'about 2x once the lever now in its gates ships' and the litepaper said the latency-shadow work 'brings the chip to about 2x' and that its edge 'falls from 5.6x to 2.1x ... at a chip core equal to the GPU's'. That 2.1x assumes the chip's core costs what the GPU's does per operation (k = 1). Bitmain's Antminer X9 reached about a third of its honest device's energy on a latency-bound random program, so k about 0.33 is a shipped product class, and at that k the same model gives 3.9x.</blockquote>
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<div class="status"><span class="badge b-fixed-or-built">Fixed, stated; restated</span> <span class="did">8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; <code>a repository file</code> 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026, the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (<code>a repository file</code>). Was: the 2.1x to 3.4x range at the 5090's knee, below.</span></div>
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<div class="status"><span class="badge b-fixed-or-built">Fixed, stated; restated</span> <span class="did">8 October 2026, afternoon, by order of main after two accepted external reviews of the class v6 close; <code>a repository file</code> 10.0f to 10.0h): the served chip text is the review's sentence, verbatim on the home line, the litepaper's abstract, chip section and limits item, and the miner page: "Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment." Every number carries its label (2.2x to 2.4x modelled on the measured RTX 5080 and RTX 5090 lock rows of 8 October 2026 and the card's measured cost of the window (a rented 5090 and 4090 at stock, within 5 percent per load), the chip core synthesised on ASAP7 and scaled to N3, claimed, its memory modelled; 2.0x node for node modelled, k 1.09; the node column claimed scaling; the 32-lane rows pending beside it). The three statements (energy resistance, economic resistance, response capability) are served separate; the harness and the scoring rule are linked beside the sentence. Struck from every served page: the 2.1x and 3.4x launch line, the 5x to 9x baseline, the ladder's 2.8x row, the USD 100 M pay-back row and the k about 0.33 column; never served and not to be: the lifetime claim, the USD 300 M and 340 M lines, any chip-arrival probability, the 725d2945 sentence. The pins for X35 moved to the new sentence (<code>a repository file</code>). Was: the 2.1x to 3.4x range at the 5090's knee, below.</span></div>
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<details><summary>The answer as first written</summary><p>One number was the model's k = 1 column; the X9 made the k = 0.33 column a product rather than a claim, so the public figure is the range. Rung 2 of the ladder (the top admissible rung on 6 October 2026) takes the X9 bracket from about 3.9x to about 2.8x and does not close it; the ladder moves at the pace of the cards that pay for it (M34).</p></details>
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</article>
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<article class="entry" id="X36" data-bucket="Fixed or built">
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<article>
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<section id="abstract">
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<h2>Abstract</h2>
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<p class="lead">Igneum is a proof-of-work blockchain built for graphics cards, where NVIDIA cards also prove every block with zero-knowledge proofs and sell proving to other chains. Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. <a href="#chip-model">The chip model</a>: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.</p>
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<p class="lead">Igneum is a proof-of-work blockchain built for graphics cards, where NVIDIA cards also prove every block with zero-knowledge proofs and sell proving to other chains. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. <a href="#chip-model">The chip model</a>: every number labelled measured, modelled or claimed, the harness and the scoring rules beside it.</p>
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<p>It runs the Ethereum virtual machine, so anything built for Ethereum runs on Igneum unchanged. Transactions are included in about one second, proven within about a minute at launch, and locked by miners within about two. There is no premine, no pre-sale, no treasury taken from emission, no stake anywhere in consensus, and no dependence on any other chain. Mining stays open to anyone with a GPU because the mining program changes every hour, so a chip built for one program is useless for the next, and a chip for the whole program space is a GPU without the graphics parts. No scheduled human release is needed to keep it that way. Writing new code, including an emergency fix to the proof system, is the one thing that takes a person, and it activates only on miner signalling.</p>
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<div class="stats">
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<div class="stat"><div class="v">1 / s</div><div class="k">blocks, rising to 10</div></div>
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<p>Three ideas carry the chip resistance. <strong>The hash rewrites itself.</strong> A new program every hour, drawn from the chain. Its memory pattern changes with it. The rules change on a schedule fixed at launch. No release, no vote. These are automatic schedule changes: they defeat a chip wired for one datapath and they need no human fork. Against a chip that stores the dataset every drawn parameter is firmware, and what meets that chip is the latency-shadow work (class v4) and the price per joule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). <strong>It waits on memory, not maths.</strong> Every hash is a chain of random reads into a table too big for a chip to carry. Measured (8 October 2026; lane D’s family harness at the acceptance rule’s own 2^20 sample over 4,900 drawn eras, and the chained-cache pass’s reading of the night before): every hash’s 128 dependent reads land across the whole dataset and the distinct-index floor holds at 0.995 on every accepted program; about half of epochs carry one load site whose address bit at the era’s stride rotation is biased, which prices about 1.6 percent of a hash’s reads to a chip storing half the dataset and nothing to a chip storing all of it; the next class folds the product’s low bits before the rotation, so no era lands a biased bit on an address bit. The wait is the same physics for everyone. <strong>Miners hold the switch.</strong> Spare defences are written into the rules, switched off. A miner signal turns one on, at the class-change threshold: miners signal three things at three thresholds, 60 percent of blue blocks over two weeks for a parameter genesis leaves open, 90 percent for an upgrade (new code), and 95 percent with a floor height for a class change. No fork.</p>
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<p><strong>The work that waits can grow.</strong> Class v4 adds a block of latency-shadow arithmetic to every hash, about 100,000 integer operations that run while the memory reads are in flight, so a chip that stores the whole dataset still has to pay for a core. That size sits on a ladder fixed at genesis, six rungs from about 100,000 to about 1,000,000 operations, and it moves one rung at a time only when 90 percent of blue blocks in each of seven consecutive days ask for it; it can never move two rungs inside a week and never past a rung the reference verifier cannot check under 10 ms with its sibling thread busy (measured on the build server, 6 October 2026: the first three rungs pass at 8.8, 8.9 and 9.2 ms, the fourth misses by 0.08 ms on a loaded box and stays out until a quiet re-measurement, the two doublings are out at 12.4 and 15.0 ms). What it buys against a chip is scored under the rule in the chip model below. What it costs, per rung, is measured too: the Apple tier gives up 3 points of rate at the first step and 6 more at the second, the RTX 5090 nothing until the second; so the miners who pay for a step are the ones who take it (<a href="/ledger#M34">ledger M34</a>).</p>
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<h3 id="chip-model">The chip model</h3>
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<p>Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.</p>
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<p><b>The labels.</b> 2.2x to 2.4x is modelled. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026. The chip side is claimed: a synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors; the window’s k is synthesis-derived and not a lower bound. The chip’s memory is modelled: the GDDR7 board of the chip model. 2.0x on the GPU’s own node is modelled: the same core node for node (k 1.09). Pending beside the sentence: against a 32-lane window core the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node for node (synthesised; the re-optimised row is due on the evening of 8 October 2026 and is served when it lands).</p>
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<p>Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment.</p>
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<p><b>The labels.</b> 2.2x to 2.4x is modelled. The GPU side is measured: an RTX 5080 at its 1,100 MHz core lock, 2.06 microjoules per hash, and an RTX 5090 at its 1,300 MHz lock, 2.33 microjoules per hash, both under class v4, on the project’s own rigs and rented pods, 8 October 2026; the card’s cost of the window is measured too (a rented RTX 5090 and RTX 4090 at stock, 8 October 2026: within 5 percent per load with the liveness chain, no register spill). The chip side is synthesised and claimed: a synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on the foundry’s headline factors; the window’s k is synthesis-derived and not a lower bound. The chip’s memory is modelled: the GDDR7 board of the chip model. 2.0x on the GPU’s own node is modelled: the same core node for node (k 1.09). Pending beside the sentence: against a 32-lane window core the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node for node (synthesised; the re-optimised row is due on the evening of 8 October 2026 and is served when it lands).</p>
|
||||
<p>Three statements, kept separate.</p>
|
||||
<div class="tbl"><table><thead><tr><th>Statement</th><th>What it says</th><th>Label and date</th></tr></thead><tbody>
|
||||
<tr><td>Energy resistance</td><td>The figures above: 2.2x to 2.4x for the strongest specialised design a node ahead of the GPU tier; 2.0x on the GPU’s own node; 2.8x two nodes ahead, on the 8-lane core. The honest tier moves to the next node with every GPU generation; a chip must tape out again.</td><td>modelled on measured cards, 8 October 2026; the node column is claimed scaling</td></tr>
|
||||
|
|
@ -826,7 +826,7 @@ body.all .pager{display:none}
|
|||
<p>Here are the limits, stated before anyone else states them.</p>
|
||||
<ul>
|
||||
<li><strong>A proof in seconds.</strong> Not at launch. Proving a full block today needs a cluster of 100 to 200 consumer GPUs, approximate, so Igneum launches with proofs within about a minute and tightens as hardware improves. Users still see their transaction land in one second.</li>
|
||||
<li><strong>A chip is impossible.</strong> No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
|
||||
<li><strong>A chip is impossible.</strong> No. A chip wired for one program is a bad bet, because the program moves before it ships. A programmable chip is not stopped by the moving target: everything it needs is public at genesis and every drawn parameter is firmware to it (an address permute, a rotator, an immediate table), so the defence against it is the latency-shadow work (class v4) and the price per joule, not the schedule (the Horizon lane analysis, 6 October 2026, section 5.4; ledger M32). Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The labels: 2.2x to 2.4x modelled (the GPU side measured on the RTX 5080 and RTX 5090 at their core locks under class v4, 8 October 2026; the chip core synthesised on ASAP7 and scaled to N3, claimed; its memory modelled); 2.0x on the GPU’s own node modelled. Class v5 makes the dataset the chain’s own state, so a chip that stores it or recomputes it is wrong on every item (designed, 7 October 2026). The strongest recompute chip we can price, holding the whole 256 MiB cache on-die, reaches under 1x per chip against an RTX 5090 (the published model, 5 October 2026: 0.92x per unit of silicon with a 3x fixed-function allowance, approximate). Sources: the class v6 close, section 10 (8 October 2026); the ASIC history’s Ethash rows; the chip model analysis (6 October 2026). No hash has stayed free of chips forever; Igneum does not claim to. Monero’s RandomX has held its miners on commodity hardware for about seven years: one chip shipped against it, Bitmain’s Antminer X5 (September 2023), an observed comparison, not a ceiling; the one announced beyond it, the Antminer X9, was withdrawn in mid-May 2026 before any unit shipped, its claimed core never measured; RandomX v2 was released on 25 March 2026 with its activation pending. That record says nothing about the price of a chip with the 256 MB cache on its die; that price is a cost model, not a measurement.</li>
|
||||
<li><strong>A guaranteed income floor.</strong> No. External proving is a small market today. Igneum's miners' electricity cost in it is close to power, but the price they must charge is the subsidy they forgo, which falls as one over network hash: an edge at scale and nothing more.</li>
|
||||
<li><strong>A memory-hard prototype on every vendor.</strong> Not yet. The 256 MB cache closed the shortcut on Apple silicon (computing items runs 4.8x slower than loading them, measured 3 October 2026). The same ratio on NVIDIA and on a discrete AMD card is Open.</li>
|
||||
<li><strong>Finality in the first month.</strong> No. No checkpoint locks until the 30-day window has 30 days of history. The first month of mainnet is proof of work with a 12-hour depth, and the text above says so wherever a day count appears.</li>
|
||||
|
|
|
|||
|
|
@ -327,7 +327,7 @@ pre b{color:var(--molten-text);font-weight:500}
|
|||
</tbody>
|
||||
</table></div>
|
||||
<p class="fair"><b>Graphics cards only.</b> A new mining program every hour, so no chip is built for it. 80% of every block to the card that finds it, 20% to the cards that prove it. No premine, no stake, no fee to any team. Every number above has a row in <a href="/miners">the bench table</a>.</p>
|
||||
<p class="fair">Your card against the strongest chip we can price. Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: an RTX 5080 and an RTX 5090 at their core locks under class v4 (8 October 2026); the chip core is synthesised and claimed; its memory is modelled. Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules</a>.</p>
|
||||
<p class="fair">Your card against the strongest chip we can price. Class v6 adopts the 64-register window and retains it across every rotation. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment. The GPU side is measured: an RTX 5080 and an RTX 5090 at their core locks under class v4 (8 October 2026); the chip core is synthesised and claimed; its memory is modelled. Under class v5 the chip is wrong on every item because the dataset is the chain’s own state (designed). <a href="/litepaper#chip-model">Every number with its label, the harness and the scoring rules</a>.</p>
|
||||
</div>
|
||||
</section>
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ const REQUIRED = {
|
|||
['C2', 'Monero has run on RandomX since November 2019'],
|
||||
['X34', 'was withdrawn in mid-May 2026 before any unit shipped; RandomX 2.0 shipped on 25 March 2026'],
|
||||
['X36', 'Bitmain opened Antminer X9 pre-orders on 26 December 2025 for July 2026 delivery, then withdrew the product in mid-May 2026 and refunded buyers before any unit shipped; none has been independently benchmarked.'],
|
||||
['X35', 'Class v6 retains the 64-register window.'],
|
||||
['X35', 'Class v6 adopts the 64-register window and retains it across every rotation.'],
|
||||
['X35', 'The long-program and select-tree proposals were rejected.'],
|
||||
['X36', 'an observed comparison, not a ceiling'],
|
||||
['M34', 'The work that waits can grow.'],
|
||||
|
|
|
|||
Loading…
Reference in a new issue