Class v6 10.0h: the served text (the review's sentence verbatim, each number's label, the lines beside it, what is withdrawn)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/design/class-v6-rotating-family.md

@@ -420,6 +420,22 @@ So for the programmable chip the lifetime unit says: above about USD 23 M to 83
 
 **(7) The next research programme**, named in the close: the connected-state experiment, the mixed integer and FP32 candidate, and the multi-family programmable adversary, three lanes launched at 15:5x UK with their clocks (their rows land as amendments under this section). Rotation is not expected to deliver the missing joule; it is the response capability of item (1).
 
+#### 10.0h The served text (for the site audit lane, served as written; each number's label; what is withdrawn)
+
+**The sentence, as the external review words it (10.0f item 5), served verbatim:** "Class v6 retains the 64-register window. Current modelling estimates a 2.2x to 2.4x energy-efficiency advantage for the strongest specialised designs assessed against the GPU tier (2.0x on the GPU's own node). The long-program and select-tree proposals were rejected. Economic resistance depends on development cost, deployment economics and productive hardware lifetime; family transitions receive an obsolescence benefit only where a loss of competitiveness is demonstrated; programmable multi-epoch designs are included in the assessment."
+
+The labels on its numbers: "2.2x to 2.4x" is modelled (the GPU side measured: the RTX 5080 at its 1,100 MHz lock 2.06 microjoules per hash and the RTX 5090 at its 1,300 MHz lock 2.33, both on class v4, PC 1 and rented pods, 8 October 2026; the chip side the k lane's synthesised 8-lane sequencer core with the 64-register window on ASAP7, scaled to N3 on TSMC's headline factors, claimed; the chip's memory the chip model's GDDR7 board, modelled). "2.0x on the GPU's own node" is modelled (the same core node-for-node, k 1.09). Against the 32-lane window core the adversary would build the same figures read about 2.4x to 2.6x a node ahead and 2.0x to 2.2x node-for-node (synthesised, pending the re-optimised row by 18:00 UK); the served sentence's range is kept as the review wrote it and the 32-lane rows sit beside it on the page as the pending row. The window's k is synthesis-derived and not a lower bound.
+
+The lines the page carries beside it, each labelled:
+- The three statements, separate (10.0g item 1): energy resistance (the figures above); economic resistance (a profitability surface under stated development cost, revenue, share, margin and productive lifetime; the conditions under which development is attractive; lane 3's cut owed, the conditional statement of 10.0f item 2 until then, modelled); response capability (a passed rotation boundary proves the rotation works, not that hardware dies; the schedule of 10.0d: hourly, weekly, 180-day family, emergency vote; measured per boundary).
+- The node column (10.0e, claimed scaling): 2.0x against a chip on the GPU's own node, 2.4x a node ahead, 2.8x two nodes ahead on the 8-lane core; the honest tier moves to the next node with every GPU generation while a chip must re-tape-out.
+- The precedents as sourced (10.0b; every figure with its URL and date, nameplate and community tables, about 20 percent either way): RandomX's rules stable since 2019, its programs varying per hash, the Antminer X5 46 months after the fork at 6.37 J per kH at the wall against a stated CPU measurement, an observed comparison, not a ceiling; Ethash 36 months to a first chip worse than a GPU, the iPollo V2H about 14x today; Kaspa 21 months, 167x to 725x.
+- The commodity cohort: the discrete-GPU population the network protects; the Apple row reported beside it, never the headline (10.0g item 3).
+- The evaluation rule (10.0g item 2) with the harness and scoring-rules links: the minimum over workloads of the maximum over free adversarial designs of E_GPU over E_adversary, under the 10 percent GPU-cost budget at the lock, the verifier limit, cross-vendor correctness and hardware accessibility; the rejected long program, select tree, wide read and scratchpad as negative controls with their measured rows.
+- The next programme (10.0g item 7): the connected-state experiment, the mixed integer and FP32 candidate, the multi-family programmable adversary; rotation is not expected to deliver the missing joule.
+
+Withdrawn, to be struck everywhere it appears: the lifetime claim ("under 1x per hash over its 180-day life"; 10.0f item 1); the USD 300 M and USD 340 M lines and any "the chain stays below X" wording (10.0f item 2); any chip-arrival probability (10.0g item 5); "Monero's hash never changes" (10.0g item 6); the 725d2945 sentence ("under 3x per joule at the knee, under 1x per hash over its life") and this lane's section 9 proposal; W = 8 as a next width (W = 4 at genesis, 8 measured not free, 16 never).
+
 #### 10.0d The rotation schedule the close adopts (the rotation lane, `docs/design/class-rotation-four-layers.md` on class-v6-rotation at bd43f808, build-3, gate green, 14:4x UK; one line per layer; both of this document's constraints held: the 180-day family epoch not shorter, W = 4 not drawn)
 
 | Layer | Boundaries a year | What it draws, from where | Exposure per boundary (this document's units) | Chip | Label |