igneum-labs
c8fcedbf04
class v5 design page: the class v6 kit row names the PC script fault (one-pack leaves check, gfx1201) and its fix at class-v6-kits 4853106f1
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:12:58 +00:00
igneum-labs
5e3344b073
class v5 design page: the class v6 kit's 5090 reads (both packs equal; the window's cost per hash and per joule)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:03:27 +00:00
igneum-labs
5c277a7685
class v5 design page: the class v6 kit's second zip (098e64c3, the window texts in) on the row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:26:08 +00:00
igneum-labs
1de224477e
class v5 design page: the class v6 all pack reads equal on Metal and Apple OpenCL with the window texts (four of six platforms at 59e6708e46f1e87c)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:24:13 +00:00
igneum-labs
2b81d3fac8
class v5 design page: the class v6 kit row (the zip 2c56bd06 from the class-v6 merge, the reads so far per pack and platform, the all pack's Mac refusals by the stub, the window texts owed, the ds55 form not in the pack)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:12:36 +00:00
igneum-labs
cb9100619c
class v5 design page: the Intel row moves to its fingerprint (the Arc B580 reads 82b19cbde8557ea5 on the rebuilt kit; the rotate fold was the whole fault; six platforms equal)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:49:15 +00:00
igneum-labs
2a6151f1cc
class v5 harness: the attempt-3 read's standalone path (--a3-only, --a3-known-failed) and the runner's stdout line; the check's live EQUAL on the rebuilt pair and the known-failed DIFFER on the page with the logs
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:18:19 +00:00
igneum-labs
a949bd88d2
class v5 harness: the pairing rule's fixed attempt-3 seed read on every run (kaspa-pow program-id beside the run's CLI, attempt and id against the record; an unreadable side fails the check); the seed's inputs pinned under the harness dir; the page row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:09:23 +00:00
igneum-labs
a56165eebd
class v5 design page: the pin's FAIL seed re-read (the freeze draws 1f1cf82877f46ee6 at attempt 3; both FAIL ids were foreign crates; the seeded attempt-3 case next)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:01:28 +00:00
igneum-labs
c9bdeb3b94
Merge remote-tracking branch 'build/master' into class-v5
2026-10-08 12:57:31 +00:00
igneum-labs
e10af3c36c
class v5 design page: the pairing read-back on the rebuilt 0.3.25 pair (PASS, id for id on epochs 8 to 10 against the freeze CLI at exactly dba17a0a; no attempt-3 seed in the run, the seeded case next), the logs
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:57:30 +00:00
igneum-labs
f7b2140071
class v5 design page: the 0.3.25 pin's pairing STOP (the attempt-3 seed divergence, the embedded crate path), the pairing rule's attempt-3 line, the read-back plan
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:36:47 +00:00
igneum-labs
7670ed9f15
Class v6: the last two 20:00 and 19:30 references pulled to the close
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
af0f82798e
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6bbb33364
2026-10-08 12:28:21 +00:00
igneum-labs
5f1090037f
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b3353fd08
2026-10-08 12:28:21 +00:00
igneum-labs
f9045cf567
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b6280dcfe
2026-10-08 12:28:21 +00:00
igneum-labs
7f93ff9092
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 78ce9ea46
2026-10-08 12:28:21 +00:00
igneum-labs
a88fd37d08
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9e3677f5e
2026-10-08 12:28:21 +00:00
igneum-labs
339236654a
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 73f2c0768
2026-10-08 12:28:21 +00:00
igneum-labs
ace2e5367c
Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 650c2ad56
2026-10-08 12:28:20 +00:00
igneum-labs
6ebe399950
Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fb93859c7
2026-10-08 12:28:20 +00:00
igneum-labs
251b0b006d
Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a836fcf50
2026-10-08 12:28:20 +00:00
igneum-labs
d8bb356de8
Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3585efb9d
2026-10-08 12:28:20 +00:00
igneum-labs
4dfa7fb769
Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fcea9a0df
2026-10-08 12:28:20 +00:00
igneum-labs
bfdf473ccb
Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of afad20f1f
2026-10-08 12:28:20 +00:00
igneum-labs
1af1c84d85
Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1989495c1
2026-10-08 12:28:20 +00:00
igneum-labs
761f2cfc7b
Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7aa9f1898
2026-10-08 12:28:19 +00:00
igneum-labs
b3774f4de9
Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 35e960090
2026-10-08 12:28:19 +00:00
igneum-labs
2bba8c521b
Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6cc3bfec8
2026-10-08 12:28:19 +00:00
igneum-labs
c1d7b1f251
Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e15f35ae
2026-10-08 12:28:19 +00:00
igneum-labs
d4fb47c1a6
Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fa8e742f6
2026-10-08 12:28:19 +00:00
igneum-labs
fcc0af77f3
Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 71f30fc80
2026-10-08 12:28:19 +00:00
igneum-labs
0abf6a24aa
Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8fee73f29
2026-10-08 12:28:18 +00:00
igneum-labs
38293eeeb1
Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8}
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 029744b7e
2026-10-08 12:28:18 +00:00
igneum-labs
b8536c901e
Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 91af4721e
2026-10-08 12:28:18 +00:00
igneum-labs
f338b190a6
Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d94c3e071
2026-10-08 12:28:18 +00:00
igneum-labs
b68041723e
Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0467872a6
2026-10-08 12:28:18 +00:00
igneum-labs
fc5a4de9d1
Merge remote-tracking branch 'build/master' into class-v5
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# Conflicts:
# site/ledger.html
2026-10-08 11:57:48 +00:00
igneum-labs
4ed9be047a
class v5 design page: Devnet 3's crossing at 68,400 (epoch 19, program 3d375a55029e7e60 at attempt 2), the worker fault (generator-5 packs refused by the pre-kit workers) and its fix
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:56:24 +00:00
igneum-labs
acac4963c3
class v5 design page: 0.3.25's pairing (the freeze, kit 65b47211, the Intel worker held out; the Arc read to 0.3.26 with the second PC dark)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:31:25 +00:00
igneum-labs
a9b3bf9b5f
class v5 section 14 and AP-F8-6: F8's residue attributed (a per-site bucket concentration of about a quarter bit at one narrow-window site; the per-site bucket bound is the next class's second test)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 08:48:31 +00:00
igneum-labs
55b8ca7821
class v5 design page: the Arc fault's cause (the kit worker lacks the Intel rotate-fold rewrite intel_rotr.h; master lacks it too; the rebuild waits on the Intel lane's landing)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 08:46:54 +00:00
igneum-labs
0cc17998fd
class v5 design page: the Intel row held out of 0.3.24 (the Arc B580's self-test fails on both classes' vector lanes with the dataset right: an Intel OpenCL evaluation fault; crossing time 09:36 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 08:38:08 +00:00
igneum-labs
0315d47b70
class v5 design page: F1's full record line (chip-view ops, the empty top bins, AP-F1-1's v5 half fixed and passed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 04:23:18 +00:00
igneum-labs
77f48b9ea5
class v5 design page: F1 PASS on the freeze (100,000 programs, max saved share 4.688 percent, 0 mismatches); the attack families on class v5 complete
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 04:22:01 +00:00
igneum-labs
b5f8f6b2a5
class v5 design page: F1's state (computing, not hung; its count exists only at its end, about 10:00 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 03:06:46 +00:00
igneum-labs
cb8b94be72
class v5 design page: F9's full record line; the Intel row stated as not measured tonight (the second PC's Arc job queued until a Windows entry exists)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 02:39:00 +00:00
igneum-labs
6a5a598dd5
class v5 design page: F9's mean attempt index corrected to 2.185 (the lane's correction)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 02:38:15 +00:00
igneum-labs
1fc3adbc77
class v5 design page: F9 PASS on the freeze (100,000 seeds, 0 exhausted, 0 panics, max attempt 30)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 02:38:01 +00:00
igneum-labs
bf6f31a026
class v5 design page: F9 and F1 interim on the freeze (0 exhausted of 73,691, 0 F1 failures)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 01:00:23 +00:00
