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Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
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igneum-labs 2026-10-08 12:19:15 +00:00
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docs/design/class-v6-rotating-family.md
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@ -288,6 +288,24 @@ The question the founder set: the stored-dataset chip pays the DRAM's own energy
The close (20:00): the honest floor per tier against each chip row, the recommended class v6 changes (the op mix, the SM-sparse default, the dataset schedule), the served chip line as a measured range, and what stays for v7, written here from the lanes' rows as they land.
### 10.0 The provisional close (the coordinator's order 13:2x UK: the founder's floor answer by 15:45 UK, one table, built on what is in by then; each missing row carries its default; the 20:00 close stays the final with the lock rows and the full documents)
The frame now, filled with the defaults, each cell replaced as its lane's row lands (lane 3 complete and re-folded by 14:30, the k lane's programmable-core row by 15:00, the SM-sparse 5090 rows on rented pods at stock by 15:00, lane 5's W = 16 row on a rented 5090 by 14:45, the denominator lane's table). The edge is whole-card joules per hash over whole-chip joules per hash; the card's energy is measured (class v4, the shadow on), the chip's memory energy modelled (chip-model-v3 5.5, lane B's 5.12 and lane 3's wire figure for the SRAM die at the genesis width of 4 words, 0.051 microjoules per hash), and the chip's shadow is priced two ways in every cell: first at the DEFAULT k of 0.5 in the record's convention (half the card's own shadow premium: 0.55 microjoules at stock, 0.33 at the lock, 0.31 on the M5 Max; marked `default`), then at the k lane's per-unit floor (0.11 microjoules per hash at N3, absolute, every unit a floor; marked `floor`), the worst case the served line must survive; the sequencer-core row replaces the default when it lands.
| Honest tier (measured joules per hash, class v4) | GDDR7 board (0.466) | HBM3 one stack (0.321) | SRAM die at W = 4 (0.051) | With SM-sparse | W = 16 variant |
|---|---|---|---|---|---|
| RTX 5090 stock (3.36; class v3 2.26) | 3.3x default / 5.8x floor | 3.9x / 7.8x | 5.6x / 21x | no change (default: dead on PC 1, 20.3b: sp43-w32 holds 98.2 percent of rate at the same draw; the rented-pod rows owed by 15:00) | not applied (default: outcome A, the card -47 percent, dead; the rented-5090 row owed by 14:45) |
| RTX 5090 at the 1,300 MHz lock, the record's operating point (2.33 = 1.67 + 0.65) | 2.9x / 4.0x | 3.6x / 5.4x | 3.9x absolute (6.1x in the record's convention, marked) / 14x | no change (same default) | not applied (same default) |
| Apple M5 Max (1.40; class v3 0.78; the GPU and DRAM channels) | 1.8x / 2.4x | 2.2x / 3.2x | 3.9x / 8.7x | not applicable (no SM lever on Apple) | not applicable (the M5 Max pays 0 at 64 bytes, measured; the chip +33 percent) |
The honest floor in one line, on the defaults: against the chip anyone can build (the GDDR7 board) the strongest honest tier by joule, the M5 Max, holds the chip to under 2x and a 5090 at its knee to about 3x; against the chip that needs an N2 project (the SRAM die) the holds are about 4x and 4x; every cell's floor-k figure is the worst case if a chip's core costs no more than its bare units.
The capex wall (lane 3, 10.3): below about USD 100 M a year of miner revenue (IGN 0.13 at launch emission) no rational SRAM project starts at any edge; above about USD 2.3 B a year (IGN 2.9) every one does; a USD 100 M project at 30 percent of the hash needs IGN 0.43 to 0.59. The project cost moves the threshold 5x, the chip's edge 1.4x.
The served line in one sentence, on the defaults: a chip that stores the dataset reaches about 3x per joule against an RTX 5090 at its knee and under 2x against an M5 Max, 4x against both if it is built on an N2 SRAM store for USD 100 M or more, and no rotating layer moves those figures; the layers decide which chip can be built and how long its tape-out lives.
The three class v6 changes it implies: (1) the op mix stays class v4's with the lossy families capped at their base (lane D: 0 of 3,000 eras exhausted under the band; the k lane: mulhi is the card's worst lever by 6x, so no re-weight helps the card); (2) no SM-sparse default (dead on the measured 5090 rows; the per-watt gift of the hot table is the chip's, 20.3c); (3) the dataset schedule 5.5 / 8.5 / 11.5 GiB with the read width pinned at 4 words (the chip's ticket USD 1,500 / 2,500 / 3,000; a tuned 5090 pays 1 to 5 percent per step; about a quarter of today's cards by count per step).
### 10.2 The shadow's k from RTL (floor lane 2, `docs/analysis/class-v6/floor/shadow-k.md` on class-v6-floor-k, build-4 and build-3, first synthesised rows 13:3x UK; RTL and flow under `tools/chip-model/rtl`; full by 19:30 UK)
**The first synthesised k is 0.18 at the 5090's lock in the absolute convention at N3, and nothing reads inside the claimed 0.3 to 0.8 band except the unscaled ASAP7 figure at the lock (0.35). These are PER-UNIT FLOORS: no fetch, no decode, no register file beyond an 8-entry window, which is the chip rotation kills (section 1). The coordinator's order (13:5x UK): the headline k for the close is the programmable sequencer-core row (fetch, decode, a 32-register file, the per-era registers, the drawn program), asked of the lane with the M5 Max column; until it lands the default is the record's shadowed rows at k 0.5 with these unit floors beside them as the lower bound, and the GDDR7 board at 4.0x at the lock and 5.8x at stock on the floor k is the WORST CASE the served line must survive, not the reading.** Method: a minimal lane (instruction register, an 8 x 32-bit register window of flops, read muxes, the unit, one write port; no fetch or decode) in Yosys 0.68 plus OpenROAD on ASAP7, routed, SPEF, power from a random-input gate-level VCD with every pin annotated, the TC corner at 0.70 V; so every chip figure is a FLOOR and every k a floor. The node scaling is claimed from TSMC's headline per-node power reductions (N5 x0.70, N3 x0.50, N2 x0.36 of ASAP7; approximate). The GPU side is the research file's 15.1a, measured.