Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/design/class-v6-rotating-family.md

@@ -245,7 +245,7 @@ Lane A's verdicts, taken into the layers where they bind:
 | Corrections to the 5 October history: the Antminer X9 withdrawn in May 2026 with zero units shipped; RandomX v2 shipped 25 March 2026 (program 256 to 384, CFROUND 16x rarer, AES in the loop, prefetch 2 ahead, +52.9 percent work; activation pending in Monero PR 10038); Vorick's "survives forks at under 5x" chip unverified | this document quotes none of the three; the research file's section 2 already retired the X9 as a `k` figure |
 | The ranked list: layer 2's floor and ceiling per tier first; the clock and the detector (two instruments: nonce pattern for a chip, share-by-key-and-template for a concentrated fleet, which is what found Qubic until it randomised); keep the read width out of the draw unless a width other than 4 B is measured latency-bound on every vendor; bound the op-mix draw by the per-vendor energy table; order the reserve by what a sequencer cannot fold into firmware, mm8 last, R0 the one unknowable item; a null per drawn parameter for layer 4; the per-load placement as research, not a draw value | taken as the order of section 6's gates; the read width: w16 is measured within 2.7 percent on the 5090 and the 9070 XT and within 1 percent on the M5 Max (latency-bound on all three), so {1, 4} words stays in the band with that measurement as its warrant; the per-load placement is already out of the draw (section 2) and dead as a construction (the research file 20.2a-close) |
 
-## 9. The served chip line reviewed against the measured and modelled rows (for main's word at 20:00 UK; nothing served moves on this document)
+## 9. The served chip line reviewed against the measured and modelled rows (for main's word at the 15:45 UK close; nothing served moves on this document)
 
 The served sentence (`docs/plans/counter-asic-3-public-text-2026-10-07.md`, the homepage paragraph and row 17): "At launch the strongest chip in our public model reaches 2.1x per joule against an RTX 5090 with a core as good as a GPU lane, 3.4x with one three times better, under class v4 from the first block; a 5090 locked at its knee pays 82 W for that shadow work. Class v5 then makes the dataset the chain's own state, so a chip that stores it or recomputes it is wrong on every item. Without class v4 the same chip would reach 5x to 9x."
 
@@ -274,7 +274,7 @@ The wording this lane proposes for main's word, if the SRAM-store reading stands
 
 Rejected by the invention lane with the number (its section 2): per-lane data-dependent branches, reads tied to the shard proof per block, randomised memory topology, the VRAM ratchet as a lever (layer 2's floor stands as written), pool-sampled witnesses, prover-gated eligibility (1.6 kW of proving network-wide at any hash rate: 0.7 percent of the hash at 100 GH/s), time-locked commitments beyond the era VDF, derived reads in the hash, row-straddling reads, scratch draws, the refresh per block. No candidate moves the per-joule identity.
 
-## 10. The floor: the stored-dataset chip's per-joule floor and everything behind it (the five floor lanes of 12:55 UK; their rows by 16:00 to 16:30 UK, their documents under `docs/analysis/class-v6/floor/` by 19:30; this section closes at 20:00 with each lane's row or its default stated and the row owed)
+## 10. The floor: the stored-dataset chip's per-joule floor and everything behind it (the five floor lanes of 12:55 UK; their rows by 16:00 to 16:30 UK, their documents under `docs/analysis/class-v6/floor/` by 19:30; this section closes at 15:45 UK on every row in by 15:30, each missing row's default stated and the row owed; later rows are amendments with their own time)
 
 The question the founder set: the stored-dataset chip pays the DRAM's own energy per random read and nothing else; the honest card pays that plus everything its silicon spends around the read; the floor is the ratio, and every term in it is a lever. The identity (the research file's section 2): at zero shadow `edge = E_card / E_mem`; with the shadow `(E_card + F) / (E_mem + k F)`. The lanes each take one term.
 
@@ -288,9 +288,9 @@ The question the founder set: the stored-dataset chip pays the DRAM's own energy
 
 The close (20:00): the honest floor per tier against each chip row, the recommended class v6 changes (the op mix, the SM-sparse default, the dataset schedule), the served chip line as a measured range, and what stays for v7, written here from the lanes' rows as they land.
 
-### 10.0 The provisional close (the coordinator's order 13:2x UK: the founder's floor answer by 15:45 UK, one table, built on what is in by then; each missing row carries its default; the 20:00 close stays the final with the lock rows and the full documents)
+### 10.0 The close at 15:45 UK (the founder's standing rule, 13:3x UK: anything doable in 30 minutes to 2 hours gets a clock inside that window; so 15:45 is THE close, not a provisional: the floor lands on every row in by 15:30, and the lock rows and the k lane's remaining unit rows go in below as amendments, each with its own time; there is no 20:00 event. Lane 3's 7bc9de4b capex numbers are final for the close; the SRAM die headlines the k lane's synthesised sequencer-core row the moment it lands, by 15:00, with its 6x to 10x at the full shadow kept beside it marked as the floor-k worst case)
 
-The frame now, filled with the defaults, each cell replaced as its lane's row lands (lane 3 complete and re-folded by 14:30, the k lane's programmable-core row by 15:00, the SM-sparse 5090 rows on rented pods at stock by 15:00, lane 5's W = 16 row on a rented 5090 by 14:45, the denominator lane's table). The edge is whole-card joules per hash over whole-chip joules per hash; the card's energy is measured (class v4, the shadow on), the chip's memory energy modelled (chip-model-v3 5.5, lane B's 5.12 and lane 3's wire figure for the SRAM die at the genesis width of 4 words, 0.051 microjoules per hash), and the chip's shadow is priced two ways in every cell: first at the DEFAULT k of 0.5 in the record's convention (half the card's own shadow premium: 0.55 microjoules at stock, 0.33 at the lock, 0.31 on the M5 Max; marked `default`), then at the k lane's per-unit floor (0.11 microjoules per hash at N3, absolute, every unit a floor; marked `floor`), the worst case the served line must survive; the sequencer-core row replaces the default when it lands.
+The table, filled with the defaults, each cell replaced as its lane's row lands before 15:30 (the k lane's sequencer-core row by 15:00; the SM-sparse 5090 knee row by 15:00; lane 5's W = 16 row on a rented 5090 by 14:45; the denominator lane's table); after 15:45 each later row is an amendment under this section with its own time. The edge is whole-card joules per hash over whole-chip joules per hash; the card's energy is measured (class v4, the shadow on), the chip's memory energy modelled (chip-model-v3 5.5, lane B's 5.12 and lane 3's wire figure for the SRAM die at the genesis width of 4 words, 0.051 microjoules per hash), and the chip's shadow is priced two ways in every cell: first at the DEFAULT k of 0.5 in the record's convention (half the card's own shadow premium: 0.55 microjoules at stock, 0.33 at the lock, 0.31 on the M5 Max; marked `default`), then at the k lane's per-unit floor (0.11 microjoules per hash at N3, absolute, every unit a floor; marked `floor`), the worst case the served line must survive; the sequencer-core row replaces the default when it lands.
 
 | Honest tier (measured joules per hash, class v4) | GDDR7 board (0.466) | HBM3 one stack (0.321) | SRAM die at W = 4 (0.051) | With SM-sparse | W = 16 variant |
 |---|---|---|---|---|---|