class v5 section 14 and AP-F8-6: F8's residue attributed (a per-site bucket concentration of about a quarter bit at one narrow-window site; the per-site bucket bound is the next class's second test)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/design/class-v5-stored-state.md

@@ -279,7 +279,7 @@ Every item of this page that has no code, no test or no measurement yet, with th
 | The hot-set cache rule (AP-F8-1, 1.067x bound) | inherited by merge from sub-version 3 (the dataflow freshness rule, the shared-operand rule, the 256 cap and the last resort); the bound itself is the attack-pass lane's F8 gate on the v5 stream | attack-pass lane (a3832b1c3b274b310) for the gate; this lane for the v5 pack export it reads | 2 |
 | The weak-day FPGA rule (AP-F4-1, NAF sum at least 163, at least 4 distinct rotations) | NO code, NO test: recorded in section 11 with the rule text; lands in `memhard.rs` `MixParams::with_shape` behind the v5 class (the mixer draw redrawn from the next stream values), with the known-failed case (the worst calendar day 29,337 at 1.121x redrawn) and the per-day rejection count (6.1e-4) | this lane | 3 |
 | The shadow-redundancy rule (AP-F1-1, 3.0 percent) | NO code, NO test: recorded in section 11 with the fraction; lands in `generator.rs` beside the shadow draw behind the v5 class (a block whose peephole-removable share exceeds 3.0 percent redrawn), with the known-failed case (the census's 5.078 percent block redrawn) | this lane | 3 |
-| The attack-pass families on v5 (F1, F4, F8's 64-seed gate at 2^24 with the 1.2x line, F9's exhaustion count) | F8 on the freeze 1c420786 PASS with the known residue (build-2, halves ended 22:58 and 23:03 UK; pairing e5a4ac5978462156 verified, 0 mismatches against the library on the Devnet 3 state): 61 of 64 seeds under 1.2x of the window model (0.9919x to 1.144x), 3 over, all in the four-seed tail (p10 1.5047x, p8 1.3787x, p4 1.2166x); p34 reads 0.9997x under the (c''') floor; p23, p19, p15, p18, p56 at 0.9997x to 1.0001x; the ratios equal sub-version 3's seed for seed within 0.001 except where the floor moved a draw. F4 on 8ca66afa PASS, AP-F4-1 FIXED-AND-PASSED against class v5 (build-1, 23:3x UK): with the agreed rule in the draw, 0 of 2^24 chain days over 1.1x on the LUT metric (median 226, minimum accepted cost 206 at day 27,016 = 1.097x, one adder above the reject line, the rule doing what it says) and 0 on the DSP-bound metric, mean 225.79, sd 6.07; day 29,337 redrawn (cost 203 to 228), day 20,729 at 219 unchanged. F9 on 1c420786 PASS (build-1, the last chunk written 03:34 UK): 100,000 of 100,000 chain-shaped seeds through the chain path, 0 exhausted, 0 panics, maximum attempt 30 (tail: 26 twice, 27, 29, 30 once each), 0 past attempt index 31, first-draw acceptance 0.3145, mean attempt index 2.185 (3.185 draws per seed), 4.86 percent at index 8 or above, 0.255 percent at 16 or above, the cap and the last resort never reached; record docs/analysis/attack-pass/f9-grind.md on the mirror's attack-pass. F1 redundancy census on 1c420786 PASS (build-1, census.csv written 05:20 UK): 100,000 of 100,000 class v5 programs; the saved share min 0.000, mean 0.623, max 4.688 percent (worst attack-f1/95060); 0 over 5 percent, 0 over 10; differential mismatches 0 of 100,000, verifier mismatches 0 of 100,000, 0 panics; chip-view ops saved mean 0.520, max 4.783; the histogram's top two bins (5 to 6 percent) empty; against class v4's max 5.078 the worst v5 program sits 0.39 points under the letter, so the class v4 10^5 letter miss does not recur on v5: F1 PASS by the letter and at honest-compiler parity, AP-F1-1's v5 half FIXED-AND-PASSED (record f1-shadow.md section 13 on the mirror's attack-pass; the run under lease pool class release, 5 h 46 min). With F8 (the known residue), F4 and F9, every lane (d) gate line for the 0.3.24 move is PASS on the full 10^5; the rest of the families are not re-run on v5 by rule. The record file: docs/analysis/attack-pass-2026-10.md, lane (d), on the mirror's attack-pass | attack-pass lane; this lane pairs the tip | 0 |
+| The attack-pass families on v5 (F1, F4, F8's 64-seed gate at 2^24 with the 1.2x line, F9's exhaustion count) | F8 on the freeze 1c420786 PASS with the known residue (attributed 8 October 2026, the hash lane on the Mac, 09:40 to 09:46 UK, tree b38b4af6 on 017e7037, the gate ratios reproduced: the residue p4, p8, p10 on class v5 and p34 on sub-version 3 is a per-site bucket concentration of about a quarter bit at one narrow-window site, with no saturated or lossy source: one load site reading a 2^22 or 2^23-item window whose largest 256-item bucket carries the excess, p4 site 1 (mad at 4) 4.5x, p8 site 14 (xor at 44) 3.1x plus site 6 (mad at 30) 3.5x, p10 site 8 (mad at 20) 5.6x, p34 site 1 (sub at 5) 3.5x, the index entropy 0.26 to 0.29 bits short of the window (p34 0.04); (c'') and (c''') pass them at 0.9927 to 0.9963 because distinctness does not see a bucket; the catch is a per-site largest-256-item-bucket bound, about 2x the window expectation at the 2^20 units the floor already runs, a generator change: the next class's second test beside the diffuse era-stride test, never the frozen 1c420786; the chip price unchanged, a few hundred reads of 2^31 per site) (build-2, halves ended 22:58 and 23:03 UK; pairing e5a4ac5978462156 verified, 0 mismatches against the library on the Devnet 3 state): 61 of 64 seeds under 1.2x of the window model (0.9919x to 1.144x), 3 over, all in the four-seed tail (p10 1.5047x, p8 1.3787x, p4 1.2166x); p34 reads 0.9997x under the (c''') floor; p23, p19, p15, p18, p56 at 0.9997x to 1.0001x; the ratios equal sub-version 3's seed for seed within 0.001 except where the floor moved a draw. F4 on 8ca66afa PASS, AP-F4-1 FIXED-AND-PASSED against class v5 (build-1, 23:3x UK): with the agreed rule in the draw, 0 of 2^24 chain days over 1.1x on the LUT metric (median 226, minimum accepted cost 206 at day 27,016 = 1.097x, one adder above the reject line, the rule doing what it says) and 0 on the DSP-bound metric, mean 225.79, sd 6.07; day 29,337 redrawn (cost 203 to 228), day 20,729 at 219 unchanged. F9 on 1c420786 PASS (build-1, the last chunk written 03:34 UK): 100,000 of 100,000 chain-shaped seeds through the chain path, 0 exhausted, 0 panics, maximum attempt 30 (tail: 26 twice, 27, 29, 30 once each), 0 past attempt index 31, first-draw acceptance 0.3145, mean attempt index 2.185 (3.185 draws per seed), 4.86 percent at index 8 or above, 0.255 percent at 16 or above, the cap and the last resort never reached; record docs/analysis/attack-pass/f9-grind.md on the mirror's attack-pass. F1 redundancy census on 1c420786 PASS (build-1, census.csv written 05:20 UK): 100,000 of 100,000 class v5 programs; the saved share min 0.000, mean 0.623, max 4.688 percent (worst attack-f1/95060); 0 over 5 percent, 0 over 10; differential mismatches 0 of 100,000, verifier mismatches 0 of 100,000, 0 panics; chip-view ops saved mean 0.520, max 4.783; the histogram's top two bins (5 to 6 percent) empty; against class v4's max 5.078 the worst v5 program sits 0.39 points under the letter, so the class v4 10^5 letter miss does not recur on v5: F1 PASS by the letter and at honest-compiler parity, AP-F1-1's v5 half FIXED-AND-PASSED (record f1-shadow.md section 13 on the mirror's attack-pass; the run under lease pool class release, 5 h 46 min). With F8 (the known residue), F4 and F9, every lane (d) gate line for the 0.3.24 move is PASS on the full 10^5; the rest of the families are not re-run on v5 by rule. The record file: docs/analysis/attack-pass-2026-10.md, lane (d), on the mirror's attack-pass | attack-pass lane; this lane pairs the tip | 0 |
 | The kit for every platform: Metal | done (branch `v5-kits`, 7 October 2026, 19:3x UK): `proto-metal/main.swift` `servePackDataset` reads `leaves.bin`, checks the pack's count and FNV-1a 64, binds buffers 2 and 3 as `packbench.swift` does, self-tests the dataset head and last word against `vectors.json` and drops the leaf buffer after the build; a v5 prepare and job served on the M5 Max at 18:37:32Z | kits lane | 0 |
 | The kit: CUDA | done (`v5-kits`): `packfile.h` reads `IGNEUM_STATE_LEAVES`, the FNV, file, root and block (generator 5 = class v5; a v5 pack without the count or another class with one is refused), `pf_load_leaves` reads and checks `leaves.bin`; `worker.cpp` uploads it (`cuMemcpyHtoD`) for `igneum_build(ds, cache, leaves, nLeaves, nItems)` and frees it after; the CPU emulation runs `--check` on v5-dn3-epoch0: PASS on igneum-build-1 at 18:40:52Z (cache FNV 7334fa46e5d972eb, dataset head, word [268435455], 64 samples, 96 of 96 lanes); the loader test carries the class v5 cases known-failed first (46 ok) | kits lane | 0 |
 | The kit: OpenCL (AMD), Intel | host done (`v5-kits`): `proto-opencl/host.c` sets the build arguments for both kernel shapes in one place and uploads the leaves in `--bench-pack`, `--serve` and the compiled-in bench (the host reference derives words from the same leaves); the Linux and Windows workers are in the kit zip; the 9070 XT run placed on PC 1 as one lock slot after the 9070 XT G1 and ladder job (the hash lane publishes `tools/class-v5/pc1-amd-v5-bench.ps1`, expected 82b19cbde8557ea5); Intel: not measured tonight, no Arc B580 on PC 1 or PC 2 and the only Arc path needs a driver click, which no PC job may raise (the coordinator's ruling, 19:5x UK), so the card's holder and a click-free driver path are owed | coordinator (PC 1 queue), the B580's holder | 1 |
@@ -320,4 +320,4 @@ The census reading (box 2, 48 pool cores under lease class v5, 20:42 to 21:03 UK
 
 The five programs main named, read by adv-accept at the acceptance's own 2^20 sample (21:35 UK, logs gap-five-d20733.log and gap-five-d20730.log on branch adv-accept): seed 4346 (bbb38e847011c354, 2.24x live) minimum site 2 at 0.9840 and seed 5245 (beaad44840bb9e4e, 1.86x live) site 8 at 0.9831, both refused by the floor; Devnet 3's epoch-0 class v4 program fce15bf61030be57 at site 0 (instruction 3, source r6) 0.9992 (live 0.9993), adv-cache-2's era-fixed-20 (11f9f955b21d56c9) site 11 at 0.9997 and era-drawn-2 (7ceb797d31eedb3e) site 13 at 0.9992: at or above the floor, the residual. Three further hot sets of adv-accept's refused: 106924 at 0.9821, 107022 at 0.9877, and 1738 (33ece54e2df5ea44, attempt 4, X at 0.1 percent +0.102 percent, 1.68x over the window model) at site 13 0.9868 (live 0.9870; log gap-hot3.log), and 170 (53a02a7c9c9b86f3, attempt 4, X at 0.1 percent +0.143 percent, 2.02x) at site 2 0.9880 (live 0.9877; log gap-hot4.log), and 122960 (4be7393ab6c84802, attempt 0, X at 0.1 percent +0.111 percent, 1.54x, the hottest item 0x81ad88 from an all-ones source at site 12, saturated-source share 0.353 percent under the (c') 1 percent) at site 12 0.9824 (live 0.9822, 1.31 percent of the site's reads on indices read 8 or more times; log gap-122960.log), and adv-accept's last three (gap-tail3.log): 228763 (2c4be0f6dc44c423, 1.82x, one item at 0.057 percent of all reads, source r0 at site 9 with no saturation) site 9 at 0.9809 refused, 638990 (682d8a67caf20d92, 1.51x) site 2 at 0.9872 refused, 623492 (283fa56f84e945f7, clean live) site 0 at 0.9922 refused; so every live hot set by X_f at or above f adv-accept found (nine, minimum sites 0.9809 to 0.9919) and both single-item programs are refused, and of its twelve deepest stand-in seeds read live at 2^24 (gap-newlow5.log, gap-deep4.log) seven clean programs are refused too (130488 at 0.9898, 19921 at 0.9912, 600738 at 0.9934, 148927 at 0.9814, 150347 at 0.9896, 34501 at 0.9929, 623492 at 0.9922; top 0.1 percent share 0.9998x to 1.0028x live), one clean passes (602822 at 0.9951) and 29307 at 0.9912 is refused beyond the gate (1.29x): the floor's statistic at 2^20 is usually a thin spread on the live set, not a hot set, which is the 2.4 percent clean rejection's population, and a floor cannot move up to the mild residuals without refusing most clean programs; the three mild concentrations it misses are worth about 1.0004x to a chip. The record's sentence (the defender's ruling, 21:4x UK): the freeze commit CLOSES THE HOT-SET HALF of the class and NOT the class: the floor refuses every program whose live hot set passes X_f at or above f that any lane measured (seven of adv-accept's, 0.9821 to 0.9919 at the minimum site, and 4346, 5245), and misses the three milder concentrations (top 0.1 percent share 1.26x to 1.45x of control, 0.03 to 0.1 percent of a hash's reads each, the shadow block's last write to the load's source register as the mechanism: a mul, a mulhi, a sub), Devnet 3's own first program among them, whose site-0 product low-bit law moves the distinct count by 0.08 percent: inside the clean population's spread at 2^20 (adv-accept's clean 1st percentile about 0.9993 on 29,032 programs), so no floor that keeps the clean rejection rate near 2.4 percent reaches it; the residual's prevalence is 3 of 432 load sites in adv-cache-2's census and its chip gain under 1.001x; its lever is a value-level source test at live scale or a per-site hot-item test, not a ratio, routed to the next class as a named item. Devnet 3's first class v5 program therefore draws the same (e5a4ac5978462156, attempt 0; the (c''') CLI on build-1 at 21:08 UK confirms). The residual's chip value: a hot table serving 0.1 percent of one site's reads is 1/16 of that over the program's loads, under the 1.067x bound of AP-F8-1 by two orders; its instrument, if main wants it closed, is a shadow-block draw rule (the last write before a load's source may not be a mul, mulhi or sub of the same register: a rule in the draw, not the acceptance), owed as a named row below, not tonight's object.
 
-Main's sentence on the record (23:4x UK), verbatim: "nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test." The reading under it. What the floor does not reach, named (corrected 23:3x UK by the era reading below; the first form of this sentence put the bound at "a top-0.1-percent share under about 1.3x", which was the wrong instrument's number): the distinct-index count at 2^20 reads concentration on FEW word indices (adv-accept's hot sets put about 3 percent of a site's reads on 512 indices, the multiples of 2^19, so the collision count moves by thousands and the ratio falls to 0.98 to 0.992), not a diffuse excess over the top 0.1 percent of items (16,384 items, 262,144 word indices: a 1.5x share there is about +0.08 percent of a site's reads spread over them, moving the distinct count by a few hundred, inside the clean spread). The era reading (box 2, 23:2x UK, `class-v5-harness/v5-listed-adv-cache-2-full.log`; adv-cache-2's census programs at their table attempts, igneum-pow 73daadc2): 0 of 29 refused, every class v5 draw on the class v4 attempt; the six over 1.2x read era-drawn-2 (1.2657x) site 13 0.9992, era-drawn-10 (1.2257x, R 22) site 7 0.9995, era-drawn-15 (1.5115x) site 14 0.9965, era-drawn-17 (1.2139x, R 11) site 0 0.9996, era-drawn-20 (1.2234x, R 29) site 11 0.9996, era-fixed-20 (1.2624x, devnet era) site 11 0.9997; the seven in the 1.04x to 1.2x band 0.9986 to 0.9998; the clean ones 0.9999 to 1.0000; the devnet-era controls of the biased pairs 0.9996 to 0.9999. So the floor closes the few-item hot-set class (nine of nine) and none of the era-stride diffuse class (a product's biased low bits placed into the index by the era's stride rotation R; hidden on the devnet by R = 29); that class is the next class's row: the per-site item-share test at live scale, or a draw rule on R and the shadow block's last write to a load's source. Its chip value is bounded by its own diffuseness: a hot table of the top 0.1 percent of items (1 MiB) serves 1.5 x 0.16 percent of one site's reads, 1/16 of that over the program's loads, about 1.0024x at the worst site read, under the AP-F8-1 bound by an order; the full 61-row reading (23:5x UK, `class-v5-harness/v5-listed-adv-cache-2-full.log`: the two real programs, 27 drawn-era, 32 devnet-era) reads 0 of 61 refused, every class v5 draw on the class v4 attempt; era-drawn-28 (1.7451x, R 15, the worst of adv-cache-2's census) reads site 15 at 0.9969 and era-drawn-25 (1.3571x, R 21) site 11 at 0.9994, both over the floor, so the diffuse class's worst member sits 0.0019 over the line while the few-item hot sets sit 0.003 to 0.013 under it; adv-accept's eight live hot sets sat at stride rotations 28, 19, 29, 29, 29, 11, 30, 10, so the two classes overlap in R and differ in shape, not in era.
+Main's sentence on the record (23:4x UK), verbatim: "nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test." The reading under it. What the floor does not reach, named (corrected 23:3x UK by the era reading below; the first form of this sentence put the bound at "a top-0.1-percent share under about 1.3x", which was the wrong instrument's number): the distinct-index count at 2^20 reads concentration on FEW word indices (adv-accept's hot sets put about 3 percent of a site's reads on 512 indices, the multiples of 2^19, so the collision count moves by thousands and the ratio falls to 0.98 to 0.992), not a diffuse excess over the top 0.1 percent of items (16,384 items, 262,144 word indices: a 1.5x share there is about +0.08 percent of a site's reads spread over them, moving the distinct count by a few hundred, inside the clean spread). The era reading (box 2, 23:2x UK, `class-v5-harness/v5-listed-adv-cache-2-full.log`; adv-cache-2's census programs at their table attempts, igneum-pow 73daadc2): 0 of 29 refused, every class v5 draw on the class v4 attempt; the six over 1.2x read era-drawn-2 (1.2657x) site 13 0.9992, era-drawn-10 (1.2257x, R 22) site 7 0.9995, era-drawn-15 (1.5115x) site 14 0.9965, era-drawn-17 (1.2139x, R 11) site 0 0.9996, era-drawn-20 (1.2234x, R 29) site 11 0.9996, era-fixed-20 (1.2624x, devnet era) site 11 0.9997; the seven in the 1.04x to 1.2x band 0.9986 to 0.9998; the clean ones 0.9999 to 1.0000; the devnet-era controls of the biased pairs 0.9996 to 0.9999. So the floor closes the few-item hot-set class (nine of nine) and none of the era-stride diffuse class (a product's biased low bits placed into the index by the era's stride rotation R; hidden on the devnet by R = 29); that class is the next class's row: the per-site item-share test at live scale, or a draw rule on R and the shadow block's last write to a load's source; and the F8 residue p4, p8, p10 on class v5 and p34 on sub-version 3 is a per-site bucket concentration of about a quarter bit at one narrow-window site, attributed 8 October 2026, whose catch, the per-site largest-256-item-bucket bound, is the next class's second test. Its chip value is bounded by its own diffuseness: a hot table of the top 0.1 percent of items (1 MiB) serves 1.5 x 0.16 percent of one site's reads, 1/16 of that over the program's loads, about 1.0024x at the worst site read, under the AP-F8-1 bound by an order; the full 61-row reading (23:5x UK, `class-v5-harness/v5-listed-adv-cache-2-full.log`: the two real programs, 27 drawn-era, 32 devnet-era) reads 0 of 61 refused, every class v5 draw on the class v4 attempt; era-drawn-28 (1.7451x, R 15, the worst of adv-cache-2's census) reads site 15 at 0.9969 and era-drawn-25 (1.3571x, R 21) site 11 at 0.9994, both over the floor, so the diffuse class's worst member sits 0.0019 over the line while the few-item hot sets sit 0.003 to 0.013 under it; adv-accept's eight live hot sets sat at stride rotations 28, 19, 29, 29, 29, 11, 30, 10, so the two classes overlap in R and differ in shape, not in era.

docs/fud-ledger.md

@@ -2526,7 +2526,7 @@ Status: Fixed in class v5 (8ca66afa, 0.3.25's igneum-pow line); sub-version 3's
 
 Finding (7 October 2026, the in-house pass adv-cache-2, report-chained-cache-2.md section 2.3 on branch adv-cache-2, 2^23 nonces per program on day 20730): under drawn eras, 13 of 27 class v4 sub-version 3 programs carry a load site whose top 0.1 percent of items take over 1.04x the window model's share (8 over 1.2x: era-drawn-2 1.2657x, -10 1.2257x, -15 1.5115x, -17 1.2139x, -20 1.2234x, -25 1.3571x, -28 1.7451x, era-fixed-20 1.2624x), against 2 of 32 under the devnet era, and Devnet 3's own epoch-0 program at site 0 reads 1.4492x at 2^26 nonces. The mechanism: a product's biased low bits (the shadow block's last write to the load's source, a mul, mulhi or sub) land at address bits R and up through the era's stride rotation `rotl(x * stride, R)`, inside the 28-bit index unless R is 28 or more; R = 29 on the devnet hid it. Class v5's floor (c''', `MIN_DISTINCT_RATIO_V5 = 0.995` at the 2^20 acceptance sample) was read on the class at 23:2x UK (box 2, class-v5 73daadc2, `docs/design/class-v5-harness/v5-listed-adv-cache-2-full.log`): 0 of 61 programs refused at their table attempts (the two real programs, 27 drawn-era, 32 devnet-era controls), the eight over 1.2x at 0.9965 (era-drawn-15, 1.51x) and 0.9969 (era-drawn-28, 1.75x) to 0.9997, the 1.04x to 1.2x band at 0.9986 to 0.9998, every class v5 draw on the class v4 attempt.
 
-Answer (main's sentence, 7 October 2026, 23:4x UK): "nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test." The reading under it: correct, and a different instrument's class. The distinct-index count at 2^20 reads concentration on FEW word indices (adv-accept's eight live hot sets put about 3 percent of a site's reads on 512 indices, the multiples of 2^19, and read 0.9809 to 0.9919: all nine refused by the floor), not a diffuse excess over the top 0.1 percent of items (16,384 items, 262,144 word indices: era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over them, a few hundred distinct indices, inside the clean spread of 0.0001). So the floor closes the few-item hot-set class and does not reach this one, and no floor would without refusing most clean programs (section 14 of the class v5 design page). Chip value, bounded by the diffuseness itself: a hot table of the top 0.1 percent of items (1 MiB) serves 1.5 x 0.16 percent of one load site's reads, 1/16 of that over the program's 16 loads, about 1.0024x at the worst site read, under the AP-F8-1 bound of 1.067x by an order; nothing in the chip model's rows moves. The next class's test, named: the per-site item-share test at live scale (the window model's top-0.1-percent share per site over 2^23 or more nonces, which costs seconds per candidate and so cannot sit in the acceptance's millisecond budget), or a draw rule on the era's R range and on the shadow block's last write to a load's source register (a mul, mulhi or sub of the same register), known-failed first on Devnet 3's epoch-0 program (fce15bf61030be57, site 0) and era-drawn-28.
+Answer (main's sentence, 7 October 2026, 23:4x UK): "nine of nine hot sets refused; the diffuse era-stride excess, bounded under 0.1 percent of a hash's reads per site, is not caught by the floor and is the next class's test." The reading under it: correct, and a different instrument's class. The distinct-index count at 2^20 reads concentration on FEW word indices (adv-accept's eight live hot sets put about 3 percent of a site's reads on 512 indices, the multiples of 2^19, and read 0.9809 to 0.9919: all nine refused by the floor), not a diffuse excess over the top 0.1 percent of items (16,384 items, 262,144 word indices: era-drawn-15's 1.51x is about +0.08 percent of the site's reads spread over them, a few hundred distinct indices, inside the clean spread of 0.0001). So the floor closes the few-item hot-set class and does not reach this one, and no floor would without refusing most clean programs (section 14 of the class v5 design page). Chip value, bounded by the diffuseness itself: a hot table of the top 0.1 percent of items (1 MiB) serves 1.5 x 0.16 percent of one load site's reads, 1/16 of that over the program's 16 loads, about 1.0024x at the worst site read, under the AP-F8-1 bound of 1.067x by an order; nothing in the chip model's rows moves. Beside it, attributed 8 October 2026 (the hash lane, 09:4x UK): F8's residue p4, p8 and p10 on class v5 and p34 on sub-version 3 is a per-site bucket concentration of about a quarter bit at one narrow-window load site (a 2^22 or 2^23-item window whose largest 256-item bucket carries 3.1x to 5.6x the expectation, no saturated or lossy source; (c'') and (c''') pass them at 0.9927 to 0.9963 because distinctness does not see a bucket), whose catch, a per-site largest-256-item-bucket bound of about 2x the window expectation at the floor's own 2^20 units, is a generator change and the next class's second test; the chip price is unchanged, a few hundred reads of 2^31 per site. The next class's test, named: the per-site item-share test at live scale (the window model's top-0.1-percent share per site over 2^23 or more nonces, which costs seconds per candidate and so cannot sit in the acceptance's millisecond budget), or a draw rule on the era's R range and on the shadow block's last write to a load's source register (a mul, mulhi or sub of the same register), known-failed first on Devnet 3's epoch-0 program (fce15bf61030be57, site 0) and era-drawn-28.
 
 Status: Answered with evidence (the miss recorded beside the nine of nine); the lever routed to the next class and CA4; nothing in class v5's frozen object 1c420786 moves.