Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/design/class-v6-rotating-family.md

@@ -39,6 +39,7 @@ PENDING the hash lane's rows (16:00 UK): the x16 mixer verifier and build; the t
 | Op-mix weights (the ten non-load families) | each weight within B points of table 1.4.2, B = 2 today; the proposal: B = 4 with the shuffle and mulhi weights capped at their class v4 values | the microbench (15.1a): shfl 55.8 pJ per op, mulhi 39.6, prmt 22.3, lop3 24.1, mul 13.9, arx 11.3 at the stock clock; a draw that raises shfl from 8 to 14 of 75 raises the premium per instruction by about 35 percent (modelled on those rows) | a chip that specialised its lane ratio loses the ratio; a general core nothing | the premium per instruction moves with the mix: pending the two packs | +0 ms | the two re-weighted packs' rows |
 | Read width `W` | {1, 4} words | w4 and w16 measured 5 October: the 5090 139.8 against 136.1 MH/s, the 9070 XT 17.90 against 18.15; w64 bandwidth-bound (71.9 MH/s on the 5090) | a 4-byte-granularity controller moves 4x the bytes at a w16 era (the Ren-Devadas lever reversed); the `f = 1` chip's energy per read rises toward the card's | 0 / pending / 0 (measured w16 on the M5 Max: within 1 percent) | 0 | none |
 | Shadow block shape | 64 to 256 instructions per block, the pass count the ladder's | 64-instruction blocks ran 2.5 to 3.5 percent FASTER than 256 on the 5090 and the M5 Max (measured 6 October); 1,024 cost the M5 Max 17 percent | nothing for any chip (the work is the same) | +2.5 to 0 percent / pending / +2.5 to 0 | 0 | none |
+| **The index fold (a design row, not a draw): `load_index` folds a product's low bits before the stride rotation, so no era's R lands a biased product bit on an address bit** | every era | lane D's family harness (build-1, 10:21 UTC, 16 drawn eras, every layer-1 parameter from the era's stream, the chain draw through the real rule, reads at the rule's own 2^20 sample): the index-bit bias fires HARD on 7 of 16 eras, abs z 130 to 511 at one site, every one at address bit R or R+1 (a product's bit 0 at P = 0.25 on era 15, R = 25, z -511; a product's bit 1 at 3/8 on era 13; an or-shaped source at 5/8 on era 6); the other 9 clean under abs z 3.8; the (c''') ratio sees none of it (0.9954 to 1.0000): adv-cache-2's era-stride class measured on class v5 accepted programs at the acceptance's own sample | a chip holding the favoured half of that site's window serves 75 percent of its reads instead of 50: about 1.6 percent of a hash's reads at f = 1/2 for one site, zero at f = 1 (the partial store already costs 1.26x the ops, chip-model 5.4): the f = 1 verdict does not move; the row is an auditor's flag on "uniform random reads", not a chip lever | nothing: the fold is one xor-rotate on the address path, measured as 0 on every card by the era-layout rows (the index form is the era draw's own) | 0 | the fold's form in `load_index` (fold the product's low bits before the rotation) and its vectors; a 6-sigma REFUSAL in layer 4 is not the lever: it would redraw about 40 percent of epochs (7 of 16 eras); the known-failed test is lane D's 7 of 16 eras at the rule's sample, which must read 0 of 16 with the fold |
 | Program length N | not drawn: the ladder's signal (latency-ladder.md) | an unconditional draw retires the Apple tier at 200,000 (measured -10 percent) | the core sized for the ladder's admissible top (rung 2, 199,600 ops) | the ladder's rows | the ladder's rows | none |
 
 ## 3. Layer 2: the dataset's size tracks the chain state with a floor, so fixed-memory silicon ages out
@@ -111,8 +112,8 @@ Every test the generator applies to a candidate program is today a function of t
 |---|---|---|---|---|
 | (c''') the distinct-item ratio floor | 0.995 over the 64 units at the genesis width and mixer | the same floor evaluated with the era's width (a 16-byte load touches one item too) and dataset size; 2.435 percent of candidates under it today, attempts +3.4 percent | class-v5 section 14 (measured census of 4,600 candidates) | a candidate below 0.995 on the exemplar seed 100767 is refused |
 | F8's uniformity (the largest 64-line bucket within 6 sigma over 2^28 derivations; the top 0.1 percent of items within 1.2x of the window model over 2^24 nonces on 64 seeds) | a gate run by hand per class on the attack board | run by the census tool per era draw at genesis (the band's corners plus 64 random eras) and by the node's acceptance as the per-site version below; a draw whose corner fails is excluded from the band | f8-uniform.md section 7: +4.84 sigma against the control's +4.18, PASS; the tail p4, p8, p10, p34 attributed this morning as per-site bucket concentration at a narrow-window site | the `quarter-lines` and `const-item` plants fire at +75.97 and +92,682 sigma (f8-uniform.md 2.1) |
-| The per-site largest-bucket bound (this morning's attribution) | named for a next class | per load site, the largest 64-item bucket over the 64 units' addresses within 6 sigma; the narrow-window sites (`k_off` a quarter) judged against their own window's expectation | AP-F8-1's tail: p10 1.50x, p8 1.38x, p34 1.25x, p4 1.22x, each a narrow-window site's bucket | the four tail seeds must be refused; the 60 passing seeds accepted |
-| The value-level bias test (adv-cache-2; the research file's 20.2b) | named for a next class | per load site, the one-count of every index bit over the 64 units within 6 sigma of n / 2 (the per-load prototype's `BiasedIndexBit`, built last night, measured as the record) | a product's low bits at P(bit 0) = 1/4 placed at address bit R by the stride rotation; 6 of 16 drawn eras over 1.04x, 14 of 17 eras flagged by the instrument on the pre-amendment generator | a program whose site is sourced by a product under an era with R under 28 is refused; the devnet era's R = 29 is not relied on |
+| The per-site largest-bucket bound (this morning's attribution) | named for a next class | per load site, the largest 256-item bucket over the units' addresses, stated in SIGMA against its own window's Poisson expectation, never as a ratio: ratios of 2.2 to 2.4 at full-window sites are the CLEAN maximum (65,536 Poisson(16) buckets read +4.4 sigma), so a ratio bound would refuse clean programs; lane D's rebuild carries the sigma column | AP-F8-1's tail: p10 1.50x, p8 1.38x, p34 1.25x, p4 1.22x, each a narrow-window site's bucket; the sigma figures from lane D's family-gate.md (17:00 UK) | the four tail seeds must be refused on sigma; the 60 passing seeds accepted |
+| The value-level bias test (adv-cache-2; the research file's 20.2b) | named for a next class | per load site, the one-count of every index bit over the 64 units within 6 sigma of n / 2 (the per-load prototype's `BiasedIndexBit`, built last night, measured as the record); AS A TEST ONLY AFTER the index fold of layer 1 is in, because on today's `load_index` it would redraw about 40 percent of epochs (lane D: 7 of 16 drawn eras at abs z 130 to 511); with the fold in, the test is the guard that the fold holds | a product's low bits at P(bit 0) = 1/4 placed at address bit R by the stride rotation; 6 of 16 drawn eras over 1.04x, 14 of 17 eras flagged by the instrument on the pre-amendment generator | a program whose site is sourced by a product under an era with R under 28 is refused; the devnet era's R = 29 is not relied on |
 | The duplicate-lane test (the research file's 20.2a) | built for the per-load class only | kept as a per-load-only test unless a drawn block shape ever places shadow work between loads (layer 1 does not: the block shape is the size, the placement stays after instruction 63) | 1,482 duplicate lanes on the per-load record, 0 to 2 on every sound class | the per-load candidate 0 is refused |
 
 ### 5.2 The cost of the redraw, and its bound
@@ -147,6 +148,8 @@ The identity of the research file's section 2, with the night's measured rows: `
 
 ## 8. Unverified and owed
 
+- Lane D's family harness (the family gate's measured coverage: the 10,000-era random stratum and the three corner strata, the lossy cap, width 4, shape 64) lands in `family-gate.md` by 17:00 UK and is layer 4's coverage table; this document's layer 4 cites it where it is named and does not restate it.
+
 - The 5070 Ti tier: no card owned; the hash lane's rented row or the 5070's row scaled (approximate).
 - The x16 mixer: the verifier and build rows, or the estimate.
 - The op-mix band: the two re-weighted packs, or the microbench arithmetic.