igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity
999 commits 305 branches 1 tag 1.5 GiB
Commit graph

465 commits

Author SHA1 Message Date
igneum-labs
eef181124f Counter ASIC 3.0 status: the program-id fix merged (e05eb0c), the re-runs open 2026-10-06 16:26:11 +00:00
igneum-labs
329d256202 Counter ASIC 3.0 status: AMD G2 job ready (chain-seed packs, own kit) 2026-10-06 16:22:31 +00:00
igneum-labs
480c0518f6 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for the project lead 2026-10-06 16:18:08 +00:00
igneum-labs
e029091c3d Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
3521d9a002 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
d2237cc566 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:15:17 +00:00
igneum-labs
85c267971c Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:14:08 +00:00
igneum-labs
ed53e96fd8 Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:30 +00:00
igneum-labs
f0b3355a7a Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:00 +00:00
igneum-labs
fa857683be Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:07:55 +00:00
igneum-labs
179443499d Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 15:58:03 +00:00
igneum-labs
e5e54a681f Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 15:52:47 +00:00
igneum-labs
2df45c43fb Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 15:45:39 +00:00
igneum-labs
3c62a8a9c7 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 15:40:42 +00:00
igneum-labs
868c13b393 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (the project lead 16:50 UTC), the gate table 2026-10-06 15:38:44 +00:00
igneum-labs
0962364e03 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 15:13:22 +00:00
igneum-labs
4bdf9af4c3 Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for the project lead; the owed list) 2026-10-06 08:48:18 +00:00
igneum-labs
f4478a8ee1 Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 08:45:48 +00:00
igneum-labs
697b8833df Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 08:45:02 +00:00
igneum-labs
aab9858068 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:31:10 +00:00
igneum-labs
c6e03662a6 Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:30:15 +00:00
igneum-labs
881ae59779 Counter ASIC 3.0 status: the detector's two calibration findings answered (ba4a995 merged; max r 0.10) 2026-10-06 08:29:28 +00:00
igneum-labs
5b0b08e17f Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
cb75491b31 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
7c53b0545a Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
e3ee3049bd Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
3959d66e55 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
3e77f1adf5 Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00
igneum-labs
1538c78141 Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 07:51:42 +00:00
igneum-labs
36202759eb Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:42 +00:00
igneum-labs
dd08267df3 Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 07:51:36 +00:00
igneum-labs
f2e79316fe Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 07:51:15 +00:00
igneum-labs
5c2131c18e Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:51:13 +00:00
igneum-labs
1c08438a12 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 07:51:00 +00:00
igneum-labs
bcc2db992e Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:50:01 +00:00
igneum-labs
8f2defa659 Counter ASIC 3.0 status: items 4 and 5 closed, the owed list opened 2026-10-06 07:48:56 +00:00
igneum-labs
ace33b9eef Merge branch 'ca3-detector' into ca3-coord 
# Conflicts:
#	docs/plans/funding.md
 2026-10-06 07:48:42 +00:00
igneum-labs
6f9b5cf2f5 Counter ASIC 3.0 items 4 and 5: the issuance trigger, the signal trigger, the FPGA lane and the layer 9 against layer 7 ranking 
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:47:21 +00:00
igneum-labs
0f3b23d7a7 Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row 2026-10-06 07:40:41 +00:00
igneum-labs
7f76308ff8 Counter ASIC 3.0 status: item 6's Mac step costs (interim) 2026-10-06 07:36:58 +00:00
igneum-labs
4ab969d182 Counter ASIC 3.0 status: the two claim drafts for the project lead with the rows that bound them (main's steering) 2026-10-06 07:35:09 +00:00
igneum-labs
216a4b90c3 Counter ASIC 3.0 status: item 1 closed (verdict over 2x, the f = 1 chip), item 8 (latency-shadow program work) opened 2026-10-06 07:33:26 +00:00
igneum-labs
188aeed9ec Counter ASIC 3.0: mixer_mult = 8 in spec 1.13.1 and mixer-x4.md section 2 (item 3's finding); item 3 closed in the status file 2026-10-06 07:31:02 +00:00
igneum-labs
265749d557 Merge branch 'ca3-crypto-brief' into ca3-coord 2026-10-06 07:30:42 +00:00
igneum-labs
013ec52445 Counter ASIC 3.0 item 3: the mixer cryptanalysis line item and brief in funding.md 
One row in the funding table (USD 80,000 to 160,000 for two independent reviews, basis the four RandomX reviews of 2019 at their published per-firm prices and person-days) and a section "The mixer cryptanalysis brief (Counter ASIC 3.0 item 3)": the target shape from memhard.rs and accept.rs, the ranked break list with the chip-model number each moves, deliverables and timebox, the soundness suite to re-run, acceptance criteria in the RandomX audit style, candidate reviewers with citations, the risk column against the two-publish rollout, the timing against the testnet go checklist, and the consequences per user tier. Nothing else in the file is touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:29:45 +00:00
igneum-labs
1a3c440977 Counter ASIC 3.0 status: the run opened 07:3x UTC, machines and rules, five workers 2026-10-06 07:20:17 +00:00
igneum-labs
ac2bca8a0a Merge branch 'master' into ca3-coord 2026-10-06 07:13:58 +00:00
igneum-labs
f8088c49c3 release 0.3.11: C35's cause on PC 1 and the ember-tune guard e600e63 in the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:03:10 +00:00
igneum-labs
2429aeef08 Counter ASIC 2.0 status 07:03: PC 1 back, the 22:31Z quit source named (C35 closed), the Ember re-run on the project lead's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:02:44 +00:00
igneum-labs
037cb780d7 Counter ASIC 2.0: the crossing verdict PASS (05:21:48Z); H re-cut to about 19:12 to 19:20Z 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 05:58:24 +00:00