Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job)

docs/plans/counter-asic-3-status.md

@@ -104,7 +104,7 @@ Either replaces "under 2x" on the site and in the litepaper once the project lea
 
 | Item | Owed | Why |
 |---|---|---|
-| 1 | the 5090's watts at the hash alone and under a cap (Ember Tune rows requested; the 5 October PC 2 sweep as the second source); every DRAM energy figure is a streaming figure applied to random reads; the 9070 XT rows | PC 1 not released; no chip measured |
+| 1 | the 5090's watts at the hash alone: the Ember Tune run of 07:21 to 07:56Z produced no 5090 step (its second engine never mined; re-run pending the project lead); the 4 October PC 1 log (miner-eff record, run win-ae432dc7-20261004-164723) gives p95 290 W at 124 MH/s in the app under a 460 W limit, and the card's cap floor is 400 W, so a power cap CANNOT bind on this kernel: item 1's 326 W denominator is a peak with the prover on, the hash alone is about 290 W (2.34 microjoules at 124 MH/s), and the lever that can move the watts is the core clock, now in item 8's PC 2 job (`-lgc` steps at 2,781 / 2,472 / 2,163 / 1,854 MHz); every DRAM energy figure is a streaming figure applied to random reads; the 9070 XT rows | PC 1 not released; no chip measured |
 | 4 | the 9070 XT rate band for the detector; the coinbase card-model tag (0.3.12) so the chain-attributed band needs no fleet log; the public testnet's first-week baseline (history check 2) | PC 1 not released; a miner change |
 | 5 | a rented FPGA hour (the soft-overlay reads-in-flight number is a model on cited HBM figures) | no FPGA in the fleet |
 | 6 | the 9070 XT step costs | PC 1 not released |