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Counter ASIC 3.0 status: the run opened 07:3x UTC, machines and rules, five workers

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igneum-labs 2026-10-06 07:20:17 +00:00
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# Counter ASIC 3.0: status
Started 6 October 2026, 07:15 UTC, on the project lead's order "run it all". Coordinator worktree `igneum-wt-ca3-coord`, branch `ca3-coord` from `50df751` (ca2-coord `9206aea` merged with master `ddfcdac`). The plan: `docs/plans/counter-asic-3.md`. The audit behind it: `docs/analysis/asic-resistance-history.md`. The 2.0 record: `docs/plans/counter-asic-2-status.md`, `docs/bench-log.md` "Counter ASIC 2.0, the numbers", `docs/analysis/chip-model-v3.md`. Class v3 is live on the devnet since DAA 154,800 (crossing 03:51:42Z, verdict PASS 05:21:48Z). Nothing in this run publishes to the devnet; what passes is a class v4 candidate behind `program_class_v4_activation_daa` under the six gates and the two-publish rollout of 2.0.
The test every result is judged against (the project lead, 6 October): a chip maker must have to build a better GPU than NVIDIA to launch an ASIC, the way Bitmain's Antminer X5 reached CPU parity per joule only at many times the price. The binding rule from 2.0: the hash stays bound by dependent random memory reads.
## 1. Machines and rules in force today
| Machine | State | Rule |
|---|---|---|
| Mac M5 Max | mining paused; Metal worker free | measurements under `with-lock.sh measure` only |
| PC 2 (1ccfe586, RTX 5090) | the proving agent's job `segments-pc2-pv1` (about 45 min from 07:3x UTC) | nothing published until "PC 2 clear"; one job at a time (`/tmp/igneum-devnet/pc2-ca3.lock`); released by message when done |
| PC 1 (ae432dc7, RTX 5090 + RX 9070 XT) | the project lead's desk | not used today; every AMD row OWED |
## 2. The items
| # | Item | Worker branch | State | Close |
|---|---|---|---|---|
| 1 | Partial-store chip and the time-memory curve | ca3-analysis | running | |
| 2 | Per-day item-derivation program (reserve entry, verifier gate, daily build) | ca3-derive | running (Mac first; 5090 job after PC 2 clears) | |
| 4 + 5 | Share-pattern detector, trigger rules, FPGA lane, layer 9 against 7 | ca3-detector | running | |
| 3 | Cryptanalysis brief in funding.md | ca3-crypto-brief | running | |
| 6 + 7 | Reserve order with step costs, vendor-share metric | ca3-reserve | running (Mac first; 5090 job after PC 2 clears) | |
## 3. Measured numbers
(filled at each close)
## 4. The chip model, before and after
(filled at the close)
## 5. What passes as class v4
(filled at the close)
## 6. Decisions for the project lead
(filled at the close)
## 7. Unverified and owed
(filled at the close)