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Merge branch 'ca3-derive' into ca3-coord

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docs/plans/counter-asic-3-derivation.md
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@ -28,6 +28,19 @@ core measurement (O-1.14) lands under 10 ms; the number that decides it is 4.88
(2.69 ms), at the x4-equivalent op count, with the chip row at 0.58x bare. The way to the 736 figure under the gate
on a laptop is the JIT (section 4.3), which is out of scope and named with its risk.
The verifier headroom each class leaves under the 10 ms gate, the budget other 3.0 items (item 8, program work in
the latency shadow: 32 N CPU ops per unit at N ops per hash) may spend on top of this one:
| Class | ms per unit, this M5 Max core (steady / worst cold) | Headroom under 10 ms (steady / worst cold) | On a 2019-class core (2.5x, approximate) | Headroom there (steady / worst cold) |
|---|---|---|---|---|
| x8 (class v3 today) | 2.06 / 2.18 | 7.9 / 7.8 ms | 5.2 / 5.4 | 4.8 / 4.6 ms |
| dr736 | 4.88 / 5.24 | 5.1 / 4.8 ms | 12.2 / 13.1 | none: over by 2.2 / 3.1 ms |
| dr368 | 2.69 / 2.90 | 7.3 / 7.1 ms | 6.7 / 7.2 | 3.3 / 2.8 ms |
So item 8's N is bounded by 4.8 ms on this core and by nothing on the approximate laptop row under dr736, by 7.1
and 2.8 ms under dr368, by 7.8 and 4.6 ms under x8 alone; the two items share one budget and the laptop row is
the one that binds, which is one more reason the O-1.14 measurement comes before either goes genesis-live.
## 1. Why: what the chip model says the fixed shape is worth
`docs/analysis/chip-model-v3.md` section 2 prices the on-die-cache recompute chip at 50 T op/s: class v3 (x8) costs