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Author SHA1 Message Date
igneum-labs
5b0b08e17f Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
cb75491b31 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
7c53b0545a Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
e3ee3049bd Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
3959d66e55 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
3e77f1adf5 Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00
igneum-labs
1538c78141 Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 07:51:42 +00:00
igneum-labs
36202759eb Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:42 +00:00
igneum-labs
dd08267df3 Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 07:51:36 +00:00
igneum-labs
f2e79316fe Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 07:51:15 +00:00
igneum-labs
5c2131c18e Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:51:13 +00:00
igneum-labs
1c08438a12 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 07:51:00 +00:00
igneum-labs
bcc2db992e Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:50:01 +00:00
igneum-labs
8f2defa659 Counter ASIC 3.0 status: items 4 and 5 closed, the owed list opened 2026-10-06 07:48:56 +00:00
igneum-labs
ace33b9eef Merge branch 'ca3-detector' into ca3-coord 
# Conflicts:
#	docs/plans/funding.md
 2026-10-06 07:48:42 +00:00
igneum-labs
6f9b5cf2f5 Counter ASIC 3.0 items 4 and 5: the issuance trigger, the signal trigger, the FPGA lane and the layer 9 against layer 7 ranking 
docs/plans/funding.md rule 5: the bounty is escrowed and the benchmark live before daily
issuance crosses USD 20,000 a day, with the price-per-IGN table per halving period.
docs/plans/epoch-length.md section 11: the detector alert held 6 net windows recommends
the next shorter ladder step, per-tier costs at 2,400 and 600, the adversary's share per
compile class. Section 12: HBM FPGA parts with sources, reads in flight per watt against
the RTX 5090 (0.3x to 0.4x at Shuhai's measured rate, up to 1.9x at the unmeasured bank
ceiling), the two FPGA lanes in one table, and the ranking: layer 9 above layer 7.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:47:21 +00:00
igneum-labs
0f3b23d7a7 Counter ASIC 3.0 items 6 and 7: proposed reserve order and spec text (docs/plans/counter-asic-3-reserve.md), the vendor-share section on the benchmark page, the observer README row 2026-10-06 07:40:41 +00:00
igneum-labs
7f76308ff8 Counter ASIC 3.0 status: item 6's Mac step costs (interim) 2026-10-06 07:36:58 +00:00
igneum-labs
4ab969d182 Counter ASIC 3.0 status: the two claim drafts for the project lead with the rows that bound them (main's steering) 2026-10-06 07:35:09 +00:00
igneum-labs
216a4b90c3 Counter ASIC 3.0 status: item 1 closed (verdict over 2x, the f = 1 chip), item 8 (latency-shadow program work) opened 2026-10-06 07:33:26 +00:00
igneum-labs
188aeed9ec Counter ASIC 3.0: mixer_mult = 8 in spec 1.13.1 and mixer-x4.md section 2 (item 3's finding); item 3 closed in the status file 2026-10-06 07:31:02 +00:00
igneum-labs
265749d557 Merge branch 'ca3-crypto-brief' into ca3-coord 2026-10-06 07:30:42 +00:00
igneum-labs
013ec52445 Counter ASIC 3.0 item 3: the mixer cryptanalysis line item and brief in funding.md 
One row in the funding table (USD 80,000 to 160,000 for two independent reviews, basis the four RandomX reviews of 2019 at their published per-firm prices and person-days) and a section "The mixer cryptanalysis brief (Counter ASIC 3.0 item 3)": the target shape from memhard.rs and accept.rs, the ranked break list with the chip-model number each moves, deliverables and timebox, the soundness suite to re-run, acceptance criteria in the RandomX audit style, candidate reviewers with citations, the risk column against the two-publish rollout, the timing against the testnet go checklist, and the consequences per user tier. Nothing else in the file is touched.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:29:45 +00:00
igneum-labs
1a3c440977 Counter ASIC 3.0 status: the run opened 07:3x UTC, machines and rules, five workers 2026-10-06 07:20:17 +00:00
igneum-labs
ac2bca8a0a Merge branch 'master' into ca3-coord 2026-10-06 07:13:58 +00:00
igneum-labs
f8088c49c3 release 0.3.11: C35's cause on PC 1 and the ember-tune guard e600e63 in the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:03:10 +00:00
igneum-labs
2429aeef08 Counter ASIC 2.0 status 07:03: PC 1 back, the 22:31Z quit source named (C35 closed), the Ember re-run on the project lead's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:02:44 +00:00
igneum-labs
037cb780d7 Counter ASIC 2.0: the crossing verdict PASS (05:21:48Z); H re-cut to about 19:12 to 19:20Z 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 05:58:24 +00:00
igneum-labs
ac4a88ce03 Counter ASIC 2.0: the coverage card counts corrected (47 mining / 18 chain mode / 6 proving-only) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:18:27 +00:00
igneum-labs
b438e10e1c Counter ASIC 2.0: proving v1 segments confirmed from PC 2's log; decision 7 (segment length or cards) for the project lead 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:18:18 +00:00
igneum-labs
9268c5a391 Counter ASIC 2.0: stamp 04:17 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:17:13 +00:00
igneum-labs
7321d1fb45 Counter ASIC 2.0: proving v1's zero segments explained from prover.rs (coverage, not a fault); the morning line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:17:08 +00:00
igneum-labs
0678ae05d5 Counter ASIC 2.0 status 04:17: proving v1 active with 0 segments proven (C47), the morning line 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 04:16:32 +00:00
igneum-labs
6cca0c4cab Counter ASIC 2.0 status 03:56: the crossing held (epoch 43 class v3 at DAA 154,814, 03:51:42Z); C46 on the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 03:55:26 +00:00
igneum-labs
9632d78921 Counter ASIC 2.0 status 01:34: the PC 2 chain closed (job 6's curve, the ledger suites, the job-runner finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:33:37 +00:00
igneum-labs
37f53c067a Counter ASIC 2.0 status: stamp 01:13 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:13:02 +00:00
igneum-labs
ea6f946587 Counter ASIC 2.0 status 01:16: the repro reading confirmed, the prover off on PC 2 since 00:49Z, job 5's parse failure 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:12:58 +00:00
igneum-labs
bdf4237b23 Counter ASIC 2.0 rollout: PC job hygiene items (parse check, result writer, card-off confirmation) on the next-cut list 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:11:47 +00:00
igneum-labs
84e709cf48 Counter ASIC 2.0 status: heading stamped 01:10 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:10:52 +00:00
igneum-labs
02ab3d94d6 Counter ASIC 2.0 status 01:12: the repro run read as beside the miner, agg-cost-pc2-5 go 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 01:10:48 +00:00
igneum-labs
aae4dbc45b Counter ASIC 2.0 status 00:59: past DAA 144,000, N4 final, the queue state 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:59:27 +00:00
igneum-labs
84393fb1b2 Counter ASIC 2.0 status: heading stamped 00:45 from the clock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:45:34 +00:00
igneum-labs
724bd5aa00 Counter ASIC 2.0 status 00:47: the M16 inline bench table, the repro run on PC 2 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:45:30 +00:00
igneum-labs
a87db8d3e1 Counter ASIC 2.0 rollout 6b: mine-and-prove measured beside the miner (sweep 4) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:38:58 +00:00
igneum-labs
b33d33a0a9 Counter ASIC 2.0 status 00:40: the mine-and-prove reading corrected to the 600 DAA-s deadline rule 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:38:49 +00:00
igneum-labs
43c2951867 Counter ASIC 2.0 status 00:40: floor-sweep-4 rows (mine-and-prove beside the miner), M16 go 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:38:33 +00:00
igneum-labs
38a78419ac Counter ASIC 2.0: the crossing watcher (infra/devnet/crossing-watch.mjs) armed for N4 = 154,800; status 00:36 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:35:45 +00:00
igneum-labs
897ec73186 Counter ASIC 2.0 status: the 00:28 and 00:29 headings stamped from the clock (were guessed ahead) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:29:39 +00:00
igneum-labs
250a7d1ebe Counter ASIC 2.0: the M20 era test fails on 89dfcb95 under igneum-pow; G6 caveat (suites ran without the feature) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:29:21 +00:00
igneum-labs
449329dea0 Counter ASIC 2.0 status 00:36: the 0.3.12 list with the paid_wei fix first, the settings.json rule for PC 2 playbooks 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 00:28:40 +00:00