igneum-labs
a1e97f773f
Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c07ef717ec07ef717ee
2026-10-08 14:51:28 +00:00
igneum-labs
1058d7e406
Merge class-v6-family-gate 8adca0c0 into master (gate: green on 8adca0c0, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:46:07 +00:00
igneum-labs
afe9300a1e
Merge class-v6-invention 5aa1b6ac into master (gate: green on 5aa1b6ac, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:40:15 +00:00
igneum-labs
8adca0c0ab
Class v6 family gate, the full report: point B's row (0 hot sets at the 64 shape, 5 over 1.2x, the floor refusing 1 of 64) and the 18:00 amendment line (the best-mix genesis table under test)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:40:03 +00:00
igneum-labs
5b9e5b4062
Merge class-v6-floor-k-docs ba6763e7 into master (gate: green on ba6763e7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 14:39:16 +00:00
igneum-labs
58895bf32a
Merge class-v6-family-gate d0808ffa into master (gate: green on d0808ffa, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:38:28 +00:00
igneum-labs
ba6763e74f
shadow-k: the 32-lane core (5.55 pJ per lane-op, k 0.45 at the lock), the shuffle row (1.24 pJ, k 0.021), the mix optimiser's best corner
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bfccc26edbfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
7e4ba45831
shadow-k: row (2'), the 32-lane 16-register core (4.2 pJ per lane-op ASAP7, k 0.34 at the lock at N3)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3e2a202febfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
b02bf30249
shadow-k: the node column (node-for-node the base core is k 0.78 and the GDDR7 board 2.4x at the lock)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 05275ca6abfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
15128f593a
shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 036c1adedbfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
d8e2f2d4cb
shadow-k: the ranking and the mixed draw (the census lane's re-weight on the unit floors and the core)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e92167057bfccc26ed4
2026-10-08 14:32:44 +00:00
igneum-labs
35e6a80e73
shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed7d2626dbfccc26ed4
2026-10-08 14:32:44 +00:00
igneum-labs
b15ba14323
chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6fab785c5bfccc26ed4
2026-10-08 14:32:43 +00:00
igneum-labs
d0808ffae5
Class v6 family gate, the full report (16:30 BST): 38,000 drawn eras, the lossy-share curve per shape (the exhaustion a 256-shape interaction, about 6x the independent estimate), the pre-floor spread per width and the width-4 floor decision (0.995 kept at its measured cost), the two live-dataset censuses (128 band epochs: 2 hot sets at the 256 shape, both refused by the class v5 floor), the seven known-failed seeds through the sigma form (one value-level test, the bucket bound retired into the bit read; p212 and p225 at bit R), the x4, x8 and x16 verifier rows (x16 outside the band on the 10 ms gate), the band stratum's gate records as JSON lines; every row's log under logs/
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:31:37 +00:00
igneum-labs
5aa1b6ac53
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 14:31:15 +00:00
igneum-labs
70f45e66af
Class v6 invention: the drawn-era F8-form read of the sound per-load form (not clean: 7 of 64 seeds with a site under the 0.995 floor, min 0.940, one item at 1,938 reads; the per-load class runs no (c'''), so the floor joins G5-draw with the seven seeds as the known-failed case; the uniform-control share column labelled as not F8's number), the harness's era option
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:31:14 +00:00
igneum-labs
b259cbc31d
Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 58635a97b58635a97b7
2026-10-08 14:05:41 +00:00
igneum-labs
af5744a888
Merge class-v6-floor-sm-docs b0d7330d into master (gate: green on b0d7330d, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:58:19 +00:00
igneum-labs
b0d7330d47
Class v6 floor lane 1: sm-sparse.md, the PC 1 table deduplicated (the job's five-minute uploads repeat earlier lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f90d260ddf90d260dda
2026-10-08 13:49:30 +00:00
igneum-labs
931ef5080e
Class v6 floor lane 1: sm-sparse.md with PC 1's ladder (class v3 at stock agrees with the rented ladder at every rung, 3 to 3.5 percent at best; class v4 at the 1,300 lock needs every SM; the class v3 lock ladder partial and re-run owed; the memory-clock ladder queued)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b2c44314af90d260dda
2026-10-08 13:49:30 +00:00
igneum-labs
ac3c92ec5a
Class v6 floor lane 1: sm-sparse.md, the decomposition rows (the awake floor 120 to 139 W on every card, the memory path 10 to 13 nJ per dependent read against the devices' modelled 2.0 or 1.2), the 5090's clean self-tune rows (sp37 of 170 at 2.5 percent under base on class v3, nothing on class v4), every pod destroyed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5d29a1c4df90d260dda
2026-10-08 13:49:30 +00:00
igneum-labs
5bc88b3438
Class v6 floor lane 1: docs/analysis/class-v6/floor/sm-sparse.md, the first full draft (four rented 5090s, the 4090 and the H100 at stock: the SM count is not the lever, 1 to 4 percent at best; the knee 43 of 170 SMs on class v3 at the 99 percent hold; the H100 decomposition; the self-tune rows; PC 1's lock and memory-clock ladders owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1a43830d6f90d260dda
2026-10-08 13:49:29 +00:00
igneum-labs
126f8008dc
Class v6 floor lane 4: the sweep closed (20 rows, the 4060 Ti's class v5 stock row, the three cards not reached), sections 2, 6 and 8 regenerated; 10 of 10 on build-3
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9d3bc250c9d3bc250cb
2026-10-08 13:41:15 +00:00
igneum-labs
dbeeabf4fc
Class v6 floor lane 4: the one page and the close reading carry the measured class v5 stock column (the lock worth 34 to 41 percent on Blackwell and Ada) and the three core figures
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5746fa4839d3bc250cb
2026-10-08 13:41:15 +00:00
igneum-labs
cbe7bdf36e
Class v6 floor lane 4: section 2 regenerated from the tiers table (the class v5 stock column measured on 14 card classes, the three core figures), section 6 the sweep's rows and its two faults
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c693703199d3bc250cb
2026-10-08 13:41:15 +00:00
igneum-labs
a738818bcb
Class v6 floor lane 4: the fold-any-k line (E_mem per chip, the k lane's 1.1 pJ column priced)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 830a500149d3bc250cb
2026-10-08 13:41:14 +00:00
igneum-labs
777caf1f43
Class v6 floor lane 4: floor lane 1's stock rows taken (the 4090 and H100; the occupancy knob 1 to 2 percent), the class v5 watts driver and the memory-clock try (box-cardbench-v2m.sh) on 16 card classes in parallel
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d0958f1279d3bc250cb
2026-10-08 13:41:13 +00:00
igneum-labs
e736c8c685
Class v6 floor lane 4: the honest denominator (docs/analysis/class-v6/floor/denominator.md): every card class under class v5 with the knobs, measured or estimated, the chip edge per row in absolute picojoules; the LPDDR6 tier five years out; the Ember tiers statement and the re-measure rule; the sweep's first rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 24c2f26329d3bc250cb
2026-10-08 13:41:13 +00:00
igneum-labs
5fa906c824
Merge class-v6-floor-invention-docs-2 c0cfcf9f into master (gate: green on c0cfcf9f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:23:22 +00:00
igneum-labs
33aa5612dd
Merge class-v6-census-docs 7e89bd6f into master (gate: green on 7e89bd6f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:16:21 +00:00
igneum-labs
c0cfcf9fd4
Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b0f67e363b0f67e3635
2026-10-08 13:11:56 +00:00
igneum-labs
7e89bd6f67
Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
3f587652de
Class v6 census: W = 16 and the op-mix re-weight through the sub-version 3 rules (docs/analysis/class-v6/census-w16-mix.md): every candidate 256 of 256 without an era and 256 of 256 across eras 0 to 7 with the window-bit refusal on, 0 exhausted; W = 16 removes the product's low bits from the address by construction; the re-weight lowers r to 0.41 and raises the stride-bit refusals; the rows, logs, scripts and commands
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d20eb04bd (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
ff1a6c5c9b
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 13:04:40 +00:00
igneum-labs
9e34838e46
Class v6 invention: the drawn-era re-read on the fixed instrument cebedaf9 (the sound per-load form 254 of 256 seeds at 0.819 per candidate under eras, 234 of 256 at 0.927 no-era; the 16 x 27 form dead on both; class v4's shape at sub-version 3's 0.67 on the same binary), the two TSVs, sections 0, 2.1, 3.3 and 4 updated
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:04:39 +00:00
igneum-labs
2df9715732
Merge class-v6-floor-invention-docs 23150fe2 into master (gate: green on 23150fe2, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
23150fe20f
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of faa43afd3faa43afd3c
2026-10-08 12:45:35 +00:00
igneum-labs
b8c5163083
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e6c2995cdfaa43afd3c
2026-10-08 12:45:35 +00:00
igneum-labs
6dc002e357
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 75144b37efaa43afd3c
2026-10-08 12:45:35 +00:00
igneum-labs
1ae8ed12e0
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 377a07482faa43afd3c
2026-10-08 12:45:34 +00:00
igneum-labs
2f856ab578
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
09fbf890dd
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
d00db296a5
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
fa2b244935
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
1baf1709e4
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
367e6b04be
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
b3e1ce9f18
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
fb2e385d7d
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 87a86c338
2026-10-08 12:28:18 +00:00
igneum-labs
04822bd936
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0d5726cb8
2026-10-08 12:28:18 +00:00
igneum-labs
b12a1014ee
Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5826f9694
2026-10-08 12:28:17 +00:00
