Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
This commit is contained in:
igneum-labs 2026-10-08 12:22:53 +00:00
parent 09fbf890dd
commit 2f856ab578

View file

@ -1,8 +1,8 @@
# Floor lane 3: the SRAM full-store die and the dataset floor
8 October 2026, 12:5x to 19:3x UK, branch `class-v6-floor-sram` from `counter-asic-4`. One of the five floor lanes of
8 October 2026, 12:5x to 13:2x UK (the close of the floor section at 15:45 UK by the founder's rule of 13:3x; later rows land as amendments under section 10 with their own time), branch `class-v6-floor-sram` from `counter-asic-4`. One of the five floor lanes of
section 10 of `docs/design/class-v6-rotating-family.md`; the rows go to the Counter ASIC 4.0 research lane for the
20:00 UK close. Nothing here touches the devnet, the testnet object or any served number. Every figure carries a
15:45 UK close. Nothing here touches the devnet, the testnet object or any served number. Every figure carries a
label: **measured** (a card on a named job in this repository), **claimed** (a vendor's or a paper's figure, with the
record's source), **modelled** (arithmetic on claimed or measured figures by the method of `docs/analysis/chip-model-v3.md`
section 5), **approximate** (an estimate; the sensitivity is given). No chip has been measured. The arithmetic is
@ -134,7 +134,7 @@ per counted op). Two conventions price the die's shadow core. **Absolute**: the
against the stock 11.3 pJ, so the die pays `k x 1.10` microjoules whatever the card does; this is the physics and the
headline. **The record's**: `k` against the card's op cost at the same operating point, so the die pays `k x 0.65`
at the lock; it flatters the die at the lock by 1.6x and is carried marked. At stock the two coincide (section 2.2).
The `k` lane's RTL rows re-fold these in absolute before 20:00.
The `k` lane's RTL rows re-fold these in absolute for the close (its sequencer-core row due 15:00).
| `W` | Absolute, k 0.5 / 1 | The record's convention (marked), k 0.5 / 1 | Label |
|---|---|---|---|
@ -399,7 +399,7 @@ file's lower threshold). The corrected floor moves the lower number 4x (from USD
| A pool user | the chip fleet that matters is one package; the share-pattern detector is the warning | the detector before the public testnet |
| The public claim | "under 2x" is not reachable against the die by any shadow: on the k lane's synthesised core 10x at the honest cards' whole latency shadow at stock, 6x to 7x at the 5090's knee, 18x to 21x under class v4; on the record's claimed band (marked) 2x at `k = 1` and 4x at `k = 0.5`; 20x to 60x without the shadow. The number a miner can act on is the project's price threshold: USD 0.13 to 2.9 per IGN | section 7's served sentence |
## 7. Recommendation, for the 20:00 close
## 7. Recommendation, for the 15:45 close
The lever is the read width: pin `W = 4` words at genesis on the measured rows (the 5090 +2.7 percent, the 9070 XT
-1.4, the M5 Max within 1) and move to `W = 8` once one PC 1 row confirms what the measured rows already say (one