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Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of c07ef717e (c07ef717ee) for the box mirror master
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igneum-labs 2026-10-08 14:49:56 +00:00
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docs/analysis/class-v6/floor/denominator.md
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@ -178,6 +178,18 @@ win, because on this hash the memory clock is the rate and the core clock is onl
climb may raise the memory clock (5 percent of the range per probe) where the vendor exposes it, and no measured row
yet shows a gain from it (the 5090's memory sits at 13,801 of 14,001 MHz).
Amendment, 15:5x UK (floor lane 1's memory-clock ladder on PC 1, the 5090 alone at the 1,300 MHz core lock, job
run-ca4-pc1-memclk-5090-20261008-b, every row bit-exact; `docs/analysis/class-v6/floor/sm-sparse.md` section 3.1 at
66bc6ca7): the memory clock is not a lever, now measured. The driver holds the 5090's memory in two states only (asks
of 8,001 MHz and above read 13,801; 6,001 and below read 7,001, the PHY's half-rate state). Class v3 at the lock:
13,801 MHz 134.1 to 134.5 MH/s at 222.7 to 223.7 W (1.66); 7,001 MHz 76.0 MH/s at 141 to 142 W (1.86 to 1.87).
Class v4: 134.3 to 134.5 at 308 to 309 W (2.29 to 2.30); 76.1 at 184 to 187 W (2.42 to 2.46). The half-rate state
loses 43 percent of the rate (the activate ceiling scales with the memory clock) for 37 percent of the watts, so the
energy per hash rises 12 percent on class v3 and 5 on class v4; the 82 W between the states at 7.4 G reads per second
lost is 11 nJ per read at the margin, equal to the DRAM chase probe's whole-path figure, so the memory-side term is 80
to 90 W of the 223 W at the lock and is bought one for one with the rate. The table's "never touched" line stands as
a measurement; the tiers table carries `mem_mhz` 0 on every row.
## 4. The LPDDR6 and unified-memory tier, five years out
The method. The M5 Max row is the only measured unified-memory point and it splits three ways at the meter: the DRAM