igneum-labs
ee2d3c8606
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
0478a6c0eb
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
7b523af541
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
745e9effc0
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
5f45de999f
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
7670ed9f15
Class v6: the last two 20:00 and 19:30 references pulled to the close
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
af0f82798e
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6bbb33364
2026-10-08 12:28:21 +00:00
igneum-labs
5f1090037f
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b3353fd08
2026-10-08 12:28:21 +00:00
igneum-labs
f9045cf567
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b6280dcfe
2026-10-08 12:28:21 +00:00
igneum-labs
7f93ff9092
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 78ce9ea46
2026-10-08 12:28:21 +00:00
igneum-labs
a88fd37d08
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9e3677f5e
2026-10-08 12:28:21 +00:00
igneum-labs
339236654a
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 73f2c0768
2026-10-08 12:28:21 +00:00
igneum-labs
ace2e5367c
Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 650c2ad56
2026-10-08 12:28:20 +00:00
igneum-labs
6ebe399950
Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fb93859c7
2026-10-08 12:28:20 +00:00
igneum-labs
251b0b006d
Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a836fcf50
2026-10-08 12:28:20 +00:00
igneum-labs
d8bb356de8
Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3585efb9d
2026-10-08 12:28:20 +00:00
igneum-labs
4dfa7fb769
Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fcea9a0df
2026-10-08 12:28:20 +00:00
igneum-labs
bfdf473ccb
Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of afad20f1f
2026-10-08 12:28:20 +00:00
igneum-labs
1af1c84d85
Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1989495c1
2026-10-08 12:28:20 +00:00
igneum-labs
761f2cfc7b
Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7aa9f1898
2026-10-08 12:28:19 +00:00
igneum-labs
b3774f4de9
Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 35e960090
2026-10-08 12:28:19 +00:00
igneum-labs
2bba8c521b
Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6cc3bfec8
2026-10-08 12:28:19 +00:00
igneum-labs
c1d7b1f251
Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e15f35ae
2026-10-08 12:28:19 +00:00
igneum-labs
d4fb47c1a6
Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fa8e742f6
2026-10-08 12:28:19 +00:00
igneum-labs
fcc0af77f3
Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 71f30fc80
2026-10-08 12:28:19 +00:00
igneum-labs
0abf6a24aa
Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8fee73f29
2026-10-08 12:28:18 +00:00
igneum-labs
38293eeeb1
Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8}
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 029744b7e
2026-10-08 12:28:18 +00:00
igneum-labs
b8536c901e
Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 91af4721e
2026-10-08 12:28:18 +00:00
igneum-labs
f338b190a6
Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d94c3e071
2026-10-08 12:28:18 +00:00
igneum-labs
b68041723e
Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0467872a6
2026-10-08 12:28:18 +00:00
igneum-labs
6cacc7a548
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 13181a296
2026-10-08 12:28:18 +00:00
igneum-labs
018a015697
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5b4db2c78
2026-10-08 12:28:18 +00:00
igneum-labs
92be169c77
Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a32060596
2026-10-08 12:28:17 +00:00
igneum-labs
46034fc9ad
Counter ASIC 4.0 research: 20.3b the SM-sparse reading (a quarter of the SMs holds 98 percent of the rate at the same draw; the draw follows the work, not the SM count): rank 2 dead on measured rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 03871c835
2026-10-08 12:28:17 +00:00
igneum-labs
65d408d164
Counter ASIC 4.0 research: 20.4 names the 1,430-tile point as the one the k column was priced at, the Apple side open, nothing served moving
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of efa39b1a0
2026-10-08 12:28:17 +00:00
igneum-labs
b6f9526f0d
Counter ASIC 4.0 research: 20.3 the card rows of the seven packs (the tile block carries the ALU shadow's premium at the same rate, 14 percent cheaper at the knee; 0.048 to 0.091 pJ per MAC measured on the 5090), 20.4 the chip-model rows, the first sentence on measured rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5f3741950
2026-10-08 12:28:17 +00:00
igneum-labs
21a689c1fc
Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 98974a8ec
2026-10-08 12:28:17 +00:00
igneum-labs
838946e9ca
Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 413d19686
2026-10-08 12:28:17 +00:00
igneum-labs
bca81a905c
Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a84c19649
2026-10-08 12:28:16 +00:00
igneum-labs
9c25ba8bf5
Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f3885df2e
2026-10-08 12:28:16 +00:00
igneum-labs
c1849034e5
Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a9c16353a
2026-10-08 12:28:16 +00:00
igneum-labs
dba2c3f57e
Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list
...
Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed83ae162
2026-10-08 12:28:16 +00:00
igneum-labs
94f6bc6eb4
Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5fd67c216
2026-10-08 12:28:16 +00:00
igneum-labs
e239f05d19
Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant
...
docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b18684240
2026-10-08 12:28:16 +00:00
igneum-labs
02bc398552
Merge ca3-coord-record e159dd28 into master (gate: green on e159dd28, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:13:44 +00:00
igneum-labs
72b33aaf84
Merge class-v6-family-gate bb52ac64 into master (gate: green on bb52ac64, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:12:39 +00:00
igneum-labs
e159dd28cc
Counter ASIC 3.0 status: Devnet 3 stalled at the class v5 floor at 12:48 BST (the fleet's workers without the kit's generator-5 worker; --exec-rpc) and crossed clean at 12:57:40, the pairing checked three ways, the worker-smoke gate rule; the pin's node sha 5f316c21 (the chain-id answer) every gate green; the research lane's section 10 and the two floor rows; kit b's 5090 rows (the x16 draw free on the GPU, the size term real at the knee); the 9070 XT row served ( 5fd703f6); the attack pass's census split; the deploys 9100269f, 5fd703f6
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:06:07 +00:00
igneum-labs
40be3175af
Merge master 5fd703f6 into wallet-bridge (master moved 24 commits during the landing's gate)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:59:16 +00:00
igneum-labs
6ca6bc657d
Merge ca3-coord-record 92b42379 into master (gate: green on 92b42379, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 11:53:54 +00:00
igneum-labs
92b42379dd
Standing rule (main's word, 8 October 2026, 12:5x UK): no kill by name on the Mac, pid file only, ad-hoc shell lines included; Counter ASIC 3.0 status: the node lane's named commit 42ce0f07 (four node fixes incl. the proof-map window, the OOM class behind the seed outage), the fleet census (36 on population A, 21 stale re-walking), the research lane's 2ae69eb4 (chip-model 5.12, the class v6 document through section 9), lane D's move to build-3 and its lossy-share curve, the F8-256 PASS, the hash lane's v6 packs rows and the byte-seed export lesson, the shipper's 12:33 line, the pkill class
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:46:11 +00:00
