igneum-labs
e35dc94d5b
Merge class-v6-connected-docs a072f589 into master (gate: green on a072f589, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:43:21 +00:00
igneum-labs
8624a02393
Merge counter-asic-4 45b40140 into master (gate: green on 45b40140, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:37:40 +00:00
igneum-labs
be0dacd7ef
Merge class-v6-adversary-docs ad5ca6e4 into master (gate: green on ad5ca6e4, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:35:33 +00:00
igneum-labs
60e16599c6
Merge release-manifest-8 d80c7fa5 into master (gate: green on d80c7fa5, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:32:32 +00:00
igneum-labs
45b401409b
Merge the mirror's master into counter-asic-4 before the third landing
2026-10-08 15:28:43 +00:00
igneum-labs
a072f58902
Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
0dc8c17ef4
Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
c51fad1875
Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
2026-10-08 15:28:38 +00:00
igneum-labs
ad5ca6e47c
multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
01452ff1ea
multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
830d8cbf65
Merge reference-apps f2ff7a3c into master (gate: green on f2ff7a3c, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:27:58 +00:00
igneum-labs
2739aece9c
Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:27:51 +00:00
igneum-labs
59915e86df
Merge ca3-coord-record e61fbdaf into master (gate: green on e61fbdaf, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:26:45 +00:00
igneum-labs
d862940d82
Merge counter-asic-4 dcfe573b into master (gate: green on dcfe573b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:25:52 +00:00
igneum-labs
d80c7fa51e
Merge the box master b216afc7 into release-manifest-8 (the evidence page rebuilt)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:25:22 +00:00
igneum-labs
e61fbdaf1e
Counter ASIC 3.0 status: the amended close on master ( b216afc7), the adversary core rows (k 0.40 node for node), the connected-state rows (the window under 1 percent on the card), every platform on 0.3.26, the enforced-proving lane's line and route, the class v5 lane's kit item, the gate kills by name found and named
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:19:19 +00:00
igneum-labs
ef31944a57
Chip text: the third review's claim statement served verbatim above the sentence on every copy; rotation named an optional improvement, not the mechanism; no threshold as the economic headline (the coexistence model owed); X35 pin added
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:18:17 +00:00
igneum-labs
dcfe573bc9
Merge the mirror's master into counter-asic-4 before the second landing
2026-10-08 15:17:45 +00:00
igneum-labs
296c4a5b66
Economics: the provers' part of the tip is designed and not in the code (the executor credits the whole 80 percent to the miner, 20 to registered developers); the fee table carries the designed row; the pool is the only thing that pays an internal prover today
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:17:22 +00:00
igneum-labs
3ee5722487
Class v6 10.0l: the third external review (the objective durable GPU competitiveness; the definition on a reference population with cost per accepted unit of work; the coexistence model replaces the capex wall, a new document by 21:00; the claim statement above the served sentence, rotation an optional improvement)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:16:26 +00:00
igneum-labs
11bb46ed28
Class v6 10.0k: the connected-state lane's first rows (63 of 64 registers necessary; the window +0.6 percent on a 5090 at stock; censuses as well as v5; the narrow per-step chain names the two-level-file re-optimisation)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:15:18 +00:00
igneum-labs
f2ff7a3cf8
Merge build/master into reference-apps (receipt.html: the payment receipt copy and the terms block kept over the og lane's older copy; the og metas kept)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:14:48 +00:00
igneum-labs
b247280c8e
Chip text: the window's defence carried with its disagreement (about 0.13 of k against a flop register file; the multi-family adversary's first core reads it as close to nothing; the placed rows settle it), its card cost measured under 5 percent
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:14:27 +00:00
igneum-labs
7ae4890164
Class v6 10.0j (after the landing): the multi-family adversary lane's macro-window core (k 0.40 node-for-node; the window knob buys the card nothing against a macro file) carried beside the k lane's model as a disagreement the placed rows settle
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:13:27 +00:00
igneum-labs
b216afc7e6
Merge counter-asic-4 d6b2b2d7 into master (gate: green on d6b2b2d7, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:12:06 +00:00
igneum-labs
509e18d7c8
Release manifest and the proving economics: site/release-manifest.json served at /release.json (network and chain id, source commits and fingerprints, mining class and dataset, finality rule v3, proof program ids, verifier off per P21, fees, versions per platform, the proving view, generated date); /build, /economics, /miner, /evidence and the litepaper read it at build through data-rm spans and a gate check holds the pages to it; /light, /receipt and the light client say two thirds of total weight; 4463 marked historical in older docs; dated log entries labelled historical; the evidence page's sixth label (activated) and the reference-repository wording; /economics gains "Who pays for proving": three incomes apart, the burned base fee stated, the measured 24-hour payout, the halving walk computed from emission.mjs at build, per card per hour, the two routes priced, no price
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:11:33 +00:00
igneum-labs
a39fecd603
Merge class-v6-floor-denominator-docs-3 4c3b55d8 into master (gate: green on 4c3b55d8, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:11:19 +00:00
igneum-labs
4cef7e3662
Chip text: the bracket serves (about 2.3x to 3.3x a node ahead, 2.0x to 2.9x node for node, approximate and provisional) in place of the provisional 2.2x to 2.4x figures, on main's order; the placed gated core row replaces it when it lands; labels, evidence row 17, X35 and the pin follow
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:10:34 +00:00
igneum-labs
c9af788dea
Merge ca3-coord-record 722b8642 into master (gate: green on 722b8642, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:07:38 +00:00
igneum-labs
8d94675db9
Merge remote-tracking branch 'build/master' into reference-apps
2026-10-08 15:06:22 +00:00
igneum-labs
8ec8a70081
Reference apps: the payment receipt. The transaction's execution outcome is authenticated through the proven segment's receipts commitment: the segment record (BLS by its aggregator, carried under the certificate) commits keccak over the shard receipts roots, the shard's receipts rebuild its ordered trie root in the browser and offline, and the transaction's receipt sits in it (status, logs). Issued for a transaction executed at a paid segment's last block; otherwise the inclusion receipt, with the reason. Eight payment negative cases pass beside the nine inclusion ones; the page and the one-file verifier name which receipt they issue
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:06:21 +00:00
igneum-labs
51d510aae5
Merge site-og-26 ff39805c into master (gate: green on ff39805c, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:05:59 +00:00
igneum-labs
d6b2b2d709
Class v6 10.0i: the adversary's re-optimised core (the gated base k 0.37 at N3, the gated window 0.50, +0.13 of k the window's honest defence; the placed ungated core +64 percent over synthesis) and the bracket the served figures sit in until the placed gated rows at 17:30
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:04:41 +00:00
igneum-labs
4c3b55d8c8
Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 93ab3d4da93ab3d4da1
2026-10-08 15:04:38 +00:00
igneum-labs
02e6588796
Merge class-v6-floor-denominator-docs-2 a1e97f77 into master (gate: green on a1e97f77, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:03:47 +00:00
igneum-labs
a9090d3ca9
Merge the mirror's master 192aa69a into counter-asic-4 (the coord record lane's earlier copy of class-v6-rotating-family.md superseded by this branch's)
...
# Conflicts:
# docs/design/class-v6-rotating-family.md
2026-10-08 15:03:33 +00:00
igneum-labs
f0850b88f2
Chip text: the served sentence opens "adopts the 64-register window and retains it across every rotation" (the close's 10.0h after the site audit read); the card's cost of the window labelled measured (rented 5090 and 4090 at stock, 8 October 2026); the X35 pin follows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:03:10 +00:00
igneum-labs
722b8642e3
Counter ASIC 3.0 status: the public 0.3.26 cut 48f65838 with the 16:00 minute, the first two class v6 packs (hl-v6-fold 482dc0da, hl-v6-rw 30628f8a) an hour early, the census lane's dry PASS and its per-pack pass line, the RX 7600 read (13.88 MH/s at 113 W), lane 5's manifest order, the floor-sm amendment
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:00:15 +00:00
igneum-labs
ff39805c83
site/og: the receipt card re-rendered with its kicker
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:59:10 +00:00
igneum-labs
91a83c88cb
Merge box/master into site-og-26 (the receipt's new wording carried into site/og/pages.mjs)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:58:52 +00:00
igneum-labs
192aa69ac2
Merge ca3-coord-record 0b469a4c into master (gate: green on 0b469a4c, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:58:07 +00:00
igneum-labs
ee0b79ffb1
Class v6: the window's card cost MEASURED (within 5 percent per load with the liveness chain, no spill); the served sentence's one word made honest (adopts, retains across every rotation); lane D's report (x16 over the verifier gate; the genesis table's 75-point spelling under test); lane C's drawn-era F8 read (the per-load class must take (c''')); lane 1's memory-clock ladder (the memory side bought one for one with the rate)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:56:22 +00:00
igneum-labs
74eed899c4
Merge class-v6-floor-sm-docs-2 cb56187a into master (gate: green on cb56187a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 14:56:22 +00:00
igneum-labs
0d911c019d
Merge reference-apps d0dc2aa5 into master (gate: green on d0dc2aa5, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 14:55:35 +00:00
igneum-labs
a1e97f773f
Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c07ef717ec07ef717ee
2026-10-08 14:51:28 +00:00
igneum-labs
496d95f354
site: share cards and metas from one source (site/og), rendered on a build box
...
Every served page now carries its og: and twitter: block from site/og/pages.mjs through site/build.mjs (injected between
share markers on the hand-written pages, through meta() on the generated ones); nothing is pasted per page. New cards under
site/og/: eighteen 1200 x 630 PNGs at about 100 KB and a 1200 x 1200 square each (the second og:image for the readers
that crop square), rendered from site/og/card.html by site/og/render.mjs on build box 2 with its Playwright, never on the
Mac. The old og.png family stays on disk for cached links; nothing points at it. Titles under 60, descriptions under 110,
checked by the build. One command refreshes every card: node site/og/render.mjs.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:51:03 +00:00
igneum-labs
0b469a4c2a
Counter ASIC 3.0 status: the register window's measured set on the 5090 and 4090 (at most 5 percent per load, no spill, no rate per unit of work), all five floor documents on master, lane C's drawn-era F8 row (layer 5 takes the floor), lane D's full report 1058d7e40, lane 5's served text read, the build order's amendments relayed; the 7 October public-text file marked superseded
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:50:51 +00:00
igneum-labs
cb56187a17
Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c2d4effebc2d4effebe
2026-10-08 14:49:41 +00:00
igneum-labs
d0dc2aa557
Merge remote-tracking branch 'build/master' into reference-apps
2026-10-08 14:48:24 +00:00
igneum-labs
3f648a53b1
Reference apps, the review's four orders: /receipt is a transaction inclusion receipt in title, copy, file and the offline verifier's output (a payment receipt authenticates the outcome and is named as the next step); /light states its trusted inputs in one block and reads as a verification path with stated trust assumptions; /oracle discloses the deployer-installed voter table and the unchecked aggregator signature on the page and in trust() (oracle redeployed on the shared verifier, 0x3ad71d46, chain id accepted before and after the class v5 floor); the four words included, executed, proven, finalised defined once in site/partials/terms.html and injected on the three pages
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:48:23 +00:00
