Merge class-v6-connected-docs a072f589 into master (gate: green on a072f589, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
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docs/analysis/class-v6/connected-state.md
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# Class v6: the connected-state variant (8 October 2026)
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The experiment of the external review the founder accepted (the 15:4x BST rules): the remaining chip edge (about 2.0x to 2.2x node-for-node, 2.2x to 2.6x a node ahead) survives because a specialist can separate storage, arithmetic and memory scheduling. This lane reorganised the class v5 work, same dataset, same read width (4 bytes), about the same operation count, so that live state feeds each load address, the memory result feeds mixed arithmetic and cross-lane exchange, and that updates the live state for the next address, with a 64-register window per lane that stays necessary across the whole dependent chain. Research class only, behind `--class cs<W>s<S>x<R>` in `igneum-pow` (`igneum-pow/src/connected.rs`, branch `class-v6-connected` on the box mirror); never a chain class.
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Every number below is measured unless marked modelled or owed. Times are UK (BST).
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## 1. The structure
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| Item | Class v5 (`mx8+sh256x27`, the control) | Connected state (`cs64s27x16`) |
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|---|---|---|
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| Registers per lane | 8 | 64 (the window) |
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| Per iteration | 64 base instructions with 16 loads, then a 256-instruction block run 27 times | 16 steps: a load, then a 27-instruction block run 16 times |
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| Load address | a base register, `x & MASK` (the era stride and site window under an era) | a window register, the same address rule |
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| Memory result | xor into the load's destination | xor into `r[m_j]`; block instruction 0 reads it |
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| Next address | whatever register the next load reads | written by the block's last instruction (add, sub, xor or shfl) from a fresh spine |
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| Result | fold of 8 registers | fold of all 64 (`lo` over the first 32 at 7 i, `hi` over the second 32 at 9 i; the v5 fold at a window of 8) |
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| Loads per hash | 128 | 128 |
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| ALU instructions per hash | 55,680 (55,296 shadow + 384 base) | 55,296 (0.7 percent fewer) |
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| Instruction text per iteration | 320 | 448 |
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| Negative controls kept out | | no long program (1,024), no select tree, no wide read (W = 16), no scratchpad |
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The draw (deterministic from the seed words, attempt k re-seeded as every class): per step `a_j` then `m_j != a_j` (and the era window draws); per block instruction the op from the ten non-load families at the v5 weights, the source from the last four spine entries (the memory result first), the destination uniform over the window, the two immediates, the rotation, the selector bit and the shuffle mask. Four rules the first census pass forced, each a construction rather than a filter:
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1. The cover: the first 64 injecting destinations walk a drawn permutation of the window, so every register takes an injecting write (rule (b)); a uniform draw left one register without one in about 70 percent of candidates.
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2. The fresh spine: only destinations of add, sub, xor, mad and shfl enter the spine, so every address is fresh by dataflow (rule (a')); with a lossy spine every seed exhausted 256 attempts.
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3. Lossy ops feed the next injection: or, mul and mulhi write the register the next injecting instruction of the block writes, so their value enters the chain and no register accumulates a lossy op across the 16 passes (a 16-pass or saturated a register the block never re-injected, a 16-pass mul cleared its low bits: rule (c) refused every candidate).
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4. The two closing instructions of a block come from add, sub, xor and shfl (the census lane's rule for a load source's writer): no product on the address writer (a 16-pass mad on the address register read bit z 57.6 at one site).
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The acceptance rule is the sub-version 3 rule over the window: (b), (a') (the fixpoint over the iteration's execution order), (c) over 64 units (constant bits per register, lane-constant sites, saturation at 1 percent of the window's final values, saturated sources, output bias, distinct addresses, the value-level index-bit read judged inside the site's era window), then (c'') at 0.98 and (c''') at 0.995 over 2^20 evaluations per site. (a) holds by construction.
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## 2. Liveness (seed `igneum-v6c/0`, attempt 0, program id 9ad55de91485542b)
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The tool (`igneum-pow liveness --class cs64s27x16 --seed <s>`) walks the unrolled trace of one hash (128 loads, 55,296 ALU instructions). `live` is the backward set at an address: registers whose value just before the load feeds this or any later address. `dep` is the forward set: registers at the previous address whose values feed this address.
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| Measure | Value |
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|---|---|
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| live before each address | 63 of 64 at every address until the last iteration's tail; iteration 7: 63 62 60 60 60 57 57 54 53 51 45 36 25 20 9 1 |
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| registers read by the result | 64 of 64 (the fold) |
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| dep per step (the same every iteration, the text repeats) | 1 9 13 14 8 15 7 8 12 14 14 13 10 9 14 9; mean 11.2 of 64 |
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| registers touched per block (read or written) | min 16, mean 20.4, max 24 of 64 |
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| reads per register per hash | min 384, mean 1,724, max 3,208 |
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| writes per register per hash | min 128, mean 866, max 1,664 |
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| op mix of the 432 block instructions | add 82, mul 62, xor 51, shfl 51, sub 46, mulhi 39, rotl 35, mad 31, rotr 20, or 15 |
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Meaning: the whole window is necessary over the hash (no register can be dropped or parked for long: the longest gap between writes to one register is under one iteration), and every value is read by a later address, so there is no side calculation a specialist can move to a separate engine. The dependent chain per step is narrow: about 11 of the 64 registers at one address feed the next address through 432 operations, and a block touches about 20. That is the shape a specialist will exploit: a two-level file, about 20 registers hot per step and 44 warm, the hot set moving along the text; the k lane prices exactly that (section 5). The program listing is `liveness.txt` and `program.json` of the pack.
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## 3. Census (the census lane's sub-version 3 harness, `tools/attack/v6-census/v6census.sh`, (c''') 0.995 on, on a rented 5090 host with 40 threads, 16:01 to 16:08 BST)
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| Run | Seeds | Accepted | Exhausted | Rejections per candidate | Mean attempt | Max attempt | Window-bit refusals | Over 6 sigma (reported) |
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|---|---|---|---|---|---|---|---|---|
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| cs64 no era | 256 | 256 | 0 | 0.283 | 0.39 | 5 | off | 146 of 256 (max z 128) |
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| control `mx8+sh256x27` no era (census lane, build-3) | 256 | 256 | 0 | 0.668 | 2.01 | 18 | off | 143 of 256 (max z 97) |
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| cs64 eras 0 to 7, window-bit refusal on | 8 x 32 | 256 | 0 | 0.635 | 1.74 | 8 | 306 | 0 (max z 5.9) |
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| control eras 0 to 7, refusal on (census lane, build-4) | 8 x 32 | 256 | 0 | 0.830 | 4.87 | 22 | 218 | 0 (max z 5.9) |
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| cs64 eras 0 to 7, refusal off | 8 x 32 | 256 | 0 | 0.304 | 0.44 | 2 | off | 94 of 256 (max z 71.5) |
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The no-era rejections are all rule (c) (constant bits, saturation or bias in the 64-unit test); the control's are mostly (a') and (a), which this class satisfies by construction. The window-bit refusals sit on eras 0, 1, 4, 5 and 6 (55 to 64 each) and nearly vanish on eras 2 and 3 (0 and 1): the product-bit class (a product's low bits reaching an address bit through the era stride), the same class the control carries and the layer-1 index fold removes; this class does not change it either way.
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F8 form (`igneum-pow cs-uniform`, 16 seeds x 2^20 nonces, no era): the top 0.1 percent item share reads 0.9987 to 1.0016 of a uniform control of the same size (the control class 0.9993 to 1.0016); the worst per-site distinct ratio 0.9941 (seed 9, site 9; the sequential-nonce sample of the F8 tool, the acceptance's own 2^20 sample passed 0.995 on every accepted program).
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Meaning: the class censuses at least as well as v5 on every instrument of the harness and takes fewer attempts; it inherits v5's product-bit bias and the fix is the same fold. The acceptance costs about 3.7 s per candidate on one core (the (c'') pass dominates, 7 G lane-ops), against v5's 2.8 s.
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## 4. GPU cost
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Instrument: the class v5 nvcc harness (`proto-newpow/class-v5/bench.cu` on `box/ds55-v5`, the v5 design page's 4090 rows), compiled per pack with `-Xptxas -v`, 250 batches of 2^24, nvidia-smi at 1 Hz, both packs on the same card minutes apart; vectors 3 of 3 PASS and the dataset self-test PASS on every row. The cs64 pack is over the class v4 memory-hard dataset (no leaves); v5-genesis carries its 93 leaves. Stock means the card's own power limit and no clock lock.
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| Card | Pack | MH/s | Mean W | Microjoules per hash | Registers per thread | Spills | Resident blocks per SM (1 warp per block) | Fingerprint of 2^24 at base 0 |
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|---|---|---|---|---|---|---|---|---|
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| RTX 5090 (Vast 54862507, driver 580.159.03, 575 W cap), stock | cs64s27x16 | 64.93 | 574.8 | 8.853 | 80 | 0 | 24 | ad0cec2a42c84aff |
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| RTX 5090, the same card | v5-genesis | 65.30 | 574.8 | 8.803 | 48 | 0 | 24 | ae74193ddad19e19 |
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| RTX 4090 (RunPod 386yytbh4bkfnz, driver 580.159.04, 450 W cap), stock | cs64s27x16 | 62.44 | 268.8 | 4.305 | 87 | 0 | 20 | ad0cec2a42c84aff |
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| RTX 4090, the same card | v5-genesis | 62.44 | 271.3 | 4.345 | 32 | 0 | 24 | ae74193ddad19e19 |
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| RTX 5090 on PC 1 at the 1,300 MHz lock | both | OWED: PC 1 booked to 17:40 BST; the bound pack and the kit are at build-1:/srv/builds/igneum-wt-connected/cs-kit (sha c9aff54aaf10d79e) and the hash lane publishes the job when PC 1 frees | | | | | | |
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The kit worker (the brief's instrument, `igneum-worker-cuda --bench --batch-log2 24 --batches 250`, the class v5 kit's NVRTC worker of 7 October loading the pack's `kernel_bound.cu`; check PASS on both packs):
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| Card | Pack | MH/s | Mean W | Microjoules per hash | Registers per thread | Fingerprint |
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|---|---|---|---|---|---|---|
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| RTX 5090 (the Vast card above), stock | cs64s27x16 (bound pack) | 62.88 | 574.2 | 9.131 | 80 | ad0cec2a42c84aff |
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| RTX 5090, the same card | v5-genesis | 62.96 | 571.4 | 9.076 | 48 | ae74193ddad19e19 |
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| RTX 4090 (the RunPod card above), stock | cs64s27x16 (bound pack) | 62.41 | 269.4 | 4.317 | 87 | ad0cec2a42c84aff |
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| RTX 4090, the same card | v5-genesis | 62.39 | 271.9 | 4.358 | 32 | ae74193ddad19e19 |
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Both instruments agree with each other on each card (the harness and the worker within 3 percent of rate) and agree on the comparison: the window moves energy per hash by +0.6 percent on the 5090 (harness and worker alike) and by -0.9 percent on the 4090 (harness and worker alike), inside the run-to-run noise of a power reading. The 4090 is not at its cap (269 W of 450) and both packs read the same rate to three figures, so there the hash is bound by the memory chain, not the ALU or the register file; the 5090 is at its 575 W cap and the window costs under 1 percent of rate. (The fingerprints are the same on both cards and both instruments: ad0cec2a42c84aff for cs64, ae74193ddad19e19 for v5-genesis.)
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Meaning: at stock the window costs the 5090 0.6 percent of energy per hash against a 10 percent budget; the compiled allocation is 80 registers per thread with no spill, so the window is in registers, not local memory, and the occupancy under this harness is the same as v5's. The harness reads 65 MH/s where the NVRTC worker reads about twice that on a 5090 (one warp per block, 24 resident blocks); the ratio between two packs on the same harness is the measurement, the absolute rate is not. The lock row is where the energy comparison binds (the 5090 at the lock reads 2.33 microjoules per hash on v5); the stock rows say the card is bound by its power cap in both cases and the window moves the rate by under 1 percent.
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## 5. The chip side
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The k lane (floor lane 2) priced the re-optimised core on the drawn program at 17:2x BST (synthesis only, a model and never a lower bound; its placed row is due 21:00 as an amendment). The core: 8 lanes, a 64 x 32-bit window per lane in clock-gated flops (a macro file reads within 5 percent), a 512-entry imem holding the 448-instruction text, one in-order op per cycle per lane (the spine's ILP is met by lane count, which is free), every class unit, the load's fold on the address path; gate-level random-input VCD, every pin annotated; 253,059 cells.
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| Row (the k lane's) | pJ per lane-op, ASAP7 | N5 (the card's node) | N3 | N2 | k at the 1,300 lock, N5 / N3 / N2 | k at stock, N5 / N3 |
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|---|---|---|---|---|---|---|
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| cs64s27x16, the re-optimised core (gated window, 512 imem) | 6.3 | 4.4 | 3.2 | 2.3 | 0.71 / 0.51 / 0.37 | 0.39 / 0.28 |
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| the same window on the class v4 draw, 256 imem | 6.2 | 4.3 | 3.1 | 2.2 | 0.70 / 0.50 / 0.36 | 0.38 / 0.27 |
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| the adversary's 32-register base, gated (the genesis window) | 4.5 | 3.2 | 2.3 | 1.6 | 0.51 / 0.37 / 0.26 | 0.28 / 0.20 |
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| the GPU-shaped 64-register core, ungated (shadow-k.md, the earlier default) | 9.7 | 6.8 | 4.9 | 3.5 | 1.09 / 0.78 / 0.56 | 0.60 / 0.43 |
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What the adversary's re-optimisation did to each part of the structure: the gated file charges only the register written, so the whole-window liveness costs it nothing beyond the write it would make anyway and the hot-20 banking of section 2 is not even needed; the 16-pass loop and the 448 text cost the shared imem 0.1 pJ per lane-op; the narrow per-step chain sets the lane count, which is free. The window itself is worth +1.2 pJ per lane-op at N5 over the genesis window (+0.14 of k at the lock), the same knob as the design document's 64-register row; the connected organisation around it adds about 0.1 pJ. The placed ungated core came in 64 percent over its synthesis, so the placed figure is expected near 8 to 10 pJ at ASAP7 (k node-for-node near 0.9 to 1.1, approximate); both rows move together and the ratio below holds.
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## 6. The score and the verdict
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E_GPU over E_adversary, absolute convention, GDDR7 board (E_mem 0.466 microjoules per hash), E_chip = E_mem + 55,296 x e_chip, E_GPU = the 5090 at the lock (2.33 microjoules per hash on class v5) x 1.006 for the window (the stock rows of section 4; the lock row is owed):
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| Core | Node-for-node (N5) | A node ahead (N3) | Two nodes (N2) |
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|---|---|---|---|
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| cs64s27x16, re-optimised | 2.344 / (0.466 + 0.243) = 3.3x | 2.344 / (0.466 + 0.177) = 3.6x | 2.344 / (0.466 + 0.127) = 4.0x |
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| the genesis window (the control) | 2.33 / (0.466 + 0.177) = 3.6x | 2.33 / (0.466 + 0.127) = 3.9x | 2.33 / (0.466 + 0.088) = 4.2x |
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| the window's effect on the chip's edge | 1.10x | 1.08x | 1.05x |
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On the placed figures (both rows 64 percent higher) the pair reads about 2.2x and 2.4x node-for-node and the ratio stays near 1.1x. The gate was 1.25x node-for-node for the 1.5x one-node-ahead ambition; the row reads 1.10x node-for-node and 1.08x a node ahead.
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**Verdict: KILL as a class.** The hypothesis was that a connected organisation of the same work, with the window independently necessary across the whole chain, would deny a specialist its separation of storage, arithmetic and scheduling. It does not: the liveness rows show the window is necessary (63 of 64 at every address) and the chip answers with a clock-gated file that pays per write, not per live register, so necessity costs it nothing; the only term that reaches the chip is the window's own width (+0.14 k at the lock), which the design document already holds as its one robust core knob, and the connected structure adds about 0.1 pJ around it. The GPU side passes its budget with room (+0.6 percent of energy per hash at stock on the 5090, -0.9 percent on the 4090, 80 to 87 registers per thread with no spill), and the census passes every instrument with fewer attempts than v5; neither moves the score. The founder's accepted review stands in a sharper form than before: a specialist's edge against this family is a per-op energy ratio on a known op mix, and reorganising the dependency graph of the same ops does not change what an op costs on either side.
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What is kept: the generator variant and the liveness tool (research class, behind the flag) for the v7 tests below; the measured fact that a 64-register window costs a card under 1 percent at stock, which fixes the design document's modelled "about 0 rate" row; the kit worker and nvcc harness agreement on two cards. What is withdrawn: the "connected state" line as a resistance mechanism.
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## 7. What a v7 variant would test next
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- The index fold on the address (the layer-1 row) in this class, which removes the window-bit refusals on eras 0, 1, 4, 5 and 6 for the control and this class alike.
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- A wider per-step chain: a spine of depth 8 to 16 so `dep` rises from about 11 toward the window, at the cost of ILP on the card (measure the rate first; the chain per step is what a two-level file exploits).
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- The window at 32 and 16 (`cs32s27x16`, `cs16s27x16`) for the k curve, and the block at 16 x 27 (`cs64s16x27`, text 272) if the imem matters to the re-optimised core.
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- The op-mix re-weight of the census lane at this structure (the two closing instructions already take the injecting table).
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- The PC 1 lock row (informational now: the verdict does not turn on it; it lands as an amendment if PC 1 runs it).
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- A knob that reaches a gated file: not more live state but more WRITES per op the chip cannot skip (every op writing two registers, or a window write per load), priced against the card's own write cost first; the k lane's placed row at 21:00 says whether even that moves k.
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docs/analysis/class-v6/logs/connected/bench-4090.log
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docs/analysis/class-v6/logs/connected/bench-4090.log
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RESULT start 2026-10-08T15:14:09Z host=dbd4e396219f arch=sm_89 card=NVIDIA GeForce RTX 4090, 580.159.04, 450.00 W
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RESULT pack packs/cs64-v6c0
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RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas packs/cs64-v6c0 ptxas info : Used 87 registers, used 0 barriers, 376 bytes cmem[0], 8 bytes cmem[2]
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RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas packs/cs64-v6c0 ptxas info : Used 40 registers, used 0 barriers, 372 bytes cmem[0]
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RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas packs/cs64-v6c0 ptxas info : Used 43 registers, used 0 barriers, 364 bytes cmem[0]
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RESULT bench packs/cs64-v6c0 class-v5 bench pack "igneum-v6c/0" class control generator 2 (test harness: no pool, no network, no wallet)
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RESULT bench packs/cs64-v6c0 GPU: NVIDIA GeForce RTX 4090 (128 SMs, cc 8.9, 24081 MiB), CUDA driver 13.0 runtime 12.8
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RESULT bench packs/cs64-v6c0 hash kernel: 87 registers/thread, 20 resident blocks/SM at 1 warp/block
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RESULT bench packs/cs64-v6c0 device memory at start: 395 MiB used of 24081 MiB
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RESULT bench packs/cs64-v6c0 cache fill (GPU): 1.84 ms first, 1.82 ms second
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RESULT bench packs/cs64-v6c0 cache head and last 16 words against the pack: PASS
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RESULT bench packs/cs64-v6c0 dataset build (GPU): 30.57 ms first, 30.54 ms second (16777216 items, 1024 MiB)
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RESULT bench packs/cs64-v6c0 device memory after the build: 1675 MiB used
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RESULT bench packs/cs64-v6c0 dataset self-test: head PASS, last PASS, samples 64 of 64
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RESULT bench packs/cs64-v6c0 vector warps against the pack: 3 of 3 PASS
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RESULT bench packs/cs64-v6c0 fingerprint of 2^24 outputs at base 0: ad0cec2a42c84aff (lane 0 c2b2466c00d3f12b)
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RESULT bench packs/cs64-v6c0 hash rate: 62.436 MH/s over 250 batches of 2^24 (GPU event time 67177.7 ms)
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RESULT bench packs/cs64-v6c0 RESULT pack=igneum-v6c/0 class=control build_ms=30.54 rate_mhs=62.436 vectors=3/3
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RESULT smi packs/cs64-v6c0 samples 64 mean_power_w 268.8 mean_sm_mhz 2811 mean_mem_mhz 10251
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RESULT pack v5-genesis
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RESULT ptxas v5-genesis cc1plus: fatal error: ../../bench.cu: No such file or directory
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RESULT ptxas v5-genesis 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas v5-genesis ptxas info : Used 32 registers, used 0 barriers, 376 bytes cmem[0]
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RESULT ptxas v5-genesis 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas v5-genesis ptxas info : Used 40 registers, used 0 barriers, 384 bytes cmem[0]
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RESULT ptxas v5-genesis 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
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RESULT ptxas v5-genesis ptxas info : Used 43 registers, used 0 barriers, 364 bytes cmem[0]
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RESULT bench v5-genesis class-v5 bench pack "igneum-genesis" class v5 generator 5 (test harness: no pool, no network, no wallet)
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RESULT bench v5-genesis GPU: NVIDIA GeForce RTX 4090 (128 SMs, cc 8.9, 24081 MiB), CUDA driver 13.0 runtime 12.8
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RESULT bench v5-genesis hash kernel: 32 registers/thread, 24 resident blocks/SM at 1 warp/block
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RESULT bench v5-genesis device memory at start: 395 MiB used of 24081 MiB
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RESULT bench v5-genesis cache fill (GPU): 1.83 ms first, 1.81 ms second
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RESULT bench v5-genesis cache head and last 16 words against the pack: PASS
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RESULT bench v5-genesis leaves: 93 x 64 B from leaves.bin (5952 bytes), FNV-1a 64 850ad094a937a5c5 against the pack's 850ad094a937a5c5: PASS; state root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, chain block af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 (159357)
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RESULT bench v5-genesis dataset build (GPU): 30.80 ms first, 30.75 ms second (16777216 items, 1024 MiB)
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RESULT bench v5-genesis device memory after the build: 1677 MiB used
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RESULT bench v5-genesis dataset self-test: head PASS, last PASS, samples 64 of 64
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RESULT bench v5-genesis vector warps against the pack: 3 of 3 PASS
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RESULT bench v5-genesis fingerprint of 2^24 outputs at base 0: ae74193ddad19e19 (lane 0 61b73fdc4b19aa6e)
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RESULT bench v5-genesis hash rate: 62.437 MH/s over 250 batches of 2^24 (GPU event time 67176.1 ms)
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RESULT bench v5-genesis RESULT pack=igneum-genesis class=v5 build_ms=30.75 rate_mhs=62.437 vectors=3/3
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RESULT smi v5-genesis samples 64 mean_power_w 271.3 mean_sm_mhz 2805 mean_mem_mhz 10251
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RESULT end 2026-10-08T15:16:34Z
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||||
40
docs/analysis/class-v6/logs/connected/bench-5090c.log
Normal file
40
docs/analysis/class-v6/logs/connected/bench-5090c.log
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
RESULT start 2026-10-08T15:09:57Z host=f271665b754f arch=sm_120 card=NVIDIA GeForce RTX 5090, 580.159.03, 575.00 W
|
||||
RESULT pack packs/cs64-v6c0
|
||||
RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
|
||||
RESULT ptxas packs/cs64-v6c0 ptxas info : Used 80 registers, used 0 barriers
|
||||
RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
|
||||
RESULT ptxas packs/cs64-v6c0 ptxas info : Used 38 registers, used 0 barriers
|
||||
RESULT ptxas packs/cs64-v6c0 0 bytes stack frame, 0 bytes spill stores, 0 bytes spill loads
|
||||
RESULT ptxas packs/cs64-v6c0 ptxas info : Used 41 registers, used 0 barriers
|
||||
RESULT bench packs/cs64-v6c0 class-v5 bench pack "igneum-v6c/0" class control generator 2 (test harness: no pool, no network, no wallet)
|
||||
RESULT bench packs/cs64-v6c0 GPU: NVIDIA GeForce RTX 5090 (170 SMs, cc 12.0, 32109 MiB), CUDA driver 13.0 runtime 12.8
|
||||
RESULT bench packs/cs64-v6c0 hash kernel: 80 registers/thread, 24 resident blocks/SM at 1 warp/block
|
||||
RESULT bench packs/cs64-v6c0 device memory at start: 6188 MiB used of 32109 MiB
|
||||
RESULT bench packs/cs64-v6c0 cache fill (GPU): 0.65 ms first, 0.65 ms second
|
||||
RESULT bench packs/cs64-v6c0 cache head and last 16 words against the pack: PASS
|
||||
RESULT bench packs/cs64-v6c0 dataset build (GPU): 29.75 ms first, 27.68 ms second (16777216 items, 1024 MiB)
|
||||
RESULT bench packs/cs64-v6c0 device memory after the build: 7468 MiB used
|
||||
RESULT bench packs/cs64-v6c0 dataset self-test: head PASS, last PASS, samples 64 of 64
|
||||
RESULT bench packs/cs64-v6c0 vector warps against the pack: 3 of 3 PASS
|
||||
RESULT bench packs/cs64-v6c0 fingerprint of 2^24 outputs at base 0: ad0cec2a42c84aff (lane 0 c2b2466c00d3f12b)
|
||||
RESULT bench packs/cs64-v6c0 hash rate: 64.929 MH/s over 250 batches of 2^24 (GPU event time 64598.6 ms)
|
||||
RESULT bench packs/cs64-v6c0 RESULT pack=igneum-v6c/0 class=control build_ms=27.68 rate_mhs=64.929 vectors=3/3
|
||||
RESULT smi packs/cs64-v6c0 samples 128 mean_power_w 574.8 mean_sm_mhz 2778 mean_mem_mhz 13801
|
||||
RESULT pack v5-genesis
|
||||
RESULT ptxas v5-genesis cc1plus: fatal error: ../../bench.cu: No such file or directory
|
||||
RESULT bench v5-genesis class-v5 bench pack "igneum-genesis" class v5 generator 5 (test harness: no pool, no network, no wallet)
|
||||
RESULT bench v5-genesis GPU: NVIDIA GeForce RTX 5090 (170 SMs, cc 12.0, 32109 MiB), CUDA driver 13.0 runtime 12.8
|
||||
RESULT bench v5-genesis hash kernel: 48 registers/thread, 24 resident blocks/SM at 1 warp/block
|
||||
RESULT bench v5-genesis device memory at start: 6188 MiB used of 32109 MiB
|
||||
RESULT bench v5-genesis cache fill (GPU): 0.65 ms first, 0.65 ms second
|
||||
RESULT bench v5-genesis cache head and last 16 words against the pack: PASS
|
||||
RESULT bench v5-genesis leaves: 93 x 64 B from leaves.bin (5952 bytes), FNV-1a 64 850ad094a937a5c5 against the pack's 850ad094a937a5c5: PASS; state root 1c583d352bb9c75a06dadb8d82d42836ebe8afa82d0b413be87bf921741f1526, chain block af89be5ddbadb6f6b4aee28ac8f249713be5d4c12621e3cea7f83ceada3c66b3 (159357)
|
||||
RESULT bench v5-genesis dataset build (GPU): 27.57 ms first, 27.53 ms second (16777216 items, 1024 MiB)
|
||||
RESULT bench v5-genesis device memory after the build: 7470 MiB used
|
||||
RESULT bench v5-genesis dataset self-test: head PASS, last PASS, samples 64 of 64
|
||||
RESULT bench v5-genesis vector warps against the pack: 3 of 3 PASS
|
||||
RESULT bench v5-genesis fingerprint of 2^24 outputs at base 0: ae74193ddad19e19 (lane 0 61b73fdc4b19aa6e)
|
||||
RESULT bench v5-genesis hash rate: 65.303 MH/s over 250 batches of 2^24 (GPU event time 64228.4 ms)
|
||||
RESULT bench v5-genesis RESULT pack=igneum-genesis class=v5 build_ms=27.53 rate_mhs=65.303 vectors=3/3
|
||||
RESULT smi v5-genesis samples 126 mean_power_w 574.8 mean_sm_mhz 2788 mean_mem_mhz 13801
|
||||
RESULT end 2026-10-08T15:12:13Z
|
||||
259
docs/analysis/class-v6/logs/connected/cs64-era-bt.tsv
Normal file
259
docs/analysis/class-v6/logs/connected/cs64-era-bt.tsv
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
# cs64-era-bt class cs64s27x16 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 4 weights base bittest 1 bin 54b905920b91becc start 2026-10-08T15:01:08Z host f271665b754f threads 40
|
||||
cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons
|
||||
cs64-era-bt 0 16 9 1 8 3.2 7 8 c,=7;c=1;
|
||||
cs64-era-bt 0 21 2 1 1 3.2 14 21 c=1;
|
||||
cs64-era-bt 0 20 1 1 0 3.8 10 1
|
||||
cs64-era-bt 0 30 2 1 1 3.0 3 18 c,=1;
|
||||
cs64-era-bt 0 19 3 1 2 3.6 1 19 c,=2;
|
||||
cs64-era-bt 1 1 2 1 1 2.8 6 20 c=1;
|
||||
cs64-era-bt 0 12 5 1 4 3.5 10 25 c,=3;c=1;
|
||||
cs64-era-bt 0 18 4 1 3 3.2 11 13 c,=3;
|
||||
cs64-era-bt 0 17 7 1 6 4.2 4 19 c,=4;c=2;
|
||||
cs64-era-bt 0 6 1 1 0 5.1 3 19
|
||||
cs64-era-bt 0 28 5 1 4 5.9 12 19 c,=2;c=2;
|
||||
cs64-era-bt 0 0 9 1 8 4.2 9 19 c,=5;c=3;
|
||||
cs64-era-bt 0 5 2 1 1 3.9 5 1 c=1;
|
||||
cs64-era-bt 0 29 1 1 0 4.2 8 22
|
||||
cs64-era-bt 1 0 9 1 8 3.2 14 26 c,=5;c=3;
|
||||
cs64-era-bt 0 11 2 1 1 3.1 5 0 c,=1;
|
||||
cs64-era-bt 0 7 4 1 3 2.9 11 20 c,=3;
|
||||
cs64-era-bt 0 15 1 1 0 2.8 14 16
|
||||
cs64-era-bt 1 7 4 1 3 3.3 12 8 c,=3;
|
||||
cs64-era-bt 0 25 2 1 1 3.3 2 14 c=1;
|
||||
cs64-era-bt 0 13 5 1 4 3.2 13 11 c,=4;
|
||||
cs64-era-bt 0 4 1 1 0 3.2 12 20
|
||||
cs64-era-bt 0 31 3 1 2 3.0 1 6 c,=1;c=1;
|
||||
cs64-era-bt 0 22 1 1 0 3.0 1 19
|
||||
cs64-era-bt 0 26 3 1 2 3.4 3 13 c,=2;
|
||||
cs64-era-bt 0 14 6 1 5 3.5 1 19 c,=4;c=1;
|
||||
cs64-era-bt 0 10 4 1 3 3.0 0 18 c=2;c,=1;
|
||||
cs64-era-bt 1 2 1 1 0 2.9 15 20
|
||||
cs64-era-bt 1 4 3 1 2 3.2 7 22 c,=2;
|
||||
cs64-era-bt 0 27 2 1 1 3.9 15 19 c,=1;
|
||||
cs64-era-bt 0 9 1 1 0 3.1 1 17
|
||||
cs64-era-bt 1 3 1 1 0 3.3 15 7
|
||||
cs64-era-bt 0 3 1 1 0 2.7 12 10
|
||||
cs64-era-bt 1 5 2 1 1 3.6 4 16 c=1;
|
||||
cs64-era-bt 0 23 3 1 2 3.7 3 20 c,=2;
|
||||
cs64-era-bt 0 8 7 1 6 5.3 8 19 c,=5;c=1;
|
||||
cs64-era-bt 1 6 9 1 8 2.8 14 19 c,=6;c=2;
|
||||
cs64-era-bt 0 1 6 1 5 3.3 0 8 c,=3;c=2;
|
||||
cs64-era-bt 0 2 1 1 0 2.8 9 21
|
||||
cs64-era-bt 0 24 6 1 5 3.0 6 9 c,=5;
|
||||
cs64-era-bt 1 8 7 1 6 5.3 8 6 c,=5;c=1;
|
||||
cs64-era-bt 1 14 6 1 5 2.9 1 6 c,=4;c=1;
|
||||
cs64-era-bt 1 15 1 1 0 3.2 6 1
|
||||
cs64-era-bt 1 22 1 1 0 3.3 4 25
|
||||
cs64-era-bt 1 11 2 1 1 3.1 3 6 c,=1;
|
||||
cs64-era-bt 1 9 1 1 0 4.0 11 0
|
||||
cs64-era-bt 1 19 3 1 2 3.2 5 13 c,=2;
|
||||
cs64-era-bt 1 10 4 1 3 4.0 10 17 c=2;c,=1;
|
||||
cs64-era-bt 1 30 2 1 1 3.1 15 15 c,=1;
|
||||
cs64-era-bt 1 13 5 1 4 3.3 7 3 c,=4;
|
||||
cs64-era-bt 2 1 2 1 1 3.3 0 4 c=1;
|
||||
cs64-era-bt 1 25 2 1 1 3.3 14 25 c,=1;
|
||||
cs64-era-bt 1 12 5 1 4 3.1 2 9 c,=3;c=1;
|
||||
cs64-era-bt 2 15 1 1 0 3.0 13 7
|
||||
cs64-era-bt 1 28 3 1 2 3.6 4 18 c,=1;c=1;
|
||||
cs64-era-bt 1 16 9 1 8 3.3 13 18 c,=7;c=1;
|
||||
cs64-era-bt 1 17 7 1 6 2.9 7 25 c,=4;c=2;
|
||||
cs64-era-bt 1 20 1 1 0 3.0 15 9
|
||||
cs64-era-bt 1 21 2 1 1 2.6 11 19 c=1;
|
||||
cs64-era-bt 2 5 2 1 1 3.0 10 12 c=1;
|
||||
cs64-era-bt 2 13 2 1 1 3.1 2 26 c=1;
|
||||
cs64-era-bt 1 27 2 1 1 5.8 15 6 c,=1;
|
||||
cs64-era-bt 2 12 2 1 1 2.8 13 23 c=1;
|
||||
cs64-era-bt 1 18 4 1 3 3.4 0 5 c,=3;
|
||||
cs64-era-bt 1 29 1 1 0 3.9 10 6
|
||||
cs64-era-bt 1 31 4 1 3 3.5 1 23 c=2;c,=1;
|
||||
cs64-era-bt 2 11 2 1 1 3.0 12 15 c=1;
|
||||
cs64-era-bt 1 23 1 1 0 4.8 12 6
|
||||
cs64-era-bt 1 26 3 1 2 3.5 5 8 c,=2;
|
||||
cs64-era-bt 2 3 1 1 0 2.6 11 1
|
||||
cs64-era-bt 1 24 6 1 5 2.9 0 19 c,=5;
|
||||
cs64-era-bt 2 16 1 1 0 3.0 7 12
|
||||
cs64-era-bt 2 4 1 1 0 2.7 0 10
|
||||
cs64-era-bt 2 8 2 1 1 3.5 13 24 c=1;
|
||||
cs64-era-bt 2 0 2 1 1 3.1 5 25 c=1;
|
||||
cs64-era-bt 2 9 1 1 0 2.6 6 1
|
||||
cs64-era-bt 2 6 1 1 0 3.1 0 1
|
||||
cs64-era-bt 2 10 1 1 0 3.1 2 20
|
||||
cs64-era-bt 2 14 1 1 0 3.2 3 15
|
||||
cs64-era-bt 2 2 1 1 0 3.3 0 0
|
||||
cs64-era-bt 2 7 2 1 1 3.2 9 24 c=1;
|
||||
cs64-era-bt 2 17 1 1 0 2.7 10 2
|
||||
cs64-era-bt 2 18 1 1 0 3.2 3 11
|
||||
cs64-era-bt 2 26 2 1 1 4.6 1 26 c=1;
|
||||
cs64-era-bt 2 21 2 1 1 2.8 15 4 c=1;
|
||||
cs64-era-bt 2 29 1 1 0 3.5 11 7
|
||||
cs64-era-bt 2 23 1 1 0 3.7 15 20
|
||||
cs64-era-bt 2 24 1 1 0 3.5 3 11
|
||||
cs64-era-bt 2 19 3 1 2 3.1 8 20 c=2;
|
||||
cs64-era-bt 2 20 1 1 0 2.8 10 3
|
||||
cs64-era-bt 3 5 2 1 1 3.1 3 20 c=1;
|
||||
cs64-era-bt 3 4 1 1 0 3.7 9 10
|
||||
cs64-era-bt 2 31 1 1 0 3.3 15 18
|
||||
cs64-era-bt 2 22 1 1 0 2.9 5 1
|
||||
cs64-era-bt 3 11 2 1 1 3.2 6 13 c,=1;
|
||||
cs64-era-bt 3 1 2 1 1 3.3 9 13 c=1;
|
||||
cs64-era-bt 2 30 1 1 0 3.1 8 20
|
||||
cs64-era-bt 3 16 1 1 0 3.2 13 0
|
||||
cs64-era-bt 3 2 1 1 0 3.1 3 25
|
||||
cs64-era-bt 3 8 2 1 1 3.3 0 14 c=1;
|
||||
cs64-era-bt 3 0 2 1 1 3.2 0 7 c=1;
|
||||
cs64-era-bt 2 28 2 1 1 3.0 2 23 c=1;
|
||||
cs64-era-bt 2 27 1 1 0 3.3 9 18
|
||||
cs64-era-bt 3 14 1 1 0 2.8 2 18
|
||||
cs64-era-bt 2 25 2 1 1 3.1 2 7 c=1;
|
||||
cs64-era-bt 3 20 1 1 0 3.4 2 2
|
||||
cs64-era-bt 3 6 1 1 0 3.1 2 9
|
||||
cs64-era-bt 3 18 1 1 0 2.8 9 2
|
||||
cs64-era-bt 3 22 1 1 0 3.0 11 11
|
||||
cs64-era-bt 3 9 1 1 0 3.4 3 9
|
||||
cs64-era-bt 3 3 1 1 0 3.3 2 14
|
||||
cs64-era-bt 3 10 1 1 0 3.8 5 4
|
||||
cs64-era-bt 3 15 1 1 0 2.7 7 3
|
||||
cs64-era-bt 3 13 2 1 1 3.1 0 25 c=1;
|
||||
cs64-era-bt 3 12 2 1 1 3.4 14 17 c=1;
|
||||
cs64-era-bt 3 7 2 1 1 3.2 8 17 c=1;
|
||||
cs64-era-bt 3 19 3 1 2 3.3 13 17 c=2;
|
||||
cs64-era-bt 3 26 2 1 1 3.3 5 16 c=1;
|
||||
cs64-era-bt 3 21 2 1 1 3.0 0 15 c=1;
|
||||
cs64-era-bt 3 29 1 1 0 3.0 5 7
|
||||
cs64-era-bt 3 31 1 1 0 3.4 15 8
|
||||
cs64-era-bt 3 17 1 1 0 3.0 2 12
|
||||
cs64-era-bt 3 23 1 1 0 2.9 3 25
|
||||
cs64-era-bt 3 25 2 1 1 3.2 13 6 c=1;
|
||||
cs64-era-bt 4 1 2 1 1 3.3 12 22 c=1;
|
||||
cs64-era-bt 3 24 1 1 0 3.5 13 5
|
||||
cs64-era-bt 3 27 1 1 0 2.9 15 13
|
||||
cs64-era-bt 3 28 2 1 1 4.4 15 0 c=1;
|
||||
cs64-era-bt 4 12 5 1 4 3.6 7 23 c,=3;c=1;
|
||||
cs64-era-bt 3 30 1 1 0 2.8 8 20
|
||||
cs64-era-bt 4 10 4 1 3 3.1 11 16 c=2;c,=1;
|
||||
cs64-era-bt 4 6 1 1 0 5.0 3 10
|
||||
cs64-era-bt 4 2 1 1 0 2.9 10 22
|
||||
cs64-era-bt 4 0 9 1 8 3.7 9 10 c,=5;c=3;
|
||||
cs64-era-bt 4 4 3 1 2 2.8 4 24 c,=2;
|
||||
cs64-era-bt 4 5 2 1 1 3.3 15 27 c=1;
|
||||
cs64-era-bt 4 11 2 1 1 3.7 8 16 c,=1;
|
||||
cs64-era-bt 4 3 1 1 0 2.7 10 11
|
||||
cs64-era-bt 4 7 4 1 3 4.4 11 10 c,=3;
|
||||
cs64-era-bt 4 19 3 1 2 3.4 2 0 c,=2;
|
||||
cs64-era-bt 4 13 5 1 4 3.1 15 14 c,=3;c=1;
|
||||
cs64-era-bt 4 8 7 1 6 5.1 12 10 c,=5;c=1;
|
||||
cs64-era-bt 4 16 9 1 8 2.7 5 8 c,=7;c=1;
|
||||
cs64-era-bt 4 15 1 1 0 3.2 14 25
|
||||
cs64-era-bt 4 9 1 1 0 3.7 6 8
|
||||
cs64-era-bt 4 24 6 1 5 3.7 7 11 c,=5;
|
||||
cs64-era-bt 4 14 6 1 5 3.3 3 20 c,=4;c=1;
|
||||
cs64-era-bt 4 21 2 1 1 2.8 8 10 c=1;
|
||||
cs64-era-bt 4 31 4 1 3 3.4 3 20 c=2;c,=1;
|
||||
cs64-era-bt 4 29 1 1 0 3.7 10 9
|
||||
cs64-era-bt 4 17 7 1 6 3.6 8 12 c,=4;c=2;
|
||||
cs64-era-bt 4 28 3 1 2 3.3 8 6 c,=1;c=1;
|
||||
cs64-era-bt 4 25 2 1 1 3.3 0 22 c=1;
|
||||
cs64-era-bt 4 18 4 1 3 3.4 3 16 c,=3;
|
||||
cs64-era-bt 4 20 1 1 0 3.2 9 11
|
||||
cs64-era-bt 5 7 4 1 3 4.0 11 22 c,=3;
|
||||
cs64-era-bt 4 22 1 1 0 3.2 8 24
|
||||
cs64-era-bt 4 30 2 1 1 2.7 7 14 c,=1;
|
||||
cs64-era-bt 5 1 2 1 1 3.2 9 2 c=1;
|
||||
cs64-era-bt 4 26 3 1 2 3.6 12 24 c,=2;
|
||||
cs64-era-bt 4 23 1 1 0 5.8 12 10
|
||||
cs64-era-bt 4 27 3 1 2 4.0 15 21 c,=2;
|
||||
cs64-era-bt 5 3 1 1 0 3.1 5 8
|
||||
cs64-era-bt 5 2 1 1 0 3.0 2 6
|
||||
cs64-era-bt 5 5 2 1 1 3.5 14 23 c=1;
|
||||
cs64-era-bt 5 6 1 1 0 4.6 3 22
|
||||
cs64-era-bt 5 8 7 1 6 5.2 8 22 c,=5;c=1;
|
||||
cs64-era-bt 5 0 9 1 8 2.7 8 23 c,=5;c=3;
|
||||
cs64-era-bt 5 4 3 1 2 3.0 12 20 c,=2;
|
||||
cs64-era-bt 5 9 1 1 0 4.1 8 7
|
||||
cs64-era-bt 5 12 5 1 4 3.2 12 13 c,=3;c=1;
|
||||
cs64-era-bt 5 14 6 1 5 3.7 1 22 c,=4;c=1;
|
||||
cs64-era-bt 5 11 2 1 1 3.1 4 11 c,=1;
|
||||
cs64-era-bt 5 10 4 1 3 3.2 6 5 c=2;c,=1;
|
||||
cs64-era-bt 5 15 1 1 0 3.6 13 2
|
||||
cs64-era-bt 5 16 9 1 8 2.8 15 2 c,=7;c=1;
|
||||
cs64-era-bt 5 20 1 1 0 3.3 2 16
|
||||
cs64-era-bt 5 21 2 1 1 3.1 10 16 c=1;
|
||||
cs64-era-bt 5 17 7 1 6 3.0 5 19 c,=4;c=2;
|
||||
cs64-era-bt 5 19 3 1 2 2.7 14 24 c,=2;
|
||||
cs64-era-bt 5 13 5 1 4 3.2 10 13 c,=4;
|
||||
cs64-era-bt 5 29 1 1 0 3.6 12 26
|
||||
cs64-era-bt 5 22 1 1 0 3.4 0 16
|
||||
cs64-era-bt 5 25 2 1 1 3.0 5 1 c=1;
|
||||
cs64-era-bt 5 18 4 1 3 2.8 11 4 c,=3;
|
||||
cs64-era-bt 5 30 2 1 1 3.0 15 21 c,=1;
|
||||
cs64-era-bt 5 24 6 1 5 2.9 14 1 c,=5;
|
||||
cs64-era-bt 5 23 1 1 0 5.7 12 22
|
||||
cs64-era-bt 5 27 2 1 1 5.0 15 22 c,=1;
|
||||
cs64-era-bt 5 28 5 1 4 3.2 12 22 c,=2;c=2;
|
||||
cs64-era-bt 6 5 2 1 1 2.8 5 11 c=1;
|
||||
cs64-era-bt 5 26 3 1 2 3.2 5 21 c,=2;
|
||||
cs64-era-bt 6 4 3 1 2 3.1 12 10 c,=2;
|
||||
cs64-era-bt 6 2 1 1 0 3.1 0 9
|
||||
cs64-era-bt 6 0 9 1 8 3.0 1 26 c,=5;c=3;
|
||||
cs64-era-bt 6 7 4 1 3 3.6 9 16 c,=3;
|
||||
cs64-era-bt 6 6 9 1 8 3.1 10 5 c,=6;c=2;
|
||||
cs64-era-bt 6 1 2 1 1 3.4 7 27 c=1;
|
||||
cs64-era-bt 5 31 4 1 3 3.7 5 7 c=2;c,=1;
|
||||
cs64-era-bt 6 11 2 1 1 3.0 6 22 c,=1;
|
||||
cs64-era-bt 6 10 4 1 3 3.3 10 1 c=2;c,=1;
|
||||
cs64-era-bt 6 3 1 1 0 4.0 10 5
|
||||
cs64-era-bt 6 18 4 1 3 3.2 13 25 c,=3;
|
||||
cs64-era-bt 6 8 7 1 6 5.7 8 3 c,=5;c=1;
|
||||
cs64-era-bt 6 9 1 1 0 2.5 9 4
|
||||
cs64-era-bt 6 14 6 1 5 4.0 12 12 c,=4;c=1;
|
||||
cs64-era-bt 6 13 5 1 4 3.7 2 25 c,=4;
|
||||
cs64-era-bt 6 12 5 1 4 2.7 2 3 c,=3;c=1;
|
||||
cs64-era-bt 6 20 1 1 0 3.0 4 26
|
||||
cs64-era-bt 6 15 1 1 0 3.0 11 24
|
||||
cs64-era-bt 6 21 2 1 1 2.7 0 13 c=1;
|
||||
cs64-era-bt 6 23 3 1 2 2.6 8 13 c,=2;
|
||||
cs64-era-bt 6 27 2 1 1 3.0 6 17 c,=1;
|
||||
cs64-era-bt 6 24 6 1 5 3.0 9 22 c,=5;
|
||||
cs64-era-bt 6 31 4 1 3 3.6 1 16 c=2;c,=1;
|
||||
cs64-era-bt 6 16 9 1 8 2.9 8 0 c,=7;c=1;
|
||||
cs64-era-bt 6 19 3 1 2 3.0 15 2 c,=2;
|
||||
cs64-era-bt 6 17 7 1 6 2.8 11 0 c,=4;c=2;
|
||||
cs64-era-bt 6 29 1 1 0 3.2 14 17
|
||||
cs64-era-bt 6 26 3 1 2 2.7 7 21 c,=2;
|
||||
cs64-era-bt 7 6 1 1 0 4.3 3 7
|
||||
cs64-era-bt 6 22 1 1 0 3.9 9 14
|
||||
cs64-era-bt 7 11 2 1 1 3.8 14 24 c,=1;
|
||||
cs64-era-bt 6 30 2 1 1 2.7 7 7 c,=1;
|
||||
cs64-era-bt 6 28 5 1 4 4.3 10 20 c,=2;c=2;
|
||||
cs64-era-bt 7 1 2 1 1 2.9 8 11 c=1;
|
||||
cs64-era-bt 6 25 2 1 1 3.0 2 1 c=1;
|
||||
cs64-era-bt 7 0 2 1 1 3.3 1 12 c=1;
|
||||
cs64-era-bt 7 5 2 1 1 3.3 4 23 c=1;
|
||||
cs64-era-bt 7 4 1 1 0 3.1 13 14
|
||||
cs64-era-bt 7 12 5 1 4 3.3 4 5 c=3;c,=1;
|
||||
cs64-era-bt 7 13 4 1 3 2.7 8 11 c,=2;c=1;
|
||||
cs64-era-bt 7 9 1 1 0 3.4 12 24
|
||||
cs64-era-bt 7 2 1 1 0 2.6 5 8
|
||||
cs64-era-bt 7 3 1 1 0 3.8 14 22
|
||||
cs64-era-bt 7 10 4 1 3 4.0 13 25 c=2;c,=1;
|
||||
cs64-era-bt 7 8 2 1 1 3.0 12 17 c=1;
|
||||
cs64-era-bt 7 7 2 1 1 2.9 13 6 c,=1;
|
||||
cs64-era-bt 7 15 1 1 0 2.7 14 22
|
||||
cs64-era-bt 7 14 1 1 0 3.1 11 1
|
||||
cs64-era-bt 7 21 2 1 1 2.8 7 21 c=1;
|
||||
cs64-era-bt 7 17 1 1 0 3.3 5 11
|
||||
cs64-era-bt 7 25 2 1 1 2.9 14 21 c=1;
|
||||
cs64-era-bt 7 24 1 1 0 3.2 3 20
|
||||
cs64-era-bt 7 26 2 1 1 2.3 3 20 c,=1;
|
||||
cs64-era-bt 7 23 1 1 0 3.8 12 27
|
||||
cs64-era-bt 7 18 1 1 0 2.9 14 23
|
||||
cs64-era-bt 7 16 2 1 1 3.7 5 11 c,=1;
|
||||
cs64-era-bt 7 27 2 1 1 3.5 13 8 c,=1;
|
||||
cs64-era-bt 7 20 1 1 0 3.0 3 14
|
||||
cs64-era-bt 7 22 1 1 0 2.8 5 25
|
||||
cs64-era-bt 7 30 1 1 0 5.9 2 27
|
||||
cs64-era-bt 7 29 1 1 0 3.2 13 4
|
||||
cs64-era-bt 7 31 1 1 0 3.8 5 27
|
||||
cs64-era-bt 7 19 3 1 2 3.0 13 1 c=2;
|
||||
cs64-era-bt 7 28 2 1 1 3.0 14 11 c=1;
|
||||
# end 2026-10-08T15:07:36Z rows=257
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
259
docs/analysis/class-v6/logs/connected/cs64-era-nobt.tsv
Normal file
259
docs/analysis/class-v6/logs/connected/cs64-era-nobt.tsv
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
# cs64-era-nobt class cs64s27x16 eras [0,1,2,3,4,5,6,7] seeds 32 era-widths 4 weights base bittest off bin 54b905920b91becc start 2026-10-08T15:01:08Z host f271665b754f threads 24
|
||||
cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons
|
||||
cs64-era-nobt 0 21 2 1 1 3.2 14 21 c=1;
|
||||
cs64-era-nobt 0 6 1 1 0 5.1 3 19
|
||||
cs64-era-nobt 0 2 1 1 0 2.8 9 21
|
||||
cs64-era-nobt 0 4 1 1 0 3.2 12 20
|
||||
cs64-era-nobt 0 16 1 1 0 24.0 13 19
|
||||
cs64-era-nobt 0 12 2 1 1 12.5 15 19 c=1;
|
||||
cs64-era-nobt 0 17 1 1 0 24.9 13 19
|
||||
cs64-era-nobt 0 8 2 1 1 32.0 3 19 c=1;
|
||||
cs64-era-nobt 0 3 1 1 0 2.7 12 10
|
||||
cs64-era-nobt 0 15 1 1 0 2.8 14 16
|
||||
cs64-era-nobt 0 1 2 1 1 7.0 1 20 c=1;
|
||||
cs64-era-nobt 0 19 3 1 2 3.6 1 19 c=2;
|
||||
cs64-era-nobt 0 11 2 1 1 3.1 5 0 c=1;
|
||||
cs64-era-nobt 0 7 2 1 1 46.9 13 19 c=1;
|
||||
cs64-era-nobt 0 22 1 1 0 3.0 1 19
|
||||
cs64-era-nobt 0 10 1 1 0 16.2 6 19
|
||||
cs64-era-nobt 0 18 1 1 0 14.6 2 19
|
||||
cs64-era-nobt 0 0 2 1 1 10.8 0 19 c=1;
|
||||
cs64-era-nobt 0 9 1 1 0 3.1 1 17
|
||||
cs64-era-nobt 0 14 1 1 0 65.0 8 19
|
||||
cs64-era-nobt 0 5 2 1 1 3.9 5 1 c=1;
|
||||
cs64-era-nobt 0 23 1 1 0 7.4 12 19
|
||||
cs64-era-nobt 0 13 2 1 1 31.2 12 19 c=1;
|
||||
cs64-era-nobt 0 20 1 1 0 3.8 10 1
|
||||
cs64-era-nobt 0 24 1 1 0 31.8 2 19
|
||||
cs64-era-nobt 0 30 1 1 0 46.5 14 19
|
||||
cs64-era-nobt 0 26 2 1 1 29.4 3 19 c=1;
|
||||
cs64-era-nobt 0 31 1 1 0 6.9 0 19
|
||||
cs64-era-nobt 0 29 1 1 0 4.2 8 22
|
||||
cs64-era-nobt 0 28 2 1 1 70.2 15 19 c=1;
|
||||
cs64-era-nobt 0 27 1 1 0 8.7 9 19
|
||||
cs64-era-nobt 1 3 1 1 0 3.3 15 7
|
||||
cs64-era-nobt 0 25 2 1 1 3.3 2 14 c=1;
|
||||
cs64-era-nobt 1 0 2 1 1 11.4 0 6 c=1;
|
||||
cs64-era-nobt 1 12 2 1 1 13.1 15 6 c=1;
|
||||
cs64-era-nobt 1 5 2 1 1 3.6 4 16 c=1;
|
||||
cs64-era-nobt 1 9 1 1 0 4.0 11 0
|
||||
cs64-era-nobt 1 4 1 1 0 10.9 6 7
|
||||
cs64-era-nobt 1 6 1 1 0 6.7 3 6
|
||||
cs64-era-nobt 1 1 2 1 1 2.8 6 20 c=1;
|
||||
cs64-era-nobt 1 7 2 1 1 46.8 13 6 c=1;
|
||||
cs64-era-nobt 1 10 1 1 0 14.5 6 6
|
||||
cs64-era-nobt 1 2 1 1 0 2.9 15 20
|
||||
cs64-era-nobt 1 11 2 1 1 3.1 3 6 c=1;
|
||||
cs64-era-nobt 1 13 2 1 1 32.6 11 6 c=1;
|
||||
cs64-era-nobt 1 15 1 1 0 3.2 6 1
|
||||
cs64-era-nobt 1 8 2 1 1 31.6 3 6 c=1;
|
||||
cs64-era-nobt 1 14 1 1 0 63.5 8 6
|
||||
cs64-era-nobt 1 16 1 1 0 24.5 13 6
|
||||
cs64-era-nobt 1 17 1 1 0 24.0 13 6
|
||||
cs64-era-nobt 1 19 3 1 2 3.2 5 13 c=2;
|
||||
cs64-era-nobt 1 21 2 1 1 2.6 11 19 c=1;
|
||||
cs64-era-nobt 1 18 1 1 0 15.9 2 6
|
||||
cs64-era-nobt 1 20 1 1 0 3.0 15 9
|
||||
cs64-era-nobt 1 30 1 1 0 47.8 14 6
|
||||
cs64-era-nobt 1 23 1 1 0 4.8 12 6
|
||||
cs64-era-nobt 1 27 1 1 0 10.1 9 6
|
||||
cs64-era-nobt 2 1 2 1 1 3.3 0 4 c=1;
|
||||
cs64-era-nobt 1 28 2 1 1 70.7 15 6 c=1;
|
||||
cs64-era-nobt 1 24 1 1 0 30.4 2 6
|
||||
cs64-era-nobt 1 26 2 1 1 29.1 3 6 c=1;
|
||||
cs64-era-nobt 1 22 1 1 0 3.3 4 25
|
||||
cs64-era-nobt 1 25 2 1 1 3.3 14 25 c=1;
|
||||
cs64-era-nobt 1 29 1 1 0 3.9 10 6
|
||||
cs64-era-nobt 2 0 2 1 1 3.1 5 25 c=1;
|
||||
cs64-era-nobt 2 3 1 1 0 2.6 11 1
|
||||
cs64-era-nobt 2 11 2 1 1 3.0 12 15 c=1;
|
||||
cs64-era-nobt 2 7 2 1 1 3.2 9 24 c=1;
|
||||
cs64-era-nobt 1 31 1 1 0 7.8 0 6
|
||||
cs64-era-nobt 2 2 1 1 0 3.3 0 0
|
||||
cs64-era-nobt 2 9 1 1 0 2.6 6 1
|
||||
cs64-era-nobt 2 10 1 1 0 3.1 2 20
|
||||
cs64-era-nobt 2 8 2 1 1 3.5 13 24 c=1;
|
||||
cs64-era-nobt 2 6 1 1 0 3.1 0 1
|
||||
cs64-era-nobt 2 4 1 1 0 2.7 0 10
|
||||
cs64-era-nobt 2 5 2 1 1 3.0 10 12 c=1;
|
||||
cs64-era-nobt 2 12 2 1 1 2.8 13 23 c=1;
|
||||
cs64-era-nobt 2 16 1 1 0 3.0 7 12
|
||||
cs64-era-nobt 2 13 2 1 1 3.1 2 26 c=1;
|
||||
cs64-era-nobt 2 14 1 1 0 3.2 3 15
|
||||
cs64-era-nobt 2 24 1 1 0 3.5 3 11
|
||||
cs64-era-nobt 2 15 1 1 0 3.0 13 7
|
||||
cs64-era-nobt 2 25 2 1 1 3.1 2 7 c=1;
|
||||
cs64-era-nobt 2 20 1 1 0 2.8 10 3
|
||||
cs64-era-nobt 2 18 1 1 0 3.2 3 11
|
||||
cs64-era-nobt 2 19 3 1 2 3.1 8 20 c=2;
|
||||
cs64-era-nobt 2 17 1 1 0 2.7 10 2
|
||||
cs64-era-nobt 2 22 1 1 0 2.9 5 1
|
||||
cs64-era-nobt 2 21 2 1 1 2.8 15 4 c=1;
|
||||
cs64-era-nobt 2 23 1 1 0 3.7 15 20
|
||||
cs64-era-nobt 2 26 2 1 1 4.6 1 26 c=1;
|
||||
cs64-era-nobt 2 29 1 1 0 3.5 11 7
|
||||
cs64-era-nobt 2 28 2 1 1 3.0 2 23 c=1;
|
||||
cs64-era-nobt 2 27 1 1 0 3.3 9 18
|
||||
cs64-era-nobt 2 30 1 1 0 3.1 8 20
|
||||
cs64-era-nobt 3 1 2 1 1 3.3 9 13 c=1;
|
||||
cs64-era-nobt 2 31 1 1 0 3.3 15 18
|
||||
cs64-era-nobt 3 0 2 1 1 3.2 0 7 c=1;
|
||||
cs64-era-nobt 3 4 1 1 0 3.7 9 10
|
||||
cs64-era-nobt 3 6 1 1 0 3.1 2 9
|
||||
cs64-era-nobt 3 5 2 1 1 3.1 3 20 c=1;
|
||||
cs64-era-nobt 3 3 1 1 0 3.3 2 14
|
||||
cs64-era-nobt 3 2 1 1 0 3.1 3 25
|
||||
cs64-era-nobt 3 7 2 1 1 3.2 8 17 c=1;
|
||||
cs64-era-nobt 3 8 2 1 1 3.3 0 14 c=1;
|
||||
cs64-era-nobt 3 17 1 1 0 3.0 2 12
|
||||
cs64-era-nobt 3 11 2 1 1 3.2 6 13 c=1;
|
||||
cs64-era-nobt 3 9 1 1 0 3.4 3 9
|
||||
cs64-era-nobt 3 15 1 1 0 2.7 7 3
|
||||
cs64-era-nobt 3 18 1 1 0 2.8 9 2
|
||||
cs64-era-nobt 3 10 1 1 0 3.8 5 4
|
||||
cs64-era-nobt 3 19 3 1 2 3.3 13 17 c=2;
|
||||
cs64-era-nobt 3 14 1 1 0 2.8 2 18
|
||||
cs64-era-nobt 3 21 2 1 1 3.0 0 15 c=1;
|
||||
cs64-era-nobt 3 12 2 1 1 3.4 14 17 c=1;
|
||||
cs64-era-nobt 3 13 2 1 1 3.1 0 25 c=1;
|
||||
cs64-era-nobt 3 16 1 1 0 3.2 13 0
|
||||
cs64-era-nobt 3 24 1 1 0 3.5 13 5
|
||||
cs64-era-nobt 3 20 1 1 0 3.4 2 2
|
||||
cs64-era-nobt 3 22 1 1 0 3.0 11 11
|
||||
cs64-era-nobt 3 26 2 1 1 3.3 5 16 c=1;
|
||||
cs64-era-nobt 3 29 1 1 0 3.0 5 7
|
||||
cs64-era-nobt 3 23 1 1 0 2.9 3 25
|
||||
cs64-era-nobt 3 31 1 1 0 3.4 15 8
|
||||
cs64-era-nobt 3 25 2 1 1 3.2 13 6 c=1;
|
||||
cs64-era-nobt 4 1 2 1 1 3.3 12 22 c=1;
|
||||
cs64-era-nobt 4 0 2 1 1 11.8 0 10 c=1;
|
||||
cs64-era-nobt 3 28 2 1 1 4.4 15 0 c=1;
|
||||
cs64-era-nobt 4 4 1 1 0 11.1 6 11
|
||||
cs64-era-nobt 3 30 1 1 0 2.8 8 20
|
||||
cs64-era-nobt 3 27 1 1 0 2.9 15 13
|
||||
cs64-era-nobt 4 3 1 1 0 2.7 10 11
|
||||
cs64-era-nobt 4 2 1 1 0 2.9 10 22
|
||||
cs64-era-nobt 4 6 1 1 0 5.0 3 10
|
||||
cs64-era-nobt 4 5 2 1 1 3.3 15 27 c=1;
|
||||
cs64-era-nobt 4 7 2 1 1 47.7 13 10 c=1;
|
||||
cs64-era-nobt 4 10 1 1 0 15.7 6 10
|
||||
cs64-era-nobt 4 9 1 1 0 3.7 6 8
|
||||
cs64-era-nobt 4 11 2 1 1 3.7 8 16 c=1;
|
||||
cs64-era-nobt 4 12 2 1 1 15.9 15 10 c=1;
|
||||
cs64-era-nobt 4 13 2 1 1 32.3 11 10 c=1;
|
||||
cs64-era-nobt 4 8 2 1 1 33.1 3 10 c=1;
|
||||
cs64-era-nobt 4 14 1 1 0 63.9 8 10
|
||||
cs64-era-nobt 4 15 1 1 0 3.2 14 25
|
||||
cs64-era-nobt 4 17 1 1 0 22.9 13 10
|
||||
cs64-era-nobt 4 16 1 1 0 22.5 13 10
|
||||
cs64-era-nobt 4 18 1 1 0 16.0 2 10
|
||||
cs64-era-nobt 4 20 1 1 0 3.2 9 11
|
||||
cs64-era-nobt 4 22 1 1 0 3.2 8 24
|
||||
cs64-era-nobt 4 28 2 1 1 70.4 15 10 c=1;
|
||||
cs64-era-nobt 4 19 3 1 2 3.4 2 0 c=2;
|
||||
cs64-era-nobt 4 29 1 1 0 3.7 10 9
|
||||
cs64-era-nobt 4 31 1 1 0 7.3 0 10
|
||||
cs64-era-nobt 4 25 2 1 1 3.3 0 22 c=1;
|
||||
cs64-era-nobt 4 21 2 1 1 2.8 8 10 c=1;
|
||||
cs64-era-nobt 4 26 2 1 1 30.5 3 10 c=1;
|
||||
cs64-era-nobt 4 24 1 1 0 30.3 2 10
|
||||
cs64-era-nobt 4 27 1 1 0 9.1 9 10
|
||||
cs64-era-nobt 4 30 1 1 0 48.5 14 10
|
||||
cs64-era-nobt 4 23 1 1 0 5.8 12 10
|
||||
cs64-era-nobt 5 0 2 1 1 10.7 0 22 c=1;
|
||||
cs64-era-nobt 5 1 2 1 1 3.2 9 2 c=1;
|
||||
cs64-era-nobt 5 4 1 1 0 9.9 6 23
|
||||
cs64-era-nobt 5 3 1 1 0 3.1 5 8
|
||||
cs64-era-nobt 5 5 2 1 1 3.5 14 23 c=1;
|
||||
cs64-era-nobt 5 2 1 1 0 3.0 2 6
|
||||
cs64-era-nobt 5 7 2 1 1 47.0 13 22 c=1;
|
||||
cs64-era-nobt 5 6 1 1 0 4.6 3 22
|
||||
cs64-era-nobt 5 9 1 1 0 4.1 8 7
|
||||
cs64-era-nobt 5 10 1 1 0 14.9 12 22
|
||||
cs64-era-nobt 5 8 2 1 1 31.2 3 22 c=1;
|
||||
cs64-era-nobt 5 11 2 1 1 3.1 4 11 c=1;
|
||||
cs64-era-nobt 5 14 1 1 0 63.4 8 22
|
||||
cs64-era-nobt 5 12 2 1 1 13.0 15 22 c=1;
|
||||
cs64-era-nobt 5 13 2 1 1 30.8 11 22 c=1;
|
||||
cs64-era-nobt 5 15 1 1 0 3.6 13 2
|
||||
cs64-era-nobt 5 16 1 1 0 24.0 13 22
|
||||
cs64-era-nobt 5 18 1 1 0 13.4 2 22
|
||||
cs64-era-nobt 5 17 1 1 0 23.8 13 22
|
||||
cs64-era-nobt 5 19 3 1 2 2.7 14 24 c=2;
|
||||
cs64-era-nobt 5 21 2 1 1 3.1 10 16 c=1;
|
||||
cs64-era-nobt 5 20 1 1 0 3.3 2 16
|
||||
cs64-era-nobt 5 26 2 1 1 29.3 3 22 c=1;
|
||||
cs64-era-nobt 5 24 1 1 0 30.5 2 22
|
||||
cs64-era-nobt 5 23 1 1 0 5.7 12 22
|
||||
cs64-era-nobt 5 22 1 1 0 3.4 0 16
|
||||
cs64-era-nobt 5 25 2 1 1 3.0 5 1 c=1;
|
||||
cs64-era-nobt 5 27 1 1 0 10.1 9 22
|
||||
cs64-era-nobt 5 28 2 1 1 71.5 15 22 c=1;
|
||||
cs64-era-nobt 5 29 1 1 0 3.6 12 26
|
||||
cs64-era-nobt 5 31 1 1 0 6.4 0 22
|
||||
cs64-era-nobt 5 30 1 1 0 46.0 14 22
|
||||
cs64-era-nobt 6 1 2 1 1 3.4 7 27 c=1;
|
||||
cs64-era-nobt 6 0 2 1 1 11.7 0 3 c=1;
|
||||
cs64-era-nobt 6 2 1 1 0 3.1 0 9
|
||||
cs64-era-nobt 6 3 1 1 0 4.0 10 5
|
||||
cs64-era-nobt 6 4 1 1 0 8.4 6 4
|
||||
cs64-era-nobt 6 6 1 1 0 6.1 3 3
|
||||
cs64-era-nobt 6 5 2 1 1 2.8 5 11 c=1;
|
||||
cs64-era-nobt 6 7 2 1 1 47.9 13 3 c=1;
|
||||
cs64-era-nobt 6 10 1 1 0 16.1 6 3
|
||||
cs64-era-nobt 6 8 2 1 1 32.0 3 3 c=1;
|
||||
cs64-era-nobt 6 11 2 1 1 3.0 6 22 c=1;
|
||||
cs64-era-nobt 6 9 1 1 0 2.5 9 4
|
||||
cs64-era-nobt 6 12 2 1 1 14.8 15 3 c=1;
|
||||
cs64-era-nobt 6 13 2 1 1 31.9 11 3 c=1;
|
||||
cs64-era-nobt 6 14 1 1 0 63.6 8 3
|
||||
cs64-era-nobt 6 15 1 1 0 3.0 11 24
|
||||
cs64-era-nobt 6 16 1 1 0 24.1 13 3
|
||||
cs64-era-nobt 6 17 1 1 0 22.9 13 3
|
||||
cs64-era-nobt 6 18 1 1 0 18.8 2 3
|
||||
cs64-era-nobt 6 19 3 1 2 3.0 15 2 c=2;
|
||||
cs64-era-nobt 6 21 2 1 1 2.7 0 13 c=1;
|
||||
cs64-era-nobt 6 20 1 1 0 3.0 4 26
|
||||
cs64-era-nobt 6 23 1 1 0 8.2 12 3
|
||||
cs64-era-nobt 6 22 1 1 0 3.9 9 14
|
||||
cs64-era-nobt 6 24 1 1 0 30.1 2 3
|
||||
cs64-era-nobt 6 26 2 1 1 29.5 3 3 c=1;
|
||||
cs64-era-nobt 6 28 2 1 1 71.3 15 3 c=1;
|
||||
cs64-era-nobt 6 25 2 1 1 3.0 2 1 c=1;
|
||||
cs64-era-nobt 6 27 1 1 0 8.6 9 3
|
||||
cs64-era-nobt 6 29 1 1 0 3.2 14 17
|
||||
cs64-era-nobt 6 30 1 1 0 47.4 14 3
|
||||
cs64-era-nobt 6 31 1 1 0 6.2 0 3
|
||||
cs64-era-nobt 7 1 2 1 1 2.9 8 11 c=1;
|
||||
cs64-era-nobt 7 0 2 1 1 3.3 1 12 c=1;
|
||||
cs64-era-nobt 7 4 1 1 0 3.1 13 14
|
||||
cs64-era-nobt 7 6 1 1 0 4.3 3 7
|
||||
cs64-era-nobt 7 3 1 1 0 3.8 14 22
|
||||
cs64-era-nobt 7 2 1 1 0 2.6 5 8
|
||||
cs64-era-nobt 7 5 2 1 1 3.3 4 23 c=1;
|
||||
cs64-era-nobt 7 7 2 1 1 2.9 13 6 c=1;
|
||||
cs64-era-nobt 7 8 2 1 1 3.0 12 17 c=1;
|
||||
cs64-era-nobt 7 10 1 1 0 15.2 6 27
|
||||
cs64-era-nobt 7 9 1 1 0 3.4 12 24
|
||||
cs64-era-nobt 7 11 2 1 1 3.8 14 24 c=1;
|
||||
cs64-era-nobt 7 12 2 1 1 12.5 15 27 c=1;
|
||||
cs64-era-nobt 7 14 1 1 0 3.1 11 1
|
||||
cs64-era-nobt 7 13 2 1 1 27.9 14 27 c=1;
|
||||
cs64-era-nobt 7 15 1 1 0 2.7 14 22
|
||||
cs64-era-nobt 7 16 1 1 0 24.0 13 27
|
||||
cs64-era-nobt 7 17 1 1 0 3.3 5 11
|
||||
cs64-era-nobt 7 18 1 1 0 2.9 14 23
|
||||
cs64-era-nobt 7 19 3 1 2 3.0 13 1 c=2;
|
||||
cs64-era-nobt 7 21 2 1 1 2.8 7 21 c=1;
|
||||
cs64-era-nobt 7 20 1 1 0 3.0 3 14
|
||||
cs64-era-nobt 7 23 1 1 0 3.8 12 27
|
||||
cs64-era-nobt 7 22 1 1 0 2.8 5 25
|
||||
cs64-era-nobt 7 26 2 1 1 2.3 3 20 c=1;
|
||||
cs64-era-nobt 7 24 1 1 0 3.2 3 20
|
||||
cs64-era-nobt 7 25 2 1 1 2.9 14 21 c=1;
|
||||
cs64-era-nobt 7 28 2 1 1 3.0 14 11 c=1;
|
||||
cs64-era-nobt 7 29 1 1 0 3.2 13 4
|
||||
cs64-era-nobt 7 27 1 1 0 10.0 9 27
|
||||
cs64-era-nobt 7 30 1 1 0 5.9 2 27
|
||||
cs64-era-nobt 7 31 1 1 0 3.8 5 27
|
||||
# end 2026-10-08T15:07:58Z rows=257
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
259
docs/analysis/class-v6/logs/connected/cs64-none.tsv
Normal file
259
docs/analysis/class-v6/logs/connected/cs64-none.tsv
Normal file
|
|
@ -0,0 +1,259 @@
|
|||
# cs64-none class cs64s27x16 eras [none] seeds 256 era-widths 4 weights base bittest off bin 54b905920b91becc start 2026-10-08T15:01:08Z host f271665b754f threads 40
|
||||
cand era seed candidates accepted attempt bit_z bit_site bit_bit reasons
|
||||
cs64-none none 12 1 1 0 3.8 4 20
|
||||
cs64-none none 8 1 1 0 55.1 1 0
|
||||
cs64-none none 36 1 1 0 3.2 15 24
|
||||
cs64-none none 2 1 1 0 2.7 12 3
|
||||
cs64-none none 14 1 1 0 2.7 0 16
|
||||
cs64-none none 10 1 1 0 3.1 1 22
|
||||
cs64-none none 37 1 1 0 42.9 6 0
|
||||
cs64-none none 38 2 1 1 20.3 3 0 c=1;
|
||||
cs64-none none 29 2 1 1 3.4 7 24 c=1;
|
||||
cs64-none none 7 1 1 0 35.3 11 0
|
||||
cs64-none none 31 1 1 0 17.2 3 0
|
||||
cs64-none none 18 1 1 0 49.8 13 0
|
||||
cs64-none none 11 1 1 0 3.3 4 26
|
||||
cs64-none none 0 1 1 0 3.6 9 17
|
||||
cs64-none none 35 1 1 0 42.4 13 0
|
||||
cs64-none none 23 3 1 2 29.2 11 0 c=2;
|
||||
cs64-none none 4 1 1 0 38.8 11 0
|
||||
cs64-none none 30 1 1 0 3.1 13 17
|
||||
cs64-none none 20 1 1 0 3.0 3 11
|
||||
cs64-none none 17 1 1 0 3.8 7 1
|
||||
cs64-none none 32 1 1 0 5.5 8 0
|
||||
cs64-none none 28 2 1 1 2.8 6 11 c=1;
|
||||
cs64-none none 39 1 1 0 3.7 9 0
|
||||
cs64-none none 21 1 1 0 31.7 9 0
|
||||
cs64-none none 9 1 1 0 59.0 9 0
|
||||
cs64-none none 33 2 1 1 30.3 11 0 c=1;
|
||||
cs64-none none 24 1 1 0 21.1 10 0
|
||||
cs64-none none 5 2 1 1 23.5 6 0 c=1;
|
||||
cs64-none none 25 1 1 0 2.8 9 27
|
||||
cs64-none none 6 1 1 0 17.3 0 0
|
||||
cs64-none none 1 1 1 0 16.6 3 0
|
||||
cs64-none none 16 1 1 0 22.5 2 0
|
||||
cs64-none none 3 1 1 0 26.8 7 0
|
||||
cs64-none none 26 1 1 0 24.3 14 0
|
||||
cs64-none none 27 1 1 0 3.4 14 7
|
||||
cs64-none none 34 2 1 1 3.1 2 26 c=1;
|
||||
cs64-none none 22 1 1 0 22.3 3 0
|
||||
cs64-none none 19 1 1 0 16.5 14 1
|
||||
cs64-none none 13 1 1 0 4.7 12 1
|
||||
cs64-none none 15 3 1 2 4.0 0 1 c=2;
|
||||
cs64-none none 46 1 1 0 2.6 3 4
|
||||
cs64-none none 42 2 1 1 4.0 10 21 c=1;
|
||||
cs64-none none 50 1 1 0 64.1 10 1
|
||||
cs64-none none 51 2 1 1 30.9 11 0 c=1;
|
||||
cs64-none none 40 1 1 0 65.4 6 0
|
||||
cs64-none none 63 1 1 0 6.3 10 0
|
||||
cs64-none none 66 1 1 0 2.6 14 24
|
||||
cs64-none none 58 3 1 2 17.7 4 0 c=2;
|
||||
cs64-none none 43 1 1 0 64.4 9 0
|
||||
cs64-none none 59 1 1 0 127.7 4 0
|
||||
cs64-none none 45 1 1 0 13.3 13 0
|
||||
cs64-none none 44 1 1 0 3.0 14 3
|
||||
cs64-none none 41 1 1 0 12.4 8 0
|
||||
cs64-none none 53 1 1 0 3.2 8 7
|
||||
cs64-none none 47 1 1 0 33.8 7 0
|
||||
cs64-none none 56 1 1 0 3.0 12 22
|
||||
cs64-none none 52 1 1 0 47.9 12 0
|
||||
cs64-none none 48 2 1 1 50.0 4 1 c=1;
|
||||
cs64-none none 49 1 1 0 3.3 7 2
|
||||
cs64-none none 60 2 1 1 9.4 6 0 c=1;
|
||||
cs64-none none 55 1 1 0 13.0 13 0
|
||||
cs64-none none 75 3 1 2 3.2 10 3 c=2;
|
||||
cs64-none none 54 3 1 2 13.5 8 0 c=2;
|
||||
cs64-none none 57 1 1 0 32.5 6 0
|
||||
cs64-none none 76 1 1 0 9.3 12 0
|
||||
cs64-none none 61 2 1 1 15.1 4 0 c=1;
|
||||
cs64-none none 64 1 1 0 3.0 2 8
|
||||
cs64-none none 70 2 1 1 20.6 2 0 c=1;
|
||||
cs64-none none 71 1 1 0 14.4 2 0
|
||||
cs64-none none 67 4 1 3 9.5 6 0 c=3;
|
||||
cs64-none none 62 1 1 0 3.0 7 20
|
||||
cs64-none none 65 3 1 2 12.0 4 0 c=2;
|
||||
cs64-none none 79 1 1 0 84.3 9 0
|
||||
cs64-none none 69 2 1 1 2.9 3 22 c=1;
|
||||
cs64-none none 77 1 1 0 19.8 15 0
|
||||
cs64-none none 68 2 1 1 31.4 3 0 c=1;
|
||||
cs64-none none 85 2 1 1 3.1 9 15 c=1;
|
||||
cs64-none none 73 1 1 0 3.5 1 2
|
||||
cs64-none none 78 3 1 2 3.1 7 13 c=2;
|
||||
cs64-none none 72 1 1 0 3.8 7 1
|
||||
cs64-none none 74 1 1 0 5.5 0 0
|
||||
cs64-none none 88 1 1 0 64.0 13 0
|
||||
cs64-none none 83 2 1 1 4.0 8 15 c=1;
|
||||
cs64-none none 101 1 1 0 29.9 11 0
|
||||
cs64-none none 80 3 1 2 4.1 1 0 c=2;
|
||||
cs64-none none 81 2 1 1 11.0 7 0 c=1;
|
||||
cs64-none none 91 1 1 0 3.4 8 22
|
||||
cs64-none none 84 1 1 0 26.1 1 0
|
||||
cs64-none none 86 1 1 0 2.9 9 24
|
||||
cs64-none none 82 1 1 0 2.9 9 19
|
||||
cs64-none none 87 1 1 0 3.3 10 21
|
||||
cs64-none none 93 1 1 0 3.1 7 26
|
||||
cs64-none none 103 1 1 0 4.4 0 0
|
||||
cs64-none none 99 3 1 2 50.9 13 0 c=2;
|
||||
cs64-none none 96 1 1 0 3.0 7 26
|
||||
cs64-none none 89 1 1 0 93.8 8 0
|
||||
cs64-none none 102 1 1 0 14.1 3 0
|
||||
cs64-none none 94 1 1 0 3.6 1 19
|
||||
cs64-none none 92 1 1 0 3.9 0 13
|
||||
cs64-none none 114 1 1 0 3.9 7 17
|
||||
cs64-none none 95 6 1 5 32.2 11 0 c=5;
|
||||
cs64-none none 97 1 1 0 6.7 6 0
|
||||
cs64-none none 90 2 1 1 2.9 8 27 c=1;
|
||||
cs64-none none 104 1 1 0 12.8 2 0
|
||||
cs64-none none 108 3 1 2 21.0 12 0 c=2;
|
||||
cs64-none none 111 1 1 0 18.4 4 0
|
||||
cs64-none none 106 1 1 0 4.8 6 0
|
||||
cs64-none none 100 1 1 0 13.0 1 0
|
||||
cs64-none none 98 1 1 0 3.2 14 25
|
||||
cs64-none none 105 1 1 0 5.4 1 0
|
||||
cs64-none none 113 1 1 0 3.7 0 26
|
||||
cs64-none none 121 2 1 1 3.4 10 6 c=1;
|
||||
cs64-none none 107 2 1 1 3.4 1 8 c=1;
|
||||
cs64-none none 118 1 1 0 27.1 15 0
|
||||
cs64-none none 110 1 1 0 2.8 15 4
|
||||
cs64-none none 115 1 1 0 67.1 0 0
|
||||
cs64-none none 122 1 1 0 128.0 4 0
|
||||
cs64-none none 117 2 1 1 25.7 6 0 c=1;
|
||||
cs64-none none 109 1 1 0 46.1 3 0
|
||||
cs64-none none 112 1 1 0 60.5 11 0
|
||||
cs64-none none 119 1 1 0 3.3 3 3
|
||||
cs64-none none 116 1 1 0 6.9 13 0
|
||||
cs64-none none 124 1 1 0 8.1 15 0
|
||||
cs64-none none 126 1 1 0 2.6 10 18
|
||||
cs64-none none 125 1 1 0 35.3 3 0
|
||||
cs64-none none 140 1 1 0 26.0 1 10
|
||||
cs64-none none 123 1 1 0 3.2 8 6
|
||||
cs64-none none 130 1 1 0 53.1 11 0
|
||||
cs64-none none 120 1 1 0 2.9 5 6
|
||||
cs64-none none 145 3 1 2 51.8 4 0 c=2;
|
||||
cs64-none none 128 1 1 0 3.3 4 1
|
||||
cs64-none none 127 4 1 3 41.6 4 0 c=3;
|
||||
cs64-none none 143 1 1 0 23.8 8 0
|
||||
cs64-none none 129 1 1 0 14.0 11 0
|
||||
cs64-none none 139 2 1 1 8.2 13 0 c=1;
|
||||
cs64-none none 144 1 1 0 3.8 13 13
|
||||
cs64-none none 134 1 1 0 54.0 5 0
|
||||
cs64-none none 132 1 1 0 3.1 12 16
|
||||
cs64-none none 131 1 1 0 20.3 0 0
|
||||
cs64-none none 138 1 1 0 3.1 3 25
|
||||
cs64-none none 133 2 1 1 30.1 4 0 c=1;
|
||||
cs64-none none 152 1 1 0 127.9 13 0
|
||||
cs64-none none 141 1 1 0 4.3 11 0
|
||||
cs64-none none 137 2 1 1 21.0 1 0 c=1;
|
||||
cs64-none none 146 1 1 0 3.5 4 22
|
||||
cs64-none none 136 1 1 0 3.0 7 16
|
||||
cs64-none none 150 1 1 0 6.4 1 0
|
||||
cs64-none none 153 1 1 0 15.0 8 0
|
||||
cs64-none none 135 6 1 5 10.2 11 0 c=5;
|
||||
cs64-none none 142 2 1 1 11.2 7 0 c=1;
|
||||
cs64-none none 149 1 1 0 24.9 11 0
|
||||
cs64-none none 148 2 1 1 43.3 9 0 c=1;
|
||||
cs64-none none 163 1 1 0 17.9 15 0
|
||||
cs64-none none 147 1 1 0 30.1 4 0
|
||||
cs64-none none 155 2 1 1 4.8 7 0 c=1;
|
||||
cs64-none none 151 4 1 3 55.9 0 0 c=3;
|
||||
cs64-none none 166 1 1 0 3.2 8 0
|
||||
cs64-none none 157 1 1 0 3.6 1 17
|
||||
cs64-none none 160 1 1 0 4.1 6 26
|
||||
cs64-none none 154 1 1 0 16.5 13 0
|
||||
cs64-none none 156 1 1 0 83.9 2 0
|
||||
cs64-none none 165 1 1 0 9.2 4 0
|
||||
cs64-none none 162 1 1 0 19.9 10 0
|
||||
cs64-none none 158 1 1 0 3.1 8 3
|
||||
cs64-none none 169 2 1 1 35.4 8 0 c=1;
|
||||
cs64-none none 159 1 1 0 5.0 7 0
|
||||
cs64-none none 161 1 1 0 3.2 13 7
|
||||
cs64-none none 164 1 1 0 59.8 8 0
|
||||
cs64-none none 180 1 1 0 4.0 11 2
|
||||
cs64-none none 177 1 1 0 21.3 0 0
|
||||
cs64-none none 175 1 1 0 3.1 12 21
|
||||
cs64-none none 168 1 1 0 3.5 0 8
|
||||
cs64-none none 171 1 1 0 18.7 2 0
|
||||
cs64-none none 172 1 1 0 18.7 3 0
|
||||
cs64-none none 170 1 1 0 22.3 0 0
|
||||
cs64-none none 176 3 1 2 3.2 1 2 c=2;
|
||||
cs64-none none 173 2 1 1 49.9 4 0 c=1;
|
||||
cs64-none none 181 1 1 0 3.3 4 8
|
||||
cs64-none none 179 1 1 0 17.5 2 0
|
||||
cs64-none none 167 1 1 0 19.3 9 0
|
||||
cs64-none none 186 1 1 0 38.4 5 0
|
||||
cs64-none none 174 1 1 0 24.1 0 0
|
||||
cs64-none none 185 2 1 1 3.0 4 14 c=1;
|
||||
cs64-none none 178 2 1 1 43.0 3 0 c=1;
|
||||
cs64-none none 182 1 1 0 3.3 0 26
|
||||
cs64-none none 187 2 1 1 82.5 0 0 c=1;
|
||||
cs64-none none 189 3 1 2 8.2 15 0 c=2;
|
||||
cs64-none none 188 1 1 0 31.2 6 0
|
||||
cs64-none none 190 1 1 0 3.5 12 11
|
||||
cs64-none none 193 1 1 0 19.7 5 0
|
||||
cs64-none none 183 1 1 0 3.0 15 21
|
||||
cs64-none none 192 1 1 0 6.8 3 0
|
||||
cs64-none none 196 1 1 0 3.6 9 0
|
||||
cs64-none none 198 1 1 0 8.6 13 0
|
||||
cs64-none none 184 1 1 0 3.5 7 0
|
||||
cs64-none none 195 1 1 0 14.5 6 0
|
||||
cs64-none none 191 2 1 1 29.9 6 0 c=1;
|
||||
cs64-none none 194 1 1 0 14.1 6 0
|
||||
cs64-none none 197 1 1 0 31.6 5 0
|
||||
cs64-none none 204 1 1 0 3.0 15 15
|
||||
cs64-none none 210 1 1 0 46.5 15 0
|
||||
cs64-none none 207 1 1 0 3.5 8 11
|
||||
cs64-none none 202 1 1 0 3.8 11 12
|
||||
cs64-none none 199 1 1 0 18.5 3 1
|
||||
cs64-none none 200 2 1 1 10.9 12 0 c=1;
|
||||
cs64-none none 209 1 1 0 3.1 10 17
|
||||
cs64-none none 214 1 1 0 3.3 5 16
|
||||
cs64-none none 201 2 1 1 3.3 8 17 c=1;
|
||||
cs64-none none 208 1 1 0 34.3 1 0
|
||||
cs64-none none 206 1 1 0 15.5 11 0
|
||||
cs64-none none 205 1 1 0 28.4 11 0
|
||||
cs64-none none 216 1 1 0 45.3 13 0
|
||||
cs64-none none 203 1 1 0 3.3 1 24
|
||||
cs64-none none 221 1 1 0 3.2 12 16
|
||||
cs64-none none 220 1 1 0 3.5 14 14
|
||||
cs64-none none 218 4 1 3 4.0 6 22 c=3;
|
||||
cs64-none none 223 3 1 2 42.6 10 0 c=2;
|
||||
cs64-none none 224 1 1 0 3.2 2 11
|
||||
cs64-none none 212 1 1 0 28.8 1 0
|
||||
cs64-none none 217 1 1 0 3.0 15 7
|
||||
cs64-none none 215 4 1 3 53.8 9 0 c=3;
|
||||
cs64-none none 225 3 1 2 3.8 4 1 c=2;
|
||||
cs64-none none 228 1 1 0 3.0 8 3
|
||||
cs64-none none 211 1 1 0 3.7 8 1
|
||||
cs64-none none 213 1 1 0 13.4 4 0
|
||||
cs64-none none 229 1 1 0 3.9 12 1
|
||||
cs64-none none 219 2 1 1 33.2 6 1 c=1;
|
||||
cs64-none none 232 1 1 0 3.2 8 13
|
||||
cs64-none none 231 1 1 0 9.3 15 0
|
||||
cs64-none none 222 1 1 0 16.5 10 0
|
||||
cs64-none none 235 1 1 0 32.7 3 0
|
||||
cs64-none none 234 1 1 0 3.6 11 23
|
||||
cs64-none none 233 1 1 0 3.1 13 21
|
||||
cs64-none none 226 3 1 2 9.0 15 0 c=2;
|
||||
cs64-none none 227 2 1 1 3.4 1 4 c=1;
|
||||
cs64-none none 238 1 1 0 15.6 13 0
|
||||
cs64-none none 230 1 1 0 20.9 0 0
|
||||
cs64-none none 237 3 1 2 3.9 5 19 c=2;
|
||||
cs64-none none 236 1 1 0 3.2 7 23
|
||||
cs64-none none 239 1 1 0 19.7 4 0
|
||||
cs64-none none 251 1 1 0 26.7 14 0
|
||||
cs64-none none 240 1 1 0 31.3 12 0
|
||||
cs64-none none 252 2 1 1 61.1 9 0 c=1;
|
||||
cs64-none none 242 1 1 0 14.0 12 0
|
||||
cs64-none none 244 1 1 0 2.7 11 8
|
||||
cs64-none none 241 1 1 0 50.7 13 0
|
||||
cs64-none none 248 1 1 0 3.1 1 17
|
||||
cs64-none none 246 2 1 1 11.2 5 0 c=1;
|
||||
cs64-none none 253 2 1 1 8.2 9 0 c=1;
|
||||
cs64-none none 247 1 1 0 34.2 5 0
|
||||
cs64-none none 249 1 1 0 3.3 7 3
|
||||
cs64-none none 250 2 1 1 25.8 9 0 c=1;
|
||||
cs64-none none 243 2 1 1 52.5 8 1 c=1;
|
||||
cs64-none none 254 1 1 0 3.1 12 10
|
||||
cs64-none none 245 1 1 0 11.4 8 0
|
||||
cs64-none none 255 1 1 0 12.2 8 0
|
||||
# end 2026-10-08T15:07:34Z rows=257
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
17
docs/analysis/class-v6/logs/connected/uniform-cs64-none.tsv
Normal file
17
docs/analysis/class-v6/logs/connected/uniform-cs64-none.tsv
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
class era seed attempt program_id min_site_ratio min_site top0.1_share control_share ratio_to_control max_item_reads control_max reads
|
||||
cs64s27x16 none 0 0 9ad55de91485542b 1.00006 15 0.002383 0.002382 1.0002 27 27 134217728
|
||||
cs64s27x16 none 4 0 ef05f7b4f74f8b34 0.99876 11 0.002381 0.002377 1.0016 26 29 134217728
|
||||
cs64s27x16 none 9 0 4f7dfb188ea079f8 0.99407 9 0.002382 0.002380 1.0010 27 28 134217728
|
||||
cs64s27x16 none 3 0 423f3fcb11ffd16c 0.99937 7 0.002380 0.002380 1.0001 27 28 134217728
|
||||
cs64s27x16 none 12 0 f2ee7ca7642ce409 1.00010 1 0.002378 0.002381 0.9987 27 27 134217728
|
||||
cs64s27x16 none 7 0 a05222bdb885f832 0.99795 11 0.002381 0.002379 1.0010 28 27 134217728
|
||||
cs64s27x16 none 10 0 d6229a4ebc3da203 1.00013 1 0.002381 0.002381 0.9999 28 27 134217728
|
||||
cs64s27x16 none 8 0 5d3c176e39a2d7bd 0.99565 1 0.002377 0.002379 0.9991 27 27 134217728
|
||||
cs64s27x16 none 1 0 118f3f6ee409eb00 1.00000 3 0.002379 0.002381 0.9990 26 27 134217728
|
||||
cs64s27x16 none 5 1 66da80dabf645c59 0.99958 6 0.002382 0.002379 1.0014 27 28 134217728
|
||||
cs64s27x16 none 15 2 7261a08393ef6b71 1.00000 2 0.002379 0.002380 0.9996 26 27 134217728
|
||||
cs64s27x16 none 6 0 0f25af70edd287cc 0.99985 0 0.002381 0.002380 1.0003 26 28 134217728
|
||||
cs64s27x16 none 11 0 b1ccae46f9288cc2 1.00008 14 0.002381 0.002382 0.9997 27 27 134217728
|
||||
cs64s27x16 none 2 0 53c13e9f37bad71f 1.00010 3 0.002380 0.002380 0.9999 26 29 134217728
|
||||
cs64s27x16 none 14 0 e84c88374beb684f 1.00010 6 0.002382 0.002382 1.0002 27 27 134217728
|
||||
cs64s27x16 none 13 0 87d88cf6b4db69a2 1.00011 10 0.002383 0.002383 1.0003 29 27 134217728
|
||||
|
17
docs/analysis/class-v6/logs/connected/worker-4090.log
Normal file
17
docs/analysis/class-v6/logs/connected/worker-4090.log
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
RESULT worker pack packs/cs64-bound 15:17:37
|
||||
RESULT check packs/cs64-bound info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
RESULT check packs/cs64-bound check PASS packs/cs64-bound in 2953 ms: nvrtc 1813 cache 2 dataset 31 hot 0 check 1106 race 0 ms variant base class v2; self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT check packs/cs64-bound epoch 69676e65756d2d7636632f30 day 6461792f323032362d31302d3033, dataset 2^28 words, cache 2^26 words in 65536 segments, 87 registers, 20 blocks/SM at 1 warp(s)/block, target sm_89
|
||||
RESULT bench packs/cs64-bound pack packs/cs64-bound on NVIDIA_GeForce_RTX_4090: nvrtc 1749 cache 2 dataset 31 hot 0 check 1101 race 0 ms variant base class v2; self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT bench packs/cs64-bound warm-up dispatch (base 0): 268.83 ms; 250 timed dispatches of 16777216 nonces: mean 268.83 ms
|
||||
RESULT bench packs/cs64-bound RESULT pack=packs/cs64-bound class=mx8+sh256x27 device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=87 blocks_per_sm=20 warps=0 resident=2560 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=ad0cec2a42c84aff mhs=62.408 loads=128 bytes=512 scratch_ops=0 time=wall
|
||||
RESULT smi packs/cs64-bound samples 66 mean_power_w 269.4 mean_sm_mhz 2809
|
||||
RESULT worker pack v5-genesis 15:18:52
|
||||
RESULT check v5-genesis info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_4090 (sm_89, 128 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_89 (the device's architecture, listed by NVRTC)
|
||||
RESULT check v5-genesis check PASS v5-genesis in 1722 ms: nvrtc 586 cache 2 dataset 31 hot 0 check 1102 race 0 ms variant base class v5 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT check v5-genesis epoch 69676e65756d2d67656e65736973 day 6461792f323032362d31302d3033, dataset 2^28 words, cache 2^26 words in 65536 segments, 32 registers, 24 blocks/SM at 1 warp(s)/block, target sm_89
|
||||
RESULT bench v5-genesis pack v5-genesis on NVIDIA_GeForce_RTX_4090: nvrtc 559 cache 2 dataset 32 hot 0 check 1100 race 0 ms variant base class v5 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT bench v5-genesis warm-up dispatch (base 0): 268.89 ms; 250 timed dispatches of 16777216 nonces: mean 268.89 ms
|
||||
RESULT bench v5-genesis RESULT pack=v5-genesis class=mx8+sh256x27+state device=NVIDIA_GeForce_RTX_4090 arch=sm_89 regs=32 blocks_per_sm=24 warps=0 resident=3072 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=ae74193ddad19e19 mhs=62.394 loads=128 bytes=512 scratch_ops=0 time=wall
|
||||
RESULT smi v5-genesis samples 65 mean_power_w 271.9 mean_sm_mhz 2805
|
||||
RESULT worker end 15:20:03
|
||||
17
docs/analysis/class-v6/logs/connected/worker-5090.log
Normal file
17
docs/analysis/class-v6/logs/connected/worker-5090.log
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
RESULT worker pack packs/cs64-bound 15:16:17
|
||||
RESULT check packs/cs64-bound info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
|
||||
RESULT check packs/cs64-bound check PASS packs/cs64-bound in 2256 ms: nvrtc 1089 cache 3 dataset 30 hot 0 check 1130 race 0 ms variant base class v2; self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT check packs/cs64-bound epoch 69676e65756d2d7636632f30 day 6461792f323032362d31302d3033, dataset 2^28 words, cache 2^26 words in 65536 segments, 80 registers, 24 blocks/SM at 1 warp(s)/block, target sm_120
|
||||
RESULT bench packs/cs64-bound pack packs/cs64-bound on NVIDIA_GeForce_RTX_5090: nvrtc 1086 cache 3 dataset 30 hot 0 check 1122 race 0 ms variant base class v2; self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT bench packs/cs64-bound warm-up dispatch (base 0): 268.09 ms; 250 timed dispatches of 16777216 nonces: mean 266.80 ms
|
||||
RESULT bench packs/cs64-bound RESULT pack=packs/cs64-bound class=mx8+sh256x27 device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=80 blocks_per_sm=24 warps=0 resident=4080 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=ad0cec2a42c84aff mhs=62.882 loads=128 bytes=512 scratch_ops=0 time=wall
|
||||
RESULT smi packs/cs64-bound samples 65 mean_power_w 574.2 mean_sm_mhz 2797
|
||||
RESULT worker pack v5-genesis 15:17:29
|
||||
RESULT check v5-genesis info igneum-worker-cuda 1.0 (4 October 2026): device 0 NVIDIA_GeForce_RTX_5090 (sm_120, 170 SMs), driver 13.0 from libcuda.so.1, NVRTC 12.8 from libnvrtc.so.12, target sm_120 (the device's architecture, listed by NVRTC)
|
||||
RESULT check v5-genesis check PASS v5-genesis in 1709 ms: nvrtc 505 cache 5 dataset 32 hot 0 check 1162 race 0 ms variant base class v5 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT check v5-genesis epoch 69676e65756d2d67656e65736973 day 6461792f323032362d31302d3033, dataset 2^28 words, cache 2^26 words in 65536 segments, 48 registers, 24 blocks/SM at 1 warp(s)/block, target sm_120
|
||||
RESULT bench v5-genesis pack v5-genesis on NVIDIA_GeForce_RTX_5090: nvrtc 500 cache 3 dataset 30 hot 0 check 1156 race 0 ms variant base class v5 (state leaves 93, uploaded for the build and freed); self-test PASS (cache head, last line and FNV-1a 64 48c4f5bf24166b2e; dataset head, word [268435455] and 64 samples; 96 of 96 vector lanes)
|
||||
RESULT bench v5-genesis warm-up dispatch (base 0): 258.26 ms; 250 timed dispatches of 16777216 nonces: mean 266.46 ms
|
||||
RESULT bench v5-genesis RESULT pack=v5-genesis class=mx8+sh256x27+state device=NVIDIA_GeForce_RTX_5090 arch=sm_120 regs=48 blocks_per_sm=24 warps=0 resident=4080 arena_mib=0 hot_mib=0 hot_slots=0 hot_fill_ms=0.00 nonces=16777216 batches=250 check=PASS fingerprint=ae74193ddad19e19 mhs=62.963 loads=128 bytes=512 scratch_ops=0 time=wall
|
||||
RESULT smi v5-genesis samples 65 mean_power_w 571.4 mean_sm_mhz 2798
|
||||
RESULT worker end 15:18:41
|
||||
Loading…
Reference in a new issue