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igneum-labs
e05eb0c43a Counter ASIC 3.0 gates (node): the program id carries the class. A class v4 program is generator 4 wherever it is made: the CLI's --era path stamps the generator from the class (era_generator_of: 4 on V4_CLASS, 3 otherwise; ProgramClass::of_load_class), show honours --program-class and --era-hex; the shadow block marks class v4 in packcheck, packfile.h and the Metal worker (a generator 3 pack with IGNEUM_SHADOW_INSTRS is refused as a v4 program stamped v3, a generator 4 pack without it is refused; generator 2 ladder packs unchanged); the seven gate packs re-exported (generator 4, id c120d7963abdcd96 against the v3 control's 73bcbfe8ccf988f1, every other line byte-identical); class-v4.mjs asserts every v4 epoch's id against the CLI's same-seed v3 and v4 ids (--id-check-against v4 is the assertion's failed case); v2 and v3 ids byte-identical (60 + 7 + 4 + 19 + 7, the pinned packs) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:24:02 +00:00
igneum-labs
480c0518f6 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for the project lead 2026-10-06 16:18:08 +00:00
igneum-labs
e029091c3d Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
3521d9a002 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
d2237cc566 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:15:17 +00:00
igneum-labs
85c267971c Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:14:08 +00:00
igneum-labs
ed53e96fd8 Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:30 +00:00
igneum-labs
f0b3355a7a Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:00 +00:00
igneum-labs
fa857683be Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:07:55 +00:00
igneum-labs
47e07e82c7 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 16:03:33 +00:00
igneum-labs
231ebab306 Counter ASIC 3.0 PC 1 AMD: the watts re-run script (sampler proven on the idle window, never blind), the sampler fed through the environment (the unquoted ArgumentList class), per-entry card restore in jobs 1 and 4, the README's record of job 1's first run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:02:55 +00:00
igneum-labs
e925b20f7c Counter ASIC 3.0 gates (node): class v4 = mx8+sh256x27 through the stack (igneum-pow ProgramClass::V4, V4_CLASS, generator 4, program_id(4, seed, attempt), the era composed as v3's; program.h and program.json class v4; packcheck, packfile.h, the CUDA and OpenCL identity rule and the Metal worker accept generator 4 and the class=v4 token, the Metal worker takes v4 from the prepared pack only; v2 and v3 byte-identical, the pinned packs diffed); the G4 harness class-v4.mjs (two switches, the never case); override-60x.json: the v4 field at never, the duplicated proving v1 block removed, the four 0.3.12/0.3.13 fields added; CI check override-json-check.sh (no duplicate key in any override file) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:58:49 +00:00
igneum-labs
179443499d Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 15:58:03 +00:00
igneum-labs
4d660ceb0a Counter ASIC 3.0 gates (hash): the class v4 packs (mx8+sh256x27 with the era at devnet epoch 0 and eras 0 to 5, the v3 control), the PC 2 G1+G2 playbook, hash-bound --count ported from ca2-era, the mixer harness on a class and an era (IGNEUM_MIXER_CLASS, IGNEUM_MIXER_ERA, the shadow contract) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:57:40 +00:00
igneum-labs
e5e54a681f Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 15:52:47 +00:00
igneum-labs
2df45c43fb Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 15:45:39 +00:00
igneum-labs
3c62a8a9c7 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 15:40:42 +00:00
igneum-labs
afc61c92ba Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 15:40:19 +00:00
igneum-labs
d04ab0f440 Counter ASIC 3.0 PC 1 AMD: the four PC 1 job scripts (G1 + ladder on the 9070 XT with ADLX watts, family step costs, dr736 derive, the 4070 ladder), the kit maker and the README with the publish commands 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:39:51 +00:00
igneum-labs
838fed7989 Counter ASIC 3.0 PC 1 AMD: OpenCL family probe (every 1.13.2 family through AMD's builtins, khr/intel sub-groups, media ops, C forms and local emulation; bit-exact on Apple OpenCL) and the clBuildProgram time line in the OpenCL worker 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:39:51 +00:00
igneum-labs
868c13b393 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (the project lead 16:50 UTC), the gate table 2026-10-06 15:38:44 +00:00
igneum-labs
0962364e03 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 15:13:22 +00:00
igneum-labs
4bdf9af4c3 Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for the project lead; the owed list) 2026-10-06 08:48:18 +00:00
igneum-labs
f4478a8ee1 Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 08:45:48 +00:00
igneum-labs
1d0cc97721 Merge branch 'ca3-shadow' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:45:48 +00:00
igneum-labs
697b8833df Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 08:45:02 +00:00
igneum-labs
9417a14ac7 Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 
PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:44:57 +00:00
igneum-labs
a3adeb2ac8 Counter ASIC 3.0 items 6 and 7: PC 2 family playbook posts both card key forms from settings.json, confirms the card quiet by the process list, restores cards and prover in a finally block 2026-10-06 08:34:28 +00:00
igneum-labs
aab9858068 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:31:10 +00:00
igneum-labs
c6e03662a6 Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:30:15 +00:00
igneum-labs
881ae59779 Counter ASIC 3.0 status: the detector's two calibration findings answered (ba4a995 merged; max r 0.10) 2026-10-06 08:29:28 +00:00
igneum-labs
ea51a82d58 Merge branch 'ca3-detector' into ca3-coord 2026-10-06 08:29:09 +00:00
igneum-labs
ba4a9956f4 Counter ASIC 3.0 items 4 and 5: the epoch common factor is the median over steady core ids 
The mean over every present id let one paused-and-resumed card (the Mac, a 178% step) push
every other residual the same way in the epochs it was off, which read as an r = 0.94 edge
between two honest 5090 keys on the merged tree (window 41 to 46). The factor is now the
median over ids that are steady and present in every window epoch (median over all present
when the core is under 3): the same window reads max r 0.10. README: the three calibration
readings (the edge, the factor-of-two from identities=2, the unsteady Mac) answered.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:28:55 +00:00
igneum-labs
5b0b08e17f Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
53382993b2 Counter ASIC 3.0 item 8: the PC 2 playbook switches the prover back on in its finally block (the clear file's constraint) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:26:22 +00:00
igneum-labs
cb75491b31 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
7c53b0545a Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
e3ee3049bd Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
3959d66e55 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
97d2590922 Counter ASIC 3.0 item 8: the CUDA text checked in the clang emulation and the OpenCL text on Apple OpenCL (gate G1 row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:10:25 +00:00
igneum-labs
4605314315 Counter ASIC 3.0 item 8: the Mac rows 
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:08:26 +00:00
igneum-labs
3e77f1adf5 Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00
igneum-labs
51dba1ce76 Counter ASIC 3.0 item 8: the latency-shadow knob (LoadClass +sh<S>x<R>), its packs and the PC 2 playbook 
A shadow block of S ALU instructions run R times at the end of every iteration, drawn from the program stream after
the 64 base instructions, behind LoadClass::shadow: v2 and v3 draw nothing and emit nothing (the pinned packs are
byte-identical, cargo test 54 + 4 + 19 + 7 green). The interpreter, the three kernel dialects (both kernels each),
program.h and program.json carry it; the acceptance rule interprets the base program only. Packs for seed
igneum-genesis over class mx8 at 4,096 to 180,224 shadow instructions per hash (proto-cuda/packs-ca3-shadow), and
the PC 2 bench playbook tools/ca3-shadow/pc2-shadow-bench.ps1 (passes the publisher's three checks).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:58:35 +00:00
igneum-labs
1538c78141 Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 07:51:42 +00:00
igneum-labs
36202759eb Merge branch 'ca3-derive' into ca3-coord 2026-10-06 07:51:42 +00:00
igneum-labs
dd08267df3 Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 07:51:36 +00:00
igneum-labs
f2e79316fe Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 07:51:15 +00:00
igneum-labs
5c2131c18e Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:51:13 +00:00
igneum-labs
1c08438a12 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 07:51:00 +00:00
igneum-labs
bcc2db992e Counter ASIC 3.0 item 2: the design, the Mac measurements, the chip-model row and the PC 2 job 
docs/plans/counter-asic-3-derivation.md (the design, the acceptance test, the interpreter, the allowance argument,
the measurements, the PROPOSED reserve entry R0 for 1.13.2, what is owed), docs/analysis/chip-model-v3.md section 6
(the per-day derivation rows at 1.0x to 3x allowances), the bench-log entry, relay/playbooks/ca3-derive-pc2.ps1
(one PC 2 job: self-fetched packs zip, the installed worker through NVRTC, the card off only under test with its
key from settings.json). Verifier 4.875 / 4.944 ms per unit on one M5 Max core under the measure lock against
x8's 2.061 / 2.063; Metal build 29 ms against 22; hash rate equal; bit-exact on Metal and Apple OpenCL.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 07:50:01 +00:00