Commit graph

2349 commits

Author SHA1 Message Date
igneum-josh
a90ec124a1 attack-pass: the status board, F8 row, gate line and re-gate paragraph read the tail as attributed
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:49:21 +01:00
igneum-josh
431a1cd5be attack-pass: AP-F8-1 tail attributed (p4, p8, p10, p34 as per-site bucket concentration at a narrow-window site; the largest-bucket bound named for a next class)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:48:03 +01:00
igneum-labs
3a4ba8938d Merge ca3-coord 0d212a2a into master (gate: green on 0d212a2a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 09:39:08 +01:00
igneum-josh
0d212a2aea Site: the bench table's lead-cell width rule applies on desktop widths only (above 1,100 px); on the phone grid the lead cell has no max-width, so the rate cell no longer sits over the card name at 390 px (the box's sweep read the 360 px cap covering the lead text on a 390 px viewport)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:32:43 +01:00
igneum-josh
c11baf3097 Site: the bench table's lead cell wraps on desktop (the row rule's nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell at 1280 px and above; the overlap sweep on the box read it COVERED, the Mac's gate had skipped the sweep for want of a browser)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:32:43 +01:00
igneum-josh
7c44354f18 Site: the bench table's desktop row is six columns (the class v4 cost and the date move under the card name as the muted second line), the card layout below 1100 px, the wrapper scrolls as a safety (the overlap gate read the eight-column row clipped at every desktop width)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:32:43 +01:00
igneum-josh
592488a44a Site: the bench table's phone layout gives every cell its own grid area (the overlap gate read the quiet cells stacked under the Details button at 390 px)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:32:42 +01:00
igneum-josh
e26746751b Site: the GPU bench table's design pass in the site's own language (the founder, 7 October 2026): the vendor mark and name lead, the rate as the big tabular number, MH per wall watt in the ember tint for the best desktop card, watts and the class v4 cost quiet, the tuned state a pill, the date muted mono; the Hive values, the source and the note in a Details row; cards you can buy and datacentre under hairline headings, the datacentre collapsed; 56 px rows on desktop, a two-line card per row on a phone; the best desktop card as the lede, the rates note under a disclosure; header sort with the arrow and the ember underline
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 09:32:42 +01:00
igneum-labs
715c79b2f6 Merge ca3-coord-record b124473c into master (gate: green on b124473c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:19:20 +01:00
igneum-josh
b124473cf8 Counter ASIC 3.0 status: the 9070 XT bench row on master (the AMD watts no longer owed), the hot-table ldcs rows (a dead lever; the hot family latency-bound), the PC 1 list main set closed on measured rows
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 08:13:01 +01:00
igneum-labs
c09dfee443 Merge ca3-v4-amend b38b4af6 into master (gate: green on b38b4af6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:11:38 +01:00
igneum-josh
b38b4af68a bench-log: the hot-table packs on the RTX 5090, ldcs against base, unlocked and at the 1,300 MHz lock (36 rows, all PASS; ldcs dead, the hot packs lose 2 percent to the lock where mx8 loses 7.5)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 08:05:19 +01:00
igneum-labs
ffb7d8fff5 Merge spec-accept-23 47690be7 into master (gate: green on 47690be7, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 07:35:03 +01:00
igneum-josh
d807651322 CA4 hot-table job: the first kit flattened the eight hot packs into one folder (the job exited 2 in 0 s, pack hot32k4 missing); kit b carries packs/<name>/ for all nine, the fetch and run ids take a b suffix
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:30:27 +01:00
igneum-labs
7d6c9333e9 Merge ca3-v4-amend 43f0918c into master (gate: green on 43f0918c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:29:02 +01:00
igneum-josh
47690be799 Bench table: the RX 9070 XT row takes the app's own power reading at the stock point (202 W at 18.9 MH/s, 0.093 MH/W; the G1 ladder's 18.8 to 19.2 as the rate; the status row of 8 October 2026), tune state "no lever" (no AMD knob in 0.3.20), the class v4 cost unchanged, Hive values none; /miners rebuilt
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:28:55 +01:00
igneum-labs
8675d10b38 Merge ca3-coord-record a4eecffe into master (gate: green on a4eecffe, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:27:36 +01:00
igneum-josh
5504abf3d1 Merge ship-docs-0321 e63ed4f6 into master (gate: green on e63ed4f6, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 07:25:18 +01:00
igneum-josh
a4eecffe0f Counter ASIC 3.0 status: the 5080 Ember tune (the lock worth +40 percent per watt over the stock climb; the knob's case), the knob on release-0.3.24 (e181f497), the 9070 XT tune (no AMD knob in 0.3.20; 18.9 MH/s at 202 W; the AMD core-clock knob a morning item), the hot-table job the last on PC 1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:21:16 +01:00
igneum-josh
e63ed4f65b release 0.3.22 section 21: the core-clock knob cherry-picked onto release-0.3.24 (the union with the efficient-point ceiling), the measured Ember line from PC 1
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:19:49 +01:00
igneum-josh
43f0918cc2 PC 1 Ember per-card job: a card the app cannot steer stores one baseline row and logs no progress line; count the stored curve before calling the run empty (the 9070 XT run exited 1 on a real row)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:18:25 +01:00
igneum-labs
4e4debdaf7 Merge ca3-v4-amend 261d7c54 into master (gate: green on 261d7c54, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:16:47 +01:00
igneum-labs
e3986db7a2 Merge ca3-coord-record a2ca6197 into master (gate: green on a2ca6197, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:14:22 +01:00
igneum-josh
a2ca619730 Chip model 5.11 and new-pow 5.1: the per-MAC figures corrected by the per-lane tile count (32 MACs per tile, not 1,024; the 4090's 0.056 pJ is 1.8 pJ, the 5090 reads 2.9 and 1.5 at the shadow's premium), the tensor-tile column withdrawn (a chip's k on tile work 0.03 to 0.3, below the ALU shadow's); Counter ASIC 3.0 status: the microbench's correction, the night's closing sentence on measured rows, the CA4 file's commits
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:08:07 +01:00
igneum-labs
bdb2fa2bdc Merge ca3-coord-record 6fb84bdd into master (gate: green on 6fb84bdd, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:06:49 +01:00
igneum-josh
261d7c5493 PC 1 Ember per-card job: the curve line cast an integer plus a string and threw (the 06:0x 5080 run's rows lost); string interpolation instead, and every card's stored curve printed at the start
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:06:24 +01:00
igneum-josh
6fb84bddf5 Counter ASIC 3.0 status: the microbench on the 5090 (20 probes at both states; shfl 55.8 pJ, mul 13.9, mulhi 39.6 against the ARX op's 11.3; int8 mma 1.36): the re-weight's re-opening condition not met on measured rows, the tile block's case in measured picojoules
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 07:00:29 +01:00
igneum-labs
e8ce959d1c Merge ca3-coord-record 4cf82754 into master (gate: green on 4cf82754, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:30:14 +01:00
igneum-josh
4cf827540f Counter ASIC 3.0 status: rank 2 closed in the CA4 file (the premium is the ops' energy whatever carries them), the op-mix re-weight's case to main as HOLD with its four-line basis and the condition that re-opens it
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 06:23:57 +01:00
igneum-labs
366ed06e38 Merge ca3-coord-record a802360f into master (gate: green on a802360f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:22:56 +01:00
igneum-josh
a802360ffb Counter ASIC 3.0 status: the SM-sparse reading exists (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw; the premium is the shadow's ALU work, the SM-sparse candidate dead; the op-mix re-weight's case to main)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 06:16:37 +01:00
igneum-labs
71d623e7fc Merge ca3-coord-record 9504651f into master (gate: green on 9504651f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:43:18 +01:00
igneum-josh
1991fd63f9 CA4 microbench job: the kit's class v4 pack as the --pack argument (the exe's parser demands one before the microbench branch; the probes read none); republished as -c after the sparse run
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:37:08 +01:00
igneum-josh
9504651f49 Counter ASIC 3.0 status: F1's record on master (54b896f3; lane (d) complete with its box-hours), the v5 lane's night closed (class-v5 1095eaa8 gated GREEN, 72 checks)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:37:03 +01:00
igneum-labs
2b75b15df5 Merge ca3-coord-record e13538b6 into master (gate: green on e13538b6, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:36:04 +01:00
igneum-josh
e13538b64a Counter ASIC 3.0 status: class-v5's F1 row on both mirrors, the CA4 packs on the 5090 (the tile premium 0.103 W per tile unlocked, 0.050 at the lock; every sound pack memory-bound), the prototypes' first sentence on measured rows (neither beats class v4's premium; the per-load class dead; the tile block at parity with the ALU shadow and worse at the chip's k), the k column's basis measured
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:29:48 +01:00
igneum-josh
54b896f3b7 Merge attack-pass 0610892b into master (gate: green on 0610892b, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 05:29:30 +01:00
igneum-labs
936335e39d Merge ca3-coord-record 83b1730a into master (gate: green on 83b1730a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:28:50 +01:00
igneum-josh
ef7a0b3888 Merge ship-docs-0321 05e698c2 into master (gate: green on 05e698c2, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 05:27:46 +01:00
igneum-josh
0610892bbd attack-pass lane (d): F1 shadow redundancy on the frozen class v5 tip 1c420786, 10^5 programs, max 4.688 percent, 0 mismatches, PASS (the 0.3.24 gate line; AP-F1-1 FIXED-AND-PASSED on v5)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:22:29 +01:00
igneum-josh
83b1730a69 Counter ASIC 3.0 status: the census harness's progress line and flushed partial (known-failed PASS), F1 PASS on class v5 (100,000 programs, max 4.688 percent saved, 0 soundness mismatches, 05:20 BST); the attack board on class v5 complete
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:22:26 +01:00
igneum-josh
05e698c26d release 0.3.22: the attack-pass record lines (F9 and F1 PASS on the full 10^5), PC 1 overnight
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:22:12 +01:00
igneum-josh
0a37fe2baa CA4 packs and hot-table jobs: $pid is PowerShell's read-only automatic variable (the 04:04Z packs run threw at its first pack); $progId instead; the packs job republished as -b
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:11:17 +01:00
igneum-labs
370eec8d98 Merge ca3-coord-record 08ccad75 into master (gate: green on 08ccad75, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:08:59 +01:00
igneum-josh
c99f147f0c attack-pass: F1 record section 12, the census flush and its known-failed test (2,000 rows after a kill at 2,000, PASS)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:08:52 +01:00
igneum-josh
eccbf941c4 CA4 microbench job: the installed worker's NVRTC DLLs copied beside the fetched exe and the exe run from its own folder (the loader refusal the research lane named)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:06:36 +01:00
igneum-josh
b2ec39c3fc CA4 microbench job: the research lane's exact command (no --device flag), every line echoed when the exe refuses (the 03:54Z run exited 2 after one unseen line); republished as -b after the packs
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:04:53 +01:00
igneum-josh
08ccad75a5 Counter ASIC 3.0 status: the pass's close at master 2882352c, the fourth --variant fix (the capture's off-by-one, ca4sparse5), adv-accept off build-1 for F1's census and one holder yielded to the flush test, adv-cache-2 closed (2^36 reads at the control's values)
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 05:02:45 +01:00
igneum-labs
f6ba94abb5 Merge ca3-coord-record a2b0b0ce into master (gate: green on a2b0b0ce, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:01:49 +01:00
igneum-josh
4052c6aa70 CA4 SM-sparse rerun (c): the research lane's ca4sparse5 exe (the parameter-capture fix); the card-free check's NVRTC compile result gates the run
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 04:56:27 +01:00