Counter ASIC 3.0 status: class-v5's F1 row on both mirrors, the CA4 packs on the 5090 (the tile premium 0.103 W per tile unlocked, 0.050 at the lock; every sound pack memory-bound), the prototypes' first sentence on measured rows (neither beats class v4's premium; the per-load class dead; the tile block at parity with the ALU shadow and worse at the chip's k), the k column's basis measured

Browse source

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

...

This commit is contained in:

igneum-josh 2026-10-08 05:29:48 +01:00

parent 936335e39d

commit e13538b64a

1 changed files with 1 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Show stats Download patch file Download diff file Expand all files Collapse all files

2

docs/plans/counter-asic-3-status.md

View file

File diff suppressed because one or more lines are too long