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igneum-labs
5656f6eeef Class v6 10.0t: the 32-lane 18-family core's synthesis row (k 0.39 same-node, a sixth under the headline placed; the same-node bracket 1.5x to 2.1x, inside the served sentence) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 17:02:26 +00:00
igneum-labs
1847d41bf0 Class v6 10.0u: the dataset schedule scored per step (5.5 GiB +14.3 percent at the Blackwell knee, over the budget, for a chip ticket that flips no verdict; 4 GiB earns its place; later steps state-forced, never scheduled); change (3) revised; the served sentence 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:57:28 +00:00
igneum-labs
0742bc0c8b Class v6 change (1): the best-mix genesis table PASSED lane D's harness (0 hot sets, 0 exhausted, the draw's cost halved against the band; the fold stays the lever for bit R) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:54:13 +00:00
igneum-labs
11f09af39f Class v6 10.3: the W = 8 lock row landed (the lock widens its loss to +11.2 percent of energy; W = 16 +78 percent); both out as regression controls 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:53:13 +00:00
igneum-labs
90523b794f Igneum 2.0 D4: the die at the reconciled USD 1.0 ticket (lane 3's 12c): the verdict moves back, failing (a), (b), (c) and (f) at every point of the band; a sunk USD 10 M fleet 42 percent of a growing chain and 62 of a flat one on landing; the success statement holds at no reconciled ticket 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:26:47 +00:00
igneum-labs
d858442228 D4 proving payment: the chain's own block-one read-back (emission 3.168808781 IGN, 2.5350470248 miner and 0.6337617562 pool, 80/20 exact) as the served table's figure; the fee the design, not a payment today 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:25:02 +00:00
igneum-labs
bee747da82 Igneum 2.0 D4: the die's ticket reconciled (two machines: zero shadow at USD 0.6, the placed shadow core at 2.94; the adversary's at about USD 1.0 per MH/s, 0.5 to 1.6, set by the power train and the core); a sunk USD 10 M fleet about 10 TH/s; the die's economics are project economics 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:23:50 +00:00
igneum-labs
b16fcc5f02 Igneum 2.0 D4: the die's ticket pinned at the adversary lane's USD 2.94 complete machine (the 0.6 row the labelled silicon floor); the die's headline verdict is the hybrid's; the range served until the 18:30 reconciliation 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:19:20 +00:00
igneum-labs
d73e9cfa7f Igneum 2.0 D4: lane 3's re-run at the final energies (12b): the die's verdict moves to the hybrid's at the adversary lane's USD 2.94 ticket and stands at the chip model's 0.6; the 5x ticket gap is the pin that decides it; the board passes six of seven at USD 4.84 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:16:39 +00:00
igneum-labs
1d0d5662ad Igneum 2.0 D4: the final placed energies (the 18-family core: the board 1.5x / 1.8x, the hybrid 1.93x / 2.4x at USD 2.80, the die 2.3x / 3.1x at USD 2.94) and the three chips re-scored: no verdict moves; condition (b) now passes for the hybrid and the die on their corrected tickets, (c) and (f) hold the verdicts; the served sentence 1.5x to 3.1x 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:12:17 +00:00
igneum-labs
bbf9dbfbff Igneum 2.0 D4 complete (lane 3 d0e2018f): the hybrid board scored with the sunk case (holds only in a growing chain at cheap electricity; the floor a real lever on it), the market-structure axis (the board holds under every structure, the die under none but private supply in a growing chain), the sensitivity workbook (171 rows; no threshold served) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:10:33 +00:00
igneum-labs
412a1a22cc Class v6 10.0o: the k lane's synthesised FP32 rows (the FMA unit k 0.65 alone, the blended op 0.15 at the lock: slightly worse forcing work than an integer op); the kill stands 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:06:35 +00:00
igneum-labs
0e35bda6b8 Igneum 2.0 D4: the market-structure axis and the sensitivity workbook pinned for 21:00; the success condition to serve, verbatim from the plan 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:05:20 +00:00
igneum-labs
5983d90cfc Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:03:43 +00:00
igneum-labs
b5ca2bdaa9 Igneum 2.0 D4: the coexistence model's second cut and the operator simulation landed (lane 3 a07be1ee: the pass line met for the DRAM board, the SRAM die fails five conditions once sunk; the fixed internal pool is a subsidy, the congestion-priced fee restores a spike in 35 periods); the hybrid board scored on the six conditions (fails the dollar conditions on the first reading) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:01:35 +00:00
igneum-labs
919293896e Class v6 10.0h and 10.0i: the sentence served at 18:30 on the tightened bracket (2.5x to 3.0x a node ahead, 2.1x to 2.6x node-for-node; the placed gated row at about 18:30 narrows it) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:47:22 +00:00
igneum-labs
ddb0976351 Merge the mirror's master into counter-asic-4 before the D4 landing 
# Conflicts:
#	site/economics.html
 2026-10-08 15:46:02 +00:00
igneum-labs
9f1c40b683 docs: the paid pilot (Igneum 2.0, proving ladder step two): customer profile from the code, three ranked candidate classes with public prices, the pilot shape and pass condition, the missing-pipeline checklist, the outreach brief 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:45:41 +00:00
igneum-labs
984aa603d8 Igneum 2.0 D4: the tip-share discrepancy resolved (the tip whole to the block, O-5.7 closed at zero; the provers paid by the congestion-priced proving base fee, 90 percent to the block's pool and 10 percent burned; the burn listed separately; the cap and no development tax untouched); spec 5.1 to 5.3, the economics page, the code pinned 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:45:00 +00:00
igneum-labs
d846bfe5d8 Merge class-v6-connected-docs e6146368 into master (gate: green on e6146368, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:43:21 +00:00
igneum-labs
4a3fbecd88 Class v6 10.0p: the 8 GB and 12 GB tiers hold at the 5.5 GiB floor (an exact 4060 and 3060, measured); the window free per load on both; proving beside mining time-shares under 16 GB 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:40:40 +00:00
igneum-labs
761ec73de0 Class v6 10.0o: the mixed FP32 candidate killed (determinism proved on CUDA; the determinism tax is the whole economics, +15 to +26 percent on every card for +7 percent of chip edge; the exponent-byte bias a new instrument reading) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:38:47 +00:00
igneum-labs
5405dd9f20 Merge counter-asic-4 03029526 into master (gate: green on 03029526, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:37:40 +00:00
igneum-labs
9f490a5b8c Merge class-v6-adversary-docs d1d29460 into master (gate: green on d1d29460, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:35:33 +00:00
igneum-labs
c67e9dae42 Merge release-manifest-8 d5ba3c3a into master (gate: green on d5ba3c3a, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 15:32:32 +00:00
igneum-labs
03029526da Merge the mirror's master into counter-asic-4 before the third landing 2026-10-08 15:28:43 +00:00
igneum-labs
e6146368b5 Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
 2026-10-08 15:28:39 +00:00
igneum-labs
0647e8976c Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
 2026-10-08 15:28:39 +00:00
igneum-labs
e9e88cf4f2 Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
 2026-10-08 15:28:38 +00:00
igneum-labs
d1d2946038 multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
30ba24bea1 multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
17b9901b67 Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:27:51 +00:00
igneum-labs
e0cfa64f17 Merge ca3-coord-record cacdb438 into master (gate: green on cacdb438, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:26:45 +00:00
igneum-labs
d5ba3c3a90 Merge the box master 31496f4e into release-manifest-8 (the evidence page rebuilt) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:25:22 +00:00
igneum-labs
cacdb438ac Counter ASIC 3.0 status: the amended close on master (31496f4e), the adversary core rows (k 0.40 node for node), the connected-state rows (the window under 1 percent on the card), every platform on 0.3.26, the enforced-proving lane's line and route, the class v5 lane's kit item, the gate kills by name found and named 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:19:19 +00:00
igneum-labs
d94c69e460 Chip text: the third review's claim statement served verbatim above the sentence on every copy; rotation named an optional improvement, not the mechanism; no threshold as the economic headline (the coexistence model owed); X35 pin added 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:18:17 +00:00
igneum-labs
a39ab8ecc3 Merge the mirror's master into counter-asic-4 before the second landing 2026-10-08 15:17:45 +00:00
igneum-labs
3b78cd5dbe Class v6 10.0l: the third external review (the objective durable GPU competitiveness; the definition on a reference population with cost per accepted unit of work; the coexistence model replaces the capex wall, a new document by 21:00; the claim statement above the served sentence, rotation an optional improvement) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:16:26 +00:00
igneum-labs
16608d4d02 Class v6 10.0k: the connected-state lane's first rows (63 of 64 registers necessary; the window +0.6 percent on a 5090 at stock; censuses as well as v5; the narrow per-step chain names the two-level-file re-optimisation) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:15:18 +00:00
igneum-labs
c43880ef41 Class v6 10.0j (after the landing): the multi-family adversary lane's macro-window core (k 0.40 node-for-node; the window knob buys the card nothing against a macro file) carried beside the k lane's model as a disagreement the placed rows settle 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:13:27 +00:00
igneum-labs
31496f4ef9 Merge counter-asic-4 7e5897dc into master (gate: green on 7e5897dc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:12:06 +00:00
igneum-labs
ffd6751e7c Release manifest and the proving economics: site/release-manifest.json served at /release.json (network and chain id, source commits and fingerprints, mining class and dataset, finality rule v3, proof program ids, verifier off per P21, fees, versions per platform, the proving view, generated date); /build, /economics, /miner, /evidence and the litepaper read it at build through data-rm spans and a gate check holds the pages to it; /light, /receipt and the light client say two thirds of total weight; 4463 marked historical in older docs; dated log entries labelled historical; the evidence page's sixth label (activated) and the reference-repository wording; /economics gains "Who pays for proving": three incomes apart, the burned base fee stated, the measured 24-hour payout, the halving walk computed from emission.mjs at build, per card per hour, the two routes priced, no price 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:11:33 +00:00
igneum-labs
b0411162c0 Merge class-v6-floor-denominator-docs-3 03b7bf05 into master (gate: green on 03b7bf05, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:11:19 +00:00
igneum-labs
abf5a5a606 Chip text: the bracket serves (about 2.3x to 3.3x a node ahead, 2.0x to 2.9x node for node, approximate and provisional) in place of the provisional 2.2x to 2.4x figures, on main's order; the placed gated core row replaces it when it lands; labels, evidence row 17, X35 and the pin follow 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:10:34 +00:00
igneum-labs
c1f082c87b Merge ca3-coord-record e8f017e7 into master (gate: green on e8f017e7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:07:38 +00:00
igneum-labs
7e5897dc32 Class v6 10.0i: the adversary's re-optimised core (the gated base k 0.37 at N3, the gated window 0.50, +0.13 of k the window's honest defence; the placed ungated core +64 percent over synthesis) and the bracket the served figures sit in until the placed gated rows at 17:30 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:04:41 +00:00
igneum-labs
03b7bf05a1 Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 394da98a9 (394da98a91) for the box mirror master
 2026-10-08 15:04:38 +00:00
igneum-labs
999fec1519 Merge class-v6-floor-denominator-docs-2 8384bfc7 into master (gate: green on 8384bfc7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:03:47 +00:00
igneum-labs
e1d397e8b0 Merge the mirror's master da5e1e8a into counter-asic-4 (the coord record lane's earlier copy of class-v6-rotating-family.md superseded by this branch's) 
# Conflicts:
#	docs/design/class-v6-rotating-family.md
 2026-10-08 15:03:33 +00:00
igneum-labs
7fab675a02 Chip text: the served sentence opens "adopts the 64-register window and retains it across every rotation" (the close's 10.0h after the site audit read); the card's cost of the window labelled measured (rented 5090 and 4090 at stock, 8 October 2026); the X35 pin follows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:03:10 +00:00