igneum-labs
2b81d3fac8
class v5 design page: the class v6 kit row (the zip 2c56bd06 from the class-v6 merge, the reads so far per pack and platform, the all pack's Mac refusals by the stub, the window texts owed, the ds55 form not in the pack)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:12:36 +00:00
igneum-labs
19b1ab6c5a
Merge remote-tracking branch 'build/master' into class-v5
2026-10-08 13:49:16 +00:00
igneum-labs
cb9100619c
class v5 design page: the Intel row moves to its fingerprint (the Arc B580 reads 82b19cbde8557ea5 on the rebuilt kit; the rotate fold was the whole fault; six platforms equal)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:49:15 +00:00
igneum-labs
11b6228151
Merge ca3-v4-amend 4a139d4c into master (gate: green on 4a139d4c, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 13:33:02 +00:00
igneum-labs
d7a41aa60d
Merge class-v6-floor-invention-docs-2 8b7e7d28 into master (gate: green on 8b7e7d28, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:23:22 +00:00
igneum-labs
c7f89a916f
Merge remote-tracking branch 'build/master' into class-v5
2026-10-08 13:18:20 +00:00
igneum-labs
2a6151f1cc
class v5 harness: the attempt-3 read's standalone path (--a3-only, --a3-known-failed) and the runner's stdout line; the check's live EQUAL on the rebuilt pair and the known-failed DIFFER on the page with the logs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:18:19 +00:00
igneum-labs
5547e6f1b6
Merge class-v6-census-docs 50c060b2 into master (gate: green on 50c060b2, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:16:21 +00:00
igneum-labs
4b3a293b51
Merge ca3-coord-record 03e0eecf into master (gate: green on 03e0eecf, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 13:14:03 +00:00
igneum-labs
013e2ea76b
ledger AP-F8-1: the F8-256 attributions p212 (the bucket class at one narrow-window site) and p225 (the value-level class); the one-one-bit prediction a hint, the by-site histogram the attribution; the consequence for the next class's bucket and value-level tests
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:13:38 +00:00
igneum-labs
8b7e7d2889
Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 828307fee828307fee2
2026-10-08 13:11:56 +00:00
igneum-labs
50c060b277
Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
c7555638b4
Class v6 census: W = 16 and the op-mix re-weight through the sub-version 3 rules (docs/analysis/class-v6/census-w16-mix.md): every candidate 256 of 256 without an era and 256 of 256 across eras 0 to 7 with the window-bit refusal on, 0 exhausted; W = 16 removes the product's low bits from the address by construction; the re-weight lowers r to 0.41 and raises the stride-bit refusals; the rows, logs, scripts and commands
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d20eb04bd (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
a949bd88d2
class v5 harness: the pairing rule's fixed attempt-3 seed read on every run (kaspa-pow program-id beside the run's CLI, attempt and id against the record; an unreadable side fails the check); the seed's inputs pinned under the harness dir; the page row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:09:23 +00:00
igneum-labs
03e0eecf86
Counter ASIC 3.0 status: the 0.3.25 pin named c9ad753a at 14:08 (every gate green, the fast-time PASS on the freeze-paired pair, the v5 read-back PASS, the FAIL seed re-read at the exact freeze, the minute 14:30 to 14:40, the fleet's census gate at 28,462), the testnet re-cut 0d05e795, the F8-256 attributions (p212 the bucket tail, p225 the value-level class), lane C's drawn-era re-read, the floor-sram and floor-invention landings, the PC 1 order and the 7600 card-in plan, the chain-id deploys
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:07:05 +00:00
igneum-labs
6babb93942
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 13:04:40 +00:00
igneum-labs
7442ec25b3
Class v6 invention: the drawn-era re-read on the fixed instrument 2ae69eb4 (the sound per-load form 254 of 256 seeds at 0.819 per candidate under eras, 234 of 256 at 0.927 no-era; the 16 x 27 form dead on both; class v4's shape at sub-version 3's 0.67 on the same binary), the two TSVs, sections 0, 2.1, 3.3 and 4 updated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:04:39 +00:00
igneum-labs
c4f90a0061
Merge class-v6-floor-invention-docs c62f15c0 into master (gate: green on c62f15c0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
a56165eebd
class v5 design page: the pin's FAIL seed re-read (the freeze draws 1f1cf82877f46ee6 at attempt 3; both FAIL ids were foreign crates; the seeded attempt-3 case next)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:01:28 +00:00
igneum-labs
c9bdeb3b94
Merge remote-tracking branch 'build/master' into class-v5
2026-10-08 12:57:31 +00:00
igneum-labs
e10af3c36c
class v5 design page: the pairing read-back on the rebuilt 0.3.25 pair (PASS, id for id on epochs 8 to 10 against the freeze CLI at exactly dba17a0a; no attempt-3 seed in the run, the seeded case next), the logs
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:57:30 +00:00
igneum-labs
3099597026
Merge class-v6-floor-sram-docs 54ada47f into master (gate: green on 54ada47f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:55:14 +00:00
igneum-labs
3105f72d8f
Merge ca3-coord-record d76cd38b into master (gate: green on d76cd38b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:54:19 +00:00
igneum-labs
d76cd38bef
Counter ASIC 3.0 status: the STOP on the pin at 13:29 (the fast-time pairing FAIL on an attempt-3 seed), its cause (the 0.3.25 worktree's pre-freeze igneum-pow copy under the paths override; the live network fingerprinted ON the freeze, cbc5bd0a), rule 19 (the build-time fingerprint refusal, packaging/pow-freeze.txt), the rebuilt shas 6ccaf9e9 and c9ad753a with the 90,000 ceiling and digest 2066aa57, the testnet re-cut 3ffcf83b, lane D's fan-out, the attack pass's twelve-chunk split, the explorer re-pointed at node1-dn3 and the 4464 chain id served, the counter-asic-4 docs landing 6af12f08
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:47:21 +00:00
igneum-labs
3c57693f62
Merge build/master into build-programme (the 4464 fact landed on both sides; this branch's wording and the second PASS line kept; the pages rebuilt)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:46:10 +00:00
igneum-labs
c62f15c0ad
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 39b8d058339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
ef198fa37b
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 68315bf8339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
79e06feb6f
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 43fcf0fed39b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
251b76846a
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b13fc428f39b8d05838
2026-10-08 12:45:34 +00:00
igneum-labs
d2ddc61baf
Merge spec-accept-23 ddb434ab into master (gate: green on ddb434ab, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 12:39:06 +00:00
igneum-labs
683a5afc99
Builder pages and faucet: Devnet 3 chain id 4464 since the class v5 floor (8 October 2026, 13:27 BST reading)
...
- the faucet reads eth_chainId from its node on every send and in its status (a fixed id signed refused transactions once the floor crossed); FAUCET_CHAIN_ID is gone from the env; the faucet now reads node1-dn3's EVM, the node the public RPC fronts
- /build, /faucet, docs/build/first-contract.md, rpc.md and faucet.md: 4464 with the floor note, "read it, never fix it"
- a second walkthrough PASS on the 4464 chain from build-2 through the public RPC and faucet: Counter at block 29878, 12 s end to end
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:38:51 +00:00
igneum-labs
362d6801e2
Merge dex-devnet3 db2db8bd into master (gate: green on db2db8bd, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:37:18 +00:00
igneum-labs
f7b2140071
class v5 design page: the 0.3.25 pin's pairing STOP (the attempt-3 seed divergence, the embedded crate path), the pairing rule's attempt-3 line, the read-back plan
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:36:47 +00:00
igneum-labs
6af12f0871
Merge counter-asic-4-docs 5f45de99 into master (gate: green on 5f45de99, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:35:08 +00:00
igneum-labs
ddb434ab3d
Devnet 3's chain id is 4464 since its class v5 floor crossed at DAA 68,400 on 8 October 2026 (eth_chainId 0x1170 on the public RPC): /metamask's devnet card, by-hand list, builders' snippet and one-click entry (chainId 0x1170, rpcUrls the public RPC, the explorer as block explorer; the local node named beside it), /faucet's two lines, the build pages' network table and walkthrough notes (docs/build), the nav pill's title on every page
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:32:22 +00:00
igneum-labs
db2db8bde8
Swap page: the chain id read from eth_chainId at load (4464 from the class v5 floor at DAA 68,400, 4463 before it), never fixed in the page; devnet-3.json notes both
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:30:51 +00:00
igneum-labs
54ada47f91
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
88924ec8f4
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
ee2d3c8606
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
0478a6c0eb
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
7b523af541
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
745e9effc0
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
5f45de999f
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
7670ed9f15
Class v6: the last two 20:00 and 19:30 references pulled to the close
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
af0f82798e
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6bbb33364
2026-10-08 12:28:21 +00:00
igneum-labs
5f1090037f
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b3353fd08
2026-10-08 12:28:21 +00:00
igneum-labs
f9045cf567
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b6280dcfe
2026-10-08 12:28:21 +00:00
igneum-labs
7f93ff9092
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 78ce9ea46
2026-10-08 12:28:21 +00:00
igneum-labs
a88fd37d08
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9e3677f5e
2026-10-08 12:28:21 +00:00
igneum-labs
339236654a
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 73f2c0768
2026-10-08 12:28:21 +00:00
