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Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy

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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 828307fee (828307fee2) for the box mirror master
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docs/analysis/class-v6/floor/invention.md
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@ -178,6 +178,18 @@ A per-block random challenge whose answer window is shorter than one DRAM round
Reading: nothing published since 2023 offers a lever outside the identity; every energy figure is a streaming pJ per bit, and no one has measured a per-random-read joule on GDDR6, GDDR7 or HBM3 at the controller, so the record's 2.0 and 1.2 nJ stand as the only model and are owed a measurement nobody can rent (the AWS F2 hour of chip-model 5.3 is still the one HBM2 instrument). The new rows change two precedents: the Ethash band's top is about 13x (claimed) not 6.8x, and the Monero chip story has a shipped-but-unverified successor to the withdrawn X9.
### 2.7 Three precedents, sourced for the 15:45 close (the research lane's ask of 14:0x UK; every figure read 8 October 2026)
A correction to the question as asked first: Monero did not go chip-free after November 2019; the Antminer X5 shipped in September 2023 at about parity to 1.5x per joule against the best measured CPU.
| Precedent (launch) | The designers' claim | The chip that shipped | Measured edge per joule against the best commodity part | Months to the first chip | Sources |
|---|---|---|---|---|---|
| Monero RandomX (fork 30 November 2019) | design.md, Introduction: a PoW "must achieve device binding by targeting specific features of existing general-purpose hardware"; section 3.4 SuperscalarHash: light-mode ASICs "will be bottlenecked by SuperscalarHash ... their efficiency will be destroyed by the high power usage"; no numeric bound anywhere in the document (claimed) | Bitmain Antminer X5, preorders 29 August 2023, delivered late September 2023: 212 kH/s at 1,350 W = 157 H/J (claimed); Antminer X9 announced 26 December 2025, 1,000 kH/s at 2,472 W = 405 H/J (claimed), USD 5,600, listed for July 2026, reported pulled on 31 July 2026 by a reseller with no Bitmain statement | Ryzen 9 9950X on xmrig 20.66 kH/s at 199 W = 104 H/J (hashrate.no, one verified submission, measured); Kryptex 27 kH/s at 170 W = 159 H/J (unlabelled); the X5 1.0x to 1.5x; the X9, if it exists, 3.9x | 46 | https://github.com/tevador/RandomX/blob/master/doc/design.md ; https://www.asicminervalue.com/miners/bitmain/antminer-x5 ; https://github.com/monero-project/monero/issues/10270 ; https://oneminers.com/blogs/news/antminer-x9-cancelled-what-bitmain-pulling-the-model-means-for-monero-mining ; https://www.hashrate.no/cpus/9950x/XMR ; https://pool.kryptex.com/device/cpu/AMD/ryzen-9-9950x |
| Ethereum Ethash (mainnet 30 July 2015; PoW ended 15 September 2022, ETC continues) | a memory-hard DAG to keep GPUs competitive; no numeric bound (claimed) | first: Antminer E3, announced 3 to 4 April 2018, 180 MH/s at 800 W = 0.23 MH/J, shipped July 2018 with most units slipping to Q4 (claimed); current: iPollo V2H, released November 2024, 3,400 MH/s at 475 W (both plus or minus 10 percent) = 7.2 MH/J (vendor page, claimed) | RTX 4090 on Etchash 127 MH/s at 249 W = 0.51 MH/J; RTX 5090 215.8 MH/s at 405 W = 0.53 (hashrate.no, community-measured); the E3 under a good 2018 GPU per joule; the V2H 14x the 4090, 13.5x the 5090 | 36 | https://cointelegraph.com/news/bitmain-releases-ethash-asic-miners ; https://www.tweaktown.com/news/61527/bitmain-pushes-back-ethereum-asic-miner-now-coming-july/index.html ; https://www.ipollo.com/products/ipollo-v2h ; https://asicminervalue.com/miners/ipollo/v2h ; https://www.hashrate.no/gpus/4090 ; https://www.hashrate.no/gpus/5090 |
| Kaspa kHeavyHash (mainnet 7 November 2021) | no resistance claimed: designed for optical PoW, described as ASIC-friendly by design (secondary sources) | IceRiver KS0, August to September 2023, 100 GH/s at 65 W = 1.54 GH/J; Antminer KS3, October 2023, 9.4 TH/s at 3,500 W = 2.7 GH/J; Antminer KS5 Pro, March 2024, 21 TH/s at 3,150 W = 6.67 GH/J (all claimed) | RTX 4090 2,080 MH/s at 226 W = 9.2 MH/J (Kryptex medium profile, GPU-reported watts); the KS0 167x, the KS5 Pro 725x | 21 to 22 | https://www.asicminervalue.com/miners/iceriver/ks0 ; https://www.asicminervalue.com/miners/bitmain/antminer-ks3 ; https://www.asicminervalue.com/miners/bitmain/antminer-ks5-pro ; https://www.kryptex.com/overclocking/nvidia-rtx-4090-micron-24gb-medium-overclock ; https://www.btc-echo.de/academy/bibliothek/kaspa-mining/ |
Reading: RandomX promised parity and got roughly it (1.0x to 1.5x after 46 months; the one chip claiming more never shipped); Ethash promised nothing numeric, bought 36 months before a chip worse than a GPU, and sits at about 14x today on a memory system without a GPU; Kaspa claimed nothing, got its chip in 21 months and went 167x to 725x in six. Every ASIC watt is nameplate and every CPU and GPU figure a community test table, so the edges carry about 20 percent either way.
## 3. This lane's own ideas
### 3.1 The second sector: W = 16 words, the whole 64-byte item (KILL at stock on measured rows; the knee row owed)
@ -272,6 +284,7 @@ Both sides are capex-dominated (the record's 16.1: 7x to 10x their electricity p
- The chip side of 3.1 is the model's own data-movement term applied twice (4.5 pJ per bit, Micron, claimed, streaming; O'Connor's 3.48 for HBM2) and lane 3's wire figure for the SRAM die; no one has measured a second-sector column read's energy on GDDR7 (section 2.6: the public record has no random-read joule on any current part).
- The tensor chip figures are vendor specifications at TDP (claimed), the M4 ANE and the H800 loop measured; the RT figures are claims and one measured RTX 2080 row; the PHY node facts are vendor IP pages read today.
- The project-cost corrections use the history's figures (a 7 nm-class startup project USD 50 M to 75 M, claimed; the 12 nm figure scaled, approximate) and the mission lane's cap model.
- The `w64` class's census under the sub-version 3 rule and its F8 row, which this lane owed before any cut, are DONE by the census lane (`docs/analysis/class-v6/census-w16-mix.md` on `class-v6-census` at d20eb04bd, 14:0x UK): 256 of 256 seeds accepted with and without an era (0.704 rejection per candidate against the control's 0.668; 0 exhaustions; 0 window-bit refusals for the instrument's reason; 189 stride-bit refusals of 1,524 candidates against the control's 218; (c''') 1.4 percent); the F8-form top-0.1-percent share 0.999 to 1.006 of the uniform control at 2^20 on 16 seeds; the verifier +0.6 percent inside a 4 percent drift on a loaded core (this file's +4 percent neither confirmed nor refuted; a quiet-box row owed). One structural row for 3.1: at 16 words the product's low bits are alignment, so the whole-item read removes the product's own bias from the address (the control carries it at bit 0 in 116 of 256 programs); the stride bit R stays until the index fold. The class is sound; it is dead on energy, not on soundness.
- Nothing ran on the Mac, on a Hetzner box or on a PC for this file; the measurements ran on four RunPod one-shot pods, all destroyed on their done (the 5090 pod when its rows are in).
## 7. Sources