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igneum-labs
22bb0ff70e Merge commit 'fb6f84e3e' into site-2.0-wipe 
# Conflicts:
#	site/lc/app.js
#	tools/reference-apps/receipt/verify-receipt.src.mjs
 2026-10-08 15:43:09 +00:00
igneum-labs
54b0268c1e Site 2.0 wipe: merge the box master into the page sweep (the receipt page takes master's newer text with the devnet number, the testnet chain entry and the 17/30 floor removed); the light client's display strings name the devnet without a number; the index pins X2 and X31 (the testnet sentences) retired 
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
 2026-10-08 15:42:51 +00:00
igneum-labs
fb6f84e3e2 Site reset to Igneum 2.0, second pass: the reference apps and the deploy smoke pins follow the Igneum 2.0 devnet 
- /light, /receipt and the offline receipt verifier say "devnet, no value" (bundle and source), the reference-app test page
  names no devnet number, the faucet API's closed message names no testnet
- /oracle drops the earlier-oracle history sentence
- tools/site-deploy-from-mirror.sh: the served-page pins no longer expect "Devnet 3 faucet" or the class v5 floor history;
  they expect the Igneum 2.0 devnet faucet title and igneum-devnet-4 on /build

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:42:20 +00:00
igneum-labs
dda5dedf44 Site reset to Igneum 2.0, first pass: /bench and /journey gone, no testnet, no 0.x history, the Igneum 2.0 devnet, the positioning line 
- build.mjs no longer writes bench.html, journey.html or journey.json; the three files are deleted; /bench -> /evidence and
  /journey -> /live redirects (permanent: false); nav, footer, sitemap, capture routes and the site-nav-check groups drop them;
  link-check resolves literal vercel.json redirects and lists every link that leans on one (evidence.html: /bench, another hand)
- every testnet card, column, row, notice and link removed from the pages this lane owns; release manifest: the testnet entry
  gone, network igneum-devnet-4 "Igneum 2.0 devnet", the Devnet 3 genesis, digest, vote domain and floor lines dropped
- "Devnet 3" leaves every owned page; the devnet state is one constant in build.mjs (DEVNET_STATE, 'starting' now: the nav
  pill and the homepage badge read "Igneum 2.0 devnet starting"; 'live' flips both and re-enables the nav's live read)
- no 0.x release history: screenshot alt texts say the current build, the miner page's "Current build:" keeps the data-rm
  spans without the node version; miner-bench.json keeps the current-program rows only, no Counter ASIC names, no versions;
  /miners drops the earlier-classes table, the history note and the miner-version column
- /income keeps the calculator; the testnet-era tier tables (docs/analysis/income-tiers.md) are not served
- the positioning line is the first line of the footer partial (every page), the homepage meta description's first sentence
  and the hero's sub-line; share metas (site/og/pages.mjs) carry no Devnet 3 or zkEVM
- ledger-text-check is red on two index.html pins (X2, X31: the testnet sentences), owned by the ledger hand

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:40:33 +00:00
igneum-labs
5405dd9f20 Merge counter-asic-4 03029526 into master (gate: green on 03029526, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:37:40 +00:00
igneum-labs
9f490a5b8c Merge class-v6-adversary-docs d1d29460 into master (gate: green on d1d29460, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:35:33 +00:00
igneum-labs
c67e9dae42 Merge release-manifest-8 d5ba3c3a into master (gate: green on d5ba3c3a, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 15:32:32 +00:00
igneum-labs
03029526da Merge the mirror's master into counter-asic-4 before the third landing 2026-10-08 15:28:43 +00:00
igneum-labs
d1d2946038 multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
30ba24bea1 multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
d944e81ad0 Merge reference-apps 272fd4ae into master (gate: green on 272fd4ae, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 15:27:58 +00:00
igneum-labs
17b9901b67 Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:27:51 +00:00
igneum-labs
e0cfa64f17 Merge ca3-coord-record cacdb438 into master (gate: green on cacdb438, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:26:45 +00:00
igneum-labs
b4de1eccfd Merge counter-asic-4 a39ab8ec into master (gate: green on a39ab8ec, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:25:52 +00:00
igneum-labs
d5ba3c3a90 Merge the box master 31496f4e into release-manifest-8 (the evidence page rebuilt) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:25:22 +00:00
igneum-labs
cacdb438ac Counter ASIC 3.0 status: the amended close on master (31496f4e), the adversary core rows (k 0.40 node for node), the connected-state rows (the window under 1 percent on the card), every platform on 0.3.26, the enforced-proving lane's line and route, the class v5 lane's kit item, the gate kills by name found and named 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:19:19 +00:00
igneum-labs
d94c69e460 Chip text: the third review's claim statement served verbatim above the sentence on every copy; rotation named an optional improvement, not the mechanism; no threshold as the economic headline (the coexistence model owed); X35 pin added 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:18:17 +00:00
igneum-labs
a39ab8ecc3 Merge the mirror's master into counter-asic-4 before the second landing 2026-10-08 15:17:45 +00:00
igneum-labs
7bb9dee35c Economics: the provers' part of the tip is designed and not in the code (the executor credits the whole 80 percent to the miner, 20 to registered developers); the fee table carries the designed row; the pool is the only thing that pays an internal prover today 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:17:22 +00:00
igneum-labs
3b78cd5dbe Class v6 10.0l: the third external review (the objective durable GPU competitiveness; the definition on a reference population with cost per accepted unit of work; the coexistence model replaces the capex wall, a new document by 21:00; the claim statement above the served sentence, rotation an optional improvement) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:16:26 +00:00
igneum-labs
16608d4d02 Class v6 10.0k: the connected-state lane's first rows (63 of 64 registers necessary; the window +0.6 percent on a 5090 at stock; censuses as well as v5; the narrow per-step chain names the two-level-file re-optimisation) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:15:18 +00:00
igneum-labs
272fd4ae9f Merge build/master into reference-apps (receipt.html: the payment receipt copy and the terms block kept over the og lane's older copy; the og metas kept) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:14:48 +00:00
igneum-labs
8b18be76f5 Chip text: the window's defence carried with its disagreement (about 0.13 of k against a flop register file; the multi-family adversary's first core reads it as close to nothing; the placed rows settle it), its card cost measured under 5 percent 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:14:27 +00:00
igneum-labs
c43880ef41 Class v6 10.0j (after the landing): the multi-family adversary lane's macro-window core (k 0.40 node-for-node; the window knob buys the card nothing against a macro file) carried beside the k lane's model as a disagreement the placed rows settle 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:13:27 +00:00
igneum-labs
31496f4ef9 Merge counter-asic-4 7e5897dc into master (gate: green on 7e5897dc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:12:06 +00:00
igneum-labs
ffd6751e7c Release manifest and the proving economics: site/release-manifest.json served at /release.json (network and chain id, source commits and fingerprints, mining class and dataset, finality rule v3, proof program ids, verifier off per P21, fees, versions per platform, the proving view, generated date); /build, /economics, /miner, /evidence and the litepaper read it at build through data-rm spans and a gate check holds the pages to it; /light, /receipt and the light client say two thirds of total weight; 4463 marked historical in older docs; dated log entries labelled historical; the evidence page's sixth label (activated) and the reference-repository wording; /economics gains "Who pays for proving": three incomes apart, the burned base fee stated, the measured 24-hour payout, the halving walk computed from emission.mjs at build, per card per hour, the two routes priced, no price 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:11:33 +00:00
igneum-labs
b0411162c0 Merge class-v6-floor-denominator-docs-3 03b7bf05 into master (gate: green on 03b7bf05, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:11:19 +00:00
igneum-labs
abf5a5a606 Chip text: the bracket serves (about 2.3x to 3.3x a node ahead, 2.0x to 2.9x node for node, approximate and provisional) in place of the provisional 2.2x to 2.4x figures, on main's order; the placed gated core row replaces it when it lands; labels, evidence row 17, X35 and the pin follow 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:10:34 +00:00
igneum-labs
c1f082c87b Merge ca3-coord-record e8f017e7 into master (gate: green on e8f017e7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:07:38 +00:00
igneum-labs
9d9b46de99 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 15:06:22 +00:00
igneum-labs
7e78bb366b Reference apps: the payment receipt. The transaction's execution outcome is authenticated through the proven segment's receipts commitment: the segment record (BLS by its aggregator, carried under the certificate) commits keccak over the shard receipts roots, the shard's receipts rebuild its ordered trie root in the browser and offline, and the transaction's receipt sits in it (status, logs). Issued for a transaction executed at a paid segment's last block; otherwise the inclusion receipt, with the reason. Eight payment negative cases pass beside the nine inclusion ones; the page and the one-file verifier name which receipt they issue 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:06:21 +00:00
igneum-labs
141abbe5e7 Merge site-og-26 bdbb4cc9 into master (gate: green on bdbb4cc9, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 15:05:59 +00:00
igneum-labs
7e5897dc32 Class v6 10.0i: the adversary's re-optimised core (the gated base k 0.37 at N3, the gated window 0.50, +0.13 of k the window's honest defence; the placed ungated core +64 percent over synthesis) and the bracket the served figures sit in until the placed gated rows at 17:30 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:04:41 +00:00
igneum-labs
03b7bf05a1 Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 394da98a9 (394da98a91) for the box mirror master
 2026-10-08 15:04:38 +00:00
igneum-labs
999fec1519 Merge class-v6-floor-denominator-docs-2 8384bfc7 into master (gate: green on 8384bfc7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:03:47 +00:00
igneum-labs
e1d397e8b0 Merge the mirror's master da5e1e8a into counter-asic-4 (the coord record lane's earlier copy of class-v6-rotating-family.md superseded by this branch's) 
# Conflicts:
#	docs/design/class-v6-rotating-family.md
 2026-10-08 15:03:33 +00:00
igneum-labs
7fab675a02 Chip text: the served sentence opens "adopts the 64-register window and retains it across every rotation" (the close's 10.0h after the site audit read); the card's cost of the window labelled measured (rented 5090 and 4090 at stock, 8 October 2026); the X35 pin follows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:03:10 +00:00
igneum-labs
e8f017e766 Counter ASIC 3.0 status: the public 0.3.26 cut 5054d0ee with the 16:00 minute, the first two class v6 packs (hl-v6-fold 482dc0da, hl-v6-rw 30628f8a) an hour early, the census lane's dry PASS and its per-pack pass line, the RX 7600 read (13.88 MH/s at 113 W), lane 5's manifest order, the floor-sm amendment 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:00:15 +00:00
igneum-labs
bdbb4cc953 site/og: the receipt card re-rendered with its kicker 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:59:10 +00:00
igneum-labs
a68a36c0e9 Merge box/master into site-og-26 (the receipt's new wording carried into site/og/pages.mjs) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:58:52 +00:00
igneum-labs
da5e1e8a69 Merge ca3-coord-record 7fdd094a into master (gate: green on 7fdd094a, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:58:07 +00:00
igneum-labs
01d2848791 Class v6: the window's card cost MEASURED (within 5 percent per load with the liveness chain, no spill); the served sentence's one word made honest (adopts, retains across every rotation); lane D's report (x16 over the verifier gate; the genesis table's 75-point spelling under test); lane C's drawn-era F8 read (the per-load class must take (c''')); lane 1's memory-clock ladder (the memory side bought one for one with the rate) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:56:22 +00:00
igneum-labs
33c0a58b65 Merge class-v6-floor-sm-docs-2 308aa4a7 into master (gate: green on 308aa4a7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 14:56:22 +00:00
igneum-labs
164803dd63 Merge reference-apps 11982954 into master (gate: green on 11982954, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 14:55:35 +00:00
igneum-labs
8384bfc795 Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6ef2a4ba8 (6ef2a4ba86) for the box mirror master
 2026-10-08 14:51:28 +00:00
igneum-labs
a4c5b6c1e8 site: share cards and metas from one source (site/og), rendered on a build box 
Every served page now carries its og: and twitter: block from site/og/pages.mjs through site/build.mjs (injected between
share markers on the hand-written pages, through meta() on the generated ones); nothing is pasted per page. New cards under
site/og/: eighteen 1200 x 630 PNGs at about 100 KB and a 1200 x 1200 square each (the second og:image for the readers
that crop square), rendered from site/og/card.html by site/og/render.mjs on build box 2 with its Playwright, never on the
Mac. The old og.png family stays on disk for cached links; nothing points at it. Titles under 60, descriptions under 110,
checked by the build. One command refreshes every card: node site/og/render.mjs.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:51:03 +00:00
igneum-labs
7fdd094ab8 Counter ASIC 3.0 status: the register window's measured set on the 5090 and 4090 (at most 5 percent per load, no spill, no rate per unit of work), all five floor documents on master, lane C's drawn-era F8 row (layer 5 takes the floor), lane D's full report 3958f0d29, lane 5's served text read, the build order's amendments relayed; the 7 October public-text file marked superseded 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:50:51 +00:00
igneum-labs
308aa4a7da Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6d666ce9d (6d666ce9d6) for the box mirror master
 2026-10-08 14:49:41 +00:00
igneum-labs
1198295463 Merge remote-tracking branch 'build/master' into reference-apps 2026-10-08 14:48:24 +00:00
igneum-labs
18ae1a31b5 Reference apps, the review's four orders: /receipt is a transaction inclusion receipt in title, copy, file and the offline verifier's output (a payment receipt authenticates the outcome and is named as the next step); /light states its trusted inputs in one block and reads as a verification path with stated trust assumptions; /oracle discloses the deployer-installed voter table and the unchecked aggregator signature on the page and in trust() (oracle redeployed on the shared verifier, 0x3ad71d46, chain id accepted before and after the class v5 floor); the four words included, executed, proven, finalised defined once in site/partials/terms.html and injected on the three pages 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:48:23 +00:00