igneum-labs
03e0eecf86
Counter ASIC 3.0 status: the 0.3.25 pin named c9ad753a at 14:08 (every gate green, the fast-time PASS on the freeze-paired pair, the v5 read-back PASS, the FAIL seed re-read at the exact freeze, the minute 14:30 to 14:40, the fleet's census gate at 28,462), the testnet re-cut 0d05e795, the F8-256 attributions (p212 the bucket tail, p225 the value-level class), lane C's drawn-era re-read, the floor-sram and floor-invention landings, the PC 1 order and the 7600 card-in plan, the chain-id deploys
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:07:05 +00:00
igneum-labs
c4f90a0061
Merge class-v6-floor-invention-docs c62f15c0 into master (gate: green on c62f15c0, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
3099597026
Merge class-v6-floor-sram-docs 54ada47f into master (gate: green on 54ada47f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:55:14 +00:00
igneum-labs
3105f72d8f
Merge ca3-coord-record d76cd38b into master (gate: green on d76cd38b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:54:19 +00:00
igneum-labs
d76cd38bef
Counter ASIC 3.0 status: the STOP on the pin at 13:29 (the fast-time pairing FAIL on an attempt-3 seed), its cause (the 0.3.25 worktree's pre-freeze igneum-pow copy under the paths override; the live network fingerprinted ON the freeze, cbc5bd0a), rule 19 (the build-time fingerprint refusal, packaging/pow-freeze.txt), the rebuilt shas 6ccaf9e9 and c9ad753a with the 90,000 ceiling and digest 2066aa57, the testnet re-cut 3ffcf83b, lane D's fan-out, the attack pass's twelve-chunk split, the explorer re-pointed at node1-dn3 and the 4464 chain id served, the counter-asic-4 docs landing 6af12f08
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:47:21 +00:00
igneum-labs
3c57693f62
Merge build/master into build-programme (the 4464 fact landed on both sides; this branch's wording and the second PASS line kept; the pages rebuilt)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:46:10 +00:00
igneum-labs
c62f15c0ad
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 39b8d058339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
ef198fa37b
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 68315bf8339b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
79e06feb6f
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 43fcf0fed39b8d05838
2026-10-08 12:45:35 +00:00
igneum-labs
251b76846a
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b13fc428f39b8d05838
2026-10-08 12:45:34 +00:00
igneum-labs
d2ddc61baf
Merge spec-accept-23 ddb434ab into master (gate: green on ddb434ab, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 12:39:06 +00:00
igneum-labs
683a5afc99
Builder pages and faucet: Devnet 3 chain id 4464 since the class v5 floor (8 October 2026, 13:27 BST reading)
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- the faucet reads eth_chainId from its node on every send and in its status (a fixed id signed refused transactions once the floor crossed); FAUCET_CHAIN_ID is gone from the env; the faucet now reads node1-dn3's EVM, the node the public RPC fronts
- /build, /faucet, docs/build/first-contract.md, rpc.md and faucet.md: 4464 with the floor note, "read it, never fix it"
- a second walkthrough PASS on the 4464 chain from build-2 through the public RPC and faucet: Counter at block 29878, 12 s end to end
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:38:51 +00:00
igneum-labs
362d6801e2
Merge dex-devnet3 db2db8bd into master (gate: green on db2db8bd, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:37:18 +00:00
igneum-labs
6af12f0871
Merge counter-asic-4-docs 5f45de99 into master (gate: green on 5f45de99, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:35:08 +00:00
igneum-labs
ddb434ab3d
Devnet 3's chain id is 4464 since its class v5 floor crossed at DAA 68,400 on 8 October 2026 (eth_chainId 0x1170 on the public RPC): /metamask's devnet card, by-hand list, builders' snippet and one-click entry (chainId 0x1170, rpcUrls the public RPC, the explorer as block explorer; the local node named beside it), /faucet's two lines, the build pages' network table and walkthrough notes (docs/build), the nav pill's title on every page
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:32:22 +00:00
igneum-labs
db2db8bde8
Swap page: the chain id read from eth_chainId at load (4464 from the class v5 floor at DAA 68,400, 4463 before it), never fixed in the page; devnet-3.json notes both
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:30:51 +00:00
igneum-labs
54ada47f91
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
88924ec8f4
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
ee2d3c8606
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
0478a6c0eb
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
7b523af541
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
745e9effc0
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
5f45de999f
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
7670ed9f15
Class v6: the last two 20:00 and 19:30 references pulled to the close
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
af0f82798e
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6bbb33364
2026-10-08 12:28:21 +00:00
igneum-labs
5f1090037f
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b3353fd08
2026-10-08 12:28:21 +00:00
igneum-labs
f9045cf567
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b6280dcfe
2026-10-08 12:28:21 +00:00
igneum-labs
7f93ff9092
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 78ce9ea46
2026-10-08 12:28:21 +00:00
igneum-labs
a88fd37d08
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9e3677f5e
2026-10-08 12:28:21 +00:00
igneum-labs
339236654a
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 73f2c0768
2026-10-08 12:28:21 +00:00
igneum-labs
ace2e5367c
Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 650c2ad56
2026-10-08 12:28:20 +00:00
igneum-labs
6ebe399950
Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fb93859c7
2026-10-08 12:28:20 +00:00
igneum-labs
251b0b006d
Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a836fcf50
2026-10-08 12:28:20 +00:00
igneum-labs
d8bb356de8
Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3585efb9d
2026-10-08 12:28:20 +00:00
igneum-labs
4dfa7fb769
Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fcea9a0df
2026-10-08 12:28:20 +00:00
igneum-labs
bfdf473ccb
Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of afad20f1f
2026-10-08 12:28:20 +00:00
igneum-labs
1af1c84d85
Class v6: kit b rows (the mixer draw costs the card nothing, measured; the shuffle-heavy base table 7 W under stock; the 5090 at the knee pays 4 / 8 / 10 percent more energy per hash at 2 / 4 / 8 GiB, replacing size-independent); floor lane 3's W = 8 and k-convention update
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1989495c1
2026-10-08 12:28:20 +00:00
igneum-labs
761f2cfc7b
Class v6: 10.3 the SRAM die and the dataset floor (floor lane 3: the read width the only wire lever, 66x at 4 bytes at zero shadow, the shadow the whole hold at 2.7x to 3.0x at k = 1; W pinned at 4 words at genesis; the floor as a ticket, 5.5 / 8.5 / 11.5 GiB; the capex wall's p* table)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7aa9f1898
2026-10-08 12:28:19 +00:00
igneum-labs
b3774f4de9
Class v6: section 10, the floor (the five floor lanes' terms, what the document already holds measured for each, the default at 19:30 and the row owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 35e960090
2026-10-08 12:28:19 +00:00
igneum-labs
2bba8c521b
Class v6: the sound per-load form's 5090 rows measured (shl4096x1 at class v4's count: 116 W over class v3 against the whole block's 152 unlocked, 59 against 84 at the knee; shl2304x3 19 W and 6.6 W over the whole block)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6cc3bfec8
2026-10-08 12:28:19 +00:00
igneum-labs
c1d7b1f251
Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e15f35ae
2026-10-08 12:28:19 +00:00
igneum-labs
d4fb47c1a6
Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fa8e742f6
2026-10-08 12:28:19 +00:00
igneum-labs
fcc0af77f3
Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 71f30fc80
2026-10-08 12:28:19 +00:00
igneum-labs
0abf6a24aa
Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8fee73f29
2026-10-08 12:28:18 +00:00
igneum-labs
38293eeeb1
Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8}
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 029744b7e
2026-10-08 12:28:18 +00:00
igneum-labs
b8536c901e
Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 91af4721e
2026-10-08 12:28:18 +00:00
igneum-labs
f338b190a6
Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d94c3e071
2026-10-08 12:28:18 +00:00
igneum-labs
b68041723e
Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0467872a6
2026-10-08 12:28:18 +00:00
igneum-labs
6cacc7a548
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 13181a296
2026-10-08 12:28:18 +00:00
igneum-labs
018a015697
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5b4db2c78
2026-10-08 12:28:18 +00:00
