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igneum-labs
13b4b42f19 Class v6 census: the post-review object's (c''') read (hl-v6-all 4de7b836cc40a4ea, generator 6, PASS: the rule with the floor, 256 of 256 at r 0.129, the window trace standing), with the 8cf53d5f2 read beside it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of b0712487f (b0712487f6) for the box mirror master
 2026-10-08 19:38:32 +00:00
igneum-labs
c0fd811463 Class v6 census: the x16 address rows for the four chain seeds; hl-v6-rw's harness outputs from build-3 (back at 19:48 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of bf666e2d2 (b0712487f6) for the box mirror master
 2026-10-08 19:38:31 +00:00
igneum-labs
3c6b2dea9d Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of e375bccf3 (b0712487f6) for the box mirror master
 2026-10-08 19:38:31 +00:00
igneum-labs
2ddb72aa75 Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of abf7711a4 (b0712487f6) for the box mirror master
 2026-10-08 19:38:31 +00:00
igneum-labs
8207f7534e Class v6 census: the x16 address rows for the four chain seeds; hl-v6-rw's harness outputs from build-3 (back at 19:48 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 258606e56 (b0712487f6) for the box mirror master
 2026-10-08 19:38:31 +00:00
igneum-labs
8fa614da28 Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 90c57eafc (b0712487f6) for the box mirror master
 2026-10-08 19:38:30 +00:00
igneum-labs
3e84124fb2 Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of d0dfcd777 (b0712487f6) for the box mirror master
 2026-10-08 19:38:30 +00:00
igneum-labs
c1b7426e73 AMD and Intel energy on class v6 (GPU-03 AMD and Intel cells, ECO-05 named cause): per 32 bits of bus the AMD and Intel cards burn the 5090s watts but do 0.21x to 0.47x its random reads; the window costs the RX 7600 and the Arc B580 no rate per unit of work; the B580 class v6 rows (11.01 MH/s, fingerprints equal, watts unreadable unelevated); hash-identical kernel candidates ranked (0 to about 10 percent); the RX 7600 metered knee owed to a queued PC 1 job 
Documents only: docs/analysis/class-v6/amd-intel-energy.md and docs/analysis/class-v6/amd-intel-energy/ (the three job scripts, the Level Zero sampler source, the offline-compile prelude and ISA summary).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>

Documents-only replay of c9e32b256 (c9e32b256a) for the box mirror master
 2026-10-08 19:21:27 +00:00
igneum-labs
cda49bef76 test registry: the hash lane's batch 1 (tools/ci/batches/hash-lane-20261008-batch1.json: bench:pc1-packs, bench:pc1-amd, bench:fleet-pods, census:class-v6, suite:pow as RUNNING with their evidence rows under docs/analysis/class-v6/rows) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 18:33:08 +00:00
igneum-labs
6aee2d5c33 Class v6 census: the per-site address census (the review's A03): the known-failed v2 case reproduced at 15.15 percent; class v5 and the v6 candidate uniform to 2.7e-7 at the worst address on the live dataset; the cache shares the era windows' by design (the adversary's 72 percent = the Devnet 3 window draw) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of b10fe1351 (b10fe1351dea53344acfa5b764d8215dc77480f3) for the box mirror master
 2026-10-08 18:11:09 +00:00
igneum-labs
4930820f38 Merge class-v6-family-gate 79557f4c into master (gate: green on 79557f4c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 18:01:23 +00:00
igneum-labs
79557f4ccd Class v6 family gate, 6.10: the hash lane's layer-8-off draw through the acceptance on class-v6 5c6b07015 against the same-crate windowed control (PASS: r 0.18 against 0.27 at width 4, the (c''') cost 2 against 13 percent, 0 hot sets and 0 over 1.2x at 2^20, the bit-R share up with the windows gone, the fold the lever); the harness port diff at 5c6b07015 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 17:54:46 +00:00
igneum-labs
ac8843f566 Publish the 2.0 evidence set on the public mirror (main's word): coexistence-model.md, operator-simulation.md, connected-state.md, coexist-rows.md and the class v6 design record leave the export-exclude list, the lane records and logs stay excluded; the zone word redacted in connected-state.md; the mirror-follows-master note beside every evidence column 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 17:29:00 +00:00
igneum-labs
0e57ff834f Merge class-v6-family-gate 83652b68 into master (gate: green on 83652b68, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:26:17 +00:00
igneum-labs
83652b680d Class v6 family gate, 6.9 closed: the best-mix table's exact or = 0 attempts rows at both widths on build-4 (r 0.29 and 0.16, 0 exhausted, the floors at the width's cost), the owed line closed; the harness ported onto class-v6 3d086fac9 for the layer-8-off acceptance 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 17:20:45 +00:00
igneum-labs
c6af580343 Merge class-v6-connected-docs-2 fe7bd9fc into master (gate: green on fe7bd9fc, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 17:15:34 +00:00
igneum-labs
1cccae2dbc Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 25098c1a2 (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
 2026-10-08 17:08:39 +00:00
igneum-labs
7df8aeabbf Merge class-v6-family-gate 3c93b0db into master (gate: green on 3c93b0db, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 17:01:32 +00:00
igneum-labs
fe7bd9fc43 Connected state: the PC 1 lock row (the window +1.6 percent of energy per hash at the 1,300 lock, +5.9 unlocked; the score re-read at x 1.016: 1.08x node-for-node, 1.07x a node ahead; the verdict unchanged) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of dd9e114c3 (dd9e114c3a) for the box mirror master
 2026-10-08 16:57:26 +00:00
igneum-labs
3c93b0db47 Class v6 family gate, amendment 6.9: the best-mix genesis table's acceptance for D1 (PASS: r 0.33 and 0.19 at widths 4 and 1, 0 exhausted, the floors at the width's cost, attack-f8 at the exact table 0 hot sets and 0 over 1.2x at 2^20; the exact or = 0 attempts rows owed with build-3 unreachable); the Igneum 2.0 pause recorded 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 16:54:11 +00:00
igneum-labs
972ba47e86 Merge counter-asic-4-docs-2 ce085ee4 into master (gate: green on ce085ee4, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 16:33:46 +00:00
igneum-labs
ce085ee4a1 Merge box/master 5984fdec into counter-asic-4-docs-2 (the export list: both additions kept, operator-simulation.md and the pre-2.0 ledger copy) 2026-10-08 16:27:51 +00:00
igneum-labs
8615bedbbc Merge class-v6-adversary-docs-2 14544a75 into master (gate: green on 14544a75, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 16:27:23 +00:00
igneum-labs
14544a758d multi-family adversary: clock stamps read from the Mac 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 10b901a46 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
 2026-10-08 16:10:22 +00:00
igneum-labs
2b7ad8fd27 multi-family adversary: the placed full-core rows, the board and D2(b) at the placed energy, the transition matrix, the one page 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 7e715b50b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
 2026-10-08 16:10:21 +00:00
igneum-labs
74678180d4 multi-family adversary: the placed board figures corrected to the model's output 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 2b30cfd0b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
 2026-10-08 16:10:21 +00:00
igneum-labs
3728ceca96 multi-family adversary: the placed genesis core rows, the 32-lane genesis row, the board at the placed energy, the D2(b) harness and its rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 90001aae6 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master; left on the branch: tools/chip-model/mf/flow/d2b.py tools/chip-model/mf/results/board-placed-base-n5.md tools/chip-model/mf/results/board-placed-full-n3.md tools/chip-model/mf/results/board-placed-full-n5.md tools/chip-model/mf/results/d2b-n3.md tools/chip-model/mf/results/d2b-n5.md tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.json tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.log tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/power_synth.log tools/chip-model/mf/results/out/mf32base/reports/asap7/mf32base/base/synth_stat.txt tools/chip-model/mf/results/out/mf32base/results/asap7/mf32base/base/mem.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/6_report.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power.log tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/VDD.rpt tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/6_report.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power.log tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/VDD.rpt tools/chip-model/mf/results/sim/mf32base/gl2sim.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md
 2026-10-08 16:10:21 +00:00
igneum-labs
9ce45b6ef2 Class v6 mixed FP32: section 6.1, the k lane's synthesised FP32 rows (FMA lane 3.4 pJ at N3, k 0.65 on the unit, 0.15 blended at the lock); the score 3.2x / 3.5x; the verdict stands 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of e6d52e198 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
 2026-10-08 16:07:14 +00:00
igneum-labs
85a90d0e7c Class v6 mixed FP32: the final rows (fp24 CPU 2^24 equal on three cards, the quiet-core verifier, the 4090's fp24 and v5-genesis rows), every pod record 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 255be0264 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
 2026-10-08 16:07:14 +00:00
igneum-labs
0d570ccd3a Class v6 mixed FP32: the rows (census on build-4, the stock 5090, the 4090 and the capped 5090, the CPU-vs-CUDA fingerprints), the chip-side reading, KILL on the GPU budget and the full-board score; the pod scripts and the records 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of a324c941e (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: tools/attack/v6-census/pod-bench.sh tools/attack/v6-census/pod-census.sh tools/attack/v6-census/sampler-summ.py
 2026-10-08 16:07:13 +00:00
igneum-labs
d20a3bfa41 Class v6 mixed resource: the FP32 candidate behind IGNEUM_FG_FP32 (fadd, fmul, ffma, fcvt in the shadow draw, xor-injected, the fp_in operand rule), the determinism rules in the emitter for CUDA, OpenCL and Metal, the CPU reference, the fingerprint subcommand, the report skeleton 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of c19e19b91 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: igneum-pow/src/accept.rs igneum-pow/src/emit.rs igneum-pow/src/generator.rs igneum-pow/src/main.rs igneum-pow/src/verify.rs igneum-pow/tests/mixer.rs
 2026-10-08 16:07:12 +00:00
igneum-labs
2e88ccba94 Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only copy of counter-asic-4 df7c85c1c (its delta over master 1ace22052: docs/analysis/class-v6, docs/design, docs/spec, the export list; nothing outside docs/ differs at that tip; the branch itself stays unmerged, its history carrying the igneum-pow research commits)
 2026-10-08 16:05:40 +00:00
igneum-labs
bf2989f443 docs: class v6 coexistence rows on an RTX 3060 12 GB and an RTX 4060 8 GB (5.5 GiB miner beside the compressed shard prover, verbatim run-log rows, the reconciliation with the 6 October 8.9 GB row and the 16 GB rule) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:48:20 +00:00
igneum-labs
e35dc94d5b Merge class-v6-connected-docs a072f589 into master (gate: green on a072f589, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:43:21 +00:00
igneum-labs
8624a02393 Merge counter-asic-4 45b40140 into master (gate: green on 45b40140, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 15:37:40 +00:00
igneum-labs
a072f58902 Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
 2026-10-08 15:28:39 +00:00
igneum-labs
0dc8c17ef4 Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
 2026-10-08 15:28:39 +00:00
igneum-labs
c51fad1875 Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
 2026-10-08 15:28:38 +00:00
igneum-labs
ad5ca6e47c multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
01452ff1ea multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
 2026-10-08 15:28:35 +00:00
igneum-labs
2739aece9c Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:27:51 +00:00
igneum-labs
4c3b55d8c8 Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of 93ab3d4da (93ab3d4da1) for the box mirror master
 2026-10-08 15:04:38 +00:00
igneum-labs
02e6588796 Merge class-v6-floor-denominator-docs-2 a1e97f77 into master (gate: green on a1e97f77, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 15:03:47 +00:00
igneum-labs
a1e97f773f Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of c07ef717e (c07ef717ee) for the box mirror master
 2026-10-08 14:51:28 +00:00
igneum-labs
cb56187a17 Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of c2d4effeb (c2d4effebe) for the box mirror master
 2026-10-08 14:49:41 +00:00
igneum-labs
1058d7e406 Merge class-v6-family-gate 8adca0c0 into master (gate: green on 8adca0c0, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:46:07 +00:00
igneum-labs
afe9300a1e Merge class-v6-invention 5aa1b6ac into master (gate: green on 5aa1b6ac, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:40:15 +00:00
igneum-labs
8adca0c0ab Class v6 family gate, the full report: point B's row (0 hot sets at the 64 shape, 5 over 1.2x, the floor refusing 1 of 64) and the 18:00 amendment line (the best-mix genesis table under test) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:40:03 +00:00
igneum-labs
5b9e5b4062 Merge class-v6-floor-k-docs ba6763e7 into master (gate: green on ba6763e7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 14:39:16 +00:00
igneum-labs
58895bf32a Merge class-v6-family-gate d0808ffa into master (gate: green on d0808ffa, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 14:38:28 +00:00