igneum-labs a1e97f773f Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts) ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com> Documents-only replay of c07ef717e (c07ef717ee) for the box mirror master		2026-10-08 14:51:28 +00:00
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floor	Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)	2026-10-08 14:51:28 +00:00
logs	Merge class-v6-invention 5aa1b6ac into master (gate: green on 5aa1b6ac, recorded by tools/ci/pre-push.sh; landed on the build mirror)	2026-10-08 14:40:15 +00:00
census-w16-mix.md	Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)	2026-10-08 13:09:44 +00:00
family-gate.md	Class v6 family gate, the full report: point B's row (0 hot sets at the 64 shape, 5 over 1.2x, the floor refusing 1 of 64) and the 18:00 amendment line (the best-mix genesis table under test)	2026-10-08 14:40:03 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, revision 3: the dataset-floor schedule priced per tier and against the chips (section 4.2a, main's ask of 11:2x UK)	2026-10-08 10:38:53 +00:00
invention.md	Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)	2026-10-08 11:45:37 +00:00