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igneum-labs
ee76f6ca70 Counter ASIC 3.0 status: the program-id fix merged (49884b9), the re-runs open 2026-10-06 16:26:11 +00:00
igneum-labs
def97dc323 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:24:30 +00:00
igneum-labs
49884b91d9 Counter ASIC 3.0 gates (node): the program id carries the class. A class v4 program is generator 4 wherever it is made: the CLI's --era path stamps the generator from the class (era_generator_of: 4 on V4_CLASS, 3 otherwise; ProgramClass::of_load_class), show honours --program-class and --era-hex; the shadow block marks class v4 in packcheck, packfile.h and the Metal worker (a generator 3 pack with IGNEUM_SHADOW_INSTRS is refused as a v4 program stamped v3, a generator 4 pack without it is refused; generator 2 ladder packs unchanged); the seven gate packs re-exported (generator 4, id c120d7963abdcd96 against the v3 control's 73bcbfe8ccf988f1, every other line byte-identical); class-v4.mjs asserts every v4 epoch's id against the CLI's same-seed v3 and v4 ids (--id-check-against v4 is the assertion's failed case); v2 and v3 ids byte-identical (60 + 7 + 4 + 19 + 7, the pinned packs) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:24:02 +00:00
igneum-labs
60414c6498 Counter ASIC 3.0 status: AMD G2 job ready (chain-seed packs, own kit) 2026-10-06 16:22:31 +00:00
igneum-labs
e7709e0d60 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 16:22:30 +00:00
igneum-labs
2a704cff30 Counter ASIC 3.0 PC 1 AMD: gate G2 on the 9070 XT (the hash lane's form: found lines to g2-<pack>.found, count and sha256 per pack, digest_match against the verifier's digests derived on the Mac), the G2 kit maker with the chain-seed packs, README rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:22:01 +00:00
igneum-labs
209ed232e2 Merge commit 'e9643c0' into ca3-pc1-amd 2026-10-06 16:19:48 +00:00
igneum-labs
2f28ac5c1b Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:19:26 +00:00
igneum-labs
e9643c04fe Counter ASIC 3.0 gates (hash): the G2 job writes its found lines to g2-<pack>.found and prints the count and sha256 (no found line in the report, every RESULT line inside the cap, the log and collect glob named); tools/ca3-v4/g2-recheck.sh derives the digest from hash-bound and diffs a found file; trusted on a known-good and a known-bad file 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:18:57 +00:00
igneum-labs
e0ac1ccde0 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for the project lead 2026-10-06 16:18:08 +00:00
igneum-labs
a1fa94e9b8 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
7380469f43 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 16:16:21 +00:00
igneum-labs
40f7b77821 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:15:17 +00:00
igneum-labs
c44281cfac Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:14:08 +00:00
igneum-labs
38b5a0e241 Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:30 +00:00
igneum-labs
a32925abbc Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:10:00 +00:00
igneum-labs
880b359d42 Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:07:55 +00:00
igneum-labs
a3058de2e7 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 16:03:33 +00:00
igneum-labs
589ee3e0e7 Counter ASIC 3.0 PC 1 AMD: the watts re-run script (sampler proven on the idle window, never blind), the sampler fed through the environment (the unquoted ArgumentList class), per-entry card restore in jobs 1 and 4, the README's record of job 1's first run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:02:55 +00:00
igneum-labs
f3e8702e71 Counter ASIC 3.0 gates (node): class v4 = mx8+sh256x27 through the stack (igneum-pow ProgramClass::V4, V4_CLASS, generator 4, program_id(4, seed, attempt), the era composed as v3's; program.h and program.json class v4; packcheck, packfile.h, the CUDA and OpenCL identity rule and the Metal worker accept generator 4 and the class=v4 token, the Metal worker takes v4 from the prepared pack only; v2 and v3 byte-identical, the pinned packs diffed); the G4 harness class-v4.mjs (two switches, the never case); override-60x.json: the v4 field at never, the duplicated proving v1 block removed, the four 0.3.12/0.3.13 fields added; CI check override-json-check.sh (no duplicate key in any override file) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:58:49 +00:00
igneum-labs
526000a614 Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 15:58:03 +00:00
igneum-labs
2818956c76 Counter ASIC 3.0 gates (hash): the class v4 packs (mx8+sh256x27 with the era at devnet epoch 0 and eras 0 to 5, the v3 control), the PC 2 G1+G2 playbook, hash-bound --count ported from ca2-era, the mixer harness on a class and an era (IGNEUM_MIXER_CLASS, IGNEUM_MIXER_ERA, the shadow contract) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:57:40 +00:00
igneum-labs
03f55677f6 Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 15:52:47 +00:00
igneum-labs
1960bbb262 Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 15:45:39 +00:00
igneum-labs
1552536365 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 15:40:42 +00:00
igneum-labs
a9e5b624f6 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 15:40:19 +00:00
igneum-labs
08e553424c Counter ASIC 3.0 PC 1 AMD: the four PC 1 job scripts (G1 + ladder on the 9070 XT with ADLX watts, family step costs, dr736 derive, the 4070 ladder), the kit maker and the README with the publish commands 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:39:51 +00:00
igneum-labs
eb19dfdb18 Counter ASIC 3.0 PC 1 AMD: OpenCL family probe (every 1.13.2 family through AMD's builtins, khr/intel sub-groups, media ops, C forms and local emulation; bit-exact on Apple OpenCL) and the clBuildProgram time line in the OpenCL worker 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 15:39:51 +00:00
igneum-labs
76c19c9516 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (the project lead 16:50 UTC), the gate table 2026-10-06 15:38:44 +00:00
igneum-labs
651b0315e4 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 15:13:22 +00:00
igneum-labs
4ae285f25e Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for the project lead; the owed list) 2026-10-06 08:48:18 +00:00
igneum-labs
ca40decd9e Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 08:45:48 +00:00
igneum-labs
40444c3b4c Merge branch 'ca3-shadow' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:45:48 +00:00
igneum-labs
0d47586d8f Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 08:45:02 +00:00
igneum-labs
ed5e4c19ae Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 
PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:44:57 +00:00
igneum-labs
bf6fab7bb0 Counter ASIC 3.0 items 6 and 7: PC 2 family playbook posts both card key forms from settings.json, confirms the card quiet by the process list, restores cards and prover in a finally block 2026-10-06 08:34:28 +00:00
igneum-labs
94cb5993d3 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 08:31:10 +00:00
igneum-labs
ee5afcfe03 Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:30:15 +00:00
igneum-labs
13013a3abd Counter ASIC 3.0 status: the detector's two calibration findings answered (8bbc524 merged; max r 0.10) 2026-10-06 08:29:28 +00:00
igneum-labs
82788325bf Merge branch 'ca3-detector' into ca3-coord 2026-10-06 08:29:09 +00:00
igneum-labs
8bbc5248bc Counter ASIC 3.0 items 4 and 5: the epoch common factor is the median over steady core ids 
The mean over every present id let one paused-and-resumed card (the Mac, a 178% step) push
every other residual the same way in the epochs it was off, which read as an r = 0.94 edge
between two honest 5090 keys on the merged tree (window 41 to 46). The factor is now the
median over ids that are steady and present in every window epoch (median over all present
when the core is under 3): the same window reads max r 0.10. README: the three calibration
readings (the edge, the factor-of-two from identities=2, the unsteady Mac) answered.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:28:55 +00:00
igneum-labs
340096939e Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 08:26:52 +00:00
igneum-labs
08aa12852c Counter ASIC 3.0 item 8: the PC 2 playbook switches the prover back on in its finally block (the clear file's constraint) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:26:22 +00:00
igneum-labs
55f3c5a158 Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 08:25:02 +00:00
igneum-labs
1c9ae00189 Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 08:24:50 +00:00
igneum-labs
c692253ea1 Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 08:24:29 +00:00
igneum-labs
236a588c67 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 08:11:03 +00:00
igneum-labs
1bc5da3d03 Counter ASIC 3.0 item 8: the CUDA text checked in the clang emulation and the OpenCL text on Apple OpenCL (gate G1 row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:10:25 +00:00
igneum-labs
43e767e964 Counter ASIC 3.0 item 8: the Mac rows 
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:08:26 +00:00
igneum-labs
e9463b504a Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 07:59:42 +00:00