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igneum-labs
36cb07830b Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 08:52:16 +00:00
igneum-labs
a9b3bf9b5f class v5 section 14 and AP-F8-6: F8's residue attributed (a per-site bucket concentration of about a quarter bit at one narrow-window site; the per-site bucket bound is the next class's second test) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:31 +00:00
igneum-labs
55b8ca7821 class v5 design page: the Arc fault's cause (the kit worker lacks the Intel rotate-fold rewrite intel_rotr.h; master lacks it too; the rebuild waits on the Intel lane's landing) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:46:54 +00:00
igneum-labs
645ddb2014 Counter ASIC 3.0 status: main's morning words (the look landed, the floor sentence to row 17, CA4 parked, the Mac rule lifted for the F8 tail, route (A) at 10:45 BST), the build-server lane's honest state and the deploy and pairs plan, the fourth cut 5b673577 (floor 68,400), the Arc B580's self-test fault on both classes and the Intel kit held out of 0.3.24, the design pass on master (d8459e79) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:40:46 +00:00
igneum-labs
80caad07b6 Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 08:38:09 +00:00
igneum-labs
0cc17998fd class v5 design page: the Intel row held out of 0.3.24 (the Arc B580's self-test fails on both classes' vector lanes with the dataset right: an Intel OpenCL evaluation fault; crossing time 09:36 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:38:08 +00:00
igneum-labs
54adb48ce0 Counter ASIC 3.0 status: the 9070 XT bench row on master (the AMD watts no longer owed), the hot-table ldcs rows (a dead lever; the hot family latency-bound), the PC 1 list main set closed on measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:13:01 +00:00
igneum-labs
cf4d5c143c Merge ca3-v4-amend 780b608d into master (gate: green on 780b608d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:11:38 +00:00
igneum-labs
780b608d4d bench-log: the hot-table packs on the RTX 5090, ldcs against base, unlocked and at the 1,300 MHz lock (36 rows, all PASS; ldcs dead, the hot packs lose 2 percent to the lock where mx8 loses 7.5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:05:19 +00:00
igneum-labs
575c07c721 Merge ca3-coord-record 0cc932f3 into master (gate: green on 0cc932f3, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:27:36 +00:00
igneum-labs
74865e3073 Merge ship-docs-0321 c67a3a77 into master (gate: green on c67a3a77, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 06:25:18 +00:00
igneum-labs
0cc932f3b9 Counter ASIC 3.0 status: the 5080 Ember tune (the lock worth +40 percent per watt over the stock climb; the knob's case), the knob on release-0.3.24 (2caf39c1), the 9070 XT tune (no AMD knob in 0.3.20; 18.9 MH/s at 202 W; the AMD core-clock knob a morning item), the hot-table job the last on PC 1 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:21:16 +00:00
igneum-labs
c67a3a77f2 release 0.3.22 section 21: the core-clock knob cherry-picked onto release-0.3.24 (the union with the efficient-point ceiling), the measured Ember line from PC 1 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:19:49 +00:00
igneum-labs
b7ea50ef69 Chip model 5.11 and new-pow 5.1: the per-MAC figures corrected by the per-lane tile count (32 MACs per tile, not 1,024; the 4090's 0.056 pJ is 1.8 pJ, the 5090 reads 2.9 and 1.5 at the shadow's premium), the tensor-tile column withdrawn (a chip's k on tile work 0.03 to 0.3, below the ALU shadow's); Counter ASIC 3.0 status: the microbench's correction, the night's closing sentence on measured rows, the CA4 file's commits 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:08:07 +00:00
igneum-labs
16ca6329d0 Counter ASIC 3.0 status: the microbench on the 5090 (20 probes at both states; shfl 55.8 pJ, mul 13.9, mulhi 39.6 against the ARX op's 11.3; int8 mma 1.36): the re-weight's re-opening condition not met on measured rows, the tile block's case in measured picojoules 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:00:29 +00:00
igneum-labs
fd3b79eb1b Counter ASIC 3.0 status: rank 2 closed in the CA4 file (the premium is the ops' energy whatever carries them), the op-mix re-weight's case to main as HOLD with its four-line basis and the condition that re-opens it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 05:23:57 +00:00
igneum-labs
e9b289d5cf Counter ASIC 3.0 status: the SM-sparse reading exists (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw; the premium is the shadow's ALU work, the SM-sparse candidate dead; the op-mix re-weight's case to main) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 05:16:37 +00:00
igneum-labs
d505302c07 Counter ASIC 3.0 status: F1's record on master (62475f87; lane (d) complete with its box-hours), the v5 lane's night closed (class-v5 1095eaa8 gated GREEN, 72 checks) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:37:03 +00:00
igneum-labs
744ca62c76 Merge ca3-coord-record 94a2e4bc into master (gate: green on 94a2e4bc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 04:36:04 +00:00
igneum-labs
94a2e4bc9f Counter ASIC 3.0 status: class-v5's F1 row on both mirrors, the CA4 packs on the 5090 (the tile premium 0.103 W per tile unlocked, 0.050 at the lock; every sound pack memory-bound), the prototypes' first sentence on measured rows (neither beats class v4's premium; the per-load class dead; the tile block at parity with the ALU shadow and worse at the chip's k), the k column's basis measured 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:29:48 +00:00
igneum-labs
62475f87f7 Merge attack-pass 15e70626 into master (gate: green on 15e70626, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 04:29:30 +00:00
igneum-labs
26d65185a9 Merge ca3-coord-record aeeedf3b into master (gate: green on aeeedf3b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 04:28:50 +00:00
igneum-labs
5c4beaa476 Merge ship-docs-0321 8e0345db into master (gate: green on 8e0345db, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 04:27:46 +00:00
igneum-labs
0315d47b70 class v5 design page: F1's full record line (chip-view ops, the empty top bins, AP-F1-1's v5 half fixed and passed) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:23:18 +00:00
igneum-labs
15e70626fb attack-pass lane (d): F1 shadow redundancy on the frozen class v5 tip dba17a0a, 10^5 programs, max 4.688 percent, 0 mismatches, PASS (the 0.3.24 gate line; AP-F1-1 FIXED-AND-PASSED on v5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:22:29 +00:00
igneum-labs
aeeedf3b19 Counter ASIC 3.0 status: the census harness's progress line and flushed partial (known-failed PASS), F1 PASS on class v5 (100,000 programs, max 4.688 percent saved, 0 soundness mismatches, 05:20 BST); the attack board on class v5 complete 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:22:26 +00:00
igneum-labs
8e0345db35 release 0.3.22: the attack-pass record lines (F9 and F1 PASS on the full 10^5), PC 1 overnight 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:22:12 +00:00
igneum-labs
3d059792d1 Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 04:22:02 +00:00
igneum-labs
77f48b9ea5 class v5 design page: F1 PASS on the freeze (100,000 programs, max saved share 4.688 percent, 0 mismatches); the attack families on class v5 complete 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:22:01 +00:00
igneum-labs
7c1784e64c attack-pass: F1 record section 12, the census flush and its known-failed test (2,000 rows after a kill at 2,000, PASS) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:08:52 +00:00
igneum-labs
4b81802099 Counter ASIC 3.0 status: the pass's close at master 4b2d8c8f, the fourth --variant fix (the capture's off-by-one, ca4sparse5), adv-accept off build-1 for F1's census and one holder yielded to the flush test, adv-cache-2 closed (2^36 reads at the control's values) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:02:45 +00:00
igneum-labs
e2f9d00a24 Counter ASIC 3.0 status: class-v5 gated and 4a162aba pushed, the lane (d) merge on master (41fb1b3b: F9 PASS, the F1 row as running, the harness progress line owed), the SM-sparse question's third run stopped at NVRTC on the rewrite's CRLF name capture (the fourth fix ordered), the microbench running 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:55:32 +00:00
igneum-labs
41fb1b3bf4 Merge attack-pass fcf92fb8 into master (gate: green on fcf92fb8, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 03:16:35 +00:00
igneum-labs
26d76d7c99 Merge ca3-coord-record ba3d419f into master (gate: green on ba3d419f, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 03:15:58 +00:00
igneum-labs
4b2d8c8ff9 Merge crypto-engage 41909de7 into master (gate: green on 41909de7, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 03:14:50 +00:00
igneum-labs
fcf92fb806 attack-pass: founder-strings scrub on the pass record (the gate's third never-push class) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:10:09 +00:00
igneum-labs
ba3d419f76 Counter ASIC 3.0 status: the step-budget fix and the GitHub guard on master, the SM-sparse rerun's second failure named and the third fix, class-v5's F9 row pushed, F1 read as computing to about 10:00 BST and the lane (d) merge ruled, the in-house adversarial pass closed at 04:08 BST (nine lanes, about 30.4 box-hours, USD 0.33, no break of the frozen object) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:09:37 +00:00
igneum-labs
0f6419ff31 Merge remote-tracking branch 'build/master' into attack-pass 
# Conflicts:
#	docs/analysis/attack-pass-2026-10.md
 2026-10-08 03:08:58 +00:00
igneum-labs
41909de797 in-house-pass.md: the close (section 14): every lane's final tip, box-hours and verdict, the totals, the pass's verdict in one paragraph 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:08:04 +00:00
igneum-labs
9a47418517 attack-pass lane (d): F1 on dba17a0a running at the 03:06 UTC reading (15 cores, projected end about 09:00 UTC); the census harness's no-progress gap named, the progress line and flushed partial owed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:07:23 +00:00
igneum-labs
b5f8f6b2a5 class v5 design page: F1's state (computing, not hung; its count exists only at its end, about 10:00 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 03:06:46 +00:00
igneum-labs
8905c8f992 Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 03:03:39 +00:00
igneum-labs
c66dfe2de8 Counter ASIC 3.0 status: F9's record on attack-pass, the design pass GREEN on the box with its four captures, the in-house pass's record on master (0c3c1c5c) with the GitHub-poll exception owned and the gate-side guard ordered, the third 5090 pass closed by its cap (the floor at or below 400 MHz, the optimum unchanged) with the four-minute lock exception, the SM-sparse rerun published 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:54:12 +00:00
igneum-labs
0c3c1c5ccb Merge crypto-engage 8dfc6453 into master (gate: green on 8dfc6453, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 02:50:14 +00:00
igneum-labs
d30f74e7fa Merge remote-tracking branch 'build/master' into class-v5 
# Conflicts:
#	site/ledger.html
 2026-10-08 02:39:20 +00:00
igneum-labs
cb8b94be72 class v5 design page: F9's full record line; the Intel row stated as not measured tonight (the second PC's Arc job queued until a Windows entry exists) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:39:00 +00:00
igneum-labs
d626b6b083 attack-pass lane (d): F9 exhaustion count on the frozen class v5 tip dba17a0a, 10^5 seeds, 0 exhausted, PASS (the 0.3.24 gate line) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:38:51 +00:00
igneum-labs
1cd8ba43e2 Counter ASIC 3.0 status: the bench log, row 17 and the 5080 bench row on master, the design pass rebased and its two overlap findings on the box fixed (2ca45001, 5158276c), adv-mixer-3's line and the pass in one line, the third 5090 pass below the knee, F9 PASS on class v5 (100,000 seeds, 0 exhausted), the pass record's wording fix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:38:49 +00:00
igneum-labs
6a5a598dd5 class v5 design page: F9's mean attempt index corrected to 2.185 (the lane's correction) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:38:15 +00:00
igneum-labs
1fc3adbc77 class v5 design page: F9 PASS on the freeze (100,000 seeds, 0 exhausted, 0 panics, max attempt 30) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 02:38:01 +00:00