igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity
2439 commits 357 branches 1 tag 2 GiB
Commit graph

2439 commits

This branch
This branch
All branches
Author SHA1 Message Date
igneum-labs
e2c54614aa class v5 kit (OpenCL host): gFlipLeafWord declared before parseArgs (the kit's C99 build read it undeclared; the 22:10 zip predated the option) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:56:19 +00:00
igneum-labs
f525c6887b class v5 kit: the Arc bench job keeps the host's whole stdout as RESULT lines (the 09:36 UK run lost the exchange, kernel and build-log lines) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:54:13 +00:00
igneum-labs
36cb07830b Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 08:52:16 +00:00
igneum-labs
7616ccd48d Merge intel-rotr-master f3d06b60 into master (gate: green on f3d06b60, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 08:51:15 +00:00
igneum-labs
a9b3bf9b5f class v5 section 14 and AP-F8-6: F8's residue attributed (a per-site bucket concentration of about a quarter bit at one narrow-window site; the per-site bucket bound is the next class's second test) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:48:31 +00:00
igneum-labs
c7915d090b Merge ca3-coord-record 645ddb20 into master (gate: green on 645ddb20, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:48:19 +00:00
igneum-labs
55b8ca7821 class v5 design page: the Arc fault's cause (the kit worker lacks the Intel rotate-fold rewrite intel_rotr.h; master lacks it too; the rebuild waits on the Intel lane's landing) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:46:54 +00:00
igneum-labs
f3d06b60fc OpenCL worker: on an Intel platform rotr_var is rewritten to the shift form before the build (the Intel rotate fold, the Arc B580 bisect of 7 October 2026) 
Intel's compiler turns rotate(x, (0u - n) & 31u) into a rotate LEFT by n: lane 0's register trace on the B580 diverged
at instruction 6 of iteration 0 (rotr) and nowhere before, in both exchange modes, with every other family and the
dataset kernels bit-exact. proto-opencl/intel_rotr.h rewrites the one helper line when the device's vendor or
platform string holds Intel (host.c's buildProgram and the prepare path), no other vendor sees a change, no pack or
consensus text moves. proto-opencl/test_intel_rotr.c (the pre-push gate runs it) feeds the line through the rewrite
under Intel, AMD and NVIDIA strings and asserts the outputs.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
(cherry picked from commit 5f8abe10a6)
 2026-10-08 08:44:23 +00:00
igneum-labs
645ddb2014 Counter ASIC 3.0 status: main's morning words (the look landed, the floor sentence to row 17, CA4 parked, the Mac rule lifted for the F8 tail, route (A) at 10:45 BST), the build-server lane's honest state and the deploy and pairs plan, the fourth cut 5b673577 (floor 68,400), the Arc B580's self-test fault on both classes and the Intel kit held out of 0.3.24, the design pass on master (d8459e79) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:40:46 +00:00
igneum-labs
d8459e7918 Merge ca3-coord 3557bf9e into master (gate: green on 3557bf9e, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 08:39:08 +00:00
igneum-labs
80caad07b6 Merge remote-tracking branch 'build/master' into class-v5 2026-10-08 08:38:09 +00:00
igneum-labs
0cc17998fd class v5 design page: the Intel row held out of 0.3.24 (the Arc B580's self-test fails on both classes' vector lanes with the dataset right: an Intel OpenCL evaluation fault; crossing time 09:36 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:38:08 +00:00
igneum-labs
3557bf9eb3 Site: the bench table's lead-cell width rule applies on desktop widths only (above 1,100 px); on the phone grid the lead cell has no max-width, so the rate cell no longer sits over the card name at 390 px (the box's sweep read the 360 px cap covering the lead text on a 390 px viewport) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:32:43 +00:00
igneum-labs
3eb188c30d Site: the bench table's lead cell wraps on desktop (the row rule's nowrap outranked the lead cell's normal by specificity, so the class v4 line ran under the rate cell at 1280 px and above; the overlap sweep on the box read it COVERED, the Mac's gate had skipped the sweep for want of a browser) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:32:43 +00:00
igneum-labs
ea9b933662 Site: the bench table's desktop row is six columns (the class v4 cost and the date move under the card name as the muted second line), the card layout below 1100 px, the wrapper scrolls as a safety (the overlap gate read the eight-column row clipped at every desktop width) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:32:43 +00:00
igneum-labs
33549c3dcc Site: the bench table's phone layout gives every cell its own grid area (the overlap gate read the quiet cells stacked under the Details button at 390 px) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:32:42 +00:00
igneum-labs
102cfa302e Site: the GPU bench table's design pass in the site's own language (the founder, 7 October 2026): the vendor mark and name lead, the rate as the big tabular number, MH per wall watt in the ember tint for the best desktop card, watts and the class v4 cost quiet, the tuned state a pill, the date muted mono; the Hive values, the source and the note in a Details row; cards you can buy and datacentre under hairline headings, the datacentre collapsed; 56 px rows on desktop, a two-line card per row on a phone; the best desktop card as the lede, the rates note under a disclosure; header sort with the arrow and the ember underline 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 08:32:42 +00:00
igneum-labs
c569ebb90f Merge ca3-coord-record 54adb48c into master (gate: green on 54adb48c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:19:20 +00:00
igneum-labs
54adb48ce0 Counter ASIC 3.0 status: the 9070 XT bench row on master (the AMD watts no longer owed), the hot-table ldcs rows (a dead lever; the hot family latency-bound), the PC 1 list main set closed on measured rows 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:13:01 +00:00
igneum-labs
cf4d5c143c Merge ca3-v4-amend 780b608d into master (gate: green on 780b608d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 07:11:38 +00:00
igneum-labs
780b608d4d bench-log: the hot-table packs on the RTX 5090, ldcs against base, unlocked and at the 1,300 MHz lock (36 rows, all PASS; ldcs dead, the hot packs lose 2 percent to the lock where mx8 loses 7.5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 07:05:19 +00:00
igneum-labs
3cde4b1980 Merge spec-accept-23 3c152ae1 into master (gate: green on 3c152ae1, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 06:35:03 +00:00
igneum-labs
9065fd7057 CA4 hot-table job: the first kit flattened the eight hot packs into one folder (the job exited 2 in 0 s, pack hot32k4 missing); kit b carries packs/<name>/ for all nine, the fetch and run ids take a b suffix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:30:27 +00:00
igneum-labs
a8b419ff64 Merge ca3-v4-amend 3b5bccae into master (gate: green on 3b5bccae, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:29:02 +00:00
igneum-labs
3c152ae10c Bench table: the RX 9070 XT row takes the app's own power reading at the stock point (202 W at 18.9 MH/s, 0.093 MH/W; the G1 ladder's 18.8 to 19.2 as the rate; the status row of 8 October 2026), tune state "no lever" (no AMD knob in 0.3.20), the class v4 cost unchanged, Hive values none; /miners rebuilt 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:28:55 +00:00
igneum-labs
575c07c721 Merge ca3-coord-record 0cc932f3 into master (gate: green on 0cc932f3, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:27:36 +00:00
igneum-labs
74865e3073 Merge ship-docs-0321 c67a3a77 into master (gate: green on c67a3a77, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 06:25:18 +00:00
igneum-labs
0cc932f3b9 Counter ASIC 3.0 status: the 5080 Ember tune (the lock worth +40 percent per watt over the stock climb; the knob's case), the knob on release-0.3.24 (2caf39c1), the 9070 XT tune (no AMD knob in 0.3.20; 18.9 MH/s at 202 W; the AMD core-clock knob a morning item), the hot-table job the last on PC 1 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:21:16 +00:00
igneum-labs
c67a3a77f2 release 0.3.22 section 21: the core-clock knob cherry-picked onto release-0.3.24 (the union with the efficient-point ceiling), the measured Ember line from PC 1 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:19:49 +00:00
igneum-labs
3b5bccaec3 PC 1 Ember per-card job: a card the app cannot steer stores one baseline row and logs no progress line; count the stored curve before calling the run empty (the 9070 XT run exited 1 on a real row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:18:25 +00:00
igneum-labs
87c0b06d42 Merge ca3-v4-amend f21fa4b9 into master (gate: green on f21fa4b9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:16:47 +00:00
igneum-labs
92bb581f42 Merge ca3-coord-record b7ea50ef into master (gate: green on b7ea50ef, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:14:22 +00:00
igneum-labs
b7ea50ef69 Chip model 5.11 and new-pow 5.1: the per-MAC figures corrected by the per-lane tile count (32 MACs per tile, not 1,024; the 4090's 0.056 pJ is 1.8 pJ, the 5090 reads 2.9 and 1.5 at the shadow's premium), the tensor-tile column withdrawn (a chip's k on tile work 0.03 to 0.3, below the ALU shadow's); Counter ASIC 3.0 status: the microbench's correction, the night's closing sentence on measured rows, the CA4 file's commits 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:08:07 +00:00
igneum-labs
aa71d750c6 Merge ca3-coord-record 16ca6329 into master (gate: green on 16ca6329, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 06:06:49 +00:00
igneum-labs
f21fa4b940 PC 1 Ember per-card job: the curve line cast an integer plus a string and threw (the 06:0x 5080 run's rows lost); string interpolation instead, and every card's stored curve printed at the start 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:06:24 +00:00
igneum-labs
16ca6329d0 Counter ASIC 3.0 status: the microbench on the 5090 (20 probes at both states; shfl 55.8 pJ, mul 13.9, mulhi 39.6 against the ARX op's 11.3; int8 mma 1.36): the re-weight's re-opening condition not met on measured rows, the tile block's case in measured picojoules 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 06:00:29 +00:00
igneum-labs
0af93068cf Merge ca3-coord-record fd3b79eb into master (gate: green on fd3b79eb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:30:14 +00:00
igneum-labs
fd3b79eb1b Counter ASIC 3.0 status: rank 2 closed in the CA4 file (the premium is the ops' energy whatever carries them), the op-mix re-weight's case to main as HOLD with its four-line basis and the condition that re-opens it 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 05:23:57 +00:00
igneum-labs
fbeb61f98f Merge ca3-coord-record e9b289d5 into master (gate: green on e9b289d5, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 05:22:56 +00:00
igneum-labs
e9b289d5cf Counter ASIC 3.0 status: the SM-sparse reading exists (a quarter of the SMs holds 98.2 percent of the class v4 rate at the same draw; the premium is the shadow's ALU work, the SM-sparse candidate dead; the op-mix re-weight's case to main) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 05:16:37 +00:00
igneum-labs
ccfbbeb006 Merge ca3-coord-record d505302c into master (gate: green on d505302c, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 04:43:18 +00:00
igneum-labs
e3bd943e0d CA4 microbench job: the kit's class v4 pack as the --pack argument (the exe's parser demands one before the microbench branch; the probes read none); republished as -c after the sparse run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:37:08 +00:00
igneum-labs
d505302c07 Counter ASIC 3.0 status: F1's record on master (62475f87; lane (d) complete with its box-hours), the v5 lane's night closed (class-v5 1095eaa8 gated GREEN, 72 checks) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:37:03 +00:00
igneum-labs
744ca62c76 Merge ca3-coord-record 94a2e4bc into master (gate: green on 94a2e4bc, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 04:36:04 +00:00
igneum-labs
94a2e4bc9f Counter ASIC 3.0 status: class-v5's F1 row on both mirrors, the CA4 packs on the 5090 (the tile premium 0.103 W per tile unlocked, 0.050 at the lock; every sound pack memory-bound), the prototypes' first sentence on measured rows (neither beats class v4's premium; the per-load class dead; the tile block at parity with the ALU shadow and worse at the chip's k), the k column's basis measured 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:29:48 +00:00
igneum-labs
62475f87f7 Merge attack-pass 15e70626 into master (gate: green on 15e70626, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 04:29:30 +00:00
igneum-labs
26d65185a9 Merge ca3-coord-record aeeedf3b into master (gate: green on aeeedf3b, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 04:28:50 +00:00
igneum-labs
5c4beaa476 Merge ship-docs-0321 8e0345db into master (gate: green on 8e0345db, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 04:27:46 +00:00
igneum-labs
0315d47b70 class v5 design page: F1's full record line (chip-view ops, the empty top bins, AP-F1-1's v5 half fixed and passed) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:23:18 +00:00
igneum-labs
15e70626fb attack-pass lane (d): F1 shadow redundancy on the frozen class v5 tip dba17a0a, 10^5 programs, max 4.688 percent, 0 mismatches, PASS (the 0.3.24 gate line; AP-F1-1 FIXED-AND-PASSED on v5) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 04:22:29 +00:00