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igneum-josh
bfccc26ed4 shadow-k: the 32-lane core (5.55 pJ per lane-op, k 0.45 at the lock), the shuffle row (1.24 pJ, k 0.021), the mix optimiser's best corner 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 15:28:57 +01:00
igneum-josh
3e2a202feb shadow-k: row (2'), the 32-lane 16-register core (4.2 pJ per lane-op ASAP7, k 0.34 at the lock at N3) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:55:35 +01:00
igneum-josh
05275ca6a9 shadow-k: the node column (node-for-node the base core is k 0.78 and the GDDR7 board 2.4x at the lock) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:53:42 +01:00
igneum-josh
036c1aded9 shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:51:23 +01:00
igneum-josh
e921670571 shadow-k: the ranking and the mixed draw (the census lane's re-weight on the unit floors and the core) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:10:39 +01:00
igneum-josh
ed7d2626d4 shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 14:05:13 +01:00
igneum-josh
49c49c340d chip-model: the programmable shadow core (core_v6: imem, fetch, decode, per-lane register file, the class units, era registers), 8, 32 and 32-lane 16-register builds, synthesis-only power path 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:18:54 +01:00
igneum-josh
6fab785c51 chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 13:05:02 +01:00
igneum-josh
9009ed0f40 chip-model: the shadow-k floor lane's RTL, testbenches and ORFS flow (ASAP7) for every class v6 mixer family 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:59:10 +01:00
igneum-josh
7618e72981 igneum-pow: the invention lane's known-failed test for the per-load bias fix (tests/v6_window_bits.rs: the sound form accepts under drawn eras 0 to 7 with 0 window-bit refusals; the no-era bit-0 refusal on seed 3 stands); 2 of 2 on igneum-build-2 at 11:41 UTC against 0ab27582's fix 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:41:56 +01:00
igneum-josh
0ab27582d6 Merge build/master into counter-asic-4 (the sub-version 3 line, the derivation recorder, master's re-exported packs); chip-model 5.12; class v6 sections; the per-load bias test judges the window's bits only 
The merge: accept.rs takes master's shadow pass in run_unit (the per-load sub-blocks keep their place inside the loop; the end-of-iteration pass is empty for that class) and its Acc fields beside site_bit_ones; generator.rs records the per-load and tile id bytes through master's recorder (r.lit "perload", r.lit "mm8/" and the tiles field), nothing for the class v4 shape; export-exclude keeps both sides.

The fix (the invention lane's finding, 8 October 2026, 10:48 UTC): BiasedIndexBit judged every index bit, and under an era a narrow-window site's top k bits are fixed by design, so every per-load form read 0 of 256 under any drawn era for the instrument's reason; it now judges only the bits inside each site's window mask (verify::window) and the (c'') pass, which runs the unit with no table, accumulates nothing. The research file's 20.2a-close reads REOPENED (the 16 x 27 form dead on the no-era census on both instruments; the sound form mx8+shl4096x1 accepts 234 of 256 seeds no-era; its drawn-era verdict the invention lane's 15:00 BST read); chip-model-v3 5.11 the same.

chip-model-v3 5.12 (main's order, 11:3x UK): the 2 GiB SRAM full store on one N2 reticle (17x at zero shadow, 2.7x to 4.8x with it, USD 400 to 600 of silicon, an N2 project of USD 100 M to 500 M) and the custom HBM4E base die (6.5x to 14x, untouched by the four layers), per-bank PIM's structural blindness, the M5 Max at 0.78 microjoules as the honest denominator; lane B's figures, labelled.

docs/design/class-v6-rotating-family.md: section 0's lead on the SRAM store, 0.1 the per-tier schedule table, layers 2 to 4 with lane A's priced schedule (5.5 / 8 / 11 GiB), lane D's three rings and the op-mix band (B = 4 on the injecting families, the lossy sum capped; 8 of 663 eras exhausting at the uncapped corner), the index fold as a layer-1 rule, the measured M5 Max size rows (-12 / -20 / -22 percent of rate at 2 / 4 / 8 GiB), the 5070 Ti stock pair, the x16 mixer rows with build-3's sibling-loaded method (11.4 ms, admissible false on the measurement), 7a lane B, 7b lane A, 7c lane C's layers 5 to 7, section 9 the served-line review for main's 20:00 word.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 12:32:09 +01:00
igneum-josh
1be20977ec Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:27:47 +01:00
igneum-josh
ad37a50c62 Class v6: 7a the hardware future beside the four layers (lane B's k bands: HBM4, the custom base die, DRAM on logic, the N2 SRAM store at 17x; the three changes taken into layers 1 and 2 and the denominator), section 0's one line extended 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:26:35 +01:00
igneum-labs
4c58ad6532 Merge class-v6-history 694c514d into master (gate: green on 694c514d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 11:26:13 +01:00
igneum-labs
34f63b3c52 Merge class-v6-hardware 59441ccb into master (gate: green on 59441ccb, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 11:24:52 +01:00
igneum-josh
5deba721c4 Class v6: lane D's two facts: the index fold as a layer-1 design row (7 of 16 drawn eras with a product bit on address bit R at abs z 130 to 511; the chip row 1.6 percent of reads at f = 1/2, zero at f = 1; the known-failed test 7 of 16 to 0 of 16 with the fold), the F8 tail bound in sigma not ratio, the bias test ordered after the fold 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:24:51 +01:00
igneum-labs
7be52d7668 Merge fast-time-decimals 689ccb3b into master (gate: green on 689ccb3b, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers) 2026-10-08 11:23:58 +01:00
igneum-labs
c6ff36ded8 Merge ca3-coord-record f53b1fe8 into master (gate: green on f53b1fe8, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 11:21:50 +01:00
igneum-josh
694c514d58 Class v6 history lane, first cut: every ASIC-resistant proof of work and its chips by mechanism, the four-layer mapping with a number per chip class, and the three lessons that bind on v6 
docs/analysis/class-v6/history.md: 21 chip rows by mechanism (what each chip specialised, what the design missed, the timeline, the v6 layer, closed or not, the per-joule number); in-depth sections for Ethash (the E3's DDR3, Linzhi's 4.4 GB beside 64 compute units, the Jasminer X4's DRAM hybrid-bonded onto a 40/45 nm die, the E9), ProgPoW (the Least Authority and Rao audits read from the PDFs, Kik, Linzhi's claim, the adopters), RandomX (the X5's RISC-V board at 1.46x, the X9 announced December 2025 and withdrawn May 2026 with zero units, RandomX v2 released 25 March 2026 with activation pending, the Qubic episode as the detector's lesson), Cuckoo (the GRN1's 512 MiB SRAM die, the G32, the iPollo G1, the 2025 bounty), Equihash (the Z9's single die, the Fudan parameter-following design), Scrypt and Argon2 (the BM1485's on-die scratchpads, Percival's lookup gap, MTP), the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows. The four layers against the history layer by layer, with the E3's death dates, Autolykos's growth rule, the design-cycle and FPGA-compile clocks, and the honest verdict that the stored-dataset chip (class C) is not closed by any layer: 5.1x per joule at zero premium, 2.1x with the shadow at k = 1. Two corrections to the 5 October file (the X9, RandomX v2) and one claim marked unverified (the 5x fork-surviving chip). First cut for 15:00 UK; the full report by 09:00 UK on 9 October.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:19:10 +01:00
igneum-josh
59441ccbd7 Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file) 
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:17:50 +01:00
igneum-labs
689ccb3bac fast-time: base_unit_decimals 8 in override-60x.json, the field the node line's test fast_time_60x_file_is_the_devnet_at_60x demands (0e4ec18a's change, added by hand after its cherry-pick conflicted; the 0.3.25 pre-pin matrix read core RED on every box without it, 8 October 2026, 11:1x UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:16:33 +01:00
igneum-josh
206e81e180 Class v6: the x16 quiet-core re-run (9.04 to 9.10 ms loaded on a quiet host, 10.1 to 14.8 under load): x16 stays admissible false at genesis, decided by the 2019-class core as ladder rung 3 is 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:16:17 +01:00
igneum-josh
f53b1fe84c Counter ASIC 3.0 status: the founder's load order on the four boxes and its placement (lane D's family sampling, the attack families at scale, lane C's packs, the pin matrix, the cross builds), the drift class settled by a fresh-walk node, the pin candidate e0644958 confirmed, the Windows installer class and the detach fix, the tiers' class-flip pair gated (081b3ba7), the rpc up, two reds on the release line from the first ten minutes of the load order (the missing 60x field; the detach's test literal) with their fixes and defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:14:50 +01:00
igneum-josh
163ba73d6c Class v6: the x16 mixer verifier measured on build-1 (8.69 ms cold alone, 10.11 ms with the sibling loaded against x8's 4.67 and 5.41): x16 inadmissible on the loaded reference core, the mixer band {4, 8} 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:14:50 +01:00
igneum-josh
55f6966063 Class v6: the 5070 Ti tier measured (a rented pod, stock: class v3 78.69 MH/s at 140.8 W, class v4 78.78 at 224.0 W, the premium 83.2 W, 10.3 pJ per counted op), the per-tier chip edges at stock 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:12:47 +01:00
igneum-josh
ca7d23a86b Merge ship-docs-0321 d0fea84e into master (gate: green on d0fea84e, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge) 2026-10-08 11:12:42 +01:00
igneum-labs
1f43cb069d Merge spec-accept-23 c32019c3 into master (gate: green on c32019c3, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 11:11:33 +01:00
igneum-labs
cdbb25f812 Merge ca3-coord-record 92ac8df1 into master (gate: green on 92ac8df1, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 11:07:39 +01:00
igneum-josh
c32019c361 Bench table: the model sweep's last rows (RTX 4070 Ti 31.24 MH/s at 95.4 W; L40S 56.41 at 220.7 W in the datacentre table; RTX 4080 Super 42.60 at 134.9 W); the GTX 1080 Ti row's flag cleared by its second host (five of five self-tests pass, the failure was the first host's VRAM); the page carries the sweep's two findings as one line (class v4 cap-proof; class v5 level on uncapped cards and 17 to 18 percent under on two power-capped hosts, so a v5 rate needs the power state beside it) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:05:26 +01:00
igneum-josh
5984ffab64 Class v6: layers 2, 3 and 4 written with their chip rows and per-tier rows, the gate plan (the family analysed as a family) and section 7 (what a fully general chip still gets); layer 1's three open numbers await the hash lane's rows or their defaults at 16:00 UK 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:04:29 +01:00
igneum-labs
fea8d7012e Merge spec-accept-23 f1696fb6 into master (gate: green on f1696fb6, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 11:03:42 +01:00
igneum-josh
d0fea84e58 release record section 24: the first lock on cc902690 (checkpoint 1931, 10:06:32 BST), the move's count and the three puller faults closed, 0.3.24 Windows take 2 (Inno stopped the app and copied nothing; the /IGNOTA=1 rule), 0.3.25 opened (tip 9b93e649, the ceiling cut e0644958, digest 1b37cb9d, the DMG 501ba293 staged, the clock), the tiers at the class flip, the signed apps pipeline (Igneum Labs LLC) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:03:40 +01:00
igneum-josh
92ac8df124 Counter ASIC 3.0 status: the 0.3.25 pairs and app tip (9b93e649 on the ceiling cut e0644958, its fast-time PASS at 10:54), the tiers' class-flip UI half (d949e274), the four builder lanes and the class v6 declaration with its four research lanes spawned and the outline on the mirror, the Arc re-read and v5lock jobs live, the held-push cause (the branch's own hook predating the per-process fix) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:01:24 +01:00
igneum-josh
7a133d7640 Class v6, the rotating family: the outline, section 0 per tier and the four layers' table with their chip rows' shape and the open numbers (the hash lane's three rows due 16:00 UK; the document complete by 18:00 UK) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 11:00:21 +01:00
igneum-labs
17d61d5215 Merge ca3-coord-record 1d70613d into master (gate: green on 1d70613d, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:58:13 +01:00
igneum-josh
f1696fb60b Bench table: the model sweep's rows 16 to 19 (RTX A6000 53.64 MH/s at 239.1 W in the datacentre table, v5 level with v4 on an uncapped sm_86; GTX 1080 Ti 16.26 at 124.3 W with the one-in-three cache self-test flag until a second host decides; RTX 4060 19.09 with no watts, the host has no power sensor; RTX 2060 14.13 at 120.6 W, the floor of the list; rented and untuned, 8 October 2026) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:57:36 +01:00
igneum-labs
c501a9754d Merge spec-accept-23 b3168ba0 into master (gate: green on b3168ba0, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 10:54:41 +01:00
igneum-josh
1d70613d08 Counter ASIC 3.0 status: the 0.3.25 pairs on 7bd2940f and the re-pointed app tip 92f004f1 (every input green at 10:33 bar the pin's gates and the crossing), main's sweep finding (class v5 17 percent under v4 on a power-capped A4000; a knee-locked card may lose a few percent at the crossing until Ember re-tunes) and its two orders with their defaults 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:48:45 +01:00
igneum-josh
b3168ba06f Bench table: the model sweep's rows 11 to 15 (RTX 2080 Ti 26.01 MH/s at 224.6 W and RTX 2070 Super 19.09 at 166.0 W, the Turing per-watt floor; A100 SXM4 138.10 at 268.6 W and H100 SXM 248.30 at 411.7 W in the datacentre table; RTX A4000 31.41 at 112.8 W under a 114 W host cap, its class v5 reading held off the page until an uncapped card confirms it; rented and untuned, 8 October 2026) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:47:14 +01:00
igneum-labs
1b0c45f82b Merge spec-accept-23 982b0bc7 into master (gate: green on 982b0bc7, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 10:45:55 +01:00
igneum-josh
982b0bc7e8 Bench table: the model sweep's rows 5 to 10 (RTX 3070 37.09 MH/s at 142.3 W; RTX 3070 Ti 38.98 at 177.1 W; RTX 4060 Ti 16 GB 20.07 at 79.2 W; RTX 5070 51.81 at 110.8 W; RTX 4070 Super 31.24 at 100.2 W under a 110 W host cap; RTX 3060 Ti 31.70 at 100.4 W; rented and untuned, 8 October 2026, the class v5 kit's fingerprint matched on each) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:39:57 +01:00
igneum-labs
c0f4bf8075 Merge spec-accept-23 89eb997f into master (gate: green on 89eb997f, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 10:38:41 +01:00
igneum-labs
910aeac2da Merge ca3-coord-record db86ee89 into master (gate: green on db86ee89, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:37:52 +01:00
igneum-josh
89eb997fbb Bench table: the model sweep's rows 2 to 4 (RTX 4070 Ti Super 41.24 MH/s at 142.6 W; RTX 3080 Ti 58.86 at 293.5 W; RTX 4080 40.71 at 128.6 W; rented and untuned, 8 October 2026, the class v5 kit's fingerprint matched on each, the hash at 0.99 to 1.00 of each card's read ceiling) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:32:03 +01:00
igneum-josh
db86ee8949 Counter ASIC 3.0 status: the 10:05 move's read-back (36 of 36 on the pin by 10:12, the first lock 10:06:32, carrying resumed; three fault classes named), the tiers gated (d3d0704a), the knob's tip e2962b89, the 0.3.25 app line assembled at 10:29 (e0d4425f), the node line's tip 7bd2940f with the one-shot gossip fix and the drift item reclassified 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:31:37 +01:00
igneum-labs
623fb07ef6 Merge ca3-coord-record f5fe9bd9 into master (gate: green on f5fe9bd9, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:26:15 +01:00
igneum-josh
7b40cf121c Bench table: the model sweep's RTX 5070 Ti row (78.45 MH/s at 135.9 W, 0.577 MH per wall watt, rented and untuned, 8 October 2026; the class v5 kit at the same rate, fingerprint matched; the hash at 0.99 of the card's read ceiling); the /miners lede recomputes from the data as three separate claims (best desktop card by rate, best stock MH per wall watt, best tuned), so a rented stock row never reads as tuned 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:25:32 +01:00
igneum-josh
f5fe9bd948 Counter ASIC 3.0 status: the 0.3.25 plan (the shipper's), main's word (the tiers both halves, gated) and the founder's word (0.3.25 today: the app line by 12:30, the pin by 13:00, the move after the 68,400 crossing reads clean, about 13:30), card-in ready, the tiers' UI half merged, the second deploy (f98e8e7c), the node line placeable ahead of its minute (c6629572), the knob's tip e2962b89, the Hetzner boxes on the founder's word 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-08 10:20:01 +01:00
igneum-labs
a3c1be5c35 Merge live-shards-8 b6ec58ad into master (gate: green on b6ec58ad, recorded by tools/ci/pre-push.sh; landed on the box mirror) 2026-10-08 10:19:53 +01:00
igneum-labs
72edef4917 Merge ca3-coord-record c5a32dcd into master (gate: green on c5a32dcd, recorded by tools/ci/pre-push.sh; landed on the build mirror) 2026-10-08 10:18:52 +01:00