Class v6: 7b the history beside the four layers (lane A's verdicts taken where they bind: layer 2 gains the per-year ceiling as its first constant, layer 4 the per-era null, the reserve order and the width warrant stated)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

docs/design/class-v6-rotating-family.md

@@ -46,7 +46,7 @@ PENDING the hash lane's rows (16:00 UK): the x16 mixer verifier and build; the t
 
 ### 3.1 The rule
 
-Class v5 (`docs/design/class-v5-stored-state.md`) already keys every item to a leaf of the chain's execution state and caps the leaf count at the dataset size (2^24 items at 1 GiB, 2^25 at the designed 2 GiB), sampling the state when it is larger. Layer 2 turns the cap into the size: the day's item count is the larger of the 1.13.3 schedule (2 GiB plus 0.5 GiB a year, the floor) and the state's record count times 64 bytes, rounded up to the power of two the index mapping needs (or the multiply-shift mapping of 1.13.3 option (a), which takes any size), with a genesis-fixed ceiling at the cache growth rule's next doubling so the verifier's lazy derivation stays bounded. Everything below the floor is today's design; everything above it is the chain's own growth deciding the memory a miner must hold.
+Class v5 (`docs/design/class-v5-stored-state.md`) already keys every item to a leaf of the chain's execution state and caps the leaf count at the dataset size (2^24 items at 1 GiB, 2^25 at the designed 2 GiB), sampling the state when it is larger. Layer 2 turns the cap into the size: the day's item count is the larger of the 1.13.3 schedule (2 GiB plus 0.5 GiB a year, the floor) and the state's record count times 64 bytes, rounded up to the power of two the index mapping needs (or the multiply-shift mapping of 1.13.3 option (a), which takes any size), with a genesis-fixed ceiling at the schedule's power-of-two step for the year (2 GiB to year 4, 4 to year 12, 8 to year 28, the cache doubling with it) so the state can only bring a step forward, never add one, the verifier's lazy derivation stays bounded, and every honest tier's lifetime is the card-lifetime table's at worst (lane A's finding: the ceiling per tier per year is the number to fix before the rate). Everything below the floor is today's design; everything above it is the chain's own growth deciding the memory a miner must hold.
 
 | State size (records) | Leaves | Dataset under layer 2 | Who holds it | Label |
 |---|---|---|---|---|
@@ -167,6 +167,19 @@ What this changes in the design, taken into the layers:
 2. **Layer 2's floor is a card-lifetime decision, not a chip lever**: the SRAM chip pays capex, not joules, for a larger dataset (USD 400 to 600 per 2 GiB die), and the real processing-near-memory threat is the custom base die, which no layer touches; the brake until about 2028 is HBM allocation and price (claimed: Samsung asking USD 4 to 5 per Gbit for HBM4 against 1.5 for HBM3E, 2 October 2026). The spec's schedule stands; the dataset stays inside 16 GB unified memory (8 GiB at the top of the schedule does).
 3. **The denominator: resistance is stated against the best honest joule** (the M5 Max at 0.78 microjoules, the 5090 at its knee at 1.67), where every chip edge is 2x to 3x smaller than against the 5090's stock point; section 0's per-tier line already reads so.
 
+## 7b. The history beside the four layers (lane A, `docs/analysis/class-v6/history.md` on master at 4c58ad65, 10:26 UTC; the first cut, the full report by 09:00 UK tomorrow)
+
+Lane A's verdicts, taken into the layers where they bind:
+
+| Finding | What it does to this document |
+|---|---|
+| The chip that stores the dataset (every Ethash chip: E3 1.0x, Linzhi 2.1x, Jasminer X4 5.1x by DRAM hybrid-bonded onto a 40 nm logic die, E9 Pro 4.1x) is closed by none of the four layers; every per-era draw and every family epoch is firmware to it; the number v6 inherits is 5.1x on GDDR7 at zero premium, 3.6x at the 5090's knee, 2.1x with the class v4 shadow at `k = 1` | section 0's frame and section 7's table say the same; the Jasminer X4 is the measured precedent for the hybrid-bonded row of 7a |
+| Layer 2 as declared is not an anti-chip rate: at 2 GiB plus 0.5 GiB a year a 32 GB chip board lasts 60 years and the 8 GB card is out at year 12; the Ethash E3 is the only chip a growth rule ever killed (DDR3 at the fleet's own 4 GB limit, 20 to 27 months after shipping); the value of layer 2 is its floor (above every SRAM die) and a CEILING per honest tier; if the state grows as Ethereum's did the dataset outgrows every card in a decade (approximate), so the ceiling in GB per tier per year is the number to fix before the rate | layer 2's rule gains the ceiling as its first constant: the dataset never exceeds the schedule's power-of-two step for the year (2 GiB to year 4, 4 to year 12, 8 to year 28), whatever the state does, so the state can only bring a step forward, never add one; section 3.2's reading ("retires cards before chips") stands and is now the reason the ceiling exists |
+| Layer 3 closes the fork (Grin's tweaks worked only as hard forks on a lane built to die; Monero's chips were back inside 4 months of v8; X16R's drawn order cost the FPGA nothing) and taxes a sequencer chip only die area (Rao: ProgPoW's whole inner loop about 1 M gates, 0.025 mm^2 at 10 nm), because a reserve readable at genesis is built in from day one | section 4.2's "USD 4 pre-wired" row is the same fact with the history's gate count beside it; the random item-derivation program (R0) is the one reserve item unknowable at genesis and keeps its place at the head of the order |
+| Layer 4 is the one layer acting on a mechanism that beat hashes after launch (Kik's 64-bit seed, Dinur-Nadler on MTP, AP-F8-1); the window-model null changes with any draw of read width, program length or windows, so the census re-derives per era (2.2 s per candidate), and the shadow-written residue (about 1.0004x) needs its own ceiling per shadow placement | section 5.1's F8 row gains the per-era null: the census tool derives the window model from the era's own draws before judging; the residue ceiling is a constant of the block shape (64 and 256 are the two shapes, each with its own) |
+| Corrections to the 5 October history: the Antminer X9 withdrawn in May 2026 with zero units shipped; RandomX v2 shipped 25 March 2026 (program 256 to 384, CFROUND 16x rarer, AES in the loop, prefetch 2 ahead, +52.9 percent work; activation pending in Monero PR 10038); Vorick's "survives forks at under 5x" chip unverified | this document quotes none of the three; the research file's section 2 already retired the X9 as a `k` figure |
+| The ranked list: layer 2's floor and ceiling per tier first; the clock and the detector (two instruments: nonce pattern for a chip, share-by-key-and-template for a concentrated fleet, which is what found Qubic until it randomised); keep the read width out of the draw unless a width other than 4 B is measured latency-bound on every vendor; bound the op-mix draw by the per-vendor energy table; order the reserve by what a sequencer cannot fold into firmware, mm8 last, R0 the one unknowable item; a null per drawn parameter for layer 4; the per-load placement as research, not a draw value | taken as the order of section 6's gates; the read width: w16 is measured within 2.7 percent on the 5090 and the 9070 XT and within 1 percent on the M5 Max (latency-bound on all three), so {1, 4} words stays in the band with that measurement as its warrant; the per-load placement is already out of the draw (section 2) and dead as a construction (the research file 20.2a-close) |
+
 ## 8. Unverified and owed
 
 - Lane D's family harness (the family gate's measured coverage: the 10,000-era random stratum and the three corner strata, the lossy cap, width 4, shape 64) lands in `family-gate.md` by 17:00 UK and is layer 4's coverage table; this document's layer 4 cites it where it is named and does not restate it.