igneum-labs
befc1121cd
Class v6 mixed FP32: the final rows (fp24 CPU 2^24 equal on three cards, the quiet-core verifier, the 4090's fp24 and v5-genesis rows), every pod record
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 255be0264 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
2026-10-08 16:07:14 +00:00
igneum-labs
beaf234e29
Class v6 mixed FP32: the rows (census on build-4, the stock 5090, the 4090 and the capped 5090, the CPU-vs-CUDA fingerprints), the chip-side reading, KILL on the GPU budget and the full-board score; the pod scripts and the records
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a324c941e (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: tools/attack/v6-census/pod-bench.sh tools/attack/v6-census/pod-census.sh tools/attack/v6-census/sampler-summ.py
2026-10-08 16:07:13 +00:00
igneum-labs
2a7d8f9a34
Class v6 mixed resource: the FP32 candidate behind IGNEUM_FG_FP32 (fadd, fmul, ffma, fcvt in the shadow draw, xor-injected, the fp_in operand rule), the determinism rules in the emitter for CUDA, OpenCL and Metal, the CPU reference, the fingerprint subcommand, the report skeleton
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c19e19b91 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: igneum-pow/src/accept.rs igneum-pow/src/emit.rs igneum-pow/src/generator.rs igneum-pow/src/main.rs igneum-pow/src/verify.rs igneum-pow/tests/mixer.rs
2026-10-08 16:07:12 +00:00
igneum-labs
003b0adb9d
Merge fleet-proving-pipeline-docs 7162f4a7 into master (gate: green on 7162f4a7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 16:05:23 +00:00
igneum-labs
ba6bf0ea16
Merge counter-asic-4 91929389 into master (gate: green on 91929389, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 16:03:13 +00:00
igneum-labs
a6549c525c
Merge ca3-coord-record d81cb3f9 into master (gate: green on d81cb3f9, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 16:01:43 +00:00
igneum-labs
9035ce35dd
Merge class-v6-rotation-docs b106bc31 into master (gate: green on b106bc31, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 16:00:10 +00:00
igneum-labs
a3562e1d70
Merge enforced-proving b2faca79 into master (gate: green on b2faca79, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:58:10 +00:00
igneum-labs
13e0905617
Merge reference-apps ddf2a1ed into master (gate: green on ddf2a1ed, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:56:54 +00:00
igneum-labs
802d258328
Merge pool-vote-key 8e1a7cf2 into master (gate: green on 8e1a7cf2, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-08 15:53:49 +00:00
igneum-labs
d81cb3f967
Igneum 2.0: the founder's reference (docs/plans/igneum-2.0-reference.txt) and the plan with the pins (docs/plans/igneum-2.0.md), decided 8 October 2026; landed from the Mac checkout, byte-identical
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:51:47 +00:00
igneum-labs
714cf36138
docs: Devnet 3 proving pipeline end to end, 8 October 2026 (the fleet lane's document, landed by the research-landing hand on the coordinator's word)
...
The document as it stood in the fleet lane's worktree at 16:46:43 BST (the same second as gpu-fleet 9991d7ce, which carried
tools/fleet/pipeline-collect.py and left this file untracked). Documents only; the collector stays on gpu-fleet.
2026-10-08 15:51:26 +00:00
igneum-labs
b106bc3159
Class rotation, four layers: the design document (the hourly program, the weekly parameter era, the 180-day family epoch from the genesis bank, the emergency miner vote over the finality votes; the five research lanes' recommendations kept or rejected with reasons; the exposure per boundary; faults 1 to 7 of the crossing day as refused-by-construction cases; what the fast-time crossing on build-3 showed, runs 1 to 4; under the Igneum 2.0 framing a capability the chain has, never a resistance claim), 8 October 2026
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:51:02 +00:00
igneum-labs
61ab6bb79c
Merge ca3-coord-record b02a141d into master (gate: green on b02a141d, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:50:02 +00:00
igneum-labs
8e222c819d
docs: paid pilot restated against the measured Devnet 3 pipeline (delivery and pass condition with the margin shown, 16 GB and up serves the pilot, the claim-window and tier-claim fixes with their files)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:49:54 +00:00
igneum-labs
62d2f939a7
Merge remote-tracking branch 'build/master' into reference-apps
2026-10-08 15:49:35 +00:00
igneum-labs
f244a76698
Igneum 2.0, compatibility as a product deliverable: /compatibility (docs/build/compatibility.md rendered by the builder programme's shell, its rows from tools/reference-apps/compat/results.json), the runner tools/reference-apps/compat/run.mjs with every row as a test against the devnet (representative contracts, wallet fee estimation, indexing, failed transactions, receipts, application assumptions, the measured differences: block context, randomness, two-dimensional fees), every row served untested until the 2.0 devnet answers; the positioning line and the three boundaries on /light, /receipt and /oracle; the Build group's nav entry
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:49:34 +00:00
igneum-labs
9915082b41
docs: class v6 coexistence rows on an RTX 3060 12 GB and an RTX 4060 8 GB (5.5 GiB miner beside the compressed shard prover, verbatim run-log rows, the reconciliation with the 6 October 8.9 GB row and the 16 GB rule)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:48:20 +00:00
igneum-labs
b2faca79dc
Merge box master 9f1c40b6 into enforced-proving (the public ledger regenerated; the fast-time case reads paid shards only)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:48:09 +00:00
igneum-labs
919293896e
Class v6 10.0h and 10.0i: the sentence served at 18:30 on the tightened bracket (2.5x to 3.0x a node ahead, 2.1x to 2.6x node-for-node; the placed gated row at about 18:30 narrows it)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:47:22 +00:00
igneum-labs
8e1a7cf285
docs/design: pool vote-key commitment (Igneum 2.0 Pools, bullet 1): the key committed in the header under proof of work, the share and job naming it, payment aggregation separate and verifiable, the attack list with custody by consent as the survivor, costs, the pool lane migration note, open questions
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:46:18 +00:00
igneum-labs
ddb0976351
Merge the mirror's master into counter-asic-4 before the D4 landing
...
# Conflicts:
# site/economics.html
2026-10-08 15:46:02 +00:00
igneum-labs
9f1c40b683
docs: the paid pilot (Igneum 2.0, proving ladder step two): customer profile from the code, three ranked candidate classes with public prices, the pilot shape and pass condition, the missing-pipeline checklist, the outreach brief
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:45:41 +00:00
igneum-labs
984aa603d8
Igneum 2.0 D4: the tip-share discrepancy resolved (the tip whole to the block, O-5.7 closed at zero; the provers paid by the congestion-priced proving base fee, 90 percent to the block's pool and 10 percent burned; the burn listed separately; the cap and no development tax untouched); spec 5.1 to 5.3, the economics page, the code pinned
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:45:00 +00:00
igneum-labs
d846bfe5d8
Merge class-v6-connected-docs e6146368 into master (gate: green on e6146368, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:43:21 +00:00
igneum-labs
b02a141d1f
Counter ASIC 3.0 status: Igneum 2.0 decided (the reference and the plan with the pins), the drain of every box read back and accepted, the 2.0 map by lane and pin, the census sheet (fold PASS, rw PASS), the window set, the research lane's three close landings, the mixed FP32 and connected-state kills, the attack pass's partial and its pool design assignment, the site reset on main's three clocks
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:42:28 +00:00
igneum-labs
050f1213f7
Enforced proving: the measured verify cost in the spec (0.668 to 0.710 s a record on one EPYC core, about 30 MB a verify); the fast-time case forges outside the exclusive window and hashes the bytes it submits
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:40:41 +00:00
igneum-labs
4a3fbecd88
Class v6 10.0p: the 8 GB and 12 GB tiers hold at the 5.5 GiB floor (an exact 4060 and 3060, measured); the window free per load on both; proving beside mining time-shares under 16 GB
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:40:40 +00:00
igneum-labs
761ec73de0
Class v6 10.0o: the mixed FP32 candidate killed (determinism proved on CUDA; the determinism tax is the whole economics, +15 to +26 percent on every card for +7 percent of chip edge; the exponent-byte bias a new instrument reading)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:38:47 +00:00
igneum-labs
5405dd9f20
Merge counter-asic-4 03029526 into master (gate: green on 03029526, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:37:40 +00:00
igneum-labs
9f490a5b8c
Merge class-v6-adversary-docs d1d29460 into master (gate: green on d1d29460, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:35:33 +00:00
igneum-labs
c67e9dae42
Merge release-manifest-8 d5ba3c3a into master (gate: green on d5ba3c3a, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 15:32:32 +00:00
igneum-labs
03029526da
Merge the mirror's master into counter-asic-4 before the third landing
2026-10-08 15:28:43 +00:00
igneum-labs
e6146368b5
Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
0647e8976c
Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
e9e88cf4f2
Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
2026-10-08 15:28:38 +00:00
igneum-labs
d1d2946038
multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
30ba24bea1
multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
17b9901b67
Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:27:51 +00:00
igneum-labs
e0cfa64f17
Merge ca3-coord-record cacdb438 into master (gate: green on cacdb438, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:26:45 +00:00
igneum-labs
883dcacf5e
Public ledger regenerated for the P21 and P22 rows (enforced proving)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:26:34 +00:00
igneum-labs
d5ba3c3a90
Merge the box master 31496f4e into release-manifest-8 (the evidence page rebuilt)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:25:22 +00:00
igneum-labs
cacdb438ac
Counter ASIC 3.0 status: the amended close on master ( 31496f4e), the adversary core rows (k 0.40 node for node), the connected-state rows (the window under 1 percent on the card), every platform on 0.3.26, the enforced-proving lane's line and route, the class v5 lane's kit item, the gate kills by name found and named
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:19:19 +00:00
igneum-labs
ed4e162100
Enforced proving docs: UK clock times (the identity grep refuses the timezone word in the public export)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:19:14 +00:00
igneum-labs
d94c69e460
Chip text: the third review's claim statement served verbatim above the sentence on every copy; rotation named an optional improvement, not the mechanism; no threshold as the economic headline (the coexistence model owed); X35 pin added
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:18:17 +00:00
igneum-labs
a39ab8ecc3
Merge the mirror's master into counter-asic-4 before the second landing
2026-10-08 15:17:45 +00:00
igneum-labs
3b78cd5dbe
Class v6 10.0l: the third external review (the objective durable GPU competitiveness; the definition on a reference population with cost per accepted unit of work; the coexistence model replaces the capex wall, a new document by 21:00; the claim statement above the served sentence, rotation an optional improvement)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:16:26 +00:00
igneum-labs
bfb8ce9e21
Enforced proving spec: the 16:15 BST suite results on build-2
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:15:58 +00:00
igneum-labs
16608d4d02
Class v6 10.0k: the connected-state lane's first rows (63 of 64 registers necessary; the window +0.6 percent on a 5090 at stock; censuses as well as v5; the narrow per-step chain names the two-level-file re-optimisation)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:15:18 +00:00
igneum-labs
c43880ef41
Class v6 10.0j (after the landing): the multi-family adversary lane's macro-window core (k 0.40 node-for-node; the window knob buys the card nothing against a macro file) carried beside the k lane's model as a disagreement the placed rows settle
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:13:27 +00:00
