igneum-labs
9954e451e3
Merge binding-review c2459ae0 into master (gate: green on c2459ae0, recorded by tools/ci/pre-push.sh; the full gate runs in CI on this merge)
2026-10-08 17:19:14 +00:00
igneum-labs
96c086371f
Merge class-v6-connected-docs-2 1c33395a into master (gate: green on 1c33395a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 17:15:34 +00:00
igneum-labs
c2459ae08f
docs/analysis: binding review of template, nonce, work and result (Igneum 2.0 register row): the chain of bindings from the code, the twelve reuse paths with their cost and rule, the measured lines, five open questions (epoch-seed VDF not in the node line, the day keyed on the timestamp)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 17:11:56 +00:00
igneum-labs
a74395f238
Class v6 census, lane 2: the six-pack sheet (fold, rw, foldrw, win, all PASS; rw2 FAIL on F8), the harness, the commands, the instrument's definition, the faults fixed, every pack's harness outputs under logs/census-packs
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 25098c1a2 (25098c1a276d80987262eda59a7f1beef8cd6ba4) for the box mirror master
2026-10-08 17:08:39 +00:00
igneum-labs
33af70442e
Merge class-v6-family-gate 8ce0956b into master (gate: green on 8ce0956b, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 17:01:32 +00:00
igneum-labs
1c33395a75
Connected state: the PC 1 lock row (the window +1.6 percent of energy per hash at the 1,300 lock, +5.9 unlocked; the score re-read at x 1.016: 1.08x node-for-node, 1.07x a node ahead; the verdict unchanged)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 042f5ba98042f5ba98a
2026-10-08 16:57:26 +00:00
igneum-labs
8ce0956b48
Class v6 family gate, amendment 6.9: the best-mix genesis table's acceptance for D1 (PASS: r 0.33 and 0.19 at widths 4 and 1, 0 exhausted, the floors at the width's cost, attack-f8 at the exact table 0 hot sets and 0 over 1.2x at 2^20; the exact or = 0 attempts rows owed with build-3 unreachable); the Igneum 2.0 pause recorded
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 16:54:11 +00:00
igneum-labs
04bda082fd
Merge counter-asic-4-docs-2 3d3ad22e into master (gate: green on 3d3ad22e, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 16:33:46 +00:00
igneum-labs
3d3ad22e89
Merge box/master ea27fdcd into counter-asic-4-docs-2 (the export list: both additions kept, operator-simulation.md and the pre-2.0 ledger copy)
2026-10-08 16:27:51 +00:00
igneum-labs
c3b05215a5
Merge class-v6-adversary-docs-2 0db43b65 into master (gate: green on 0db43b65, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 16:27:23 +00:00
igneum-labs
5087e14b8c
Merge box/master 33ffe78c into counter-asic-4-docs-2 (the export list: both additions kept, operator-simulation.md and the proving-pipeline record)
2026-10-08 16:14:15 +00:00
igneum-labs
0db43b6578
multi-family adversary: clock stamps read from the Mac
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 10b901a46 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:22 +00:00
igneum-labs
23f3073676
multi-family adversary: the placed full-core rows, the board and D2(b) at the placed energy, the transition matrix, the one page
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7e715b50b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:21 +00:00
igneum-labs
6b6c5e783e
multi-family adversary: the placed board figures corrected to the model's output
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2b30cfd0b (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master
2026-10-08 16:10:21 +00:00
igneum-labs
a0abb94cdc
multi-family adversary: the placed genesis core rows, the 32-lane genesis row, the board at the placed energy, the D2(b) harness and its rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 90001aae6 (10b901a46934c24ce9b44c74bc6fd4db7c40d2b0) for the box mirror master; left on the branch: tools/chip-model/mf/flow/d2b.py tools/chip-model/mf/results/board-placed-base-n5.md tools/chip-model/mf/results/board-placed-full-n3.md tools/chip-model/mf/results/board-placed-full-n5.md tools/chip-model/mf/results/d2b-n3.md tools/chip-model/mf/results/d2b-n5.md tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.json tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/1_synth.log tools/chip-model/mf/results/out/mf32base/logs/asap7/mf32base/base/power_synth.log tools/chip-model/mf/results/out/mf32base/reports/asap7/mf32base/base/synth_stat.txt tools/chip-model/mf/results/out/mf32base/results/asap7/mf32base/base/mem.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/6_report.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power.log tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/VDD.rpt tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/6_report.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power.log tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/2_floorplan_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_detailed_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_global_place.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/3_resizer.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/4_cts_final.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_global_route.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/5_route_drc.rpt-5.rpt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/VDD.rpt tools/chip-model/mf/results/sim/mf32base/gl2sim.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf32base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md
2026-10-08 16:10:21 +00:00
igneum-labs
12ba299bd0
Class v6 mixed FP32: section 6.1, the k lane's synthesised FP32 rows (FMA lane 3.4 pJ at N3, k 0.65 on the unit, 0.15 blended at the lock); the score 3.2x / 3.5x; the verdict stands
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e6d52e198 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
2026-10-08 16:07:14 +00:00
igneum-labs
befc1121cd
Class v6 mixed FP32: the final rows (fp24 CPU 2^24 equal on three cards, the quiet-core verifier, the 4090's fp24 and v5-genesis rows), every pod record
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 255be0264 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master
2026-10-08 16:07:14 +00:00
igneum-labs
beaf234e29
Class v6 mixed FP32: the rows (census on build-4, the stock 5090, the 4090 and the capped 5090, the CPU-vs-CUDA fingerprints), the chip-side reading, KILL on the GPU budget and the full-board score; the pod scripts and the records
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a324c941e (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: tools/attack/v6-census/pod-bench.sh tools/attack/v6-census/pod-census.sh tools/attack/v6-census/sampler-summ.py
2026-10-08 16:07:13 +00:00
igneum-labs
2a7d8f9a34
Class v6 mixed resource: the FP32 candidate behind IGNEUM_FG_FP32 (fadd, fmul, ffma, fcvt in the shadow draw, xor-injected, the fp_in operand rule), the determinism rules in the emitter for CUDA, OpenCL and Metal, the CPU reference, the fingerprint subcommand, the report skeleton
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c19e19b91 (e6d52e19845cdffe5bb24f26e6eeda400f1ef4a8) for the box mirror master; left on the branch: igneum-pow/src/accept.rs igneum-pow/src/emit.rs igneum-pow/src/generator.rs igneum-pow/src/main.rs igneum-pow/src/verify.rs igneum-pow/tests/mixer.rs
2026-10-08 16:07:12 +00:00
igneum-labs
143c514786
Igneum 2.0 D4: the placed energies (the complete GDDR7 machine 1.6x node-for-node, 1.9x a node ahead; the hybrid 2.4x / 2.9x; the die 2.4x / 3.3x; per-dollar unchanged) and the three chips scored at them, no verdict changed; the served energy sentence on them; the proving-payment pin in the code behind its constant, the guest's mirror owed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only copy of counter-asic-4 df7c85c1c (its delta over master 919293896
2026-10-08 16:05:40 +00:00
igneum-labs
714cf36138
docs: Devnet 3 proving pipeline end to end, 8 October 2026 (the fleet lane's document, landed by the research-landing hand on the coordinator's word)
...
The document as it stood in the fleet lane's worktree at 16:46:43 BST (the same second as gpu-fleet 9991d7ce, which carried
tools/fleet/pipeline-collect.py and left this file untracked). Documents only; the collector stays on gpu-fleet.
2026-10-08 15:51:26 +00:00
igneum-labs
9915082b41
docs: class v6 coexistence rows on an RTX 3060 12 GB and an RTX 4060 8 GB (5.5 GiB miner beside the compressed shard prover, verbatim run-log rows, the reconciliation with the 6 October 8.9 GB row and the 16 GB rule)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:48:20 +00:00
igneum-labs
d846bfe5d8
Merge class-v6-connected-docs e6146368 into master (gate: green on e6146368, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:43:21 +00:00
igneum-labs
5405dd9f20
Merge counter-asic-4 03029526 into master (gate: green on 03029526, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 15:37:40 +00:00
igneum-labs
e6146368b5
Connected state: the chip rows (the k lane's re-optimised core: 4.4 pJ per lane-op at N5, k 0.71 at the lock), the score (3.3x node-for-node, 3.6x a node ahead; the window moves the chip's edge 1.10x against a 1.25x gate), verdict KILL as a class, what is kept and what v7 tests
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ccd2a6fe (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
0647e8976c
Connected state: every GPU row at stock (5090 and 4090, harness and kit worker), the census TSVs and bench logs under logs/connected; the chip row, the score and the lock row still open
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of aa6f60af8 (6ccd2a6fe) for the box mirror master
2026-10-08 15:28:39 +00:00
igneum-labs
e9e88cf4f2
Connected state: the header-bound kernel in the pack (the NVRTC worker loads it: check PASS on a 5090), docs/analysis/class-v6/connected-state.md with the structure, the liveness rows, the census rows and the first GPU rows (the 4090, worker, lock and chip rows to follow)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ecf98c0dd (6ccd2a6fe) for the box mirror master; left on the branch: igneum-pow/src/connected.rs igneum-pow/src/main.rs
2026-10-08 15:28:38 +00:00
igneum-labs
d1d2946038
multi-family adversary: the routed clock relaxation, the tier table, the statement, the data-local cost model and the dataset comparison
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2db208912 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
30ba24bea1
multi-family adversary: the mf core RTL (SRAM window and imem, every bank entry, operand isolation, 5-phase slot), the flow, the collector, the board and hash models, the first rows (synthesis only, 8 lanes, full and base)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of a807edd84 (2db208912e5fc0656930aaabd7db74ec2a68ca8e) for the box mirror master; left on the branch: tools/chip-model/mf/Makefile tools/chip-model/mf/flow/board.py tools/chip-model/mf/flow/collect.py tools/chip-model/mf/flow/gl2sim.sh tools/chip-model/mf/flow/hash.py tools/chip-model/mf/flow/mf32base.mk tools/chip-model/mf/flow/mf32base.sdc tools/chip-model/mf/flow/mf32full.mk tools/chip-model/mf/flow/mf32full.sdc tools/chip-model/mf/flow/mf8base.mk tools/chip-model/mf/flow/mf8base.sdc tools/chip-model/mf/flow/mf8full.mk tools/chip-model/mf/flow/mf8full.sdc tools/chip-model/mf/flow/power.tcl tools/chip-model/mf/flow/sim.sh tools/chip-model/mf/results/board-mf8full-n3.md tools/chip-model/mf/results/board-mf8full-n5.md tools/chip-model/mf/results/hash-mf8base.md tools/chip-model/mf/results/hash-mf8full.md tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.json tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/1_synth.log tools/chip-model/mf/results/out/mf8base/logs/asap7/mf8base/base/power_synth.log tools/chip-model/mf/results/out/mf8base/objects/asap7/mf8base/base/copyright.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_check.txt tools/chip-model/mf/results/out/mf8base/reports/asap7/mf8base/base/synth_stat.txt tools/chip-model/mf/results/out/mf8base/results/asap7/mf8base/base/mem.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.json tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/1_synth.log tools/chip-model/mf/results/out/mf8full/logs/asap7/mf8full/base/power_synth.log tools/chip-model/mf/results/out/mf8full/objects/asap7/mf8full/base/copyright.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_check.txt tools/chip-model/mf/results/out/mf8full/reports/asap7/mf8full/base/synth_stat.txt tools/chip-model/mf/results/out/mf8full/results/asap7/mf8full/base/mem.json tools/chip-model/mf/results/sim/mf8base/gl2sim.log tools/chip-model/mf/results/sim/mf8base/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_add_s500.log tools/chip-model/mf/results/sim/mf8base/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_load_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8base/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_or_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8base/sim_xor_s500.log tools/chip-model/mf/results/sim/mf8full/gl2sim.log tools/chip-model/mf/results/sim/mf8full/sim_add_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_add_s500.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_andn_s500.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_bfe_s500.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_clz_s500.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_fwd_s500.log tools/chip-model/mf/results/sim/mf8full/sim_load_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_load_s500.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_lop3_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mad_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix1_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix2_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix64_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mix_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixld_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mixw4_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mm8_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mul_s500.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_mulhi_s500.log tools/chip-model/mf/results/sim/mf8full/sim_or_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_or_s500.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_popc_s500.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_prmt_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_rotr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sel_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shfla_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shl_s500.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_shr_s500.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_sub_s500.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s2000.log tools/chip-model/mf/results/sim/mf8full/sim_xor_s500.log tools/chip-model/mf/results/table.csv tools/chip-model/mf/results/table.md tools/chip-model/mf/rtl/core_mf.v tools/chip-model/mf/rtl/mf32base.v tools/chip-model/mf/rtl/mf32full.v tools/chip-model/mf/rtl/mf8base.v tools/chip-model/mf/rtl/mf8full.v tools/chip-model/mf/tb/sram_models.v tools/chip-model/mf/tb/tb_mf32base.v tools/chip-model/mf/tb/tb_mf32full.v tools/chip-model/mf/tb/tb_mf8base.v tools/chip-model/mf/tb/tb_mf8full.v tools/chip-model/mf/tb/tb_mf_common.vh
2026-10-08 15:28:35 +00:00
igneum-labs
17b9901b67
Class v6 10.0m and 10.0n: the multi-family adversary's whole-machine rows (1.8x the 5090 node-for-node, the bank zero obsolescence credit, capex the larger half of the edge); the coexistence model landed (the board passes six conditions, the die fails five once sunk); the three statements re-read; the connected-state class killed; the window under 1 percent measured
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 15:27:51 +00:00
igneum-labs
03b7bf05a1
Class v6 floor lane 4: the RX 7600 (8 GB) measured on PC 1 (13.88 MH/s at 113 W, 8.14 microjoules, the card-in job 15:50 UK) added to the tiers table and the AMD estimates re-based on it; 10 of 10 on build-3
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 394da98a9394da98a91
2026-10-08 15:04:38 +00:00
igneum-labs
999fec1519
Merge class-v6-floor-denominator-docs-2 8384bfc7 into master (gate: green on 8384bfc7, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 15:03:47 +00:00
igneum-labs
8384bfc795
Class v6 floor lane 4: section 3 amendment, the memory clock is not a lever (floor lane 1's PC 1 ladder at the 1,300 lock: two driver states, the half-rate state costs 43 percent of rate for 37 percent of watts)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6ef2a4ba86ef2a4ba86
2026-10-08 14:51:28 +00:00
igneum-labs
308aa4a7da
Class v6 floor lane 1: sm-sparse.md amendment, the memory-clock ladder on PC 1 at the 1,300 lock (the 5090's PHY has two states, 13,801 and 7,001 MHz; the half-rate state loses 43 percent of rate for 37 percent of watts, energy per hash up 12 percent on class v3 and 5 on class v4: the memory clock is not a lever; the memory path read as 11 nJ per read at the margin, equal to the DRAM chase probes)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6d666ce9d6d666ce9d6
2026-10-08 14:49:41 +00:00
igneum-labs
3958f0d29c
Merge class-v6-family-gate 4eca18c3 into master (gate: green on 4eca18c3, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:46:07 +00:00
igneum-labs
513bca993b
Merge class-v6-invention f812e800 into master (gate: green on f812e800, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:40:15 +00:00
igneum-labs
4eca18c34e
Class v6 family gate, the full report: point B's row (0 hot sets at the 64 shape, 5 over 1.2x, the floor refusing 1 of 64) and the 18:00 amendment line (the best-mix genesis table under test)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:40:03 +00:00
igneum-labs
bcdce0f120
Merge class-v6-floor-k-docs e0a81517 into master (gate: green on e0a81517, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 14:39:16 +00:00
igneum-labs
781fc1b549
Merge class-v6-family-gate 72b58cec into master (gate: green on 72b58cec, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 14:38:28 +00:00
igneum-labs
e0a81517b5
shadow-k: the 32-lane core (5.55 pJ per lane-op, k 0.45 at the lock), the shuffle row (1.24 pJ, k 0.021), the mix optimiser's best corner
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bfccc26edbfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
b039ded194
shadow-k: row (2'), the 32-lane 16-register core (4.2 pJ per lane-op ASAP7, k 0.34 at the lock at N3)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3e2a202febfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
f5e1045318
shadow-k: the node column (node-for-node the base core is k 0.78 and the GDDR7 board 2.4x at the lock)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 05275ca6abfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
44bb0b406d
shadow-k: the design sweep (64 registers k 0.78, 1,024 imem 0.97 as built and about 0.6 with SRAM, select tree 0.55), the sweep variants' RTL and configs, the synthesis-row driver, the steady-state solve in the collector
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 036c1adedbfccc26ed4
2026-10-08 14:32:45 +00:00
igneum-labs
069d4f032f
shadow-k: the ranking and the mixed draw (the census lane's re-weight on the unit floors and the core)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e92167057bfccc26ed4
2026-10-08 14:32:44 +00:00
igneum-labs
a97605d7c0
shadow-k: the programmable core's synthesis-only row (6.9 pJ per lane-op ASAP7, k 0.56 at the lock at N3), the edge table in the absolute convention, the lease-routed Makefile
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ed7d2626dbfccc26ed4
2026-10-08 14:32:44 +00:00
igneum-labs
7784bdc7d1
chip-model: shadow-k collector, mix optimiser, edge rows; the report's method sections
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6fab785c5bfccc26ed4
2026-10-08 14:32:43 +00:00
igneum-labs
72b58cec74
Class v6 family gate, the full report (16:30 BST): 38,000 drawn eras, the lossy-share curve per shape (the exhaustion a 256-shape interaction, about 6x the independent estimate), the pre-floor spread per width and the width-4 floor decision (0.995 kept at its measured cost), the two live-dataset censuses (128 band epochs: 2 hot sets at the 256 shape, both refused by the class v5 floor), the seven known-failed seeds through the sigma form (one value-level test, the bucket bound retired into the bit read; p212 and p225 at bit R), the x4, x8 and x16 verifier rows (x16 outside the band on the 10 ms gate), the band stratum's gate records as JSON lines; every row's log under logs/
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:31:37 +00:00
igneum-labs
f812e800ee
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 14:31:15 +00:00
igneum-labs
c6f999bd6b
Class v6 invention: the drawn-era F8-form read of the sound per-load form (not clean: 7 of 64 seeds with a site under the 0.995 floor, min 0.940, one item at 1,938 reads; the per-load class runs no (c'''), so the floor joins G5-draw with the seven seeds as the known-failed case; the uniform-control share column labelled as not F8's number), the harness's era option
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 14:31:14 +00:00
igneum-labs
3471075c32
Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c8e8b82adc8e8b82add
2026-10-08 14:05:41 +00:00
