docs/analysis/class-v6/history.md 4.2a: main's 6, 10 and 14 GiB steps checked against every tier's room under the standing 75 percent budget rule (the card-lifetime method, the bench table's 32 measured consumer cards as the population): 6 GiB does not fit the 8 GB tier under the rule (78 to 82 percent of the card; it fits only at a headless-rig reading of about 85 percent), 10 GiB retires the 10, 11 and 12 GB tiers and the Apple 16 GB laptop at year 2, 14 GiB retires the 16 GB tier at year 4, leaving 24 GB and above; beside it the schedule that drops the tiers in the order main named (5.5 GiB at the v6 epoch, 8 GiB at two years, 11 GiB at four) with the year each tier falls and its share of the measured cards (6 GB 3 percent at day one; 8 GB plus the 10 GB RTX 3080 plus Apple 16 GB 25 percent at year 2; 12 GB 22 percent at year 4; 16 GB 28 percent at the 16 GiB step; 24 GB and above hold). Against the chips: the hybrid-bonded or soldered chip sized at launch dies at the first step it cannot carry (the E3's shape, 20 to 27 months) but a maker reading a public consensus field sizes to the step it wants (USD 160 more of GDDR7 on a USD 470 part; about 3x the memory die area for the Jasminer shape); the f = 1 GDDR7 chip's 32 GB board pays USD 0 through 16 GiB and keeps 5.1x; the SRAM store pays capex only at the cache doubling (USD 46 to 111 per die) and keeps 0.92x and 1.86x. The fleet's hashrate-weighted card census is owed. The arithmetic is checked by script against the card-lifetime working sets.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/analysis/class-v6/history.md: layer 2's open ceiling question replaced by the synthesis lane's resolution (the per-year ceiling as layer 2's first constant, the schedule's power-of-two step for the year; the state brings a step forward and never adds one), with the Ethereum-state figure kept as the reason the ceiling exists; the read-width rank reworded on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max; the band is {4 B, 16 B}, nothing wider); the Jasminer X4 finding cross-cited to lane B's hybrid-bonded DRAM row (hardware-future.md 4.4, 13x to 17x modelled) as that row's shipped precedent at 5x on a planar node; the header records the 11:26 UK landing (eb71eaf3). No number changes.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/analysis/class-v6/history.md: 21 chip rows by mechanism (what each chip specialised, what the design missed, the timeline, the v6 layer, closed or not, the per-joule number); in-depth sections for Ethash (the E3's DDR3, Linzhi's 4.4 GB beside 64 compute units, the Jasminer X4's DRAM hybrid-bonded onto a 40/45 nm die, the E9), ProgPoW (the Least Authority and Rao audits read from the PDFs, Kik, Linzhi's claim, the adopters), RandomX (the X5's RISC-V board at 1.46x, the X9 announced December 2025 and withdrawn May 2026 with zero units, RandomX v2 released 25 March 2026 with activation pending, the Qubic episode as the detector's lesson), Cuckoo (the GRN1's 512 MiB SRAM die, the G32, the iPollo G1, the 2025 bounty), Equihash (the Z9's single die, the Fudan parameter-following design), Scrypt and Argon2 (the BM1485's on-die scratchpads, Percival's lookup gap, MTP), the no-chip hashes, kHeavyHash, CryptoNight, X16R, Lyra2REv2, the compute rows. The four layers against the history layer by layer, with the E3's death dates, Autolykos's growth rule, the design-cycle and FPGA-compile clocks, and the honest verdict that the stored-dataset chip (class C) is not closed by any layer: 5.1x per joule at zero premium, 2.1x with the shadow at k = 1. Two corrections to the 5 October file (the X9, RandomX v2) and one claim marked unverified (the 5x fork-surviving chip). First cut for 15:00 UK; the full report by 09:00 UK on 9 October.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
docs/analysis/class-v6/hardware-future.md: one table over PIM and PNM (HBM-PIM, AiM, LPDDR5X-PIM, UPMEM), HBM3E, HBM4 and the custom HBM4E base die, fine-grained DRAM on logic, LPDDR6, 3D DRAM, RLDRAM 3 and Folded Banks, FPGA with HBM2e, wafer-scale, CXL, optical I/O, chiplets and UCIe, and SRAM at N2: energy per dependent read, latency, cost per GB, availability to a non-hyperscaler, the k_read and shadow k bands, the edge per joule at zero shadow against the 5090 and the M5 Max, and the one layer of the four that blunts each with a number. The three findings: a 2 GiB SRAM full store on one N2 reticle is the strongest five-year chip (13x to 17x per joule, about USD 0.3 per MH/s) and no layer reaches it (layer 2 moves its capex, not its joules; the shadow at k = 0.5 holds 4.8x); per-bank PIM is blind (1.6 percent of reads in-bank at 2 GiB) and the custom HBM4E base die is the f = 1 chip with its controller in the stack (6.5x to 14x), untouched by layers 1 to 4; the denominator is the wrong card (the M5 Max at 0.78 microjoules halves to thirds every chip edge). Section 5 carries the k bands for the research lane's chip rows; section 7 the four decisions with defaults and deadlines; section 9 the sources with URLs and dates. tools/ci/export-exclude.txt: docs/analysis/class-v6 is research, not public export.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
