igneum-labs 697fdd23a1 Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited ... docs/analysis/class-v6/history.md: layer 2's open ceiling question replaced by the synthesis lane's resolution (the per-year ceiling as layer 2's first constant, the schedule's power-of-two step for the year; the state brings a step forward and never adds one), with the Ethereum-state figure kept as the reason the ceiling exists; the read-width rank reworded on the measured warrant (w16 latency-bound within 2.7 percent on the 5090 and the 9070 XT, within 1 percent on the M5 Max; the band is {4 B, 16 B}, nothing wider); the Jasminer X4 finding cross-cited to lane B's hybrid-bonded DRAM row (hardware-future.md 4.4, 13x to 17x modelled) as that row's shipped precedent at 5x on a planar node; the header records the 11:26 UK landing (eb71eaf3). No number changes. Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 10:29:17 +00:00
..
history.md	Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited	2026-10-08 10:29:17 +00:00