igneum-labs 5abdf18115 Merge build/master into class-v6-invention (the export-exclude line for docs/analysis/class-v6 kept once, the history lane's wording) ... Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>		2026-10-08 10:40:05 +00:00
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logs	Class v6 invention lane: first cut of docs/analysis/class-v6/invention.md (every candidate layer beyond the four with its paragraph, known-failed harness run and chip row; the sound per-load shadow measured today: 0.927 rejection per candidate on 256 seeds, verifier 8.3 to 8.8 ms loaded, two packs exported; the per-load prototype's era-window instrument fault found; the ranked list: per-load placement, register width, warp-uniform block selection, the reserve's order), the census script and its two TSVs	2026-10-08 10:20:52 +00:00
hardware-future.md	Class v6 research lane B: the hardware future, five years out (first cut and the full report in one file)	2026-10-08 10:17:50 +00:00
history.md	Class v6 history lane, revision 2: the synthesis lane's reading of the six items folded in, lane B's hardware file cross-cited	2026-10-08 10:29:17 +00:00
invention.md	Class v6 invention lane: first cut of docs/analysis/class-v6/invention.md (every candidate layer beyond the four with its paragraph, known-failed harness run and chip row; the sound per-load shadow measured today: 0.927 rejection per candidate on 256 seeds, verifier 8.3 to 8.8 ms loaded, two packs exported; the per-load prototype's era-window instrument fault found; the ranked list: per-load placement, register width, warp-uniform block selection, the reserve's order), the census script and its two TSVs	2026-10-08 10:20:52 +00:00