igneum-labs
4b5f18859a
Class v6 floor lane 1: sm-sparse.md, the PC 1 table deduplicated (the job's five-minute uploads repeat earlier lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 661522a8f661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
8843b1d661
Class v6 floor lane 1: sm-sparse.md with PC 1's ladder (class v3 at stock agrees with the rented ladder at every rung, 3 to 3.5 percent at best; class v4 at the 1,300 lock needs every SM; the class v3 lock ladder partial and re-run owed; the memory-clock ladder queued)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1172d7a1661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
e6696d2680
Class v6 floor lane 1: sm-sparse.md, the decomposition rows (the awake floor 120 to 139 W on every card, the memory path 10 to 13 nJ per dependent read against the devices' modelled 2.0 or 1.2), the 5090's clean self-tune rows (sp37 of 170 at 2.5 percent under base on class v3, nothing on class v4), every pod destroyed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 95909a47e661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
7323a1abbc
Class v6 floor lane 1: docs/analysis/class-v6/floor/sm-sparse.md, the first full draft (four rented 5090s, the 4090 and the H100 at stock: the SM count is not the lever, 1 to 4 percent at best; the knee 43 of 170 SMs on class v3 at the 99 percent hold; the H100 decomposition; the self-tune rows; PC 1's lock and memory-clock ladders owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 56d422c33661522a8f8
2026-10-08 13:49:29 +00:00
igneum-labs
46d0f96aa5
Merge ca3-v4-amend bf60ef92 into master (gate: green on bf60ef92, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 13:33:02 +00:00
igneum-labs
9d63a214b1
Merge class-v6-floor-invention-docs-2 99aa9729 into master (gate: green on 99aa9729, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:23:22 +00:00
igneum-labs
8fed9a23ca
Merge class-v6-census-docs a5cc338a into master (gate: green on a5cc338a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:16:21 +00:00
igneum-labs
a1004fdcae
Merge ca3-coord-record 82256559 into master (gate: green on 82256559, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 13:14:03 +00:00
igneum-labs
3522962340
ledger AP-F8-1: the F8-256 attributions p212 (the bucket class at one narrow-window site) and p225 (the value-level class); the one-one-bit prediction a hint, the by-site histogram the attribution; the consequence for the next class's bucket and value-level tests
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:13:38 +00:00
igneum-labs
99aa972994
Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 43302b4b243302b4b29
2026-10-08 13:11:56 +00:00
igneum-labs
a5cc338abb
Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
844fa7ec50
Class v6 census: W = 16 and the op-mix re-weight through the sub-version 3 rules (docs/analysis/class-v6/census-w16-mix.md): every candidate 256 of 256 without an era and 256 of 256 across eras 0 to 7 with the window-bit refusal on, 0 exhausted; W = 16 removes the product's low bits from the address by construction; the re-weight lowers r to 0.41 and raises the stride-bit refusals; the rows, logs, scripts and commands
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d20eb04bd (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
8225655999
Counter ASIC 3.0 status: the 0.3.25 pin named c9ad753a at 14:08 (every gate green, the fast-time PASS on the freeze-paired pair, the v5 read-back PASS, the FAIL seed re-read at the exact freeze, the minute 14:30 to 14:40, the fleet's census gate at 28,462), the testnet re-cut 0d05e795, the F8-256 attributions (p212 the bucket tail, p225 the value-level class), lane C's drawn-era re-read, the floor-sram and floor-invention landings, the PC 1 order and the 7600 card-in plan, the chain-id deploys
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:07:05 +00:00
igneum-labs
860e6d6f3e
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 13:04:40 +00:00
igneum-labs
aee75e737f
Class v6 invention: the drawn-era re-read on the fixed instrument b6799782 (the sound per-load form 254 of 256 seeds at 0.819 per candidate under eras, 234 of 256 at 0.927 no-era; the 16 x 27 form dead on both; class v4's shape at sub-version 3's 0.67 on the same binary), the two TSVs, sections 0, 2.1, 3.3 and 4 updated
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:04:39 +00:00
igneum-labs
e266d8a376
Merge class-v6-floor-invention-docs ca381a45 into master (gate: green on ca381a45, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
53f1e65b7f
Merge class-v6-floor-sram-docs 8c201157 into master (gate: green on 8c201157, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:55:14 +00:00
igneum-labs
de2a7e43e2
Merge ca3-coord-record bbb7bfcb into master (gate: green on bbb7bfcb, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:54:19 +00:00
igneum-labs
bbb7bfcb32
Counter ASIC 3.0 status: the STOP on the pin at 13:29 (the fast-time pairing FAIL on an attempt-3 seed), its cause (the 0.3.25 worktree's pre-freeze igneum-pow copy under the paths override; the live network fingerprinted ON the freeze, cbc5bd0a), rule 19 (the build-time fingerprint refusal, packaging/pow-freeze.txt), the rebuilt shas 6ccaf9e9 and c9ad753a with the 90,000 ceiling and digest 2066aa57, the testnet re-cut 3ffcf83b, lane D's fan-out, the attack pass's twelve-chunk split, the explorer re-pointed at node1-dn3 and the 4464 chain id served, the counter-asic-4 docs landing 2db1ba3b
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:47:21 +00:00
igneum-labs
b891188261
Merge build/master into build-programme (the 4464 fact landed on both sides; this branch's wording and the second PASS line kept; the pages rebuilt)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:46:10 +00:00
igneum-labs
ca381a45f7
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0a8c7883e0a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
9083c305ad
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6e59abcb30a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
32c0796e76
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ef79c5e710a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
d78167db48
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cf602a0310a8c7883e9
2026-10-08 12:45:34 +00:00
igneum-labs
9a794fa2d5
Merge spec-accept-23 8b9fb311 into master (gate: green on 8b9fb311, recorded by tools/ci/pre-push.sh; landed on the box mirror)
2026-10-08 12:39:06 +00:00
igneum-labs
e15464ac58
Builder pages and faucet: Devnet 3 chain id 4464 since the class v5 floor (8 October 2026, 13:27 BST reading)
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- the faucet reads eth_chainId from its node on every send and in its status (a fixed id signed refused transactions once the floor crossed); FAUCET_CHAIN_ID is gone from the env; the faucet now reads node1-dn3's EVM, the node the public RPC fronts
- /build, /faucet, docs/build/first-contract.md, rpc.md and faucet.md: 4464 with the floor note, "read it, never fix it"
- a second walkthrough PASS on the 4464 chain from build-2 through the public RPC and faucet: Counter at block 29878, 12 s end to end
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:38:51 +00:00
igneum-labs
0d172a1af5
Merge dex-devnet3 319d63f4 into master (gate: green on 319d63f4, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:37:18 +00:00
igneum-labs
2db1ba3b07
Merge counter-asic-4-docs 0e23ca3f into master (gate: green on 0e23ca3f, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 12:35:08 +00:00
igneum-labs
8b9fb311c7
Devnet 3's chain id is 4464 since its class v5 floor crossed at DAA 68,400 on 8 October 2026 (eth_chainId 0x1170 on the public RPC): /metamask's devnet card, by-hand list, builders' snippet and one-click entry (chainId 0x1170, rpcUrls the public RPC, the explorer as block explorer; the local node named beside it), /faucet's two lines, the build pages' network table and walkthrough notes (docs/build), the nav pill's title on every page
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:32:22 +00:00
igneum-labs
319d63f4d9
Swap page: the chain id read from eth_chainId at load (4464 from the class v5 floor at DAA 68,400, 4463 before it), never fixed in the page; devnet-3.json notes both
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 12:30:51 +00:00
igneum-labs
8c201157c1
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
6a1943efc0
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
d057c76304
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
783f8fb664
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
de85e8f848
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
75430525e7
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
0e23ca3f89
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
270aebfc9b
Class v6: the last two 20:00 and 19:30 references pulled to the close
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 086411627 (counter-asic-4) for the box mirror master
2026-10-08 12:28:21 +00:00
igneum-labs
aae3ef5246
Class v6: the coordinator's 13:30 UK clocks (floor rows by 15:30, the synthesis on master by 16:30; the decision stays the founder's)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 931798ead
2026-10-08 12:28:21 +00:00
igneum-labs
ebe0467309
Class v6 10.1: the 5090 SM ladder on four rented hosts (the ceiling held to 43 of 170 SMs, the occupancy 1.3 to 3.9 percent at best), the H100 power decomposition, the fraction a chip cannot strip per tier
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f21f256a0
2026-10-08 12:28:21 +00:00
igneum-labs
105fa65d5e
Class v6 10.4: the honest denominator per tier (floor lane 4: the 16 GB Blackwell card at its knee is the honest NVIDIA floor, the 5080 2.06 measured; the only lever the operating point; the Ember tier table); the close table gains the 5080 row
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9629fd8db
2026-10-08 12:28:21 +00:00
igneum-labs
f2b13d062f
Class v6: 15:45 UK is the close (the founder's clock rule); later rows are amendments with their own time; no 20:00 event
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of b351f3fdf
2026-10-08 12:28:21 +00:00
igneum-labs
1cbf16eb37
Class v6: 10.1 SM-sparse measured dead on the 4090, H100 and 5090 (the residual is the clock domain); lane 3's close rows (the capex wall on the corrected project floor: USD 23 M and 340 M a year; W = 16 per chip; the SRAM rows on the synthesised core); 10.0 carries them with the 4090 and H100 rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 00890f9cc
2026-10-08 12:28:21 +00:00
igneum-labs
cbaa34c9ff
Class v6 10.0: the provisional close frame for 15:45 UK (one table, honest tier per row, chip per column, default k 0.5 and the floor k per cell; the capex wall's two thresholds; the served line in one sentence; the three class v6 changes), every missing row's default stated
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of f0146c2c2
2026-10-08 12:28:21 +00:00
igneum-labs
d4d2ac5791
Class v6: 10.5 invention lane's KEEP/KILL table (the second sector conditional on the w64 job; everything else killed with its number); 10.2 reframed as per-unit floors with the sequencer-core row owed as the headline and k 0.5 the default; lane D's complete lossy curve and ring-C progress in 5.1b
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 89ea64861
2026-10-08 12:28:20 +00:00
igneum-labs
62ccca7d3b
Class v6 10.2: the shadow's k from RTL (floor lane 2: k 0.18 at the lock at N3 absolute, a floor; the GDDR7 chip with the class v4 shadow 4.0x at the knee and 5.8x at stock against the served 2.1x; mulhi the worst lever on the card by 6x); the lead and the served-line review carry it
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 4e7bac031
2026-10-08 12:28:20 +00:00
igneum-labs
13a8ae3159
Class v6 layer 4: lane D's 17:00 cut as 5.1b (24,000 drawn eras: the op-mix band's known-failed test reads 0 of 3,000 under the cap; the lossy curve's edge at +2 to +3; the (c''') per-width calibration; the bit-R bias law; the measured bound n)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of dd692978a
2026-10-08 12:28:20 +00:00
igneum-labs
1dd00f838c
Class v6 layer 1: kit c, the multiply-heavy base table measured (three tables within 7 W unlocked and 0.6 W at the lock on the 5090)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 3f6ee5878
2026-10-08 12:28:20 +00:00
igneum-labs
d0968f6703
Class v6 10.3: the SRAM die's lock rows in both conventions, absolute first (2.0x at k 1, 3.7x to 4.0x at k 0.5, every read width; floor lane 3 d550dadd)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1bce62079
2026-10-08 12:28:20 +00:00
igneum-labs
65ef3ebcf3
Class v6: the k convention rule for the floor and the served-line review (absolute rows the headline, the record's beside them marked; the k lane's rows re-fold lane 3's shadowed rows before the close)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ac0fe332f
2026-10-08 12:28:20 +00:00
