Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>

Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master

docs/analysis/class-v6/census-w16-mix.md

@@ -10,7 +10,7 @@ Both class v6 changes pass the sub-version 3 rules, measured, on 256 seeds each
 - **(b) W = 4 at the re-weighted mix (13, 11, 6, 10, 8, 8, 7, 2, 6, 4: mulhi 6 to 2, mul 8 to 6, mad 8 to 10, add, xor, rotl, sub +1 each): PASS on the rules.** 256 of 256 both ways, 0 exhausted, rejection 0.407 (the fewest lossy ops), (c''') 1.2 percent, verifier within drift. Weaker than (a) on the address: at 4 words the product law lands on bit 2 (75 of 256 programs), and the extra `mad` raises the stride-bit refusals to 1.6 per seed on the eras whose R is in range (the control 1.2).
 - **(c) both: PASS on the rules**, 256 of 256 both ways, rejection 0.426, (c''') 3.4 percent, F8-form 0.999 to 1.002, verifier -0.1 percent; the address as (a) at the low bits and as (b) at the stride bit.
 
-The order this implies: W = 16 first; the re-weight after layer 1's index fold, which is the remedy for the stride-bit bias on every candidate and on the record alike.
+The order (the coordinator's correction at 14:1x UK, taken into the close): W = 16 passes the rules but is dead on energy, measured today by floor lane 5 on the 5090, 4090, H100 and 3090 (the card pays the second sector through its own fabric, +25 to +34 percent energy per hash, equal to the chip's +33, so the edge does not move and the honest card loses a quarter of its efficiency). So the class order is: W = 8 pins (lane 3), the index fold lands first, then the re-weight (b) at W = 8 goes through this harness again (five box-minutes on 16 cores) before it enters. What this census keeps from (a): the rules hold at the widest width, and a wider read removes the product's own low bits from the address by construction (at W = 8 bits 0 to 2 are alignment, so the bit-2 law of the W = 4 rows is gone there too); the stride bit R is the fold's to remove. The W = 8 class is not a width the generator draws today (`WIDTH_WORDS` is 1, 4, 16), so lane 3's construction lands before its census runs.
 
 ## 1. The candidates and the rules
 
@@ -90,7 +90,7 @@ The line: 256 of 256 seeds accepted on the no-era census inside the chain's cap
 | (b) W = 4 at the re-weighted mix | 256 of 256, 0 exhausted, r 0.407 | 256 of 256, 0 exhausted, 0 instrument refusals; 273 stride-bit refusals of 814 | bit 2 carries the product law in 75 of 256 programs (the width's, not the mix's: the w16 reference reads 74); the stride bit refused 1.6 times per seed on R-in-range eras against the control's 1.2 | 1.2 percent | 0.999 to 1.008 of the control | within drift | **PASS on the rules; weaker than (a) on the bias count** |
 | (c) both | 256 of 256, 0 exhausted, r 0.426 | 256 of 256, 0 exhausted, 0 instrument refusals; 247 stride-bit refusals of 781 | as (a) at bits 0 to 3; the stride bit refused 1.6 times per seed on R-in-range eras | 3.4 percent | 0.999 to 1.002 of the control | -0.1 percent, within drift | **PASS on the rules; the re-weight's stride-bit cost as in (b)** |
 
-Meaning for the two changes. The read width W = 16 passes every sub-version 3 rule at the record's own rates and is the cleanest of the three on the address: it is the one change that removes the product's low-bit law from the address by construction. The re-weight passes the rules with a lower rejection rate (fewer lossy ops, fewer (a') refusals) and costs nothing on the verifier, but it moves weight onto `mad`, a product the (a') rule accepts at a load's source, so the era-stride bias is refused about a third more often per seed until layer 1's index fold lands; with the fold in, that cost disappears and the re-weight's chip-side gain (the k lane's ranking) stands on its own. Nothing here moves the design's 10.0 defaults by itself: it says both changes may enter the class under the rules, and that W = 16 should enter first.
+Meaning for the two changes. The read width W = 16 passes every sub-version 3 rule at the record's own rates and is the cleanest of the three on the address: a wider read removes the product's low-bit law from the address by construction. It does not enter: floor lane 5's card rows of today (the 5090, 4090, H100 and 3090) read the second sector at +25 to +34 percent energy per hash on the card, paid through its own fabric and equal to the chip's +33, so the edge does not move and the honest card loses a quarter of its efficiency; W = 16 is dead on energy, and the rules' verdict here is what it would have needed beside that. The re-weight passes the rules with a lower rejection rate (fewer lossy ops, fewer (a') refusals) and costs nothing on the verifier, but it moves weight onto `mad`, a product the (a') rule accepts at a load's source, so the era-stride bias is refused about a third more often per seed until layer 1's index fold lands; with the fold in, that cost disappears and the re-weight's chip-side gain (the k lane's ranking) stands on its own. The class order, per the coordinator's close: W = 8 pins (lane 3), the index fold lands first, then the re-weight (b) at W = 8 goes through this harness again (five box-minutes) before it enters; the W = 8 draw is lane 3's construction (the generator's widths are 1, 4 and 16 today), and the harness takes it the day it parses.
 
 ## 7. The exact commands