igneum-labs
3471075c32
Class v6 floor lane 5 (invention): the knee row from PC 1 (the hash lane, kit d): at the 1,300 lock the hinted w64 form reads 37.6 against the 4-byte row's 100.6 MH/s at 2.3x the energy per hash, so W = 16 is dead at the knee as at stock; every row this lane owed on W = 16 is closed
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of c8e8b82adc8e8b82add
2026-10-08 14:05:41 +00:00
igneum-labs
c18f4d3acc
Merge class-v6-floor-sm-docs 4b5f1885 into master (gate: green on 4b5f1885, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:58:19 +00:00
igneum-labs
4b5f18859a
Class v6 floor lane 1: sm-sparse.md, the PC 1 table deduplicated (the job's five-minute uploads repeat earlier lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 661522a8f661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
8843b1d661
Class v6 floor lane 1: sm-sparse.md with PC 1's ladder (class v3 at stock agrees with the rented ladder at every rung, 3 to 3.5 percent at best; class v4 at the 1,300 lock needs every SM; the class v3 lock ladder partial and re-run owed; the memory-clock ladder queued)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1172d7a1661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
e6696d2680
Class v6 floor lane 1: sm-sparse.md, the decomposition rows (the awake floor 120 to 139 W on every card, the memory path 10 to 13 nJ per dependent read against the devices' modelled 2.0 or 1.2), the 5090's clean self-tune rows (sp37 of 170 at 2.5 percent under base on class v3, nothing on class v4), every pod destroyed
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 95909a47e661522a8f8
2026-10-08 13:49:30 +00:00
igneum-labs
7323a1abbc
Class v6 floor lane 1: docs/analysis/class-v6/floor/sm-sparse.md, the first full draft (four rented 5090s, the 4090 and the H100 at stock: the SM count is not the lever, 1 to 4 percent at best; the knee 43 of 170 SMs on class v3 at the 99 percent hold; the H100 decomposition; the self-tune rows; PC 1's lock and memory-clock ladders owed)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 56d422c33661522a8f8
2026-10-08 13:49:29 +00:00
igneum-labs
611c3975f5
Class v6 floor lane 4: the sweep closed (20 rows, the 4060 Ti's class v5 stock row, the three cards not reached), sections 2, 6 and 8 regenerated; 10 of 10 on build-3
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2a8572e482a8572e489
2026-10-08 13:41:15 +00:00
igneum-labs
d7f0c3e910
Class v6 floor lane 4: the one page and the close reading carry the measured class v5 stock column (the lock worth 34 to 41 percent on Blackwell and Ada) and the three core figures
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cb43665db2a8572e489
2026-10-08 13:41:15 +00:00
igneum-labs
8479ca94fc
Class v6 floor lane 4: section 2 regenerated from the tiers table (the class v5 stock column measured on 14 card classes, the three core figures), section 6 the sweep's rows and its two faults
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e985c19292a8572e489
2026-10-08 13:41:15 +00:00
igneum-labs
75618b8a50
Class v6 floor lane 4: the fold-any-k line (E_mem per chip, the k lane's 1.1 pJ column priced)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5e77445c72a8572e489
2026-10-08 13:41:14 +00:00
igneum-labs
43c94502ad
Class v6 floor lane 4: floor lane 1's stock rows taken (the 4090 and H100; the occupancy knob 1 to 2 percent), the class v5 watts driver and the memory-clock try (box-cardbench-v2m.sh) on 16 card classes in parallel
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 2b7cafee12a8572e489
2026-10-08 13:41:13 +00:00
igneum-labs
48d74807e6
Class v6 floor lane 4: the honest denominator (docs/analysis/class-v6/floor/denominator.md): every card class under class v5 with the knobs, measured or estimated, the chip edge per row in absolute picojoules; the LPDDR6 tier five years out; the Ember tiers statement and the re-measure rule; the sweep's first rows
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1a0a0e95e2a8572e489
2026-10-08 13:41:13 +00:00
igneum-labs
9d63a214b1
Merge class-v6-floor-invention-docs-2 99aa9729 into master (gate: green on 99aa9729, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:23:22 +00:00
igneum-labs
8fed9a23ca
Merge class-v6-census-docs a5cc338a into master (gate: green on a5cc338a, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:16:21 +00:00
igneum-labs
99aa972994
Class v6 floor lane 5 (invention): the three sourced precedents for the close (RandomX X5 1.0x to 1.5x after 46 months, the X9 unshipped; Ethash E3 36 months and the iPollo V2H about 14x; Kaspa KS0 21 months at 167x to the KS5 Pro's 725x); the w64 census and F8 row closed by the census lane (256 of 256 with and without an era): the class is sound and dead on energy
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 43302b4b243302b4b29
2026-10-08 13:11:56 +00:00
igneum-labs
a5cc338abb
Class v6 census: the recommendation amended on the coordinator's close (W = 16 dead on energy by floor lane 5's card rows; the order is W = 8 pins, the index fold first, then the re-weight at W = 8 through this harness before it enters)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cfd0b1db9 (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
844fa7ec50
Class v6 census: W = 16 and the op-mix re-weight through the sub-version 3 rules (docs/analysis/class-v6/census-w16-mix.md): every candidate 256 of 256 without an era and 256 of 256 across eras 0 to 7 with the window-bit refusal on, 0 exhausted; W = 16 removes the product's low bits from the address by construction; the re-weight lowers r to 0.41 and raises the stride-bit refusals; the rows, logs, scripts and commands
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d20eb04bd (cfd0b1db936c45275e33697c5b283eb12b25a424) for the box mirror master
2026-10-08 13:09:44 +00:00
igneum-labs
860e6d6f3e
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 13:04:40 +00:00
igneum-labs
aee75e737f
Class v6 invention: the drawn-era re-read on the fixed instrument b6799782 (the sound per-load form 254 of 256 seeds at 0.819 per candidate under eras, 234 of 256 at 0.927 no-era; the 16 x 27 form dead on both; class v4's shape at sub-version 3's 0.67 on the same binary), the two TSVs, sections 0, 2.1, 3.3 and 4 updated
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 13:04:39 +00:00
igneum-labs
e266d8a376
Merge class-v6-floor-invention-docs ca381a45 into master (gate: green on ca381a45, recorded by tools/ci/pre-push.sh; landed on the box mirror under the exception declared by main: main's ruling, 7 Oct 2026 19:5x UK: the GitHub account is suspended, lanes land on the box mirror's master, the box gate stamp is the verdict; GitHub gets the fast-forward when it answers)
2026-10-08 13:02:33 +00:00
igneum-labs
ca381a45f7
Class v6 floor lane 5 (invention): the 5090 W = 16 stock row measured on a secure-cloud pod: the hinted form at sp170-w4 holds the 4-byte rate (145.7 against 142.6 MH/s) at 401 W against 316, +25 percent energy per hash, the second sector 4.7 nJ on the card (k about 0.24); the kill stands at stock; all five pods destroyed, USD 9 spent
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0a8c7883e0a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
9083c305ad
Class v6 floor lane 5 (invention): the second sector measured on rented 4090, H100 and 3090 at stock and KILLED: a hinted one-request load (ld.global.L2::64B) holds the 4-byte rate on Ada (63.65 against 64.73 MH/s) and fails on Hopper (-21 percent) and Ampere (-13), but the card pays the sector at about 8.6 nJ through its own fabric (296 against 225 W on the 4090), +34 percent energy per hash against the modelled chip's +33, k about 0.13; W = 16 stays out of class v6, W = 32 dies with it; the KEEP list is now two model corrections, one measured card figure and the Ethash precedent row
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 6e59abcb30a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
32c0796e76
Class v6 floor lane 5 (invention), corrected for the read-width naming: the whole 64-byte item is class w64 (W = 16 words), not w16; its card side is measured at two occupancies that disagree (the hash -47 percent at full occupancy, the probe -13 percent at its best lane count) and unmeasured in a one-request form, so rank 1 is conditional on one PC 1 job with a 95 percent pass line; the chip side unchanged (+33 percent GDDR7, +24 HBM3) and, on floor lane 3's wire figure, the SRAM die 66x to 19x; the three outcomes priced (5.3x dead, 3.4x, 3.0x to 3.2x)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of ef79c5e710a8c7883e9
2026-10-08 12:45:35 +00:00
igneum-labs
d78167db48
Class v6 floor lane 5 (invention): the second sector as the one k = 1 lever (W = 16 words, the whole 64-byte item: the chip's GDDR7 read 2.0 to 3.2 nJ, E_mem +33 percent, the 5090 about +10 percent energy at +2.7 percent rate measured, every chip column down 10 to 15 percent, modelled); the tensor k band corrected to 0.2 to 0.7 (never above the ALU shadow); RT, proof of latency, drawn address map, video decode, row-straddle, scratch and independent chains killed with numbers; no 28 nm GDDR7 PHY exists so the chip's floor project is USD 20 M to 75 M; W = 32 held for v7
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of cf602a0310a8c7883e9
2026-10-08 12:45:34 +00:00
igneum-labs
8c201157c1
Class v6 floor lane 3: the close is 15:45 UK (the founder's rule of 13:3x); the four clock references updated, later rows as amendments
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8e9588de0 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
6a1943efc0
Class v6 floor lane 3: section 2.2c (W = 16 across the three chips: the die 66x to 19x if the 5090 passes, 36x at the measured w64 row; GDDR7 4.4x, HBM3 6.7x) and section 4.3 (the capex wall on the corrected USD 20 to 75 M project floor: no chip project below USD 23 M a year of miner revenue, every DRAM-board project above USD 340 M)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 7bc9de4b4 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
d057c76304
Class v6 floor lane 3: section 2.2b, the shadowed SRAM rows re-folded on the k lane's synthesised core (0.11 microjoules of shadow at N3, absolute k about 0.1): 21x at W = 4 and 18x at W = 8 under class v4, 10x at the full shadow, 6x to 7x at the knee; finding 1, the public-claim row and the served sentence carry the range with the record's band marked
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of bed2aebe3 (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
783f8fb664
Class v6 floor lane 3: section 2.2a, the shadowed rows at the 5090's knee in both k conventions, absolute first (3.8x / 2.0x at W = 4; the record's 6.1x / 3.3x marked)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d550dadda (8e9588de0) for the box mirror master
2026-10-08 12:29:15 +00:00
igneum-labs
de85e8f848
Class v6 floor lane 3: W = 8 free by the measured w16 and w64 rows (one sector per load, the crate's width set caveat); the 5090's size rows (4, 8, 10 percent per hash at the knee at 2, 4, 8 GiB) as the floor's honest-side cost; the k convention at the lock stated both ways
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e1e433638 (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
75430525e7
Class v6 floor lane 3: the SRAM full-store die and the dataset floor (the read width as the wire lever, 66x to 31x at zero shadow and 5.7x to 5.4x with it; the floor as a ticket lever, 5.5 / 8.5 / 11.5 GiB; the capex wall on the spec's emission, USD 0.13 to 2.9 per IGN; the four candidates killed)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 708d01b4d (8e9588de0) for the box mirror master
2026-10-08 12:29:14 +00:00
igneum-labs
0e23ca3f89
counter-asic-4 documents: the branch's text at 086411627 taken whole for the documents-only landing (what the replayed commits did not carry: the branch's merge resolutions)
2026-10-08 12:28:21 +00:00
igneum-labs
070d319ce6
Counter ASIC 4.0 research: 20.3c the hot-table rows as a record and the call (the replaced form is a per-watt gift to every miner and a larger one to the stored-dataset chip: a loss for resistance; ldcs a dead lever)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 93a5e401b
2026-10-08 12:28:18 +00:00
igneum-labs
f5f34eb36e
Counter ASIC 4.0 research: 15.1b the op-mix re-weight's hold on measured rows (shfl 4.9x the add; the chip's k on shuffle work would have to be 0.4 to 0.5 for 2.9x to be honest, unmeasured)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 963235c7c
2026-10-08 12:28:18 +00:00
igneum-labs
777098f829
Counter ASIC 4.0 research: 15.1a the microbench rows (20 probes on the 5090 at both states) and the correction they force: a tile is 32 MACs per lane, not 1,024, so the int8 MAC costs 1.5 to 4 pJ measured (the 6 October 4090 figure 1.8, not 0.056); the tensor shadow is the worse lever (k 0.03 to 0.3); the shuffle at 55.8 pJ per op is the card's dearest instruction (the re-weight's GPU side against it); an L2 hit at 2.4 nJ kills the hot-table lever; the first sentence and the ranking corrected
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of fc16c2ef1
2026-10-08 12:28:17 +00:00
igneum-labs
afca2b06d4
Counter ASIC 4.0 research: 20.3b the SM-sparse reading (a quarter of the SMs holds 98 percent of the rate at the same draw; the draw follows the work, not the SM count): rank 2 dead on measured rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 100d50aab
2026-10-08 12:28:17 +00:00
igneum-labs
7a5e13a4fb
Counter ASIC 4.0 research: 20.4 names the 1,430-tile point as the one the k column was priced at, the Apple side open, nothing served moving
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 9422f42a7
2026-10-08 12:28:17 +00:00
igneum-labs
c343a2a6d9
Counter ASIC 4.0 research: 20.3 the card rows of the seven packs (the tile block carries the ALU shadow's premium at the same rate, 14 percent cheaper at the knee; 0.048 to 0.091 pJ per MAC measured on the 5090), 20.4 the chip-model rows, the first sentence on measured rows
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 8522caca0
2026-10-08 12:28:17 +00:00
igneum-labs
19d64f2c86
Counter ASIC 4.0 research: --bench honours --variant through the pinned race (the SM-sparse run of 00:22 to 00:41 UTC served base on all 48 rows); RESULT carries variant, sparse_blocks and block_warps, variant_not_installed is the known-failed line; 20.3a records the run and its knee rows (v4 309.9 W, v3 219.4 W, premium 90.5 W at 1,300 MHz)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 0b0151b55
2026-10-08 12:28:17 +00:00
igneum-labs
a3b0f01364
Counter ASIC 4.0 research: 20.2a-close, the per-load 16 x 27 construction dead as a chain class (1.4 percent acceptance, 42 of 64 seeds without a program), the sound form named, rank 4 marked
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 4072cd7f0
2026-10-08 12:28:17 +00:00
igneum-labs
ecbd82956e
Counter ASIC 4.0 research: 20.2a the per-load fault fixed with clock readings, the drawn-era census (0 pairs across 16 eras), the Metal fingerprints (the tile reference bit-exact; the Apple emulation costs 35 and 78 percent of rate at 1,024 and 4,096 tiles per hash); 20.2b the biased-product-bits requirement from adv-cache-2
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of d26704367
2026-10-08 12:28:16 +00:00
igneum-labs
5fbc907c87
Counter ASIC 4.0 research: 20.2 the verifier rows (AVX2 tile path 0.047 us per tile per unit, mm1430 10.14 ms loaded; the per-load placement derives 11 percent fewer distinct items per warp: a uniformity fault as drawn, with its fix)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 598fd20f0
2026-10-08 12:28:16 +00:00
igneum-labs
e0dc3bcb79
Counter ASIC 4.0 research: section 20, the two prototypes built (what, where, gates; the verifier and card rows pending)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 1a7689e1b
2026-10-08 12:28:16 +00:00
igneum-labs
cc36d4db03
Counter ASIC 4.0 research, second pass: the k-above-1 hunt, the capex lever and the re-ranked list
...
Sections 15 to 19: every GPU block gaming and AI paid for, priced against the best public 4 to 5 nm chip figure with its k band, verifier cost and the edge at the measured premium (the one-sentence answer: nothing reads k above 1 with certainty; the int8 tensor tile is the only block near or above 1, so the tensor shadow with a SIMD byte-dot verifier is the new rank 3); the capex column added to the chip model (both sides capex-dominated at 7x to 10x their electricity; the per-unit capex wall unreachable by 3x to 7x; the project wall doubled from USD 100 M to about USD 200 M of break-even cap by the shadow-per-load design, the mission lane's method); the microbench of 20 probes documented as built (section 18); the owed list.
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of e76770109
2026-10-08 12:28:16 +00:00
igneum-labs
c4de71072e
Counter ASIC 4.0 research: clock stamps in UTC (the box compile at 20:48 UTC, the knee reading at 20:5x UTC)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 30c2d2211
2026-10-08 12:28:16 +00:00
igneum-labs
596f284ddc
Counter ASIC 4.0 research: the identity that forbids a zero-premium chip lever, the ranked designs, and the SM-sparse worker variant
...
docs/analysis/counter-asic-4-research.md (excluded from the public export): edge = (E_card + F) / (E_mem + k F); at zero premium the stored-dataset chip keeps E_card / E_mem, 3.6x on a 5090 locked at 1,400 MHz (measured card, modelled chip), about 2x at that card's idle-plus-memory bound, 1.7x on the M5 Max; class v5 at zero shadow leaves it at 5.1x to 9.1x; the shadow buys 2.1x at k = 1 for the measured 88 W (81.8 W at the knee) and turns against us below 1.8 pJ per op; per-card classes, the refresh as a cost, proof of useful work, memory shaping and the tensor block priced out with their arithmetic; ten designs ranked with the chip edge, the 5090 and 4070 premiums, the verifier cost, agent hours and what breaks each; the recommendation in five sentences; consequences per tier.
proto-cuda/nvrtc/worker.cpp: opt-in SM-sparse variants sp<N> and sp<N>-w<W> (a persistent grid of N blocks of W warps over the dispatch's nonces; the bound kernel rewritten at compile time with exact anchors into a unit function plus a wrapper of the kernel's name; made on demand by name, never in the default race; refused on variant-5 packs and with minBlocks). Gate: mingw cross-compile on igneum-build-1 under lease pool (class measure, label "ca4 research"), exit 0 with -Wall -Wextra, 22:48 UTC; exe sha256 ee8d0e70dd101f125f42c0c7cf07481a794ee18a1317acf68561b37ea18d72be; unrun on a card (the hash lane's PC 1 job run-ca4-pc1-ca4sparse-5090-20261007 is its first run).
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Documents-only replay of 5abb666ae
2026-10-08 12:28:16 +00:00
igneum-labs
cd123dbaf1
Merge class-v6-family-gate a39dbeca into master (gate: green on a39dbeca, recorded by tools/ci/pre-push.sh; landed on the build mirror)
2026-10-08 12:12:39 +00:00
igneum-labs
5eeb2299d3
Class v6 invention: the 5090 rows for the two per-load packs (the sound form costs the card 15 to 20 percent more per shadow instruction than the whole block, +19 W unlocked and +6.6 W at the knee at class v4's count; rank 1's GPU column corrected, the verdict restated with the honest sign)
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:45:37 +00:00
igneum-labs
a39dbeca29
Class v6 family gate, the 17:00 cut: the harness as a plain diff at 3dc3117c (the founder-strings check refuses the patch form's author lines)
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Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:25 +00:00
igneum-labs
4ad3e4013c
Merge remote-tracking branch 'build/master' into class-v6-invention
2026-10-08 11:35:21 +00:00
igneum-labs
053c387132
Class v6 invention: the uniformity read at 2^20 on 64 seeds (the sound per-load forms clean, 0 over 1.2x and 0 sites under 0.995; the raw class v4 shape through the v2/v3 rule 41 of 64 hot at 7x to 36x, AP-F8-1's class as the harness's known-failed firing), the harness crate, the box OOM record, the offered window-bits test
...
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
2026-10-08 11:35:11 +00:00
