igneum-network/igneum
1
0
Fork 0
Code Issues Pull requests Releases Activity
1004 commits 305 branches 1 tag 1.5 GiB
Commit graph

1004 commits

This branch
This branch
All branches
Author SHA1 Message Date
igneum-josh
18cc4ec127 Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 17:19:26 +01:00
igneum-josh
b7cd99ee26 Counter ASIC 3.0 gates (hash): the G2 job writes its found lines to g2-<pack>.found and prints the count and sha256 (no found line in the report, every RESULT line inside the cap, the log and collect glob named); tools/ca3-v4/g2-recheck.sh derives the digest from hash-bound and diffs a found file; trusted on a known-good and a known-bad file 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:18:57 +01:00
igneum-josh
ff5c103f50 Counter ASIC 3.0 status: every gate green on the hash, the program-id blocker on the cut, the one line for Josh 2026-10-06 17:18:08 +01:00
igneum-josh
601f152103 Merge branch 'ca3-v4-node' into ca3-coord 2026-10-06 17:16:21 +01:00
igneum-josh
7a48950c3a Merge branch 'ca3-v4-hash' into ca3-coord 2026-10-06 17:16:21 +01:00
igneum-josh
c3ddf1e017 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 JSON summaries 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:15:17 +01:00
igneum-josh
1ecb730462 Counter ASIC 3.0 gates (hash): the RTX 5090 G1 and G2 evidence from the collected job.log (eight fingerprints equal to the Mac's, 8 x 1,024 of 1,024); hash-gates.md and the bench-log entry closed 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:14:08 +01:00
igneum-josh
4f52d4f66e Counter ASIC 3.0 gates (node): G6 row, the two crates whose lines the relay upload does not carry 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:10:30 +01:00
igneum-josh
393bd7a374 Counter ASIC 3.0 gates (node): G4, G4b, G5 and G6 GREEN for class v4 (the three fast-time summaries incl. the known-failed case, node-gates.md, counter-asic-3-node.md) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:10:00 +01:00
igneum-josh
5e2fbdd0c6 Counter ASIC 3.0 gates (hash): the gate directory (hash-gates.md, G1 Mac, G2 Mac, G3 and verifier JSON) and the bench-log entry; the RTX 5090 G1 rows pending the collected job.log 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:07:55 +01:00
igneum-josh
306d649265 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 17:03:33 +01:00
igneum-josh
e546d0a36b Counter ASIC 3.0 PC 1 AMD: the watts re-run script (sampler proven on the idle window, never blind), the sampler fed through the environment (the unquoted ArgumentList class), per-entry card restore in jobs 1 and 4, the README's record of job 1's first run 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 17:02:55 +01:00
igneum-josh
a522d046e1 Counter ASIC 3.0 gates (node): class v4 = mx8+sh256x27 through the stack (igneum-pow ProgramClass::V4, V4_CLASS, generator 4, program_id(4, seed, attempt), the era composed as v3's; program.h and program.json class v4; packcheck, packfile.h, the CUDA and OpenCL identity rule and the Metal worker accept generator 4 and the class=v4 token, the Metal worker takes v4 from the prepared pack only; v2 and v3 byte-identical, the pinned packs diffed); the G4 harness class-v4.mjs (two switches, the never case); override-60x.json: the v4 field at never, the duplicated proving v1 block removed, the four 0.3.12/0.3.13 fields added; CI check override-json-check.sh (no duplicate key in any override file) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:58:49 +01:00
igneum-josh
4ce9d6589a Counter ASIC 3.0 status: job 1 closed (G1 AMD green, the 9070 XT ladder flat to 330,700 ops, watts owed) 2026-10-06 16:58:03 +01:00
igneum-josh
63303a25a5 Counter ASIC 3.0 gates (hash): the class v4 packs (mx8+sh256x27 with the era at devnet epoch 0 and eras 0 to 5, the v3 control), the PC 2 G1+G2 playbook, hash-bound --count ported from ca2-era, the mixer harness on a class and an era (IGNEUM_MIXER_CLASS, IGNEUM_MIXER_ERA, the shadow contract) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:57:40 +01:00
igneum-josh
01b092d859 Counter ASIC 3.0 status: G1 AMD green on the candidate pack (interim, job 1 running) 2026-10-06 16:52:47 +01:00
igneum-josh
8aba68002b Counter ASIC 3.0 status: the Ember run 5 rows for the 5090 (the cap never binds, 0.41 MH per W flat) 2026-10-06 16:45:39 +01:00
igneum-josh
1fdb1e0d26 Counter ASIC 3.0 status: the PC 1 AMD scripts ready (checks pass, kit verified) 2026-10-06 16:40:42 +01:00
igneum-josh
0cdd348176 Merge branch 'ca3-pc1-amd' into ca3-coord 2026-10-06 16:40:19 +01:00
igneum-josh
e054ed71a1 Counter ASIC 3.0 PC 1 AMD: the four PC 1 job scripts (G1 + ladder on the 9070 XT with ADLX watts, family step costs, dr736 derive, the 4070 ladder), the kit maker and the README with the publish commands 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:39:51 +01:00
igneum-josh
1f33cc6969 Counter ASIC 3.0 PC 1 AMD: OpenCL family probe (every 1.13.2 family through AMD's builtins, khr/intel sub-groups, media ops, C forms and local emulation; bit-exact on Apple OpenCL) and the clBuildProgram time line in the OpenCL worker 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 16:39:51 +01:00
igneum-josh
c93a999e82 Counter ASIC 3.0 status: the gate run opened on mx8+sh256x27 (Josh 16:50 UTC), the gate table 2026-10-06 16:38:44 +01:00
igneum-josh
3213ee9942 Counter ASIC 3.0 status: the PC 1 AMD job queue (prepared, not published) 2026-10-06 16:13:22 +01:00
igneum-josh
18c762ee8c Counter ASIC 3.0 status: the close (items 6, 7 and 8 closed; the chip model before and after; the class v4 candidate mx8+sh256x27 ready for the gate run; nine decisions for Josh; the owed list) 2026-10-06 09:48:18 +01:00
igneum-josh
820f4d4eed Merge branch 'ca3-reserve' into ca3-coord 2026-10-06 09:45:48 +01:00
igneum-josh
12d8a9302a Merge branch 'ca3-shadow' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 09:45:48 +01:00
igneum-josh
b85f0f18ed Counter ASIC 3.0 items 6 and 7: the RTX 5090 step-cost rows (PC 2 job run-ca3-family-pc2-20261006, every family bit-exact, mm8 included) in the bench-log and the reserve document 2026-10-06 09:45:02 +01:00
igneum-josh
70eaf06456 Counter ASIC 3.0 item 8: the RTX 5090 rows, the chip side on the measured 11 pJ per op, the verdict 
PC 2 job run-ca3-shadow-pc2-20261006 (card empty, every pack bit-exact against the Mac): the 5090 holds its rate to
150,800 ops per hash and loses 2.7 percent at 199,600 under the app's 431 W cap, which binds from 102,100 ops up and
takes the clock from 3,037 to 1,834 MHz (86 MH/s at 330,700 ops); 350 W at the control, 2.65 to 3.27 microjoules per
hash; marginal ALU energy 10 to 13 pJ per counted op. Clock rows OWED (nvidia-smi refused -lgc without rights). Chip
side at N = 100,000 and k = 1: 2.1x over the 5090 on GDDR7, 0.9x over the M5 Max. GO at mx8+sh256x27.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:44:57 +01:00
igneum-josh
f66c4eeca5 Counter ASIC 3.0 items 6 and 7: PC 2 family playbook posts both card key forms from settings.json, confirms the card quiet by the process list, restores cards and prover in a finally block 2026-10-06 09:34:28 +01:00
igneum-josh
bc148a85ec Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
 2026-10-06 09:31:10 +01:00
igneum-josh
54bc188a5d Counter ASIC 3.0 item 2: the RTX 5090 rows from PC 2 (bit-exact on CUDA, +1.1 s NVRTC per pack, the card-off key finding) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:30:15 +01:00
igneum-josh
1828e3e631 Counter ASIC 3.0 status: the detector's two calibration findings answered (9c7838e merged; max r 0.10) 2026-10-06 09:29:28 +01:00
igneum-josh
4728dd604b Merge branch 'ca3-detector' into ca3-coord 2026-10-06 09:29:09 +01:00
igneum-josh
9c7838e5b3 Counter ASIC 3.0 items 4 and 5: the epoch common factor is the median over steady core ids 
The mean over every present id let one paused-and-resumed card (the Mac, a 178% step) push
every other residual the same way in the epochs it was off, which read as an r = 0.94 edge
between two honest 5090 keys on the merged tree (window 41 to 46). The factor is now the
median over ids that are steady and present in every window epoch (median over all present
when the core is under 3): the same window reads max r 0.10. README: the three calibration
readings (the edge, the factor-of-two from identities=2, the unsteady Mac) answered.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:28:55 +01:00
igneum-josh
7bd1943231 Counter ASIC 3.0 status: PC 2 clear, the detector and vendor-share dry rows on the live tables, the restart constraint 2026-10-06 09:26:52 +01:00
igneum-josh
d40b880dc3 Counter ASIC 3.0 item 8: the PC 2 playbook switches the prover back on in its finally block (the clear file's constraint) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:26:22 +01:00
igneum-josh
477729e9dc Counter ASIC 3.0 status: the marker guard exists in CI already 2026-10-06 09:25:02 +01:00
igneum-josh
fa603bc378 Counter ASIC 3.0 status: items 6 and 7 merged (5090 rows queued), the marker slip recorded 2026-10-06 09:24:50 +01:00
igneum-josh
fcce185eeb Merge branch 'ca3-reserve' into ca3-coord 
# Conflicts:
#	docs/bench-log.md
#	tools/observer/observer.mjs
 2026-10-06 09:24:29 +01:00
igneum-josh
45f30196b9 Merge ca3-shadow (item 8's Mac rows) into ca3-coord: LoadClass carries derive_len and shadow; igneum-pow suite 96 passed 2026-10-06 09:11:03 +01:00
igneum-josh
8b520c1eaf Counter ASIC 3.0 item 8: the CUDA text checked in the clang emulation and the OpenCL text on Apple OpenCL (gate G1 row) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:10:25 +01:00
igneum-josh
a050a54c65 Counter ASIC 3.0 item 8: the Mac rows 
The M5 Max ladder (Metal, packbench, IOReport GPU and DRAM watts without root): latency-bound to about 100,000 ops per
hash, the 5 percent point about 130,000, 11 to 27 W GPU at 100,000 ops, 0.78 to 1.40 microjoules per hash; the
verifier's law 2.06 ms + 3.2 us per 1,000 shadow instructions per warp on one core; every pack bit-exact. The
analysis file with the knob, the chip side (k = 1, 1.5, 0.3), the gates and the consequences; the bench-log entry;
the 5090 rows pending the PC 2 job (the playbook now carries the core-clock rows and the sh256x40 rung).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 09:08:26 +01:00
igneum-josh
533a659287 Counter ASIC 3.0 status: the 5090 draws about 290 W at the hash, cap floor 400 W, clocks are the lever (item 8's job) 2026-10-06 08:59:42 +01:00
igneum-josh
d4b7300788 Counter ASIC 3.0 item 8: the latency-shadow knob (LoadClass +sh<S>x<R>), its packs and the PC 2 playbook 
A shadow block of S ALU instructions run R times at the end of every iteration, drawn from the program stream after
the 64 base instructions, behind LoadClass::shadow: v2 and v3 draw nothing and emit nothing (the pinned packs are
byte-identical, cargo test 54 + 4 + 19 + 7 green). The interpreter, the three kernel dialects (both kernels each),
program.h and program.json carry it; the acceptance rule interprets the base program only. Packs for seed
igneum-genesis over class mx8 at 4,096 to 180,224 shadow instructions per hash (proto-cuda/packs-ca3-shadow), and
the PC 2 bench playbook tools/ca3-shadow/pc2-shadow-bench.ps1 (passes the publisher's three checks).

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:58:35 +01:00
igneum-josh
a6a7ad6a39 Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite 2026-10-06 08:51:42 +01:00
igneum-josh
82211d3153 Merge branch 'ca3-derive' into ca3-coord 2026-10-06 08:51:42 +01:00
igneum-josh
2070915cff Counter ASIC 3.0 status: PC 2 clear about 08:35Z, the job order 2026-10-06 08:51:36 +01:00
igneum-josh
9142d95691 Counter ASIC 3.0 status: item 2 interim (GO as reserve, NO-GO genesis-live at dr736), PC 2 clear about 08:35Z 2026-10-06 08:51:15 +01:00
igneum-josh
bdc07d3a1d Counter ASIC 3.0 item 2: the verifier headroom per class under the 10 ms gate (the budget item 8 shares) 
Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
 2026-10-06 08:51:13 +01:00
igneum-josh
08755f5680 Merge branch 'ca3-derive' into ca3-coord 
# Conflicts:
#	docs/analysis/chip-model-v3.md
 2026-10-06 08:51:00 +01:00