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Counter ASIC 3.0 status: item 2's verifier headroom table and the crate suite

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igneum-josh 2026-10-06 08:51:42 +01:00
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docs/plans/counter-asic-3-status.md
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@ -48,6 +48,8 @@ What moves the f = 1 rows (chip-model-v3.md section 5.7): not the dataset size (
| dr368 (9 x 368 instructions) | about half of dr736 | 2.69 | 6.7, passes | | | | |
| dr736 (9 x 736 instructions, the genesis-day draw: 9,992 / 10,659 / 1,461) | | 4.875 to 4.944 (5.241) | 12, over the gate | 29.0 ms | 27.1 MH/s (equal) | yes (Metal and Apple OpenCL, fingerprint 50e3eaa779da4f1e) | 0.29x / 0.34x / 0.43x |
Verifier headroom under the 10 ms gate (bdc07d3, the budget item 8's shadow ops may spend; steady / worst cold): on this M5 Max core x8 7.9 / 7.8 ms, dr368 7.3 / 7.1, dr736 5.1 / 4.8; on the approximate 2019-class core x8 4.8 / 4.6, dr368 3.3 / 2.8, dr736 none (over by 2.2 / 3.1). `cargo test -p igneum-pow` on acb96ee under the build lock: 95 passed, 0 failed; the pinned v2 and v3 packs regenerate byte for byte.
Consequence: the derivation costs no hash rate on any card and 7 ms a day of build on the Mac (29 against 22 ms; the 5090 and the 9070 XT rows owed, the loaded-iGPU tier is the one to watch); it costs the verifier, and the verifier budget is shared with item 8's shadow ops under the one 10 ms gate, so the class v4 candidate is the pairing that fits, not either lever alone (both workers told).
### Item 6, the Mac rows (interim, ca3-reserve 192a683; the 5090 job waits on PC 2)